31st week of 2019 patent applcation highlights part 68 |
Patent application number | Title | Published |
20190237562 | Techniques for Vertical FET Gate Length Control - Techniques for VFET gate length control are provided. In one aspect, a method of forming a VFET device includes: patterning fins in a substrate; forming first polymer spacers alongside opposite sidewalls of the fins; forming second polymer spacers offset from the fins by the first polymer spacers; removing the first polymer spacers selective to the second polymer spacers; reflowing the second polymer spacers to close a gap to the fins; forming a cladding layer above the second polymer spacers; removing the second polymer spacers; forming gates along opposite sidewalls of the fins exposed in between the bottom spacers and the cladding layer, wherein the gates have a gate length Lg set by removal of the second polymer spacers; forming top spacers above the cladding layer; and forming top source and drains above the top spacers. A VFET device is also provided. | 2019-08-01 |
20190237563 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device may include forming a fin structure on a substrate; forming an interface film having a first thickness on the fin structure using a first process; forming a gate dielectric film having a second thickness on the interface film using a second process different from the first process; and densifying the gate dielectric film using a third process different from the first and second processes. The second thickness may be greater than the first thickness, and the first thickness of the interface film may be unchanged after the densifying of the gate dielectric film. | 2019-08-01 |
20190237564 | HYBRID FINFET STRUCTURE WITH BULK SOURCE/DRAIN REGIONS - A transistor including a source and a drain each formed in a substrate; a channel disposed in the substrate between the source and drain, wherein the channel includes opposing sidewalls with a distance between the opposing sidewalls defining a width dimension of the channel and wherein the opposing sidewalls extend a distance below a surface of the substrate; and a gate electrode on the channel. A method of forming a transistor including forming a source and a drain in an area of a substrate; forming a source contact on the source and a drain contact on the drain; after forming the source contact and the drain contact, forming a channel in the substrate in an area between the source and drain, the channel including a body having opposing sidewalls separated by a length dimension; and forming a gate contact on the channel. | 2019-08-01 |
20190237565 | SMOOTHING SURFACE ROUGHNESS OF III-V SEMICONDUCTOR FINS FORMED FROM SILICON MANDRELS BY REGROWTH - A method of forming a III-V semiconductor vertical fin is provided. The method includes forming a fin mandrel on a substrate, forming a spacer layer on the substrate surrounding the fin mandrel, forming a wetting layer on each of the sidewalls of the fin mandrel, forming a fin layer on each of the wetting layers, removing the fin mandrel, removing the wetting layer on each of the fin layers, and forming a fin layer regrowth on each of the sidewalls of the fin layers exposed by removing the wetting layer from each of the fin layers. | 2019-08-01 |
20190237566 | BIPOLAR TRANSISTOR AND METHOD FOR PRODUCING THE SAME - A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer. | 2019-08-01 |
20190237567 | SEMICONDUCTOR DEVICE - Trenches each have longer sides extending in a longitudinal direction, and shorter sides linking the longer sides together. The trenches are periodically arranged in the longitudinal direction and a transverse direction. A first region is on a drift layer of a first conductivity type, has a second conductivity type, and is penetrated by the trenches. A second region is on the first region so as to be away from the drift layer, has the first conductivity type, and is in contact with the longer sides of each of the trenches so as to be away from the ends of the longer sides. A third region is on the first region, has the second conductivity type, and has a higher impurity concentration than the first region. The gate electrode is in the trench with a gate insulating film interposed therebetween. | 2019-08-01 |
20190237568 | SILICON CONTROLLED RECTIFIERS INTEGRATED INTO A HETEROJUNCTION BIPOLAR TRANSISTOR PROCESS - Fabrication methods and device structures for a silicon controlled rectifier. A cathode is arranged over a top surface of a substrate and a well is arranged beneath the top surface of the substrate. The cathode is composed of a semiconductor material having a first conductivity type, and the well also has the first conductivity type. A semiconductor layer, which has a second conductivity type opposite to the first conductivity type, includes a section over the top surface of the substrate. The section of the semiconductor layer is arranged to form an anode that adjoins the well along a junction. | 2019-08-01 |
20190237569 | Group III-Nitride High-Electron Mobility Transistors with Buried P-Type Layers and Process for Making the Same - An apparatus includes a substrate. The apparatus further includes a group III-nitride buffer layer on the substrate; a group III-nitride barrier layer on the group III-nitride buffer layer, the group III-nitride barrier layer including a higher bandgap than a bandgap of the group III-nitride buffer layer. The apparatus further includes a source electrically coupled to the group III-nitride barrier layer; a gate electrically coupled to the group III-nitride barrier layer; a drain electrically coupled to the group III-nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate below said group III-nitride barrier layer. | 2019-08-01 |
20190237570 | HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) DEVICE - A high electron mobility transistor (HEMT) device with epitaxial layers that provide an electron Hall mobility of 1080±5% centimeters squared per volt-second (cm | 2019-08-01 |
20190237571 | BIDIRECTIONAL POWER MOSFET STRUCTURE WITH A CATHODE SHORT STRUCTURE - A field effect device includes a semiconductor body separating a source and a drain, both source and drain coupled to the semiconductor body. An insulated control gate is located over the semiconductor body between the source and drain and configured to control a conductive channel extending between the source and drain. First and second doped regions such as highly-doped regions are adjacent to the source. The first or second doped region may be a cathode short region electrically coupled to the source. The cathode short region may be used in a bidirectional power MOSFET. | 2019-08-01 |
20190237572 | FinFETs with Source/Drain Cladding - A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions of the isolation regions, wherein the semiconductor fin is over top surfaces of the isolation regions. A gate stack overlaps the semiconductor fin. A source/drain region is on a side of the gate stack and connected to the semiconductor fin. The source/drain region includes an inner portion thinner than the semiconductor fin, and an outer portion outside the inner portion. The semiconductor fin and the inner portion of the source/drain region have a same composition of group IV semiconductors. | 2019-08-01 |
20190237573 | MULTI-GATE SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A method for forming a multi-gate semiconductor device includes providing a substrate including at least a fin structure and a dummy gate structure over the fin structure and the substrate, disposing a conductive spacer over sidewalls of the dummy gate structure, portions of the fin structure are exposed from the dummy gate structure and the conductive spacer, forming a source/drain region in the portions of the fin structures exposed from the dummy gate structure and the conductive spacer, disposing a dielectric structure over the substrate, removing the dummy gate structure to form a gate trench in the dielectric structure, the conductive spacer is exposed from sidewalls of the gate trench, disposing at least a gate dielectric layer over a bottom of the gate trench, and disposing a gate conductive structure in the gate trench, sidewalls of the gate conductive structure are in contact with the conductive spacer. | 2019-08-01 |
20190237574 | RECTIFIER AND ROTATING ELECTRIC MACHINE INCLUDING RECTIFIER - A rectifier has a rectification circuit configured to rectify multi-phase alternating current generated by a rotating electric machine into direct current. The rectifier includes upper-arm semiconductor switching elements included in an upper arm of the rectification circuit, upper-arm protection diodes included in the upper arm and each being electrically connected in parallel with one of the upper-arm semiconductor switching elements, lower-arm semiconductor switching elements included in a lower arm of the rectification circuit, and lower-arm protection diodes included in the lower arm and each being electrically connected in parallel with one of the lower-arm semiconductor switching elements. Each of the upper-arm and lower-arm protection diodes is configured to have, when a reverse voltage higher than a breakdown voltage of the protection diode is applied to the protection diode, an operating resistance that is higher than three times an operating resistance of any of the upper-arm and lower-arm semiconductor switching elements. | 2019-08-01 |
20190237575 | Semiconductor Component with Edge Termination Region - A semiconductor component includes a semiconductor body having opposing first surface and second surfaces, and a side surface surrounding the semiconductor body. The semiconductor component also includes an active region including a first semiconductor region of a first conductivity type, which is electrically contacted via the first surface, and a second semiconductor region of a second conductivity type, which is electrically contacted via the second surface. The semiconductor component further includes an edge termination region arranged in a lateral direction between the first semiconductor region of the active region and the side surface, and includes a first edge termination structure and a second edge termination structure. The second edge termination structure is arranged in the lateral direction between the first edge termination structure and the side surface and extends from the first surface in a vertical direction more deeply into the semiconductor body than the first edge termination structure. | 2019-08-01 |
20190237576 | POWER SEMICONDUCTOR DEVICES - A power semiconductor device including a first conductivity type semiconductor substrate, a drain metal electrode, a first conductivity type semiconductor drift region, and a second conductivity type semiconductor body region. The second conductivity type semiconductor body region includes a first conductivity type semiconductor source region and anti-punch-through structure; the anti-punch-through structure is a second conductivity type semiconductor body contact region or metal structure; the lower surface of the anti-punch-through structure coincides with the upper surface of the first conductivity type semiconductor drift region or the distance between the two is less than 0.5 μm, so that make the device avoid from punch-through. An anti-punch-through structure is introduced at the source end of the device to avoid punch-through breakdown caused by short channel and light-doped body region. | 2019-08-01 |
20190237577 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench. | 2019-08-01 |
20190237578 | SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device (A | 2019-08-01 |
20190237579 | Method and Apparatus for use in Improving Linearity of MOSFETs using an Accumulated Charge Sink-Harmonic Wrinkle Reduction - A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink. | 2019-08-01 |
20190237580 | LONG-CHANNEL FIN FIELD EFFECT TRANSISTORS - A method of forming a long-channel fin field effect device is provided. The method includes forming a trench in a substrate, forming a pedestal in the trench, wherein the pedestal extends above the surface of the substrate, forming a sacrificial pillar on the pedestal, forming a rounded top surface on the sacrificial pillar to form a sacrificial support structure, forming a fin material layer on the exposed surface of the sacrificial support structure, and removing the sacrificial support structure to leave a free-standing inverted U-shaped fin. | 2019-08-01 |
20190237581 | TRANSISTOR, SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF MANUFACTURING TRANSISTOR - According to one embodiment, a transistor includes first to third conductors, first and second oxide semiconductors, and a gate insulating film. The first and second conductors are stacked via an insulator above a substrate. The first oxide semiconductor is formed on the first conductor. The second oxide semiconductor is formed on the first oxide semiconductor. The second oxide semiconductor have a pillar shape through the second conductor along a first direction crossing a surface of the substrate. The second oxide semiconductor is different from the first oxide semiconductor. The gate insulating film is formed between the second conductor and the second oxide semiconductor. The third conductor is formed on the second oxide semiconductor. | 2019-08-01 |
20190237582 | MAGNESIUM ZINC OXIDE-BASED HIGH VOLTAGE THIN FILM TRANSISTOR - Magnesium Zinc Oxide (MZO)—based high voltage thin film transistor (MZO-HVTFT) is built on a transparent substrate, such as glass. The device has the circular drain and ring-shaped source and gate to reduce non-uniformity of the electric field distribution. Controlled Mg doping in the channel and modulated Mg doping in a transition layer located at the channel-gate dielectric interface improve the device's operating stability and increase its blocking voltage capability over 600V. The MZO HVTFT can be used for fabricating the micro-inverter in photovoltaic system on glass (PV-SOG), and for self-powered smart glass. | 2019-08-01 |
20190237583 | LIQUID CRYSTAL DISPLAY DEVICE - To provide a liquid crystal display device suitable for a thin film transistor which uses an oxide semiconductor. In a liquid crystal display device which includes a thin film transistor including an oxide semiconductor layer, a film having a function of attenuating the intensity of transmitting visible light is used as an interlayer film which covers at least the oxide semiconductor layer. As the film having a function of attenuating the intensity of transmitting visible light, a coloring layer can be used and a light-transmitting chromatic color resin layer is preferably used. An interlayer film which includes a light-transmitting chromatic color resin layer and a light-blocking layer may be formed in order that the light-blocking layer is used as a film having a function of attenuating the intensity of transmitting visible light. | 2019-08-01 |
20190237584 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region. | 2019-08-01 |
20190237585 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion. | 2019-08-01 |
20190237586 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator. | 2019-08-01 |
20190237587 | THIN FILM TRANSISTOR, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR - A thin film transistor, a method for manufacturing the thin film transistor, and a display device are provided. The thin film transistor includes a substrate, a semiconductor layer, a source electrode, a drain electrode, a gate electrode, an insulating layer, and a number of floating electrodes. The semiconductor layer is formed at the substrate. Two first doped regions are respectively formed at two ends of the semiconductor layer. The source electrode and the drain electrode are respectively disposed at the first doped regions. The gate electrode is disposed between the source electrode and the drain electrode. The semiconductor layer between the gate electrode and the drain electrode forms an offset region. A number of spaced second doped regions is formed at the offset region. The insulating layer covers the offset region without the second doped regions formed thereon. A number of floating electrodes is disposed at the insulating layer. | 2019-08-01 |
20190237588 | TRENCH SEMICONDUCTOR DEVICE HAVING SHAPED GATE DIELECTRIC AND GATE ELECTRODE STRUCTURES AND METHOD - A semiconductor device includes a region of semiconductor material having first and second opposing major surfaces. A trench structure includes a trench extending into the region of semiconductor material from the first major surface, wherein the first major surface defines a first horizontal plane in a cross-sectional view. The trench structure further includes a conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region. A Schottky contact region is disposed adjacent the first major surface on opposing sides of the trench structure, the Schottky contact region having an upper surface residing on a second horizontal plane in the cross-sectional view. The dielectric region comprises an uppermost surface and configured such that a major portion of the uppermost surface is disposed above the first horizontal plane in the cross-sectional view. The structure and method provide a semiconductor device with improved performance (e.g., reduced leakage and more stable breakdown voltage) and improved reliability. | 2019-08-01 |
20190237589 | STANDARD INTEGRATED CELL WITH CAPACITIVE DECOUPLING STRUCTURE - A standard integrated cell includes a semiconductor region with a functional domain for logic circuits including a transistor and an adjacent continuity domain that extends out to an edge of the standard integrated cell. The edge is configured to be adjacent to another continuity domain of another standard integrated cell. The standard integrated cell further includes at capacitive element. This capacitive element may be housed in the continuity domain, for example at or near the edge. Alternatively, the capacitive element may be housed at a location which extends around a substrate region of the transistor. | 2019-08-01 |
20190237590 | SENSOR - A sensor includes a printed circuit board; at least one semiconductor chip arranged on the printed circuit board and includes a front-side contact, wherein the semiconductor chip is a radiation-detecting semiconductor chip; an embedding layer arranged on the printed circuit board and laterally adjoining the at least one semiconductor chip; and a contact layer connected to the front-side contact of the at least one semiconductor chip. | 2019-08-01 |
20190237591 | LIGHT DETECTING DEVICE, LIGHT DETECTING METHOD AND DISPLAY DEVICE - The light detecting device provided by the present disclosure includes a reset circuit, a photoelectric conversion circuit, a voltage follower circuit, a selection circuit, and a light fluctuation detecting circuit. The light fluctuation detecting circuit is connected to each of a light fluctuation detection control terminal, a photoelectric node and an input terminal of the voltage follower circuit. The light fluctuation detecting circuit is configured to enable or disable a connection between the photoelectric node and the input terminal of the voltage follower circuit. When the light fluctuation detecting circuit is turned off, a drain current of the light fluctuation detecting circuit may change as the brightness of light received by the light fluctuation detecting circuit changes. The voltage at the output node is used to determining brightness of light received by the photoelectric conversion circuit and whether is a fluctuation in the in the brightness of the light. | 2019-08-01 |
20190237592 | PHOTOVOLTAIC SYSTEM AND COMPONENTS - A solar module has a plurality of strips that are configured with each other using high quality crystalline silicon increases power output even though total internal reflection in the module has been reduced or even eliminated. A module that is configured to eliminate reflective surfaces such as ribbon wire and exposed bus bars while making other surfaces such as a back sheet black or antireflective has no or minimal internal reflections while having higher efficiency and power yields per unit area than conventional modules that use white backsheets. | 2019-08-01 |
20190237593 | PRODUCTION OF SENSORS - A method of producing sensors includes providing a carrier plate; arranging semiconductor chips on the carrier plate, wherein the semiconductor chips include at least radiation-detecting semiconductor chips; providing radiation-transmissive optical elements on the carrier plate provided with the semiconductor chips, wherein a plurality of radiation-transmissive optical elements are provided jointly on the carrier plate provided with the semiconductor chips; and singulating the carrier plate provided with the semiconductor chips and the radiation-transmissive optical elements, thereby forming separate sensors including a section of the carrier plate, at least one radiation-detecting semiconductor chip and at least one radiation-transmissive optical element. | 2019-08-01 |
20190237594 | In-Plane Resonant-Cavity Infrared Photodetectors with Fully-Depleted Absorbers - Resonant-cavity infrared photodetector (RCID) devices that include a thin absorber layer contained entirely within the resonant cavity. In some embodiments, the absorber is a single type-II InAs—GaSb interface situated between an AlSb/InAs superlattice n-type region and a p-type AlSb/GaSb region. In other embodiments, the absorber region comprises quantum wells formed on an upper surface of the n-type region. In other embodiments, the absorber region comprises a “W”-structured quantum well situated between two barrier layers, the “W”-structured quantum well comprising a hole quantum well sandwiched between two electron quantum wells. In other embodiments, the RCID includes a thin absorber region and an nBn or pBp active core within a resonant cavity. In some embodiments, the RCID is configured to absorb incident light propagating in the direction of the epitaxial growth of the RCID structure, while in other embodiments, it absorbs light propagating in the epitaxial plane of the structure. | 2019-08-01 |
20190237595 | In-Plane Resonant-Cavity Infrared Photodetectors with Fully-Depleted Absorbers - Resonant-cavity infrared photodetector (RCID) devices that include a thin absorber layer contained entirely within the resonant cavity. In some embodiments, the absorber is a single type-II InAs—GaSb interface situated between an AlSb/InAs superlattice n-type region and a p-type AlSb/GaSb region. In other embodiments, the absorber region comprises quantum wells formed on an upper surface of the n-type region. In other embodiments, the absorber region comprises a “W”-structured quantum well situated between two barrier layers, the “W”-structured quantum well comprising a hole quantum well sandwiched between two electron quantum wells. In other embodiments, the RCID includes a thin absorber region and an nBn or pBp active core within a resonant cavity. In some embodiments, the RCID is configured to absorb incident light propagating in the direction of the epitaxial growth of the RCID structure, while in other embodiments, it absorbs light propagating in the epitaxial plane of the structure. | 2019-08-01 |
20190237596 | In-Plane Resonant-Cavity Infrared Photodetectors with Fully-Depleted Absorbers - Resonant-cavity infrared photodetector (RCID) devices that include a thin absorber layer contained entirely within the resonant cavity. In some embodiments, the absorber is a single type-II InAs—GaSb interface situated between an AlSb/InAs superlattice n-type region and a p-type AlSb/GaSb region. In other embodiments, the absorber region comprises quantum wells formed on an upper surface of the n-type region. In other embodiments, the absorber region comprises a “W”-structured quantum well situated between two barrier layers, the “W”-structured quantum well comprising a hole quantum well sandwiched between two electron quantum wells. In other embodiments, the RCID includes a thin absorber region and an nBn or pBp active core within a resonant cavity. In some embodiments, the RCID is configured to absorb incident light propagating in the direction of the epitaxial growth of the RCID structure, while in other embodiments, it absorbs light propagating in the epitaxial plane of the structure. | 2019-08-01 |
20190237597 | THREE-DIMENSIONAL CONDUCTIVE ELECTRODE FOR SOLAR CELL - A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack. | 2019-08-01 |
20190237598 | SOLAR CELL - Provided is a solar cell comprising a first electrode; a second electrode; a perovskite photoabsorber layer located between the first electrode and the second electrode; a first semiconductor layer located between the first electrode and the photoabsorber layer; and a second semiconductor layer located between the second electrode and the photoabsorber layer. At least one electrode selected from the group consisting of the first electrode and the second electrode is light-transmissive. The first semiconductor layer contains Li. The second semiconductor layer contains LiN(SO | 2019-08-01 |
20190237599 | METHOD FOR PRODUCING ELECTRICAL CONTACTS ON A COMPONENT - The present invention relates to a method for producing one or more electrical contacts on a component, comprising the following steps:—providing a component which has a front and a rear, an outer layer of a transparent, electrically conductive oxide (TCO) or a self-passivating metal or semiconductor being present on the front and/or rear;—applying a structured, electrically conductive seed layer, the application of the seed layer taking place non-galvanically;—galvanically depositing at least one metal on the seed layer. | 2019-08-01 |
20190237600 | FULL-LASER SCRIBING METHOD FOR FLEXIBLE STAINLESS STEEL SUBSTRATE SOLAR CELL MODULE - The invention relates a full-laser scribing method for a flexible stainless steel substrate solar cell module, comprising: preparing an insulating layer and a molybdenum layer on a stainless steel substrate in sequence; using a laser I to scribe the prepared insulating layer and molybdenum layer to form a first scribed line (P1); preparing the following film layers in sequence on the molybdenum layer in which P1 has been scribed: a CIGS layer, a cadmium sulfide layer and an intrinsic zinc oxide layer; using a laser II to make scribe and thus form a second scribed line (P2), wherein the second scribed line P2 is parallel with the first scribed line P1; and preparing an aluminum-doped zinc oxide layer on the intrinsic zinc oxide layer in which P2 has been scribed, and using a laser III to make scribe and thus form a third scribed line (P3), wherein the third scribed line P3 is parallel with the first scribed line P1. The invention may avoid disadvantages caused by the screen printing, such as large dead zone, expensive screen printing paste and frequent replacement of screens for screen printing, thereby improve efficiency and stability of the module and save cost and increase production efficiency. | 2019-08-01 |
20190237601 | DEVICE, SOLAR CELL MODULE, MAKING METHOD AND INSTALLING METHOD - The present disclosure relates to a device, a solar cell module, a method of making a flexible sunlight redirecting film, a method of installing a solar cell module at an installation site, and a method of making a solar cell module. A sunlight redirecting film comprises a first layer having a first major surface and a second major surface that includes a plurality of structures. A largest triangle that can be inscribed in a cross section of each structure taken perpendicular to the first surface has first and second facets extending away from the first major surface to a peak of the triangle. A length of the first facet differs from a length of the second facet by at least 10%. The sunlight redirecting film also comprises a second layer disposed on and conforming to the structures. The second layer is configured to redirect sunlight impinging on the second layer. | 2019-08-01 |
20190237602 | DELAMINATION-PREVENTING COMPOSITE SEALING MATERIAL AND SOLAR CELL MODULE - In a super straight solar cell module structure, a solar cell module that remains delamination-free over an ultralong period of time can be provided by using a composite filling material obtained by sandwiching, by an EVA sealing material with a melting point of 55° C. or higher and 75° C. or lower, a cyclic olefin-based copolymer film having a glass transition temperature ranging from 70° C. to 80° C. and a thickness ranging from 20 μm to 50 μm. | 2019-08-01 |
20190237603 | LIGHT REDIRECTING FILMS AND ITS MAKING METHOD AND PHOTOVOLTAIC MODULES - The present disclosure relates to a flexible sunlight redirecting film, a photovoltaic module, a light redirecting film and a method of making a sunlight redirecting film. The flexible sunlight redirecting film includes a plurality of microstructures that extend away from a plane of the film. A second layer is disposed on and conforms to the microstructures of the first layer. The second layer is configured to redirect sunlight impinging on the second layer. A third layer comprising a thermally activated adhesive is disposed over the second layer. | 2019-08-01 |
20190237604 | OPTIMIZED INTERFACE FOR PHOTOVOLTAIC MODULE AND SYSTEM EFFICIENCY - A photovoltaic module with an improved interface includes a plurality of strings, each string comprising a plurality of PV strips coupled in series, each strip of the plurality of strips including first and second end strips disposed at opposing ends of the string and at least one middle strip disposed between the first and second end strips. Each strip has an aperture side, a back side, a single backside bus disposed on the back side of the strip, a plurality of conductive fingers disposed on the aperture side, a layer of electrically conductive adhesive that attaches the backside bus of every middle strip to the aperture side of an adjacent strip. The aperture sides of the plurality of strips are free from metallic materials between the plurality of conductive fingers, such that no bus bars are present on the aperture sides of the plurality of strips. | 2019-08-01 |
20190237605 | CONCENTRATOR PHOTOVOLTAIC MODULE, CONCENTRATOR PHOTOVOLTAIC DEVICE, AND HYDROGEN GENERATING SYSTEM - A concentrator photovoltaic module according to one embodiment of the present disclosure includes: a case; a substrate disposed on a bottom surface of the case and having a plurality of stacked wiring layers; and concentrator photovoltaic elements disposed on the substrate and connected to the wiring layers. The concentrator photovoltaic elements connected to different wiring layers are connected to each other in parallel. According to the concentrator photovoltaic module according to the one embodiment of the present disclosure, output voltage can be decreased. | 2019-08-01 |
20190237606 | CONCENTRATING SOLAR POWER GENERATION MODULE, CONCENTRATING SOLAR POWER GENERATION PANEL, AND CONCENTRATING SOLAR POWER GENERATION DEVICE - A concentrator photovoltaic module including: a concentrating portion formed by arranging a plurality of lens elements each configured to concentrate sunlight; and a housing configured to accommodate a plurality of power generating elements disposed at positions respectively corresponding to the lens elements, wherein the housing includes: a frame body formed from resin; and a bottom plate formed from metal, the bottom plate being mounted to the frame body and having the power generating elements mounted thereto, and the frame body includes: a frame body portion forming an outer frame; and a liner portion extending along an upper surface of the bottom plate at an inner side of the frame body portion, the liner portion having both end portions thereof formed integrally with the frame body portion. | 2019-08-01 |
20190237607 | THIN-FILM SOLAR CELL - A thin-film solar cell is disclosed. The thin-film solar cell comprises a substrate on which a first conductive layer, a first alkaline element layer, a light absorption layer, a second alkaline element layer and a transparent conductive layer are sequentially disposed. According to the thin-film solar cell of the present disclosure, by disposing the second alkaline element layer, an alkali metal element in the second alkaline element layer reacts with elements in the light absorption layer to form a film layer containing the alkali metal element, thereby changing the composition of the surface of the light absorption layer, and further changing the electronic structure of the light absorption layer by ion exchange, reducing the surface recombination of charge carriers between the layers, so that an open-circuit voltage of the cell is increased in the post-preparation processing, thereby improving the photoelectric conversion efficiency of the cell. | 2019-08-01 |
20190237608 | SOLAR CELL AND METHOD OF MANUFACTURING SOLAR CELL - A solar cell includes a photoelectric converter having a p-type surface and an n-type surface on a principal surface, a p-side conductor, a p-side Sn layer, an n-side conductor, an n-side Sn layer, a p-side seed layer between the p-type surface and p-side conductor, an n-side seed layer between the n-type surface and n-side conductor, a p-side metal layer covering the p-side seed layer and including metal different from metal of the p-side seed layer, and an n-side metal layer covering the n-side seed layer and including metal different from metal of the n-side seed layer. The diffusion coefficient of copper with respect to the p-side metal layer is less than the diffusion coefficient of copper with respect to a p-side Sn layer. The diffusion coefficient of copper with respect to the n-side metal layer is less than the diffusion coefficient of copper with respect to an n-side Sn layer. | 2019-08-01 |
20190237609 | Controlling Detection Time in Photodetectors - Example embodiments relate to controlling detection time in photodetectors. An example embodiment includes a device. The device includes a substrate. The device also includes a photodetector coupled to the substrate. The photodetector is arranged to detect light emitted from a light source that irradiates a top surface of the device. A depth of the substrate is at most 100 times a diffusion length of a minority carrier within the substrate so as to mitigate dark current arising from minority carriers photoexcited in the substrate based on the light emitted from the light source. | 2019-08-01 |
20190237610 | DIRECTIONAL PHOTODETECTOR AND OPTICAL SENSOR ARRANGEMENT - A directional photodetector comprises a photosensitive element and a light selector. The photosensitive element comprises a single-photon avalanche diode, SPAD, or an array of SPADs or SPAD array. The light selector is arranged on or above the photosensitive element, in particular on or above an active surface of the photosensitive element. The light selector is configured to restrict a field of view of the photosensitive element at least for light with a wavelength within a specified wavelength range. The light selector is configured to restrict the field of view by predominantly passing light with a direction of incidence within a range of passing directions of the light selector. | 2019-08-01 |
20190237611 | UNIT PIXEL OF IMAGE SENSOR AND LIGHT-RECEIVING ELEMENT THEREOF - Provided are a light-receiving element which has more capability of detecting wavelengths than that of existing silicon light-receiving elements and a unit pixel of an image sensor by using it. The light-receiving element includes: a light-receiving unit which is floated or connected to external voltage and absorbs light; an oxide film which is formed to come in contact with a side of the light-receiving unit; a source and a drain which stand off the light-receiving unit with the oxide film in between and face each other; a channel which is formed between the source and the drain and forms an electric current between the source and the drain; and a wavelength expanding layer which is formed in at least one among the light-receiving unit, the oxide film and the channel and forms a plurality of local energy levels by using strained silicon. | 2019-08-01 |
20190237612 | WAFER LEVEL SENSING MODULE AND MANUFACTURING METHOD THEREOF - The instant disclosure provides a wafer level sensing module and a manufacturing method thereof. The wafer level sensing module includes a chip substrate, a proximity sensing unit, and an ambient light sensing unit. The proximity sensing unit is disposed on the chip substrate and includes an emitter, a first receptor, and a shielding assembly. The shielding assembly includes a first shielding member, a second shielding member, a third shielding member, a first lens, and a second lens. The ambient light sensing unit is disposed on the chip substrate and is separate from the proximity sensing unit. The ambient light sensing unit includes a second receptor and a transparent shielding plate. The first receptor and the second receptor are formed on the chip substrate and exposed from a top surface of the chip substrate, and the transparent shielding plate corresponds in position to the second receptor. | 2019-08-01 |
20190237613 | FILM COATING APPARATUS - The present disclosure provides a film coating apparatus. In the film coating apparatus, by disposing the position sensor outside the coating chamber to detect the position of the coating carrier through the through hole and the light transmitting window of the sensor detection path, the position sensor may not directly contact the coating carrier, so that the coating carrier may not be damaged by the position sensor, and the position sensor may not be influenced by the extreme environment in the coating chamber. Furthermore, by disposing the protection device in the coating chamber to protect the through hole and the light transmitting window from covering by the coating material, the normal working of the position sensor can be ensured. The film coating apparatus of the present disclosure has simple structure and low cost, and is easy to use. | 2019-08-01 |
20190237614 | SILANIZED ITO ELECTRODE WITH ITO NANOPARTICLES FOR AQUEOUS SULFIDE DETECTION - A silanized ITO electrode modified with ITO nanoparticles is described. ITO nanoparticles of cubic and semispherical shapes are immobilized on a silanized ITO film. The electrode may be used in an electrolytic cell to detect aqueous sulfide with a 0.5-1.4 μM limit of detection. The electrode shows high specificity towards aqueous sulfide and a high reproducibility in measurement. | 2019-08-01 |
20190237615 | Semiconductor Body - A semiconductor body is disclosed. In an embodiment a semiconductor body includes an n-doped region comprising a first layer sequence comprising pairs of alternating layers, wherein a first layer and a second layer of each pair differ in their doping concentration, and wherein the first and second layers of each pair have the same material composition except for their doping and a second layer sequence comprising pairs of alternating layers, wherein a first layer and a second layer of each pair differ in their material composition, an active region, wherein the second layer sequence is disposed between the first layer sequence and the active region and a p-doped region, wherein the active region is disposed between the n-doped region and the p-doped region. | 2019-08-01 |
20190237616 | DISLOCATION FILTER FOR SEMICONDUCTOR DEVICES - A dislocation filter for a semiconductor device has a buffer layer comprising a short-period superlattice (SPSL) layer. The SPSL layer has first sub-layers of a first material that alternate with second sub-layers of a second material, the first material and the second material being group III-N binary materials that are different from each other. Each of the first sub-layers and each of the second sub-layers has a sub-layer thickness less than or equal to 12 monolayers. The buffer layer also includes a third layer of a third material, the third material being a group III-N material. The SPSL forms a sandwich structure with the third layer. The buffer layer bends dislocations away from a growth direction of the buffer layer. | 2019-08-01 |
20190237617 | OPTOELECTRONIC COMPONENT - An optoelectronic component includes an active layer having a multiple quantum well structure, wherein the multiple quantum well structure includes quantum well layers, including Al | 2019-08-01 |
20190237618 | DISPLAY DEVICE AND ELECTRONICS APPARATUS - A display device and an electronics apparatus are provided. The display device comprises: a display substrate; and arrays of light-emitting elements on the display substrate, wherein the light-emitting elements include at least two types of electroluminescent quantum-dot LED, photoluminescent quantum-dot LED and micro-LED, wherein at least one type of the light-emitting elements is an electroluminescent quantum-dot LED, or at least two types of the light-emitting elements are micro-LED. | 2019-08-01 |
20190237619 | HIGH EFFICIENCY VISIBLE AND ULTRAVIOLET NANOWIRE EMITTERS - GaN-based nanowire heterostructures have been intensively studied for applications in light emitting diodes (LEDs), lasers, solar cells and solar fuel devices. Surface charge properties play a dominant role on the device performance and have been addressed within the prior art by use of a relatively thick large bandgap AlGaN shell covering the surfaces of axial InGaN nanowire LED heterostructures has been explored and shown substantial promise in reducing surface recombination leading to improved carrier injection efficiency and output power. However, these lead to increased complexity in device design, growth and fabrication processes thereby reducing yield/performance and increasing costs for devices. Accordingly, there are taught self-organising InGaN/AlGaN core-shell quaternary nanowire heterostructures wherein the In-rich core and Al-rich shell spontaneously form during the growth process. | 2019-08-01 |
20190237620 | ULTRA-WIDEBAND, FREE SPACE OPTICAL COMMUNICATION APPARATUS - Devices, systems, and methods for providing wireless personal area networks (PANs) and local area networks (LANs) using visible and near-visible optical spectrum. Various constructions and material selections are provided herein. According to one embodiment, a free space optical (FSO) communication apparatus includes a digital data port, an array of light-emitting diodes (LEDs) each configured to have a transient response time of less than 500 picoseconds (ps), and current drive circuitry coupled between the digital data port and the array of LEDs. | 2019-08-01 |
20190237621 | ULTRATHIN SOLID STATE DIES AND METHODS OF MANUFACTURING THE SAME - Various embodiments of SST dies and solid state lighting (“SSL”) devices with SST dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a SST die includes a substrate material, a first semiconductor material and a second semiconductor material on the substrate material, an active region between the first semiconductor material and the second semiconductor material, and a support structure defined by the substrate material. In some embodiments, the support structure has an opening that is vertically aligned with the active region. | 2019-08-01 |
20190237622 | HIGH LIGHT EXTRACTION EFFICIENCY (LEE) LIGHT EMITTING DIODE (LED) - A light-emitting diode, comprising a substrate that has a first surface and an opposing second surface. A reflection layer is disposed on the first surface of the substrate and a light-emitting diode structure is arranged on the second surface of the substrate. The light-emitting diode structure includes a first semiconducting layer, an active layer and a second semiconducting layer disposed consecutively on the second surface. A plurality of protruding asymmetric micro-structured elements define at least a part of the second surface of the substrate such that at least a portion of a surface of each micro-structured element is disposed at an obtuse angle to the first surface of the substrate when measured from within the respective micro-structured element. The first semiconducting layer and the second semiconducting layer respectively have a first electrode and a second electrode. | 2019-08-01 |
20190237623 | SEMICONDUCTOR DEVICE - An embodiment includes a semiconductor device including a semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first insulation layer disposed on the semiconductor structure; a first electrode disposed on the first conductive semiconductor layer; a second electrode disposed on the second conductive semiconductor layer; a first cover electrode disposed on the first electrode; a second cover electrode disposed on the second electrode; and a second insulation layer extending from an upper surface of the first cover electrode to an upper surface of the second cover electrode. The semiconductor structure includes a first surface extending from an upper surface of the first conductive semiconductor layer where the first electrode is disposed to a side surface of the active layer and an upper surface of the second conductive semiconductor where the second electrode is disposed. The first insulation layer is disposed on the first surface to be spaced apart from the first electrode. The first insulation layer is disposed on the first surface to overlap with the first cover electrode in a first direction perpendicular to the upper surface of the first conductive semiconductor layer. | 2019-08-01 |
20190237624 | LIGHT-EMITTING DEVICES - A light-emitting device comprises a semiconductor layer sequence comprising a first semiconductor layer having a first electrical conductivity, a second semiconductor layer having a second electrical conductivity, and an active layer interposed between the first semiconductor layer and the second semiconductor layer; a plurality of beveled trenches formed in the semiconductor layer sequence; a plurality of protruding structures respectively formed in the plurality of beveled trenches; a dielectric layer formed on the second semiconductor layer and an inner sidewall of the plurality of beveled trenches; a reflecting layer interposed between the semiconductor layer sequence and the dielectric layer; and a metal layer formed along the inner sidewall of the plurality of beveled trenches, wherein the dielectric layer, the reflecting layer and the metal layer are overlapping, the plurality of protruding structures and the reflecting layer are not overlapping. | 2019-08-01 |
20190237625 | SOLID STATE LIGHTING DEVICES WITH ACCESSIBLE ELECTRODES AND METHODS OF MANUFACTURING - Various embodiments of light emitting dies and solid state lighting (“SSL”) devices with light emitting dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a light emitting die includes an SSL structure configured to emit light in response to an applied electrical voltage, a first electrode carried by the SSL structure, and a second electrode spaced apart from the first electrode of the SSL structure. The first and second electrode are configured to receive the applied electrical voltage. Both the first and second electrodes are accessible from the same side of the SSL structure via wirebonding. | 2019-08-01 |
20190237626 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes: a light emitting structure having a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer stacked therein along a stacking direction, a transparent electrode layer on the second conductivity-type semiconductor layer and divided into first and second regions, the transparent electrode layer having a plurality of first through-holes disposed in the first region, an insulating reflective layer covering the transparent electrode layer and having a plurality of second through-holes in a region overlapping the second region along the stacking direction, and a reflective electrode layer on the region of the insulating reflective layer and connected to the transparent electrode layer through the plurality of second through-holes. | 2019-08-01 |
20190237627 | LIGHT EMITTING DIODE STRUCTURE - A light emitting diode structure including a substrate, a semiconductor epitaxial structure, a first insulating layer, a first reflective layer, a second reflective layer, a second insulating layer and at least one electrode. The substrate has a tilt surface. The semiconductor epitaxial structure at least exposes the tilt surface. The first insulating layer exposes a portion of the semiconductor epitaxial structure. The first reflective layer is at least partially disposed on the portion of the semiconductor epitaxial structure and electrically connected to the semiconductor epitaxial structure. The second reflective layer is disposed on the first reflective layer and the first insulating layer, and covers at least the portion of the tilt surface. The second insulating layer is disposed on the second reflective layer. The electrode is disposed on the second reflective layer and electrically connected to the first reflective layer and the semiconductor epitaxial structure. | 2019-08-01 |
20190237628 | LIGHT-EMITTING DEVICE - A light-emitting device includes: a light-emitting stack formed on a first conductivity type contact layer and including an active layer and a second conductivity type semiconductor layer on the active layer; a first trench dividing the light-emitting stack into a first portion and a second portion, wherein the first trench includes a bottom exposing a top surface of the first conductivity type contact layer; a non-conductive material layer formed in the first trench and being a film conformal to a profile of the first trench; a connecting layer formed in the first trench and electrically connecting the first and the second portions of the light-emitting stack, wherein the connecting layer is a film conformal to a profile of the non-conductive material layer; and a first electrode formed on the first conductivity type contact layer and electrically connected to the first conductivity type semiconductor layer. | 2019-08-01 |
20190237629 | OPTICALLY TRANSPARENT ADHESION LAYER TO CONNECT NOBLE METALS TO OXIDES - A reflective layer for use in lighting devices and methods of forming the reflective layer are provided. The reflective layer may include a dielectric layer including one or more insulating materials. An intermediate layer may be formed on the dielectric layer. The intermediate layer may include one or more materials having a higher enthalpy of reaction than the one or more insulating materials. Because of the higher enthalpy of reaction, atoms of the one or more materials in the intermediate layer may form bonds with atoms of the one or more insulating materials. A metal layer may be formed on the intermediate layer to reflect light emitted from an active region of a light emitting diode (LED). | 2019-08-01 |
20190237630 | REFLECTIVE LAYERS FOR LIGHT-EMITTING DIODES - A light-emitting diode (LED) chip with reflective layers having high reflectivity. The LED chip may include an active LED structure including an active layer between an n-type layer and a p-type layer. A first reflective layer is adjacent the active LED structure and comprises a plurality of dielectric layers with varying optical thicknesses. The plurality of dielectric layers may include a plurality of first dielectric layers and a plurality of second dielectric layers of varying thicknesses and compositions. The LED chip may further include a second reflective layer that includes an electrically conductive path through the first reflective layer. | 2019-08-01 |
20190237631 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light-emitting device includes a substrate on which a semiconductor light-emitting element is mounted, the substrate having a first coefficient of thermal expansion, a lid member that covers the semiconductor light-emitting element, the lid member having a second coefficient of thermal expansion smaller than the first coefficient of thermal expansion, and a joining member that joins the lid member to the substrate to seal the semiconductor light-emitting element. The joining member includes a eutectic alloy solder. | 2019-08-01 |
20190237632 | FILLING MATERIAL, RESIN COMPOSITION, PACKAGE, AND LIGHT-EMITTING DEVICE - A filling material for a resin composition includes a base material and a coating material coating at least a portion of a surface of a particle of the base material. The base material comprises a first inorganic compound containing a Group II element. The coating material comprises a second inorganic compound containing the Group II element and is different from the first inorganic compound. A method of manufacturing the filling material is provided. A resin composition comprising the filling material, a package, a light-emitting device, and methods of manufacturing them are also provided. | 2019-08-01 |
20190237633 | LIGHT-EMITTING DIES INCORPORATING WAVELENGTH-CONVERSION MATERIALS AND RELATED METHODS - In accordance with certain embodiments, electronic devices feature a polymeric binder, a frame defining an aperture therethrough, and a semiconductor die (e.g., a light-emitting or light-detecting element) suspended in the binder and within the aperture of the frame. | 2019-08-01 |
20190237634 | LIGHT EMITTING DEVICE - A light emitting device includes a light emitting element including a first surface; a light guide member covering at least a part of a lateral surface of the light emitting element; a first wavelength conversion member covering the first surface and including a first wavelength conversion particles; and a reflective member being in contact with the light emitting element. The first wavelength conversion member has a thickness of 60 μm or more and 120 μm or less. The first wavelength conversion particles have an average particle size of 4 μm or longer and 12 μm or smaller; the first wavelength conversion particles have a central particle size of 4 μm or longer and 12 μm or smaller. A weight ratio of the first wavelength conversion particles is 60% by weight or more and 75% by weight or less with respect to the total weight of the first wavelength conversion member. | 2019-08-01 |
20190237635 | LIGHT EMITTING DEVICE AND LIGHT SOURCE - A light emitting device includes at least one first light emitting element to emit a first light and at least one fluorescent material to convert the first light to a second light. The second light has chromaticity existing in an enclosed area in a CIE 1931 chromaticity diagram. The CIE 1931 chromaticity diagram has a curved boundary indicating a spectral locus. The enclosed area is enclosed with a first straight line, a second straight line, a third straight line, and a curved line. The first straight line connects a first point at which x is equal to 0.643 and y is equal to 0.334 and a second point at which x is equal to 0.643 and y is equal to 0.334. The second straight line connects the second point and a third point at which x is equal to 0.576 and y is equal to 0.291. The third straight line connects the third point and a fourth point at which x is equal to 0.737 and y is equal to 263. The curved line connects the fourth point and the first point. The curved line is a part of the curved boundary. | 2019-08-01 |
20190237636 | LIGHT EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF - A light-emitting diode package includes a light-emitting diode chip disposed in a housing, a first phosphor configured to emit green light, and a second phosphor configured to emit red light. White light is configured to be formed by a synthesis of light emitted from the light-emitting diode chip, the first phosphor, and the second phosphor. The second phosphor has a chemical formula of A | 2019-08-01 |
20190237637 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - The application discloses a light-emitting device including a carrier, a light-emitting element and a connecting structure. The carrier includes a first connecting portion and a first necking portion extended from the first connecting portion. The first connecting portion has a first width, and the first necking portion has a second width. The second width is less than the first width. The light-emitting element includes a first light-emitting layer being able to emit a first light and a first contacting electrode formed under the first light-emitting layer. The first contacting electrode is corresponded to the first connecting portion. The connecting structure includes a first electrical connecting portion and a protecting portion surrounding the first electrical connecting portion. The first electrical connecting portion is electrically connected to the first connecting portion and the first contacting electrode. The first connecting portion substantially is located within a range surrounded by the protecting portion. | 2019-08-01 |
20190237638 | LIGHT EMITTING DIODES, COMPONENTS AND RELATED METHODS - Light emitting diodes, components, and related methods, with improved performance over existing light emitting diodes. In some embodiments, light emitter devices included herein include a submount, a light emitter, a light affecting material, and a wavelength conversion component. Wavelength conversion components provided herein include a transparent substrate having an upper surface and a lower surface, and a phosphor compound disposed on the upper surface or lower surface, wherein the wavelength conversion component is configured to alter a wavelength of a light emitted from a light source when positioned proximate to the light source. | 2019-08-01 |
20190237639 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device includes: at least one light-emitting element; a first light-transmissive member covering the light-emitting element; a second light-transmissive member covering the first light-transmissive member; and a light-diffusing member in the second light-transmissive member. The light-diffusing member comprises hollow particles. The second light-transmissive member has a bottom surface having irregularities due to presence of the light-diffusing member. | 2019-08-01 |
20190237640 | METHOD AND APPARATUS FOR GENERATING WHITE LIGHT FROM SOLID STATE LIGHT EMITTING DEVICES - An optical device capable of generating warm light using an array of phosphor islands situated over a phosphor layer is disclosed. The device includes a solid state light emitter, a phosphor layer, and phosphor islands. The solid state light emitter, in an aspect, is a light emitting diode (“LED”) capable of converting electrical energy to optical light. The phosphor layer is disposed over the solid state light emitter for generating luminous cool light in response to the optical light. Multiple phosphor islands are disposed on the phosphor layer for converting cool light to warm light, wherein the phosphor islands are evenly distributed over the phosphor layer. | 2019-08-01 |
20190237641 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device | 2019-08-01 |
20190237642 | QUANTUM DOT (QD) LEDS, BACKLIGHT MODULES AND DISPLAYS - The present disclosure relates to a quantum dot (QD) light emitting diode (LED), a backlight module, and a display. The QD LED includes a support; an LED chip; at least one optical fiber layer; and a packaging layer; wherein: the LED chip is fixed and connected with the support; the at least one optical fiber layer is disposed on the LED chip, and the at least one optical fiber layer includes optical fibers encapsulated with QDs; and the packaging layer encapsulates the at least one optical fiber layer and the chip on the support. | 2019-08-01 |
20190237643 | LIGHT SOURCE AND CORRESPONDING LUMINOUS MOTOR-VEHICLE MODULE - A luminous module includes a light source and an optical part for shaping the light rays emitted by the light source. The light source is a semiconductor source that includes a plurality of electroluminescent units of submillimetre dimensions, and at least one positioning outgrowth configured to participate in the positioning of the light source on an optical part. The light source is positioned with respect to the optical part by interaction of the at least one positioning outgrowth with a corresponding receiving orifice formed in the optical part. | 2019-08-01 |
20190237644 | LIGHT EMITTING DEVICE WITH MULTI-LAYER ISOLATION STRUCTURE - A display device includes a substrate, a multi-layer isolation structure, and a plurality of light emitting device sets is provided. The multi-layer isolation structure is formed on the substrate. The multi-layer isolation structure includes a first isolation structure which is in contact with the substrate, and a second isolation structure which is above the first isolation structure. The first isolation structure and the second isolation structure have different reflectances. The plurality of light emitting device sets are present on the substrate. Each of the light emitting device sets includes at least one light emitting device, and the light emitting device sets are spaced apart from each other at least by the multi-layer isolation structure. | 2019-08-01 |
20190237645 | CONVERSION MODULE WITH LEAD FRAME - A conversion module for a conversion lamp includes a lead frame; and a conversion element received in the lead frame. | 2019-08-01 |
20190237646 | SUPERLATTICE THERMOELECTRIC MATERIAL AND THERMOELECTRIC DEVICE USING SAME - The present disclosure relates to a thermoelectric material, and more specifically to a superlattice thermoelectric material and a thermoelectric device using the same. The superlattice thermoelectric material has a composition of a following Chemical Formula 1: | 2019-08-01 |
20190237647 | METHOD OF MANUFACTURING THERMOELECTRIC MODULE USING INK FORMULATIONS - A method of manufacturing a conductive layer includes the step of dissolving an organic semiconductor polymer in a first solvent, the first solvent being an aromatic or heterocyclic compound comprising one or more electron-rich carbon atom(s) and/or heteroatom(s). The method also includes dissolving a dopant in a second solvent, the second solvent being a polar solvent. The method also includes mixing the solutions of the organic semiconductor polymer and the dopant to form a dispersion comprising doped conductive polymer particles suspended in the solvent blend. The method also includes depositing the dispersion by a solution deposition technique to form a conductive layer. The solution deposition technique is preferably an inkjet printing, dispense printing or drop casting method. The dispersion provides a stable ink composition for the manufacturing of thick and uniform layers with excellent conductivity and thermopower, and allows simple fabrication of thermoelectric legs with enhanced performance. | 2019-08-01 |
20190237648 | CONTROLLING A STATE OF A QUBIT ASSEMBLY VIA TUNABLE COUPLING - Methods and apparatuses are provided for controlling the state of a qubit. A qubit apparatus includes a load, a qubit, and a compound Josephson junction coupler coupling the qubit to the load. A coupling controller controls the coupling strength of the compound Josephson junction coupler such that a coupling between the qubit and the load is a first value when a reset of the qubit is desired and a second value during operation of the qubit. | 2019-08-01 |
20190237649 | LOW LOSS ARCHITECTURE FOR SUPERCONDUCTING QUBIT CIRCUITS - A technique relates to a structure. A first surface includes an inductive element of a resonator. A second surface includes a first portion of a capacitive element of the resonator and at least one qubit. A second portion of the capacitive element of the resonator is on the first surface. | 2019-08-01 |
20190237650 | Reel-to-Reel Exfoliation and Processing of Second Generation Superconductors - The substrate and buffer layers, of either one-sided or two-sided superconducting tape, are separated from the YCBO layer(s) of the tape by a combined action of radiative or inductive heat and mechanical force via a reel-to-reel manufacturing process. The exfoliation process may also utilize an air blade(s) to facilitate the separation of the layers of the tape. | 2019-08-01 |
20190237651 | EAP ACTUATOR AND DRIVE METHOD - An electroactive polymer actuator comprises an electroactive polymer structure and a driver for providing an actuation drive signal. In one aspect a first drive level is used to charge the electroactive polymer structure from a non-actuated state to an actuated state. When or after the electroactive polymer structure reaches the actuated state, a lower second drive level is used to hold the electroactive polymer structure at the actuated state. This temporary overdrive scheme improves the speed response without damaging the electroactive polymer structure. In another aspect, a driving method makes use of several different level segments over time which compensate for the delayed actuation response of the EAP actuator. | 2019-08-01 |
20190237652 | MULTI-LAYER PIEZOELECTRIC CERAMIC COMPONENT AND PIEZOELECTRIC DEVICE - A multi-layer piezoelectric ceramic component includes: a piezoelectric ceramic body having a cuboid shape, having upper and lower surfaces facing in a thickness direction, first and second end surfaces facing in a length direction, and a pair of side surfaces facing in a width direction, and including first and second regions; first internal electrodes in the first region; second internal electrodes in the second region; third internal electrodes in the first and second regions; a first terminal electrode formed on the first end surface and electrically connected to the first internal electrodes; a second terminal electrode formed on the first end surface and electrically connected to the second internal electrodes; a third terminal electrode formed on the second end surface and electrically connected to the third internal electrodes; a first surface electrode formed on the upper surface; and a second surface electrode formed on the lower surface. | 2019-08-01 |
20190237653 | MULTI-LAYER PIEZOELECTRIC CERAMIC COMPONENT AND PIEZOELECTRIC DEVICE - A multi-layer piezoelectric ceramic component includes: a piezoelectric ceramic body having a cuboid shape, having upper and lower surfaces facing in a thickness direction, first and second end surfaces facing in a length direction, and a pair of side surfaces facing in a width direction, and including first and second regions; first internal electrodes in the first region; second internal electrodes in the second region; third internal electrodes in the first and second regions; a first terminal electrode formed on the first end surface and electrically connected to the first internal electrodes; a second terminal electrode formed on the first end surface and electrically connected to the second internal electrodes; and a third terminal electrode formed on the second end surface and electrically connected to the third internal electrodes, the first, second, and third internal electrodes each having a width equal to a distance between the pair of side surfaces. | 2019-08-01 |
20190237654 | MEMS Heater or Emitter Structure for Fast Heating and Cooling Cycles - According to various embodiments, a MEMS device includes a substrate, an electrically movable heating element having a first node coupled to a first terminal of a first voltage source and the second node coupled to a reference voltage source, a first anchor anchoring the first node and a second anchor anchoring the second node of the electrically movable heating element to the substrate, and a cavity between the first anchor and the second anchor and between the electrically movable heating element and the substrate. | 2019-08-01 |
20190237655 | ACTUATOR DEVICE AND LIQUID EJECTION APPARATUS - An actuator device includes: an actuator including piezoelectric elements arranged in a first direction and first contacts arranged in the first direction; a protector including a first wall opposed to the piezoelectric elements and a second wall coupled to the first wall and joined to a region of the actuator at which the first contacts are disposed; first connection terminals disposed on the first; and first through electrodes formed in the second wall to bring the first contacts and the first connection terminals into conduction with each other. A distance between two of the first through electrodes which respectively correspond to two of the piezoelectric elements which are adjacent to each other in the first direction is greater than a distance in the first direction between the two of the piezoelectric elements which are adjacent to each other in the first direction. | 2019-08-01 |
20190237656 | MULTI-LAYER PIEZOELECTRIC CERAMIC COMPONENT AND PIEZOELECTRIC DEVICE - A multi-layer piezoelectric ceramic component includes: a piezoelectric ceramic body having a cuboid shape having upper and lower surfaces facing in a thickness direction, first and second end surfaces facing in a length direction, and a pair of side surfaces facing in a width direction; first internal electrodes formed in the piezoelectric ceramic body and drawn to the first end surface; second internal electrodes formed in the piezoelectric ceramic body and drawn to the second end surface; a first terminal electrode formed on the first end surface; and a second terminal electrode formed on the second end surface, the first and second internal electrodes each having a width equal to a distance between the pair of side surfaces, at least one of the pair of side surfaces including a groove extending in non-parallel with the length direction. | 2019-08-01 |
20190237657 | METHOD OF PRODUCING A MULTI-LAYER PIEZOELECTRIC CERAMIC COMPONENT, MULTI-LAYER PIEZOELECTRIC CERAMIC COMPONENT, AND PIEZOELECTRIC DEVICE - A method of producing a multi-layer piezoelectric ceramic component includes: laminating ceramic green sheets to form a laminate, each of the ceramic green sheets being made of a piezoelectric ceramic material and including an electrically conductive pattern, the electrically conductive pattern including a base metal, being to be an internal electrode, and being formed on an inner side of an outer edge of the ceramic green sheet; sintering the laminate; and cutting the sintered laminate and causing the internal electrodes to be exposed. | 2019-08-01 |
20190237658 | INTEGRATED CIRCUITS WITH MAGNETIC RANDOM ACCESS MEMORY (MRAM) DEVICES AND METHODS FOR FABRICATING SUCH DEVICES - Integrated circuits with magnetic random access memory (MRAM) devices and methods for fabricating such devices are provided. In an exemplary embodiment, a method for fabricating MRAM bitcells includes determining a desired inter-cell spacing between a first bitcell and a second bitcell and double patterning a semiconductor substrate to form semiconductor fin structures, wherein the semiconductor fin structures are formed in groups with an intra-group pitch between grouped semiconductor fin structures and with the inter-cell spacing between adjacent groups of semiconductor fin structures different from the intra-group pitch. The method further includes forming a first MRAM memory structure over the semiconductor fin structures in the first bitcell and forming a second MRAM memory structure over the semiconductor fin structures in the second bitcell. Also, the method includes forming a first source line for the first bitcell between the first MRAM memory structure and the second MRAM memory structure. | 2019-08-01 |
20190237659 | ANNEALED SEED LAYER FOR MAGNETIC RANDOM ACCESS MEMORY - A semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate. At least one trench line is formed within the substrate. A pad layer is formed in contact with the at least one trench line. A seed layer is formed on and in contact with the pad layer. The seed layer has a Root Mean Square surface roughness equal to or less than 3 Angstroms. A magnetic tunnel junction stack is formed on and in contact with the seed layer. The method includes forming a seed layer on and in contact with a semiconductor structure. The seed layer is annealed and then planarized. A magnetic tunnel junction stack is formed on and in contact with the seed layer after the seed layer has been planarized. | 2019-08-01 |
20190237660 | MAGNETORESISTIVE RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetoresistive random access memory (MRAM) is provided in the present invention, including a conductive plug with a protruding portion extending outwardly on one side and a notched portion concaving inwardly on the other side of the upper edge of conductive plug, and a memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction (MTJ) on the bottom electrode, and a top electrode on the magnetic tunnel junction, wherein the bottom surface of memory cell completely overlaps the top surface of conductive plug. | 2019-08-01 |
20190237661 | Nitride Capping Layer for Spin Torque Transfer (STT)-Magnetoresistive Random Access Memory (MRAM) - A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, a capping layer that is a conductive metal nitride such as MoN contacts an opposite surface of the Hk enhancing layer with respect to the first interface to reduce interdiffusion of oxygen and nitrogen compared with a TiN capping layer and maintain an acceptable resistance×area (RA) product. In other embodiments, the capping layer may comprise an insulating nitride such as AlN that is alloyed with a conductive metal to minimize RA. Furthermore, a metallic buffer layer may be inserted between the capping layer and Hk enhancing layer. As a result, electrical shorts are reduced and the magnetoresistive ratio is increased. | 2019-08-01 |