31st week of 2011 patent applcation highlights part 29 |
Patent application number | Title | Published |
20110188264 | LIGHT SOURCE ASSEMBLY AND RELATED LENS TESTING DEVICE - A lens testing device includes a light source assembly, a pattern plate, and an imaging sensor. The light source assembly includes a transparent base plate, a light guide plate, and a number of illuminants. The light source assembly uses the light guide plate to uniformize a light come from the illuminants and emit the light onto the pattern plate. The imaging sensor is placed beneath the transparent base plate to sense the light passing through the pattern plate and focused by a lens. | 2011-08-04 |
20110188265 | ILLUMINATION DEVICE - The luminance in the front direction is enhanced in an illumination device provided with a light source, a light diffusion means, and a light-collecting means disposed in this order. The light source | 2011-08-04 |
20110188266 | SEMICONDUCTOR LIGHT EMITTING DEVICE, COMPOSITE LIGHT EMITTING DEVICE WITH ARRANGEMENT OF SEMICONDUCTOR LIGHT EMITTING DEVICES, AND PLANAR LIGHT SOURCE USING COMPOSITE LIGHT EMITTING DEVICE - A semiconductor light emitting device includes a recess portion defined by a pair of opposing first side wall portions and a pair of opposing second side wall portions extending between the first side wall portions and shorter than the first side wall portions. Light emitting elements are arranged on the bottom surface of the recess portion in a direction of the first side wall portions. The light emitting elements include a first light emitting element for emitting light of a first color and a second light emitting element for emitting light of a second color different from the first color and placed closest to the second side wall portion among the light emitting elements. A resin portion containing a phosphor for wavelength-converting a part of the light of the second color into a complementary color of the light of the second color is filled into the recess portion. | 2011-08-04 |
20110188267 | SHIFT FULL BRIDGE POWER CONVERTING SYSTEM AND CONTROL METHOD THEREOF - A phase shift full bridge power converting system and a control method has the phase shift full bridge power converting system with a power converter, a controller, a load state detecting module, a switching controller, a switch module, a command generating module, a comparator, and a modulator module. The load state detecting module interfaces with the power converter and the switching controller. The load state detects module detects load parameter data of the power converter and switches a state at an output by using the switching controller. The controller obtains an error value between an output voltage of the comparator and a command voltage and calculates a duty cycle parameter by using the error value. According to the duty cycle parameter, a pulse control signal is generated to be outputted to a drive module for controlling the driving of the power converter. | 2011-08-04 |
20110188268 | SIGNAL STATUS DIAGNOSING DEVICE FOR EXTERNAL CONTROL MEANS TO BE ACTIVATED WHEN FED WITH DRIVING ELECTRIC POWER BY ON/OFF SIGNAL TRANSMITTED THROUGH INSULAIING MEANS - This aims to provide a signal status diagnosing device for an external control means, which is enabled even by a simple constitution to prevent the rise of a production cost due to the increase in a parts count or the complexity of a circuit constitution, and which can perform a signal status diagnosis of an actuator (the external control means) such as an electromagnetic valve, a lamp, a relay or a small-sized DC motor precisely. The signal status diagnosing device comprises a switch circuit connected with an intermediate tap disposed on the primary side of a transformer, for sending a driving electric power to the external control means disposed on the secondary side, in response to an ON/OFF signal of the external control means, and a means connected with the switch circuit and driven by the external control means, for measuring the primary side electric current to flow in a manner to correspond to the electric current to flow to the transformer secondary side. The signal status diagnosing device diagnoses the signal status of the external control means in accordance with the measurement result of the current measuring means. | 2011-08-04 |
20110188269 | SWITCHING POWER-SUPPLY APPARATUS - In a switching power-supply apparatus, a primary-side power converter circuit includes a half bridge system and a synchronous rectifier circuit is provided as a rectifier circuit of a secondary-side power converter circuit. An on time ratio of the on time of a first switching element to the on time of a second switching element is controlled so as to provide an operation mode in which energy is regenerated from the secondary side to the primary side when the load is light. | 2011-08-04 |
20110188270 | CIRCUIT - A circuit comprising a power factor correction stage having a DC input, a ground input, a DC output and a ground output; a capacitor; a diode; and discharge means. A first terminal of the diode is connected to an input of the power factor correction stage, a second terminal of the diode is connected to the first plate of the capacitor; and the second plate of the capacitor is connected to the other input of the PFC stage. The discharge means is connected to the capacitor and is configured to discharge the capacitor such that it contributes to the output of the PFC stage when the level of a signal at the input of the PFC stage falls below a threshold value. | 2011-08-04 |
20110188271 | SWITCHING REGULATOR DEVICE - A switching regulator device including a power conversion transformer for converting an input voltage from a power source at a primary side to a predetermined output voltage and outputting the output voltage to a load circuit connected to a secondary side, a power converter circuit that has a primary-side circuit and a secondary-side circuit insulated from each other, and transmits a load driving control signal input to the primary-side circuit through the secondary-side circuit to the load circuit, and a feedback circuit that performs feedback control on the output voltage on the basis of feedback current generated at the primary side of the power conversion transformer, a part of the feedback current of the feedback circuit being consumed in synchronism with the load driving control signal. | 2011-08-04 |
20110188272 | CIRCUIT FOR DIRECT ENERGY EXTRACTION FROM A CHARGED-PARTICLE BEAM - Provided herein is a fusion energy extraction circuit (FEEC) device having a grid-tied bidirectional converter and a resonant converter. The resonant converter can include an inverse cyclotron converter with two or more or quadruple plates and a plurality of circuit switches. The bidirectional converter can include a three-phase grid-tied converter. The FEEC device is capable of decelerating plasma particle beams, thereby extracting the energy from the deceleration, converting the extracted energy to electric energy, and sending the electric energy to a power grid. | 2011-08-04 |
20110188273 | POWER FACTOR CORRECTION STAGE - A power factor correction stage comprising: an input terminal configured to receive an input signal; an output terminal configured to provide an output signal; a first converter stage and one or more further converter stages, wherein each of the converter stages is connected to the input terminal and the output terminal, and each converter stage comprises a switch; and a controller configured to operate the switches of the converter stages. The controller is configured to operate the switch of the one or more further converter stages at a period of time after operation of the switch of the first converter stage for a current switching cycle, wherein the period of time corresponds to a proportion of the switching frequency for an earlier switching cycle that does not correspond to substantially the period of the earlier switching cycle divided by the number of converter stages. | 2011-08-04 |
20110188274 | FAULT CONDITION PROTECTION - A regulator for a switched mode power supply includes switching regulator logic, a counter and a switching transistor. The switching regulator logic is coupled to receive a feedback signal and to generate a switching signal in response. The feedback signal periodically cycles between a first state and a second state when the power supply operates normally. The counter is coupled to receive the feedback signal and an output of the counter indicates an auto-restart mode of the regulator in response to the feedback signal remaining in the first state for a predetermined count. The switching transistor is turned on and off in response to the switching signal when the output of the counter does not indicate the auto-restart mode and is disabled when the output of the counter indicates the auto-restart mode. | 2011-08-04 |
20110188275 | METHOD FOR STARTING UP DC-DC CONVERTER - Aspects of the invention provide a method for starting up a DC-DC converter by which an output voltage can be prevented from overshooting and body diodes of switching devices can be prevented from reverse recovery. In the start-up method, the phases of gate signals of third and fourth switching devices are gradually shifted relative to the phases of gate signals of first and second switching devices. With increase of the phase shift, a voltage on a primary side of a transformer is also increased, and an output voltage is also increased. | 2011-08-04 |
20110188276 | CIRCUIT ARRANGEMENT HAVING A BOOST CONVERTER, AND INVERTER CIRCUIT HAVING SUCH A CIRCUIT ARRANGEMENT - An inverter circuit contains a first and second DC sources for providing a DC voltage, a common boost converter for boosting the DC voltage, an intermediate circuit capacitor connected between the outputs of the common boost converter, and an inverter for converting the DC voltage provided by the capacitor into an AC voltage. The common boost converter contains a series circuit having a first inductance and a first rectifier element and is connected between an output of the first DC source and one side of the intermediate circuit capacitor as well as a series circuit which includes a second inductance and a second rectifier element and is connected between an output of the second DC source and another side of the intermediate circuit capacitor. The common boost converter further contains a common switching element formed by at least two circuit-breakers which are connected between the first and second DC sources. | 2011-08-04 |
20110188277 | CIRCUIT CONFIGURATION WITH A STEP-UP CONVERTER, AND INVERTER CIRCUIT HAVING SUCH A CIRCUIT CONFIGURATION - An inverter circuit contains a first and second DC sources for providing a DC voltage, a common step-up converter for boosting the DC voltage, an intermediate circuit capacitor connected between the outputs of the common step-up converter, and an inverter for converting the DC voltage provided by the capacitor into an AC voltage. The common step-up converter contains a series circuit having a first inductance and a first rectifier element and is connected between an output of the first DC source and one side of the intermediate circuit capacitor as well as a series circuit which includes a second inductance and a second rectifier element and is connected between an output of the second DC source and another side of the intermediate circuit capacitor. The common step-up converter further contains a common switching element which is connected between the first and second DC sources. | 2011-08-04 |
20110188278 | Electron avalanche drive circuit - Disclosed herein is an electron avalanche drive circuit whereby electron avalanche is produced in a high voltage spark gap exposed to open air or other suitable gaseous medium. The electrochemical process of electron avalanche produces additional current that is delivered to an inductive load. | 2011-08-04 |
20110188279 | POWER CONVERTER - A power converter including a switching element, a switching power module containing a driving circuit for driving the switching element, a smoothing capacitor module for smoothing an input to the switching power module, and a heat sink for cooling the switching power module, wherein the switching power module is mounted on the heat sink, and the smoothing capacitor module is provided on a side surface of the heat sink. | 2011-08-04 |
20110188280 | ELECTRIC POWER CONVERTER - An electric power converter includes a cooler and an electronic circuit. The cooler includes a heat sink, a cooling fan, and a wind tunnel. A plurality of radiator fins are provided on a heat-sink base in the heat sink. The cooling fan is configured to feed cooling air through the plurality of radiator fins. The wind tunnel covers the plurality of radiator fins and the cooling fan. The electronic circuit includes a plurality of rectifiers and a plurality of input terminals. The plurality of rectifiers are provided on a side of the heat-sink base opposite to the plurality of radiator fins and are arranged side by side in a longitudinal direction of the heat-sink base. The plurality of input terminals are connected to the plurality of rectifiers with band-shaped conductors and are provided on a side of the plurality of rectifiers opposite to the heat sink. | 2011-08-04 |
20110188281 | Local bit lines and methods of selecting the same to access memory elements in cross-point arrays - Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements. | 2011-08-04 |
20110188282 | Memory architectures and techniques to enhance throughput for cross-point arrays - Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement memory architectures configured to enhance throughput for cross point arrays including memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes arrays that include memory elements being formed BEOL above a FEOL logic layer within a boundary in a plane parallel to a substrate, and array lines. Further, the integrated circuit includes array line decoders disposed in the logic layer within a region located coextensive with the boundary and between the substrate and the arrays. In some embodiments, the disposition of peripheral circuitry, such as the array line decoders, under the arrays can preserve or optimize die efficiency for throughput enhancement. | 2011-08-04 |
20110188283 | Circuits and techniques to compensate data signals for variations of parameters affecting memory cells in cross-point arrays - Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations that affect the operation of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point array comprising memory elements disposed among word lines and bit lines, where a parameter can affect the operating characteristics of a memory element. The integrated circuit further includes a data signal adjuster configured to modify the operating characteristic to compensate for a deviation from a target value for the operating characteristic based on the parameter. In some embodiments, the memory element, such as a resistive memory element, is configured to generate a data signal having a magnitude substantially at the target value independent of variation in the parameter. | 2011-08-04 |
20110188284 | Circuits and techniques to compensate memory access signals for variations of parameters in multiple layers of memory - Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory. | 2011-08-04 |
20110188285 | PERMANENT SOLID STATE MEMORY - A permanent solid state memory device is disclosed. Recording data in the permanent solid state memory device forms voids in a data layer between a first wire array and a second wire array. Wires of the first wire array extend transversely to wires in the second wire array. The data layer is at least partially conductive such that a voltage applied between a selected first wire in the first wire array and a selected second wire in the second wire array creates a heating current through the data layer at a data point between the first wire and the second wire. The heating current causes a data layer material to melt and recede to form a permanent void. Control elements are operably connected to apply voltages to predetermined combinations of wires to form permanent voids at data points throughout the solid state memory device. | 2011-08-04 |
20110188286 | ELECTROMECHANICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - In a memory device and a method of forming the same, in one embodiment, the memory device comprises a first word line structure on a substrate, the first word line structure extending in a first direction. A bit line is provided over the first word line structure and spaced apart from the first word line by a first gap, the bit line extending in a second direction transverse to the first direction. A second word line structure is provided over the bit line and spaced apart from the bit line by a second gap, the second word line structure extending in the first direction. The bit line is suspended between the first word line structure and the second word line structure such that the bit line deflects to be electrically coupled with a top portion of the first word line structure through the first gap in a first bent position and deflects to be electrically coupled with a bottom portion of the second word line structure through the second gap in a second bent position, and is isolated from the first word line structure and the second word line structure in a rest position. | 2011-08-04 |
20110188287 | High speed FRAM including a deselect circuit - High speed FRAM including a deselect circuit is realized for replacing SRAM, wherein the deselect circuit is connected to a local bit line pair for forcing a middle voltage to storage nodes of ferroelectric capacitors of unselected memory cell while a plate line of the ferroelectric capacitors is forced to the middle voltage, so that the unselected memory cell is not polarized while selected memory cell is polarized by changing the local bit line pair when writing. With the deselect circuit, half of the memory cells are not accessed, which reduces number of sense amps. Furthermore, half of metal routing lines on the memory cells can be used for selecting columns and connecting global power as the convention SRAM configuration, while other half of metal routing lines are used for global bit lines. And various circuits for implementing the memory with the deselect circuit are described. | 2011-08-04 |
20110188288 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREFOR - A memory includes a first conductive-type first diffusion layer on the semiconductor substrate; second conductive-type bodies on the first diffusion layer(s); first conductive-type second diffusion layers on the bodies; first gate dielectric films comprising ferroelectric films and provided on first side surfaces of the bodies; second gate dielectric films comprising ferroelectric films and provided on second side surfaces of the bodies; first gate electrodes on the first gate dielectric film; and second gate electrodes on the second gate dielectric film, wherein the first and the second diffusion layers, the body, the first and the second gate dielectric films, and the first and the second gate electrodes constitute memory cells, and each of the memory cells stores a plural pieces of logical data depending on a polarization state of the first gate dielectric film and on a polarization state of the second gate dielectric film. | 2011-08-04 |
20110188289 | Access signal adjustment circuits and methods for memory cells in a cross-point array - Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array. | 2011-08-04 |
20110188290 | Semiconductor devices including variable resistance materials and methods of operating the same - Semiconductor devices including variable resistance materials and methods of operating the semiconductor devices. The semiconductor devices use variable resistance materials with resistances that vary according to applied voltages as channel layers. | 2011-08-04 |
20110188291 | Preservation circuit and methods to maintain values representing data in one or more layers of memory - Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer. | 2011-08-04 |
20110188292 | VARIABLE RESISTANCE MEMORY, OPERATING METHOD AND SYSTEM - Provided is an operating method of a variable resistance memory device. The operating method applies a set pulse to a plurality of memory cells to be written in a set state, and applies a reset pulse to a plurality of memory cells to be written in a reset state. The width of the set pulse is narrower than the width of the reset pulse. | 2011-08-04 |
20110188293 | Non-Volatile Memory Cell With Non-Ohmic Selection Layer - A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold. | 2011-08-04 |
20110188294 | Multiplexer/de-multiplexer Memristive Device - A multiplexing/de-multiplexing memristive device ( | 2011-08-04 |
20110188295 | High Performance eDRAM Sense Amplifier - Embedded dynamic random access memory (eDRAM) sense amplifier circuitry in which a bit line connected to each of a first plurality of eDRAM cells is controlled by cell control lines tied to each of the cells. During a READ operation the eDRAM cell releases its charge indicating its digital state. The digital charge propagates through the eDRAM sense amplifier circuitry to a mid-rail amplifier inverter circuit which amplifies the charge and provides it to a latch circuit. The latch circuit, in turn, inverts the charge to correctly represent at its output the logical value stored in the eDRAM cell being read, and returns the charge through the eDRAM sense amplifier circuitry to replenish the eDRAM cell. | 2011-08-04 |
20110188296 | Semiconductor Memory Device and Semiconductor Device - The semiconductor memory device includes an initialization memory cell having a first inverter circuit including a first transistor and a second transistor, and a second inverter circuit whose input portion is connected to an output portion of the first inverter circuit and output portion is connected to an input portion of the first inverter circuit, and including a third transistor and a fourth transistor. An absolute value of a threshold voltage of the third transistor is smaller than that of the first transistor. | 2011-08-04 |
20110188297 | MAGNETIC MEMORY ELEMENT, DRIVING METHOD FOR SAME, AND NONVOLATILE STORAGE DEVICE - In accordance with one aspect of the invention, a magnetic memory element records information in a spin valve structure having a free layer, a pinning layer, and a nonmagnetic layer sandwiched therebetween. The magnetic memory element further has, on the free layer, a separate nonmagnetic layer and a magnetic change layer having magnetic characteristics which change according to temperature. Multiple cutouts, including one cutout with a different shape, are provided in a peripheral portion of the spin valve structure. A method of driving the magnetic memory element is characterized in that information is recorded by applying unipolar electric pulses. | 2011-08-04 |
20110188298 | MAGNETORESISTANCE ELEMENT, MRAM, AND INITIALIZATION METHOD FOR MAGNETORESISTANCE ELEMENT - A magnetoresistance element is provided with: a magnetization recording layer that is a ferromagnetic layer. The magnetization recording layer includes: a magnetization reversal region having a reversible magnetization; a first magnetization fixed region connected to a first boundary of the magnetization reversal region and having a magnetization direction fixed in a first direction; and a second magnetization fixed region connected to a second boundary of the magnetization reversal region and having a magnetization direction fixed in a second direction. At least one magnetization reversal facilitation structure which is a structure in which a magnetization is reversed more easily than the remaining portion is provided for a portion of the second magnetization fixed region. | 2011-08-04 |
20110188299 | DATA STORAGE DEVICE - A data storage device ( | 2011-08-04 |
20110188300 | NON-VOLATILE MEMORY WITH STRAY MAGNETIC FIELD COMPENSATION - A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that has a perpendicular anisotropy is coupled to the first tunneling barrier and a nonmagnetic spacer layer. A compensation layer that has a perpendicular anisotropy and a second magnetization direction in substantial opposition to the first magnetization direction is coupled to the nonmagnetic spacer layer. Further, the memory cell is programmable to a selected resistance state with application of a current to the recording structure. | 2011-08-04 |
20110188301 | SHARED BIT LINE AND SOURCE LINE RESISTIVE SENSE MEMORY STRUCTURE - A resistive sense memory apparatus includes a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element and a second semiconductor transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second resistive sense memory element. A bit line is electrically connected to the first resistive sense memory element and the second resistive sense memory element. | 2011-08-04 |
20110188302 | METHOD OF DRIVING PHASE CHANGE MEMORY DEVICE CAPABLE OF REDUCING HEAT DISTURBANCE - A method of driving phase change memory device which reduces or prevents unwanted heat disturbances from interfering with memory states in adjacent memory cells is presented. The phase change memory cells are disposed at word and bit line intersections. The method includes collectively erasing all of the memory cells as a unit in the bit line into a reset state. The method then includes individually programming only selected memory cells of the memory cells into set states. | 2011-08-04 |
20110188303 | Phase change memory device generating program current and mehtod thereof - A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation. | 2011-08-04 |
20110188304 | MULTIPLE LEVEL CELL PHASE-CHANGE MEMORY DEVICES HAVING PRE-READING OPERATION RESISTANCE DRIFT RECOVERY, MEMORY SYSTEMS EMPLOYING SUCH DEVICES AND METHODS OF READING MEMORY DEVICES - A memory device comprises a plurality of memory cells, each memory cell comprising a memory cell material that has an initial resistance that is determined in response to an applied programming current in a programming operation, the resistance of the memory cell varying from the initial resistance over a time period following the programming operation, and each memory cell being connected to a conduction line of the memory device that is used to apply the programming current to program the resistance of the corresponding memory cell in the programming operation and that is used to apply a read current to read the resistance of the corresponding memory cell in a read operation. A modification circuit modifies the resistance of a memory cell of the plurality of memory cells selected for a read operation to return its resistance to near the initial resistance prior to a read operation of the memory cell. | 2011-08-04 |
20110188305 | Read disturb free SMT MRAM reference cell circuit - An array of SMT MRAM cells has a read reference circuit that provides a reference current that is the sum of a minimum current through a reference SMT MRAM cell programmed with a maximum resistance and a maximum current through an reference SMT MRAM cell programmed with a minimum resistance. The reference current forms an average reference voltage at the reference input of a sense amplifier for reading a data state from selected SMT MRAM cells of the array such that the reference SMT MRAM cells will not be disturbed during a read operation. The read reference circuit compensates for current mismatching in the reference current caused by a second order non matching effect. | 2011-08-04 |
20110188306 | Increased Magnetic Damping for Toggle MRAM - Magnetic random access memory (MRAM) devices and techniques for use thereof are provided. In one aspect, a magnetic memory cell is provided. The magnetic memory cell comprises at least one fixed magnetic layer; at least one first free magnetic layer separated from the fixed magnetic layer by at least one barrier layer; at least one second free magnetic layer separated from the first free magnetic layer by at least one spacer layer; and at least one capping layer over a side of the second free magnetic layer opposite the spacer layer. One or more of the first free magnetic layer and the second free magnetic layer comprise at least one rare earth element, such that the at least one rare earth element makes up between about one percent and about 10 percent of one or more of the first free magnetic layer and the second free magnetic layer. | 2011-08-04 |
20110188307 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a charge storage film and a memory cell transistor. The transistor is provided for each of storage regions configured to store charge in the film. The control unit sets the transistors to an erase threshold by setting erase information in the regions; subsequently sets the transistors to thresholds corresponding to information having n values by programming the information having the n values to at least one of the regions in which the erase information is set; and controls information of at least one storage region before being programmed adjacent to the regions programmed with the information to have a value providing a threshold of the transistor nearer than the erase threshold to the thresholds corresponding to the information having the n values in the state of the transistors provided in the regions being set to the thresholds corresponding to the information having the n values. | 2011-08-04 |
20110188308 | OVER ERASE CORRECTION METHOD OF FLASH MEMORY APPARATUS - An over erase correction method of a flash memory apparatus is provided. The flash memory apparatus includes at least a microprocessor, a memory array, a bit line exchange unit and a column decoder. By controlling the column decoder of the flash memory during a period of the over-erase correction, the column decoder outputs control signals to the bit line exchange unit for selecting at least one of the bit lines according to a magnitude of the bit line leakage current. The drop in the charge pump voltage due to the bit line leakage current is reduced, and thus, the over-erase correction is executed effectively during the period of the over-erase correction. | 2011-08-04 |
20110188309 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first circuit unit having first and second interconnects, a second circuit unit having third and fourth interconnects, and an intermediate unit provided therebetween and having first and second transistors juxtaposed to each other along a direction perpendicular to a direction from the first circuit unit toward the second circuit unit. A high impurity concentration region in a first connection region of one diffusion layer of the first transistor is connected to the first interconnect, and other diffusion layer is connected to the third interconnect. A distance from the first connection region to a gate is longer than a distance from the second connection region to a gate. An midpoint region with a narrower width than the first connection region is provided between the gate and the first connection region of the one diffusion layer of the first transistor. | 2011-08-04 |
20110188310 | NONVOLATILE MEMORY DEVICES WITH COMMON SOURCE LINE VOLTAGE COMPENSATION AND METHODS OF OPERATING THE SAME - A memory device includes a plurality of memory cells serially connected between a bit line and a common source line and a plurality of word lines, respective ones of which are connected to respective gates of the plurality of memory cells. The memory device further includes a common source line compensation circuit configured to generate a compensated bias voltage on the bit line or at least one of the plurality of word lines responsive to a common source line voltage on the common source line. Related methods of operating memory devices are also provided. | 2011-08-04 |
20110188311 | Efficient Memory Sense Architecture - Memory architecture, such as for a flash EEPROM memory embedded within a processor or other large scale integrated circuit, and including differential sense circuitry. The memory includes an array of memory cells in rows and columns, and organized into sectors, each sector split into portions. Columns of the array are grouped into small groups from which a final stage column decode selects a column from the group based on the least significant bits of the column address. Adjacent groups of columns are paired, with a selected column from each group coupled to a differential input of the sense amplifier, but with one of the selected columns associated with an unselected sector portion and thus serving as a dummy bit line. Conductor routing is simplified, and chip area is reduced, by maintaining unselected column groups adjacent or nearby to selected column groups. | 2011-08-04 |
20110188312 | METHOD FOR MEMORY CELL ERASURE WITH A PROGRAMMING MONITOR OF REFERENCE CELLS - Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells. | 2011-08-04 |
20110188313 | DATA RETENTION OF LAST WORD LINE OF NON-VOLATILE MEMORY ARRAYS - Techniques for operating non-volatile storage compensate for differences in floating gate coupling effect experienced by non-volatile storage elements on different word lines. An erase of a group of non-volatile storage elements is performed. A set of the non-volatile storage elements are for storing data and at least one of the non-volatile storage elements is a dummy that is not for storing data. The dummy is a neighbor to one of the data non-volatile storage elements. The data non-volatile storage elements are programmed at some point after the erase. Then, a programming voltage is applied to the dummy non-volatile storage element to increase the threshold voltage of the dummy to cause floating gate coupling effect to the neighbor non-volatile storage element to compensate for lesser floating gate coupling effect that the neighbor experienced during programming. | 2011-08-04 |
20110188314 | BIT LINE STABILITY DETECTION - A power supply and monitoring apparatus such as in a nonvolatile memory system. A power supply circuit provides power to a large number of sense modules, each of which is associated with a bit line and a string of non-volatile storage elements. During a sensing operation, such as a read or verify operation, a discharge period is set in which a sense node of each sense module discharges into the associated bit line and string of non-volatile storage elements, when the string of non-volatile storage elements, is conductive. This discharge sinks current from the power supply, causing a perturbation. By sampling the power supply, a steady state condition can be detected from a rate of change. The steady state condition signals that the discharge period can be concluded and data can be latched from the sense node. The discharge period automatically adapts to different memory devices and environmental conditions | 2011-08-04 |
20110188315 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING NON-SELECTED WORD LINES ADJACENT TO SELECTED WORD LINES BEING CHARGED AT DIFFERENT TIMING FOR PROGRAM DISTURB CONTROL - A non-volatile semiconductor memory device includes a memory cell array of data-rewritable non-volatile memory cells or memory cell units containing the memory cells, and a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array. In write pulse applying during data writing, a high voltage for writing is applied to a selected word line, and an intermediate voltage for writing is applied to at least two of non-selected word lines. The beginning of charging a first word line located between the selected word line and a source line to a first intermediate voltage for writing is followed by the beginning of charging a second word line located between the selected word line and a bit line contact to a second intermediate voltage for writing. | 2011-08-04 |
20110188316 | SEMICONDUCTOR MEMORY DEVICE - This invention offers a semiconductor memory device, with which a resolution to read-out data is not reduced even at the time of verify and a stable read-out operation is possible even when a power supply voltage is reduced. A read-out circuit is provided with a current-voltage conversion circuit, that converts a cell current into a data voltage, and a sense amplifier that compares the data voltage with a reference voltage. The current-voltage conversion circuit is formed to include a variable load resistor that is connected to the memory cell through a bit line. The variable load resistor is formed to include P channel type MOS transistors that make load resistors and P channel type MOS transistors that constitute a switching circuit. | 2011-08-04 |
20110188317 | NON-VOLATILE MEMORY WITH FAST BINARY PROGRAMMING AND REDUCED POWER CONSUMPTION - In a non-volatile storage system, the time needed to perform a programming operation is reduced by minimizing data transfers between sense modules and a managing circuit. A sense module is associated with each storage element. Based on write data, a data node in the sense module is initialized to “0” for a storage element which is to remain in an erased state, and to “1” for a storage element which is to be programmed to a programmed state, then flipped to “0” when programmed is completed. The managing circuit is relieved of the need to access the write data to determine whether a “0” represents a storage element for which programming is completed. Power consumption can also be reduced by keeping a bit line voltage high between a verify phase of one program-verify iteration and a program phase of a next program-verify iteration. | 2011-08-04 |
20110188318 | Flash Memory Device and a Method of Verifying the Same - Provided are a flash memory device and a method of verifying the same. The flash memory device includes: a memory cell for storing data; a sense amplifier for reading information of the memory cell; a load current input device for providing a load current to the sense amplifier; and a control circuit for controlling the load current input device to provide a load current during a memory cell reading operation, verifying the memory cell by using a program verify voltage if the memory cell is a programmed memory cell, and verifying the memory cell by using a compensated erase verify voltage if the memory cell is an erased memory cell. | 2011-08-04 |
20110188319 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM - A nonvolatile semiconductor memory device and a nonvolatile memory system having a unit which suppresses erroneous reading of a nonvolatile semiconductor memory device of a multi-level memory system are provided. In the nonvolatile semiconductor memory device and the nonvolatile memory system of the multi-level memory system, a first verify voltage is used when data is written before a packaging process, and the verify voltage is switched to a second verify voltage lower than the first verify voltage when data is written after the packaging process. | 2011-08-04 |
20110188320 | MEMORY DEVICES AND METHODS OF THEIR OPERATION INCLUDING SELECTIVE COMPACTION VERIFY OPERATIONS - Memory devices and methods of their operation, where following an erasure of a string of memory cells, a selective compaction verify operation is performed on one or more, but less than all, of the memory cells of the string, and, if the selective compaction verify operation indicates compaction is desired, a soft programming pulse is applied to one or more of the memory cells of the string. | 2011-08-04 |
20110188321 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a charge storage film, a first insulating film provided adjacent to one surface of the charge storage film, a second insulating film provided adjacent to one other surface of the charge storage film, a semiconductor portion provided adjacent to the first insulating film and a plurality of electrode portions provided adjacent to the second insulating film. The control unit performs a control of applying a first voltage to electrode portions adjacent to each other in one direction at different timing respectively, in an erasing. The erasing is performed by at least one selected from injecting electron holes into the charge storage film and removing electrons from the charge storage film. The first voltage is applied from one of the electrode portions to the charge storage film to be erased. | 2011-08-04 |
20110188322 | MEMORY DEVICE WITH DATA PATHS FOR OUTPUTTING COMPRESSED DATA - A memory device is provided. The memory device includes a plurality of memory array banks, a bus, a data buffer, and four data paths. The data buffer provides data from the memory array banks to an external node. The first data path includes a first compression module for compressing the data from the memory array banks to the bus. The second data path transmits the data from the memory array banks to the bus. The third data path includes a second compression module for compressing data from the bus to the data buffer. The fourth data path transmits the data from the bus to the data buffer. | 2011-08-04 |
20110188323 | DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY AND RELATED METHOD - Various embodiments of a data output circuit of a semiconductor memory and related method are disclosed. In one exemplary embodiment, a data output circuit may include a plurality of global lines, a sense amplifier block configured to output a plurality of data to the plurality of global lines at different timings, a pipe latch block configured to latch the plurality of data transmitted through the plurality of global lines at different timings, and a control unit configured to control output timings of the plurality of data from the sense amplifier block and latch timings of the pipe latch block using an address signal. | 2011-08-04 |
20110188324 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal. | 2011-08-04 |
20110188325 | Semiconductor device and data processing system - A semiconductor device comprises a bit line transmitting a signal to be sensed, a single-ended sense amplifier sensing and amplifying the signal transmitted from the bit line to the input node, and a reference voltage supplying circuit outputting a reference voltage. The sense amplifier includes a first transistor for charge transfer between the bit line and an input node, and the voltage value of the reference voltage is controlled in association with a threshold voltage of the first transistor. The reference voltage is set to a first logical value of the transfer control signal which controlled to be first and second logical values. | 2011-08-04 |
20110188326 | DUAL RAIL STATIC RANDOM ACCESS MEMORY - A static random access memory (SRAM) macro includes a first power supply voltage and a second power supply voltage that is different from the first power supply voltage. A precharge control is connected to the second power supply voltage. The precharge control is coupled to a bit line through a bit line precharge. At least one level shifter receives a level shifter input. The level shifter converts the level shifter input having a voltage level closer to the first power supply voltage than the second power supply voltage to a level shifter output having a voltage level closer to the second power supply voltage than the first power supply voltage. The level shifter output is provided to the precharge control. | 2011-08-04 |
20110188327 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a plurality of memory cells each including a holding circuit for holding memory data, and a read-only output circuit for outputting a signal corresponding to the data held by the holding circuit. The read-only output circuit has a read drive transistor controlled in accordance with a signal held by the holding circuit. A gate length of the read drive transistor is longer than a gate length of a transistor included in the holding circuit. Alternatively, the read-only output circuit has a read access transistor controlled in accordance with a read word select signal, and a gate length of the read access transistor is longer than a gate length of a transistor included in the holding circuit. | 2011-08-04 |
20110188328 | Systems and Methods for Writing to Multiple Port Memory Circuits - A multiple-port RAM circuit has a data-in line coupled to multiple bit lines and multiple bit line bars. The circuit also has multiple word lines. A memory cell is coupled to the bit lines, bit line bars, and word lines. The circuit further includes a controller than enables the word lines to substantially simultaneously write a value from the bit lines to the memory cell. | 2011-08-04 |
20110188329 | SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor integrated circuit ( | 2011-08-04 |
20110188330 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic. | 2011-08-04 |
20110188331 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus having a plurality of chips stacked therein is disclosed. At least two of the plurality of chips are configured to receive a column command and generate a column control signal based on the column command. Generation timing of the column control signal generated based on a column command in one of the at least two of the plurality of chips substantially coincide with the generation timing in the other of the at least two of the plurality of chips. | 2011-08-04 |
20110188332 | Semiconductor memory device having regular area and spare area - Memory arrays ARY | 2011-08-04 |
20110188333 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A semiconductor memory device can include a first driver configured to generate a pair of first sense amplifier driving signals having an activation period at a predetermined level during command execution; and a second driver that can be configured to generate a pair of second sense amplifier driving signals for increasing a driving strength of a pair of sense amplifiers when logic values of a pair of bit lines are constant during the command execution and decreasing the driving strength of the pair of sense amplifiers when the logic values of the pair of bit lines change. | 2011-08-04 |
20110188334 | FUSE CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - Provided is a fuse circuit capable of selectively using a power supply voltage for a logic operation according to an operation mode. The fuse circuit includes a mode generating circuit, a power supply voltage selection circuit, and at least one fuse unit. The mode generating circuit generates a plurality of mode signals. The power supply voltage selection circuit selects one out of a plurality of power supply voltages in response to the plurality of mode signals and outputs the selected power supply voltage to a first node. Each of the fuse units is coupled between the first node and a ground voltage and uses the selected power supply voltage as a power supply voltage for a logic operation. Thus, a semiconductor device including the fuse circuit may accurately test a connection state of a fuse. | 2011-08-04 |
20110188335 | Hierarchical Multi-Bank Multi-Port Memory Organization - A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead. | 2011-08-04 |
20110188336 | DRIVE ARRANGEMENT IN A DEGASSING EXTRUDER - The invention relates to a vented extruder ( | 2011-08-04 |
20110188337 | METHOD AND DEVICE FOR GENERATING MOVEMENT IN A THIN LIQUID FILM - The invention relates to a method for generating motion in a thin liquid film on a substrate, in particular in a capillary gap, in which at least one ultrasound wave is sent right through the substrate in the direction of the liquid film, and a device for carrying out the inventive method. | 2011-08-04 |
20110188338 | STEPPED DOWN GAS MIXING DEVICE - An apparatus and method for mixing gas streams of different temperatures and/or compositions contemplates that at least one of the streams contains particle. The apparatus includes a main duct for the first gas stream and a plurality of duct assemblies extending in the main duct generally transversely to the first gas stream. Each assembly has plural inlets and outlets for receiving and discharging separate parts of the second gas stream, moving initially generally transverse to the first stream. The assemblies each have plural secondary ducts of mutually different lengths from inlet to outlet, the outlets being spaced from each other across the main duct for distributing the parts of the second gas stream into the first gas stream. A gas flow deflector is connected to each duct assembly for temporarily deflecting the first gas stream before it is combined with the parts of the second gas stream. | 2011-08-04 |
20110188339 | Rotationally Actuated Magnetic Bead Trap and Mixer - A magnetic bead trap-and-mixer includes a channel having openings at opposing ends, and a rotor adjacent to the channel and comprising a permanent magnet, wherein the rotor is adapted to apply a magnetic field to the channel of sufficient strength to direct the movement of magnetic beads therein. In aspects, the channel is straight and/or has narrowed end. In further aspects, the rotor generates in the channel areas of areas of strong magnetic fields alternating with areas of very weak magnetic fields and the strong magnetic fields extend entirely across the channel. | 2011-08-04 |
20110188340 | Blender container and cover with tethered plug - The open top of a blender container ( | 2011-08-04 |
20110188341 | MIXING DEVICE FOR LIQUID CHROMATOGRAPHY - The invention relates to a mixing device for liquid chromatography for the radial mixing of at least two fluids, in particular for the mixing of at least two eluents in high-performance liquid chromatography, with a tubular mixing line ( | 2011-08-04 |
20110188342 | DEVICE AND METHOD FOR ACOUSTIC DISPLAY - A device for acoustic display of a position of an object in a reproduction space, a plurality of loudspeakers being arranged in the reproduction space at spatially different positions such that different spatial positions may be represented acoustically by differently driving the loudspeakers, includes a signal associater and a loudspeaker driver. The signal associater is configured to associate an acoustic signal to the object. The loudspeaker driver is configured to establish one or several loudspeaker signals for the plurality of loudspeakers, wherein the one or several loudspeaker signals by which the position of the object is displayed are based on the acoustic signal associated to the object by the signal associater. The one or several loudspeaker signals may be established such that, when reproducing the one or several loudspeaker signals, the position of the object in the reproduction space is displayed acoustically. | 2011-08-04 |
20110188343 | Random Transmitter Placement Method For Stationary Seismic Imaging - A method for at least one of imparting seismic energy into formations below the bottom of a body of water and detecting seismic energy therefrom includes releasing a plurality of acoustic transducers into the water. The transducers move to the bottom by gravity. A geodetic position of each of the transducers on the water bottom is determined. At least one of the following is performed: actuating each of the transducers as a transmitter at least once, the actuating of each transducer occurring at a time selected to cause seismic energy to be imparted into the formations in a beam along a selected direction, the selected time related to relative positions of the transducers; and recording signals detected by each of the transducers, the recording including adding a selected time delay to cause response of the transducers to be amplified along a selected direction. | 2011-08-04 |
20110188344 | SYSTEMS AND METHODS FOR DISTRIBUTED INTERFEROMETRIC ACOUSTIC MONITORING - This disclosure relates in general to a method and system for acoustic monitoring using a fibre optic cable. More specifically, but not by way of limitation, embodiments of the present invention provide for using an optical fiber as a distributed interferometer that may be used to monitor a conduit, wellbore or reservoir. In certain aspects, the distributed interferometric monitoring provides for accurate detection of acoustic occurrences along the fibre optic cable and these acoustic occurrences may include fluid flow in a pipeline or wellbore, processes taking place in a wellbore or pipeline, fracturing, gravel packing, production logging and/or the like. | 2011-08-04 |
20110188345 | Downhole Sonic Logging Tool Including Irregularly Spaced Receivers - A downhole acoustic measurement tool includes at least one transmitter longitudinally spaced apart from a non-uniformly spaced longitudinal array of acoustic receivers. The array has a non-uniform spacing such that a first spacing between a first pair of consecutive acoustic receivers in the array is not equal to a second spacing between a second pair of consecutive acoustic receivers in the array. Non-uniform spacing of the receivers in the array reduces aliasing when the received waveforms are processed, for example, to obtain semblance data. | 2011-08-04 |
20110188346 | METHOD FOR DETECTING AND LOCATING FLUID INGRESS IN A WELLBORE - A method for detecting fluid ingress in a wellbore, and if detected, obtaining an indication of where along said wellbore said fluid ingress is occurring. Acoustic sensing means, adapted to sense individual acoustic signals from a plurality of corresponding locations along said wellbore, are analyzed to determine if there exists a common acoustic component in acoustic signals generated from proximate locations in said wellbore. If so, the acoustic signal having the common acoustic component which appears earliest in phase, by virtue of such acoustic signal's corresponding location in the wellbore, determines the location in the wellbore of likely fluid ingress. In a preferred embodiment the acoustic sensing means comprises a fibre optic cable extending substantially the length of the wellbore, or alternatively a plurality of microphones situated at various locations along the wellbore comprising substantially the length of the wellbore. | 2011-08-04 |
20110188347 | VOLUME IMAGING FOR HYDRAULIC FRACTURE CHARACTERIZATION - Methods and systems are described for measuring effects of a hydraulic fracturing process. The techniques can utilizes cross-well seismic technology, such as used in Schlumberger's DeepLook-CS tools and service, or in some case surface to borehole or borehole to surface seismic technology. The downhole seismic sources at known locations can be conventional sources or can be other types of equipment operating at known locations such as perforation guns. The source is activated or swept creating energy which is transmitted through the formation. The energy is recorded at the receiver array and processed to yield a tomographic image indicating changes in the subterranean formation resulting from the hydraulic fracturing process. The process can be performed pre and post hydraulic fracture stimulation to generate a difference image of propped fractures in the reservoir. | 2011-08-04 |
20110188348 | METHOD AND APPARATUS FOR MONITORING ACOUSTIC ACTIVITY IN A SUBSURFACE FORMATION - A method and apparatus is disclosed for monitoring microseismic activity in a formation. The method and apparatus include placing a tool string having a shuttle including a sensor thereon in a stimulation well, and activating the shuttle to acoustically couple the sensor to an inner surface of a casing. The sensor is acoustically decoupled from the tool string. Fluid is then injected into the formation via the tool string. The sensor is reengaged with the tool string. The tool string may then be removed from the stimulation well or moved to another position along the wellbore. | 2011-08-04 |
20110188349 | System and Method of Determining an Underwater Location - An underwater device receives underwater signals from a pair of beacon units. Based on these signals, a processing circuit in the device determines a distance and a direction to each beacon unit. The underwater device also measures a depth for the device, and an angle of arrival of one or both of the incoming signals. Based on the distances to the two beacon units, the depth of the device, and the measured angle of arrival, the processing circuit can determine a current underwater location for the device. | 2011-08-04 |
20110188350 | SYSTEM AND METHOD FOR DEPTH DETERMINATION OF AN IMPULSE ACOUSTIC SOURCE - A system and method for making an accurate estimate of the activation depth for an impulse acoustic source includes recording sounds produced by the activation of the underwater impulse acoustic source over a time period sufficient to capture reverberation, performing a cepstral scan of the recording to determine a quefrequency corresponding to the impulse from the underwater impulse acoustic source and deriving a depth estimate from the quefrequency corresponding to the impulse from the underwater impulse acoustic source. | 2011-08-04 |
20110188351 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR SCHEDULE MANAGEMENT BASED ON LOCATIONS OF WIRELESS DEVICES - A method for managing appointments using a wireless device includes receiving scheduling data for a future appointment including a time associated with the future appointment. A current location of the wireless device is determined, and a reminder for the future appointment is provided at a time prior to the future appointment based on the current location of the wireless device. For example, the reminder may be provided at a time that varies based on the current location of the wireless device, a location associated with the future appointment, and an estimated travel time between the current location of the device and the location associated with the future appointment. Related methods, devices, and computer program products are also discussed. | 2011-08-04 |
20110188352 | Stepping motor control circuit and analogue electronic watch - The invention provides a stepping motor control circuit including a rotation detecting circuit configured to detect an induced signal generated according to the state of rotation of a stepping motor, and a control unit configured to select any one of a plurality of drive pulses having different energy from each other according to the result of detection detected by the rotation detecting circuit and controls the drive of the stepping motor alternately with the selected drive pulses having different polarities from each other, wherein if the difference of detected time points of the induced signals generated when driving the stepping motor with the drive pulses having the same energy and different polarities is not shorter than a predetermined time, the control unit changes the drive pulse to a drive pulse having a larger energy than that of the above-described drive pulse and drives the stepping motor. | 2011-08-04 |
20110188353 | ELECTRON BEAM LITHOGRAPHY METHOD, ELECTRON BEAM LITHOGRAPHY APPARATUS, METHOD FOR PRODUCING A MOLD, AND METHOD FOR PRODUCING A MAGNETIC DISK MEDIUM - Irradiation of an electron beam onto a base plate having resist coated thereon is controlled by ON/OFF signals output to a blanking element. Beam deflecting operations are controlled by deflecting signals output to a deflecting element. Patterns of servo areas and data areas are scanned and drawn on the base plate over a plurality of rotations. The electron beam is scanned in two directions so as to fill the shapes of patterns in the servo areas during a specific rotation, patterns in the data area are drawn as a continuous line or broken line with a single electron beam emission. The patterns of the data area are not drawn during other rotations, by shielding irradiation of the electron beam. | 2011-08-04 |
20110188354 | HEAT-ASSISTED MAGNETIC RECORDING HEAD WITH CONVERGENT LENS - A heat-assisted magnetic recording head includes a magnetic pole, a waveguide that allows light to propagate therethrough, a near-field light generating element that generates near-field light based on the light propagating through the waveguide, a convergent lens, and a laser diode disposed above the waveguide. The convergent lens transmits light that is emitted from the laser diode, so that the light transmitted through the convergent lens is incident on the waveguide. | 2011-08-04 |
20110188355 | INFORMATION RECORDING AND REPRODUCTION APPARATUS - The present invention relates to an information recording and reproduction apparatus which records the information on a disk by heating the disk with near-field light and causing magnetization reversal by applying a recording magnetic field to the disk. A photoelectric composite wiring line | 2011-08-04 |
20110188356 | HEAD GIMBAL ASSEMBLY AND DATA RECORDING AND REPRODUCING APPARATUS HAVING THE SAME - A head gimbal assembly includes: a suspension extending along a surface of a recording medium and being flexibly deformable in the thickness direction; a slider arranged so as to oppose the surface of the recording medium on a distal side of the suspension; a supporting portion configured to support the slider in a rotatable state with respect to two axes being parallel to the surface of the recording medium and orthogonal to each other on the opposite side of the slider from the recording medium; and a light waveguide connected to the slider and configured to introduce an optical flux emitted from a light source to the slider. The slider includes a spotlight generating element configured to generate a spotlight from the optical flux, and record data in the recording medium using the spotlight. A positioning portion having a flat surface and being used for positioning between the light waveguide and the slider is arranged between the supporting portion and the slider. | 2011-08-04 |
20110188357 | LABELING A DISC WITH AN OPTICAL DISC DRIVE - A system and method for labeling with a laser an optical disc having a plurality of markable locations. Signals indicative of a focus of the laser to the disc are measured, while rotating the disc at a constant angular velocity. Focus positions for designated ones of the locations to be marked on the disk are determined from the measured signals. The designated locations are marked with the laser while rotating the disc at a constant linear velocity and positioning the laser at the corresponding focus position. For at least some radial positions of the laser, an angular velocity corresponding to the constant linear velocity is less than the constant angular velocity. | 2011-08-04 |
20110188358 | OPTICAL DISK DRIVE DEVICE AND ADDITIONAL RECORDING METHOD - Disclosed herein are an optical recording medium driving device and an additional recording method, which performs tracking servo control for moving an objective lens in a direction orthogonal to a tangential direction of a guide track so that a guide tracking error signal is decreased with respect to a guide track of a guide layer separation type recording medium, detects an additional recording start position subsequent to a recorded track if the recorded track is present in a recording layer of the optical recording medium, generates a tracking correction signal according to the reproduction tracking error signal upon tracking servo control of the recorded track just before the additional recording start position, and corrects tracking servo control according to the tracking correction signal upon additional recording start. | 2011-08-04 |
20110188359 | Optical Disk Apparatus, Semiconductor Integrated Circuit, and Laser Diode Driver - In an optical disk apparatus, the same signal path is used to both reduce an interchannel phase shift in write strategy signals and also to perform the actual writing to the disk. The optical disk apparatus includes a laser diode, a laser diode driver, and a semiconductor integrated circuit. The semiconductor integrated circuit includes a write strategy circuit and a control unit for controlling the operation of the write strategy circuit. Information collection for interchannel delay adjustment is performed through the use of the same signal path as that used for transmitting pulse signals from a pulse generation circuit to the laser diode driver for actual writing to an optical disk. Based thereon, an interchannel delay amount for applying laser light to the optical disk is set, thereby reducing the interchannel phase shift in the write strategy signals. | 2011-08-04 |
20110188360 | RECORDING METHOD FOR OPTICAL DISK AND OPTICAL DISK RECORDING REPRODUCTION DEVICE - There is proposed an optical disk recording method that can prevent degradation of recording quality due to occurrence of thermal interference, and an optical disk recording reproduction device used in this recording method. The recording method has a step of executing a test record on an output proofing area of the optical disk | 2011-08-04 |
20110188361 | RECORDING DEVICE AND METHOD, AND COMPUTER PROGRAM - A recording apparatus includes: a recording device for recording data onto a recording medium by applying a laser beam whose power can be adjusted; a first controlling device controlling the recording device to record calibration data while adjusting power; a first detecting device detecting calibration data recording quality; a second detecting device detecting push-pull signal amplitude by reading the calibration data; a first calculating device calculating a power by which the recording quality is desired quality, as a first optimum power; a second calculating device calculating a power by which the amplitude of the recorded push-pull signal satisfies a first condition and by which the recording quality satisfies a second condition, as a second optimum power, if the push-pull amplitude fails the first condition; and a second controlling device controlling the recording device to start recording record data by applying the laser beam with the first or second optimum power. | 2011-08-04 |
20110188362 | WRITE POWER SETTING METHOD AND OPTICAL DISC DEVICE - A disc write power setting method and a disc device are provided. The write power setting method comprises reading writing characteristic information from a disc; writing test data for each of n write power values and detecting modulation with respect to the written data; calculating, for each of k power coefficients, a straight line approximating a curve composed of n points which have x coordinates corresponding to differences between a corresponding power coefficient and the write power values used for the test data writing and y coordinates corresponding to the product of modulation for the write power values and a corresponding difference and selecting a straight line having the smallest error with a corresponding curve among k straight lines and the power coefficient corresponding to the straight line; and setting optimum write power based on the selected straight line, the selected power coefficient and the read writing characteristic information. | 2011-08-04 |
20110188363 | Automatic Power Control System for Optical Disc Drive and Method Thereof - A method and system for calibrating an initial driving signal for driving an optical pick-up head of an optical disk drive is provided. On one embodiment, said optical disk drive is utilized for reading or writing data on an optical disk, the optical disk includes a plurality of auto power control areas (APC areas) and a plurality of data areas, and the APC areas and the data areas are interleaved in between. In at least one of the APC areas that before the data areas for a normal data writing, an initial driving signal is used for the normal data writing to drive the optical pick-up head to emit laserbeam. A detected level of the laserbeam is then obtained. An update initial driving signal is then calibrated according to the detected level and a target level. | 2011-08-04 |