31st week of 2022 patent applcation highlights part 63 |
Patent application number | Title | Published |
20220246639 | 3-DIMENSIONAL NAND MEMORY WITH REDUCED THERMAL BUDGET - Methods of manufacture and memory cells manufactured according to the methods are described. The manufacture has a lower thermal budget and experiences less heating by including a blocking layer including MgO. The method of manufacture may include annealing following deposition of the MgO, with the annealing occurring at temperatures below 900° C. or below 800° C. The blocking layers may be a first blocking layer made of SiO | 2022-08-04 |
20220246640 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a substrate, insulating films and first films alternately stacked on the substrate, at least one of the first films including an electrode layer and a charge storage layer provided on a face of the electrode layer via a first insulator, and a semiconductor layer provided on a face of the charge storage layer via a second insulator. The device further includes at least one of a first portion including nitrogen and provided between the first insulator and the charge storage layer with an air gap provided in the first insulator, a second portion including nitrogen, provided between the charge storage layer and the second insulator, and including a portion protruding toward the charge storage layer, and a third portion including nitrogen and provided between the second insulator and the semiconductor layer with an air gap provided in the first insulator. | 2022-08-04 |
20220246641 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a stack structure including insulating layers and conductive layers, which are alternately stacked; a channel structure penetrating the stack structure; data storage patterns respectively interposed between the conductive layers and the channel structure; blocking patterns respectively interposed between the conductive layers and the data storage patterns; insulating patterns respectively interposed between the insulating layers and the channel structure; and insulative liners interposed between the insulating layers and the insulating patterns, the insulative liners respectively surrounding the insulating patterns. | 2022-08-04 |
20220246642 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure. | 2022-08-04 |
20220246643 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device including a mold structure including a plurality of gate electrodes on a substrate, the plurality of gate electrodes including first, second, and third string selection lines sequentially stacked on the substrate; a channel structure that penetrates the mold structure and intersects each of the gate electrodes; a first cutting region that cuts each of the gate electrodes; a second cutting region that is spaced apart from the first cutting region in a first direction and cuts each of the gate electrodes; a first cutting line that cuts the first string selection line between the first cutting region and the second cutting region; a second cutting line that cuts the second string selection line between the first cutting region and the second cutting region; and a third cutting line that cuts the third string selection line between the first cutting region and the second cutting region. | 2022-08-04 |
20220246644 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A terminal cell includes: third and fourth nanosheets formed at the same positions as first and second nanosheets, respectively, in the Y direction; and first and second dummy gate interconnects surrounding the peripheries of the third and fourth nanosheets, respectively, in the Y direction. Faces of the first and third nanosheets on one side in the Y direction are exposed from a first gate interconnect and the first dummy gate interconnect, respectively. Faces of the second and fourth nanosheets on one side in the Y direction are exposed from a second gate interconnect and the second dummy gate interconnect, respectively. | 2022-08-04 |
20220246645 | ARRAY SUBSTRATE AND DISPLAY DEVICE - According to an aspect, an array substrate includes a first scan line, a second scan line, and a signal line. A semiconductor film has a coupling portion coupling one end of a first linear portion to one end of a second linear portion. Another end of the first linear portion of the semiconductor film and another end of the second linear portion of the semiconductor film are coupled to the signal line. In a plan view, the semiconductor film is disposed between the first scan line and the second scan line, the first linear portion intersects two first gate electrodes, and the second linear portion intersects two second gate electrodes. | 2022-08-04 |
20220246646 | THIN FILM TUNNEL FIELD EFFECT TRANSISTORS HAVING RELATIVELY INCREASED WIDTH - Thin film tunnel field effect transistors having relatively increased width are described. In an example, integrated circuit structure includes an insulator structure above a substrate. The insulator structure has a topography that varies along a plane parallel with a global plane of the substrate. A channel material layer is on the insulator structure. The channel material layer is conformal with the topography of the insulator structure. A gate electrode is over a channel portion of the channel material layer on the insulator structure. A first conductive contact is over a source portion of the channel material layer on the insulator structure, the source portion having a first conductivity type. A second conductive contact is over a drain portion of the channel material layer on the insulator structure, the drain portion having a second conductivity type opposite the first conductivity type. | 2022-08-04 |
20220246647 | ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAYING DEVICE - The disclosure provides an array substrate, a display panel and a displaying device, relating to the technical field of display ambient light. The array substrate has an active area and a peripheral area located on at least one side of the active area. The array substrate comprises a brightness detection module and a reference module. The brightness detection module is arranged in the peripheral area, comprising at least one first thin-film transistor. The brightness detection module is configured to receive ambient light, generate an ambient light brightness detecting current signal in response to the ambient light and output the ambient light brightness detecting current signal. The reference module is arranged in the peripheral area, comprising at least one second thin-film transistor. The reference module is configured to, in a dark state without ambient light, generate and output a reference current signal. | 2022-08-04 |
20220246648 | ELECTRONIC MODULATING DEVICE - An electronic modulating device is provided. The electronic modulating device includes a first modulating unit. The first modulating unit includes a first transistor including a channel arranged in an extending direction. The first modulating unit also includes a first modulating electrode electrically connected to the first transistor and arranged in a first longitudinal direction. The electronic modulating device also includes a second modulating unit. The second modulating unit includes a second transistor including a channel arranged in the extending direction. The second modulating unit also includes a second modulating electrode electrically connected to the second transistor and arranged in a second longitudinal direction that is different from the first longitudinal direction. The first included angle between the extending direction and the first longitudinal direction is different from a second included angle between the extending direction and the second longitudinal direction. | 2022-08-04 |
20220246649 | ARRAY SUBSTRATE AND OLED DISPLAY PANEL - An array substrate and an OLED display panel are provided. The array substrate includes a base substrate, a first film layer set and a second film layer set. A bending area of the array substrate has a first trench throughout the first film layer set and a second trench throughout the second film layer set. The first film layer set close to the second film layer set has a blocking part having an etching opening corresponding to the first trench. The etching opening is throughout the blocking part. A bottom of the etching opening connects to a top of the first trench. A bottom of the second trench connects to a top of the blocking part. | 2022-08-04 |
20220246650 | IMAGE SENSING DEVICE - An image sensing device includes a plurality of unit pixels, each of which includes a plurality of sub-pixels. Each of the unit pixels is structured to respond to incident light to produce photocharges indicative of detected incident light and includes sub-pixels. Each sub-pixel includes a control region configured to generate, within a substrate in which the sub-pixels are disposed, a current that carries the photocharges, a detection region spaced from the control region and configured to capture the photocharges carried by the current, a plurality of first isolation portions disposed between two adjacent sub-pixels, a second isolation portion disposed to surround the sub-pixels, and a voltage applying region disposed at a center portion of the unit pixel and configured to receive a first voltage. | 2022-08-04 |
20220246651 | PHOTOELECTRIC CONVERSION APPARATUS - A photoelectric conversion apparatus includes a photoelectric conversion region provided with a plurality of photoelectric conversion units, a signal processing unit configured to process an output signal from the plurality of photoelectric conversion units, and a processing unit configured to perform processing based on a learned model on data processed by the signal processing unit. The photoelectric conversion apparatus also includes a first pad connected to the processing unit and a second pad connected to the signal processing unit. | 2022-08-04 |
20220246652 | PHOTOELECTRIC CONVERSION DEVICE AND PHOTOELECTRIC CONVERSION SYSTEM - A photoelectric conversion device includes a first substrate including a pixel array portion, in which a plurality of photoelectric conversion portions is arranged in a two-dimensional array shape in planar view, and a first wiring pattern, and a second substrate including a machine learning portion configured to perform processing of a signal obtained from electric charge generated by the photoelectric conversion portions and a second wiring pattern, the first substrate and the second substrate being stacked on each other, wherein the first wiring pattern of the first substrate and the second wiring pattern of the second substrate are joined to each other to configure a metal joining portion, wherein a heat dissipation portion including the metal joining portion connected to the machine learning portion is located at a position overlapping the machine learning portion, and wherein the pixel array portion and the machine learning portion do not overlap each other. | 2022-08-04 |
20220246653 | SOLID-STATE IMAGING ELEMENT AND SOLID-STATE IMAGING ELEMENT MANUFACTURING METHOD - A solid-state imaging element including a semiconductor substrate having a photodiode and a floating diffusion; a capacitor that includes a PD side electrode disposed on a surface of the photodiode opposite to a surface into which the light enters, and an opposite PD side electrode facing the PD side electrode with a dielectric film therebetween; an amplification transistor; and an FD side wiring electrode. At least a part of the PD side electrode and the FD side wiring electrode are formed in the semiconductor substrate and extend in a thickness direction of the semiconductor substrate. One end of a first contact hole in which at least a part of the PD side electrode is formed and one end of a second contact hole in which the FD side wiring electrode is formed are both positioned in a surface of the semiconductor substrate on a side opposite to the photodiode side. | 2022-08-04 |
20220246654 | PHOTOSENSING PIXEL, IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - A photosensing pixel includes a substrate, a photosensing region, a floating diffusion region, a transfer gate and a control electrode. The photosensing region is located within the substrate. The floating diffusion region is located within the substrate aside the photosensing region. The transfer gate is disposed on the substrate and extending into the photosensing region. The control electrode is located on the substrate and extending into the floating diffusion region. | 2022-08-04 |
20220246655 | SOLID-STATE IMAGING UNIT, METHOD OF PRODUCING THE SAME, AND ELECTRONIC APPARATUS - The present technology relates to a solid-state imaging unit that makes it possible to increase the number of terminals, a method of producing the same, and an electronic apparatus. A solid-state imaging unit includes: an image sensor substrate including a light receiving region in which pixels that each convert incoming light to an electric signal are arranged in a matrix; a solder ball; a glass substrate opposite the image sensor substrate and the solder ball; and a through electrode that couples a wiring line pattern and the solder ball to each other by penetrating a glass adhesive resin interposed between the wiring line pattern and the solder ball. The solder ball is disposed outside the image sensor substrate in a plane direction. The wiring line pattern being formed on the glass substrate. The present disclosure is applicable, for example, to a package and the like including the image sensor substrate. | 2022-08-04 |
20220246656 | TRANSISTOR HAVING INCREASED EFFECTIVE CHANNEL WIDTH - Methods of forming transistors include providing a substrate material, forming a recess to a first depth in the substrate material, the recess corresponding to a gate region and extending in a channel length direction and a channel width direction that is perpendicular to the channel length direction, forming a trench structure in the substrate material by deepening the recess to a second depth using an isotropic process, forming an isolation layer on the substrate material, forming a gate portion of the isolation layer on the substrate material such that the gate portion of the isolation layer extends into the trench structure, and forming a gate on the isolation layer such that the gate extends into the trench structure. | 2022-08-04 |
20220246657 | SOLID-STATE IMAGE SENSOR - The solid-state image sensor includes a semiconductor substrate having first and second photoelectric conversion elements, a color filter layer, and a hybrid layer. The isolation structure is disposed between the first and second photoelectric conversion elements. The color filter layer is disposed above the semiconductor substrate. The hybrid layer is disposed between the semiconductor substrate and the color filter layer. The hybrid layer includes a first partition structure, a second partition structure, and a transparent layer. The first partition structure is disposed to correspond to the isolation structure. The second partition structure is surrounded by the first partition structure. The transparent layer is between the first partition structure and the second partition structure. The refractive index of the first partition structure and the refractive index of the second partition structure are lower than the refractive index of the transparent layer. | 2022-08-04 |
20220246658 | IMAGE SENSOR AND METHOD FOR MAKING THE SAME - An image sensor including an isolation structure and a plurality of photodiodes arranged in a photosensitive area. The isolation structure isolates the plurality of the photodiodes from each other to form an array structure, and a closed air cavity structure is formed in the isolation structure between two adjacent photodiodes. A method for manufacturing an image sensor includes: providing a base layer; selectively etching the base layer to form a deep trench in a photosensitive area of the base layer; the deep trench extending from the first surface to the second surface of the base layer in a longitudinal direction to divide the base layer into device units arranged in an array; and gradually growing an epitaxial layer on the surface of the deep trench by means of an epitaxial growth process, so that the space in the deep trench tapers to form a closed air cavity structure. | 2022-08-04 |
20220246659 | IMAGING DEVICE AND IMAGING APPARATUS - Reflected light from a back-illuminated imaging device is to be reduced. The imaging device includes an on-chip lens, a photoelectric conversion unit, and an absorption film. The on-chip lens included in the imaging device condenses incident light. The photoelectric conversion unit included in the imaging device is formed in a semiconductor substrate, and performs photoelectric conversion on the condensed incident light. The absorption film included in the imaging device is disposed adjacent to the semiconductor substrate, has an opening of substantially the same size as the condensing size of the condensed incident light, and absorbs reflected light of the incident light. | 2022-08-04 |
20220246660 | SEMICONDUCTOR PACKAGE AND RELATED METHODS - Implementations of image sensor packages may include an image sensor chip, a first layer including an opening therethrough coupled to a first side of the image sensor chip, and a optically transmissive cover coupled to the first layer. The optically transmissive cover, the first layer, and the image sensor chip may form a cavity within the image sensor. The image sensor package may also include at least one electrical contact coupled to a second side of the image sensor chip opposing the first side and an encapsulant coating an entirety of the sidewalls of the image sensor package. | 2022-08-04 |
20220246661 | PHOTOELECTRIC CONVERSION APPARATUS, PHOTOELECTRIC CONVERSION SYSTEM, AND MOBILE BODY - A photoelectric conversion apparatus includes a first substrate having a pixel area, a second substrate disposed in a multilayer structure on the first substrate, and a heat dissipation structure. The second substrate includes a processing unit configured to execute a machine learning process on an image signal output from the pixel area. The heat dissipation structure is disposed in a region adjacent to or in a region overlapping the processing unit when seen in a plan view, the processing unit. The heat dissipation structure is formed on the first or second substrate by a semiconductor active region, polysilicon, a structure including a metal connection part, a TSV structure, or a cavity structure, or the heat dissipation structure is attached to the first substrate in an area other than the pixel area. When the structure is formed on the first substrate, it is electrically connected to the second substrate. | 2022-08-04 |
20220246662 | SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a multilayered wiring layer including an insulation layer ( | 2022-08-04 |
20220246663 | PHOTOELECTRIC CONVERSION APPARATUS, PHOTOELECTRIC CONVERSION SYSTEM, MOBILE BODY, AND SEMICONDUCTOR SUBSTRATE - An apparatus includes a first substrate having a pixel area and a second substrate superimposed on the first substrate, a first processing unit for processing signals output from a plurality of pixels, and a second processing unit for performing processing based on a neural network calculation model. At least part of the first processing unit and at least part of the second processing unit are disposed on either the first substrate or the second substrate. A wiring density of a plurality of first wirings connected to the first processing unit is different from a wiring density of a plurality of second wirings connected to the second processing unit. | 2022-08-04 |
20220246664 | PHOTOELECTRIC CONVERSION APPARATUS, PHOTOELECTRIC CONVERSION SYSTEM, MOBILE BODY, AND SEMICONDUCTOR SUBSTRATE - An apparatus includes a first substrate having a pixel area and a second substrate superimposed on the first substrate, a first processing unit for processing signals output from a plurality of pixels, and a second processing unit for performing processing based on a calculation model. At least part of the first processing unit and at least part of the second processing unit are disposed on either the first substrate or the second substrate. A first power supply voltage to the first processing unit and a second power supply voltage to the second processing unit are supplied via different paths. | 2022-08-04 |
20220246665 | SEMICONDUCTOR PACKAGE - A yield drop of a semiconductor package including a via is reduced. The semiconductor package includes a solid-state imaging element, a circuit layer, a wiring layer, and a support substrate. The solid-state imaging element in the semiconductor package generates image data. A signal processing circuit that performs predetermined signal processing on the image data is disposed in the circuit layer. An output side via the other end of which is connected to an external terminal penetrates the support substrate. The wiring layer is disposed between the support substrate and the circuit layer. A signal line that connects the signal processing circuit and one end of the output side via is wired in the wiring layer. | 2022-08-04 |
20220246666 | IMAGING ELEMENT AND IMAGING DEVICE - Leakage of incident light to a charge holding part is reduced in a back surface irradiation type imaging element. The imaging element includes a photoelectric conversion part, a reflection part, and a reflection part formation member. The photoelectric conversion part is formed in a semiconductor substrate and performs photoelectric conversion of incident light. The reflection part is disposed in a front surface of the semiconductor substrate, which is different from a surface on which the incident light is incident, to reflect transmitted light transmitted through the photoelectric conversion part to the photoelectric conversion part. The reflection part formation member has a bottom surface disposed adjacent to the front surface of the semiconductor substrate and a side on which the reflection part is formed. | 2022-08-04 |
20220246667 | SEMICONDUCTOR STRUCTURE AND THE MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor structure for forming a CMOS image sensor. The semiconductor structure includes at least a photodiode formed in the substrate for collecting photoelectrons, and the photodiode has a pinning layer, a first doped region and a second doped region in order from top to bottom in a height direction of the substrate. The semiconductor structure further includes a third doped region located in the substrate corresponding to a laterally extending region of the second doped region. The first doped region has an ion doping concentration greater than the ion doping concentration of the second doped region, the ion doping concentration of the second doped region is greater than the ion doping concentration of the third doped region, and the third doped region is in contact with the second doped region after diffusion. The present invention also provides a method of manufacturing the above-described semiconductor structure. | 2022-08-04 |
20220246668 | SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS - A semiconductor device including a first semiconductor section including a first wiring layer at one side thereof, the first semiconductor section further including a photodiode, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together, a third semiconductor section including a third wiring layer at one side thereof, the second and the third semiconductor sections being secured together such the first semiconductor section, second semiconductor section, and the third semiconductor section are stacked together, and a first conductive material electrically connecting at least two of (i) the first wiring layer, (ii) the second wiring layer, and (iii) the third wiring layer such that the electrically connected wiring layers are in electrical communication. | 2022-08-04 |
20220246669 | ONE-PIECE DEVICE FOR DETECTING PARTICLES WITH SEMICONDUCTOR MATERIAL - A one-piece device for detecting particles with semiconductor material includes a substrate layer and at least one additional layer disposed on a first face of the substrate layer so as to form at least one first detector comprising a first space charge zone through which a beam of particles passes and first collector means for charge carriers produced by this passage. It further includes at least one other additional layer disposed on a second face of the same substrate layer, opposite the first face, so as to form at least one second detector comprising a second space charge zone through which the beam of particles also passes and second collector means for charge carriers produced by this passage. | 2022-08-04 |
20220246670 | INTEGRATED STRUCTURE FOR AN OPTOELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME - An integrated structure for an optoelectronic device and a method of fabricating an integrated structure for an optoelectronic device. The method comprises the steps of providing a complementary metal-oxide-semiconductor, CMOS, backplane comprising a driver circuit for the optoelectronic device; and providing a plurality of optical elements on the CMOS backplane, wherein the plurality of optical elements are based on a material system different from CMOS and are disposed in different device layers; wherein a first bonding dielectric is provided between the CMOS backplane and a first one of the different device layers for monolithic integration; and wherein a second bonding dielectric is provided between respective ones of the different device layers for monolithic integration, the second bonding dielectric being transparent. | 2022-08-04 |
20220246671 | MICRO LIGHT EMITTING DIODE DISPLAY PANEL - A micro light-emitting diode display panel includes a substrate, at least one light-emitting element, a reflective layer and a light-absorbing layer. The at least one light-emitting element is disposed on the substrate to define at least one pixel, and each light-emitting element includes micro light-emitting diodes. The reflective layer is disposed on the substrate and located between the micro light-emitting diodes. The reflective layer has cavities surrounding the micro light-emitting diodes, such that a thickness of a portion of the reflective layer close to any one of the micro light-emitting diodes is greater than a thickness of a portion of the reflective layer away from the corresponding micro light-emitting diode. The light-absorbing layer is at least disposed in the cavities of the reflective layer. | 2022-08-04 |
20220246672 | DISPLAY MODULE AND MANUFACTURING METHOD THEREOF - A display module is disclosed. The display module includes pixels provided on the substrate, one of which includes: inorganic light emitting elements configured to emit light of a same color; light dispersing layers provided on light emitting surfaces of the inorganic light emitting elements; color conversion layers provided on the light dispersing layers; and color filters provided on the color conversion layers. When viewed from above an upper surface of the substrate, the light dispersing layers are larger than the inorganic light emitting elements. | 2022-08-04 |
20220246673 | DISPLAY MODULE AND MANUFACTURING METHOD THEREOF - A display module includes a substrate, and a plurality of pixels provided on the substrate, wherein each of the plurality of pixels includes a first inorganic light emitting element including a distributed Bragg reflectors (DBR) layer, a second inorganic light emitting element including a DBR layer, a third inorganic light emitting element, a first color conversion layer provided adjacent to the first inorganic light emitting element, a second color conversion layer provided adjacent to the second inorganic light emitting element, and a first color filter provided adjacent to the first color conversion layer, a second color filter provided adjacent to the second color conversion layer, wherein a size of the first color conversion layer is larger than a size of the first inorganic light emitting element, and a size of the second color conversion layer is larger than a size of the second inorganic light emitting element. | 2022-08-04 |
20220246674 | DISPLAY DEVICE - A display device including a first substrate structure, a second substrate structure and an adhesive layer is provided by the present disclosure. The first substrate structure includes a first recess. The second substrate structure is disposed opposite to the first substrate structure. The adhesive layer is sandwiched between the first substrate structure and the second substrate structure, wherein a part of the adhesive layer is filled in the first recess. | 2022-08-04 |
20220246675 | LIGHT-EMITTING DEVICE AND DISPLAY APPARATUS INCLUDING THE SAME - Provided is a light-emitting device including a plurality of light-emitting cells, each of the plurality of light-emitting cells being configured to independently emit light, a common semiconductor layer provided on the plurality of light-emitting cells, a first electrode provided on the common semiconductor layer, and a plurality of second electrodes provided spaced apart from the first electrode and respectively provided on the plurality of light-emitting cells. | 2022-08-04 |
20220246676 | LIGHT-EMITTING DEVICE - This disclosure discloses a light-emitting display module display. The light-emitting display module comprises: a board; and a plurality of light-emitting diode modules arranged in an array configuration on the board; wherein one of the light-emitting diode modules comprises a plurality of encapsulated light-emitting units spaced apart from each other; and one of the encapsulated light-emitting units comprises a plurality of optoelectronic units, a first supporting, and a fence; and wherein the plurality of optoelectronic units are covered by the first supporting structure, and the fence surrounds the first supporting structure and the plurality of optoelectronic units. | 2022-08-04 |
20220246677 | SINGLE LINE QUBIT CONTROL - A quantum computing device includes: a qubit; a single XYZ control line, in which the qubit and the single control line are configured and arranged such that, during operation of the quantum computing device, the single XYZ control line allows coupling of an XY qubit control flux bias, from the single XYZ control line to the qubit, over a first frequency range at a first predetermined effective coupling strength, and coupling of a Z qubit control flux bias, from the single XYZ control line to the qubit, over a second frequency range at a second predetermined effective coupling strength. | 2022-08-04 |
20220246678 | SPACER-DEFINED BACK-END TRANSISTOR AS MEMORY SELECTOR - The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device comprises a substrate and a lower interconnect metal layer disposed over the substrate. A selecting transistor is disposed over the lower interconnect metal layer. A memory cell is disposed over the selecting transistor and comprises a bottom electrode electrically connected to the selecting transistor, a data storage structure disposed over the bottom electrode, and a top electrode disposed over the data storage structure. | 2022-08-04 |
20220246679 | VARIABLE RESISTANCE MEMORY DEVICE - A variable resistance memory device includes a support layer including an insulating material; a variable resistance layer on the support layer and including a variable resistance material; a capping layer between the support layer and the variable resistance layer and protecting the variable resistance layer; a channel layer on the variable resistance layer; a gate insulating layer on the channel layer; and a plurality of gate electrodes and a plurality of insulators alternately and repeatedly arranged on the gate insulating layer in a first direction parallel with the channel layer. The capping layer may maintain oxygen vacancies formed in the variable resistance layer. | 2022-08-04 |
20220246680 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device and method of forming the same are provided. The semiconductor device includes a first conductive line over a substrate and a memory structure over the first conductive line. The memory structure is electrically coupled to the first conductive line through a conductive via. A spacer layer is laterally aside the memory structure and covers sidewalls of the memory structure. A first dielectric layer is on the spacer layer and laterally aside the memory structure. A second dielectric layer is on the memory structure, the spacer layer and the first dielectric layer. A second conductive line penetrates through the second dielectric layer, the first dielectric layer and the spacer layer to electrically couple to the memory structure. The second conductive line includes a body part at least partially embedded in the second dielectric layer and an extension part underlying the body part and laterally protruding from a sidewall of the body part. The extension part is electrically connected to an upper electrode of the memory structure and surrounded by the spacer layer. | 2022-08-04 |
20220246681 | METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a first control logic region comprising first control logic devices, and a first memory array region vertically overlying the first control logic region and comprising an array of vertically extending strings of memory cells. An additional microelectronic device structure comprising a semiconductive material is attached to an upper surface of the microelectronic device structure. A portion of the semiconductive material is removed. A second control logic region is formed over the first memory array region. The second control logic region comprises second control logic devices and a remaining portion of the semiconductive material. A second memory array region is formed over the second control logic region. The second memory array region comprises an array of resistance variable memory cells. Microelectronic devices, memory devices, and electronic systems are also described. | 2022-08-04 |
20220246682 | METHOD TO PRODUCE 3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH MEMORY - A method for producing a 3D semiconductor device, the method comprising: providing a first level, said first level comprising a first single crystal layer; forming first alignment marks and control circuits in and/or on said first level, wherein said control circuits comprise first single crystal transistors, and wherein said control circuits comprise at least two interconnection metal layers; forming at least one second level disposed on top of said control circuits; performing a first etch step into said second level; and performing additional processing steps to form a plurality of first memory cells within said second level, wherein each of said memory cells comprise at least one second transistors, and wherein said additional processing steps comprise depositing a gate electrode for said second transistors. | 2022-08-04 |
20220246683 | SOLID-STATE IMAGING ELEMENT AND SOLID-STATE IMAGING APPARATUS - A solid-state imaging element according to an embodiment of the present disclosure includes: a photoelectric conversion layer; an insulation layer provided on one surface of the photoelectric conversion layer and having a first opening; and a pair of electrodes opposed to each other with the photoelectric conversion layer and the insulation layer interposed therebetween. Of the pair of electrodes, one electrode provided on a side on which the insulation layer is located includes a first electrode and a second electrode each of which is independent, and the first electrode is embedded in the first opening provided in the insulation layer to be electrically coupled to the photoelectric conversion layer. | 2022-08-04 |
20220246684 | DISPLAY DEVICE - A display device includes a first substrate including a first emission area emitting light of a first color, a second emission area emitting light of a second color having a peak wavelength shorter than a peak wavelength of light of the first color, and a light blocking area which blocks light; a color filter layer disposed on a surface of the first substrate; and a wavelength control layer disposed on the color filter layer and including a bank layer and a wavelength control structure. The bank layer is disposed in the light blocking area on the color filter layer. The wavelength control structure is disposed in a first opening and the second opening of the bank layer. The first opening, the second opening, and the bank hole are spaced apart from each other. The bank hole surrounds an edge of the first opening. | 2022-08-04 |
20220246685 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device with increased reliability and outgassing mitigation includes: a display element layer disposed on a substrate, the display element layer including pixels; an encapsulation layer covering the display element layer; and a touch sensor disposed on the encapsulation layer. The touch sensor includes: a first inorganic insulating layer disposed on the encapsulation layer; a first surface reinforcing layer formed by performing surface treatment on the first inorganic insulating layer and disposed on the first inorganic insulating layer; a first conductive layer disposed on the first surface reinforcing layer; a first organic insulating layer covering the first conductive layer; and a second conductive layer disposed on the first organic insulating layer and connected to the first conductive layer while penetrating the first organic insulating layer. | 2022-08-04 |
20220246686 | DISPLAY DEVICE - A display device includes: a display panel including a base substrate having a display region and a hole region included in the display region; a touch sensor including a light blocking member disposed on the display panel, a first sensing insulating layer covering the light blocking member, a sensing electrode layer disposed on the first sensing insulating layer, and a second sensing insulating layer covering the sensing electrode layer; a polarizing layer disposed on the touch sensor; and a cover window disposed on the polarizing layer. At least one of the first sensing insulating layer and the second sensing insulating layer exposes at least a portion of the hole region. | 2022-08-04 |
20220246687 | DISPLAY APPARATUS - A display apparatus includes a substrate including a main display area and an auxiliary display area, the auxiliary display area including a component area and a middle area, a main pixel circuit and a main display element connected to the main pixel circuit, the main pixel circuit and the main display element being arranged on the main display area, a first auxiliary display element arranged on the component area, a first auxiliary pixel circuit, a second auxiliary pixel circuit, and a second auxiliary display element connected to the second auxiliary pixel circuit, wherein the first auxiliary pixel circuit, the second auxiliary pixel circuit, and the second auxiliary display element are arranged on the middle area, and a connecting line connecting the first auxiliary display element to the first auxiliary pixel circuit. | 2022-08-04 |
20220246688 | DISPLAY APPARATUS - A display apparatus includes a substrate including a component area including a first auxiliary display area and a transmission area and a main display area, a first main pixel circuit disposed in the main display area, a first main conductive line disposed in the main display area and electrically connected to the first main pixel circuit, a first auxiliary pixel circuit disposed in the first auxiliary display area, a first auxiliary conductive line disposed in the first auxiliary display area and electrically connected to the first auxiliary pixel circuit, and a first connection line disposed in the component area, at least partially overlapping the transmission area, and electrically connecting the first main conductive line to the first auxiliary conductive line. | 2022-08-04 |
20220246689 | DISPLAY DEVICE - A display device includes a substrate including a first display area and a second display area, first pixels disposed on the substrate in the first display area, a functional module disposed below the substrate in the second display area, and a light block layer disposed on the functional module. The light block layer includes patterns disposed in a matrix in the second display area. The second display area includes a transmission area as an area in the second display area not including the light block layer. Each of the patterns include a main part having a substantially rectangular shape with substantially rounded corners and line parts substantially curved away from the main part. | 2022-08-04 |
20220246690 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A display device includes a first substrate including a display area in which a plurality of pixels are arranged and a light transmitting area disposed in the display area, an interlayer insulating layer covering the display area and exposing the light transmitting area, an inner sidewall of the interlayer insulating layer defining the light transmitting area, and an inorganic film disposed directly on the first substrate in the light transmitting area and overlapping the entire light transmitting area. A size of the light transmitting area is larger than a size of a pixel of the plurality of pixels. | 2022-08-04 |
20220246691 | DISPLAY PANEL, DISPLAY APPARATUS, LIGHT EMITTING ELEMENT, AND METHOD OF FABRICATING DISPLAY PANEL - A light emitting element, includes a first light emitting layer and a second light emitting layer sequentially stacked; and an intermediate layer between the first light emitting layer and the second light emitting layer, and being in direct contact with the first light emitting layer on one side and in direct contact with the second light emitting layer on another side. Each of the intermediate layer, the first light emitting layer, and the second light emitting layer includes a same host material. The intermediate layer is a non-light emitting layer, and is an undoped layer absent of a dopant for emitting light. The light emitting element is configured to emit a composite light including the first light of the first wavelength range and the second light of the second wavelength range. The first wavelength range includes wavelength longer than the second wavelength range. | 2022-08-04 |
20220246692 | PIXEL ARRANGEMENT, MANUFACTURING METHOD THEREOF, DISPLAY PANEL, DISPLAY DEVICE AND MASK - A pixel arrangement including: first groups of sub-pixels arranged in a first direction, each of the first groups including first sub-pixels and third sub-pixels arranged alternately; and second groups of sub-pixels arranged in the first direction, each of the second groups including third sub-pixels and second sub-pixels arranged alternately. The first groups and the second groups are alternately arranged in a second direction perpendicular to the first direction. The first groups and the second groups are arranged to form third groups of sub-pixels arranged in the second direction and fourth groups of sub-pixels arranged in the second direction. The third groups and the fourth groups are alternately arranged in the first direction. Each of the third groups includes first sub-pixels and third sub-pixels arranged alternately. Each of the fourth groups includes third sub-pixels and second sub-pixels arranged alternately. | 2022-08-04 |
20220246693 | LIGHT-EMITTING DEVICE, DISPLAY DEVICE, AND METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE - This light-emitting device includes: a light-emitting diode including a light-emitting layer of quantum dots or an organic light-emitting material; and a protection diode located adjacent to, and connected in parallel with, the light-emitting diode, wherein the protection diode is operated in reverse bias to protect the light-emitting diode. | 2022-08-04 |
20220246694 | DISPLAY APPARATUS, DISPLAY MODULE, AND ELECTRONIC DEVICE - A display apparatus having a photosensing function is provided. The display apparatus includes a first pixel circuit and a second pixel circuit. The first pixel circuit includes a light-receiving device, a first transistor, and a second transistor. The second pixel circuit includes a light-emitting device. The light-receiving device includes a first pixel electrode, an active layer, and a common electrode. The light-emitting device includes a second pixel electrode, a light-emitting layer, and the common electrode. The active layer is positioned over the first pixel electrode and includes a first organic compound. The light-emitting layer is positioned over the second pixel electrode and includes a second organic compound different from the first organic compound. The common electrode includes a portion overlapping with the first pixel electrode with the active layer therebetween and a portion overlapping with the second pixel electrode with the light-emitting layer therebetween. The first transistor includes low-temperature polysilicon as a semiconductor layer and the second transistor includes a metal oxide as a semiconductor layer. | 2022-08-04 |
20220246695 | TEXTURE RECOGNITION APPARATUS AND MANUFACTURING METHOD THEREOF - A texture recognition apparatus and a manufacturing method thereof are provided. The texture recognition apparatus includes a base substrate, a light source array and an image sensor array. The light source array is on a side of the base substrate and includes a plurality of light sources; the image sensor array is on a side of the base substrate and includes a plurality of image sensors, the plurality of image sensors are configured to receive light emitted from the plurality of light sources and reflected to the plurality of image sensors by a texture for texture collection; at least part of an photosensitive element of at least one image sensor of the plurality of image sensors is inclined relative to a surface of the base substrate. | 2022-08-04 |
20220246696 | ELECTROLUMINESCENCE DISPLAY DEVICE HAVING A THROUGH-HOLE IN DISPLAY AREA - An electroluminescence display device including a substrate having a display area and a non-display area arranged near the display area, a light emitting diode in the display area, an encapsulation layer on the light emitting diode, the encapsulation layer including a first inorganic encapsulation layer, a second inorganic encapsulation layer and an organic encapsulation layer disposed between the first and second inorganic encapsulation layers, a through-hole arranged inside the display area to penetrate the substrate, an inner dam surrounding the through-hole, a trench arranged between the inner dam and the through-hole, and an etch-stopper arranged between the trench and the through-hole, wherein the first inorganic encapsulation layer and the second inorganic encapsulation layer are disposed on the display area and covering the inner dam and the trench. | 2022-08-04 |
20220246697 | DISPLAY PANEL AND DISPLAY DEVICE - Embodiments of the present disclosure disclose a display panel and a display device. The display panel includes: a base substrate, a light-emitting device located on the base substrate, a first flat layer located on a side of the light-emitting device away from the base substrate, and a black matrix located on a side of the first flat layer away from the base substrate, wherein the black matrix has a plurality of opening regions, and color filters are arranged in corresponding opening regions; the color filters are configured to filter external incident light; and the first flat layer has a plurality of first concave faces arranged corresponding to the opening regions, the color filters fill the first concave faces, and the color filters further cover peripheral regions of the first concave faces. | 2022-08-04 |
20220246698 | DISPLAY APPARATUS - A display apparatus includes: a substrate; a | 2022-08-04 |
20220246699 | Array Substrate, Method of Fabricating Array Substrate, Display Panel, and Method of Fabricating Display Panel - The present disclosure generally relates to the field of display technology, and in particular, to an array substrate, a method of fabricating the array substrate, a display panel including the array substrate, and a method of fabricating the display panel. An array substrate includes: a base substrate; an electrode layer provided on the substrate; a first pixel defining layer on the electrode layer defining a plurality of pixel regions; and a second pixel defining layer on the first pixel defining layer, wherein the second pixel defining layer has a plurality of first grooves and a plurality of second grooves alternately arranged between two adjacent rows of pixel regions. | 2022-08-04 |
20220246700 | Organic Light Emitting Display Panel and Organic Light Emitting Display Device Including the Same - A display panel and an organic light emitting display device with enhanced light extraction efficiency is described. The display panel and the display device include an insulating film including at least one concave portion, a first electrode disposed to cover the concave portion, a bank including a first part on the first electrode and overlapping a part of the flat portion of the concave portion, a second part extending from the first part and overlapping an inclined portion of the concave portion, and a third part extending from the second part and disposed on the side portion, an organic layer overlapping the concave portion, and a second electrode on the organic layer and the bank. A width of the first part of the bank is wider than a width of the second part of the bank. Thus, it is possible to provide a display device with enhanced light extraction efficiency. | 2022-08-04 |
20220246701 | DISPLAY DEVICE - A display device includes: a substrate including a display area and a peripheral area surrounding an opening; a transistor disposed in the display area; a first electrode electrically connected to the transistor; an auxiliary layer disposed between the transistor and the first electrode and overlapping the first electrode in a plan view; a pixel definition layer overlapping the first electrode and an edge of the auxiliary layer in the plan view; an intermediate layer, an emission layer, and a second electrode disposed on the first electrode; at least one or more dams disposed on the peripheral area; and an encapsulation layer disposed on the light-emitting element. The intermediate layer includes a cutting part disposed between the display area and the opening. | 2022-08-04 |
20220246702 | DISPLAY DEVICE AND MANUFACTURING METHOD FOR THE SAME - A display device includes: a substrate; a first signal line and a second signal line disposed on the substrate; and an interlayer-insulating layer disposed between the first signal line and the second signal line. The interlayer-insulating layer includes a first portion and a second portion having different heights measured from a surface of the substrate along a first direction that is perpendicular to the surface of the substrate, an upper surface of the first portion of the interlayer-insulating layer is flat, a surface of the second portion of the interlayer-insulating layer is flat, a height of the first portion is lower than a height of the second portion, the interlayer-insulating layer defines a contact hole, and the contact hole is disposed in the first portion of the interlayer-insulating layer. | 2022-08-04 |
20220246703 | ORGANIC EL DISPLAY DEVICE AND MANUFACTURING METHOD FOR ORGANIC EL DISPLAY DEVICE - This organic-EL display apparatus comprises: a substrate with a drive circuit comprising a thin-film transistor (TFT), a planarizing layer to cover the drive circuit, and an organic light-emitting element formed upon the surface of the planarizing layer facing the opposite direction from the drive circuit. The TFT comprises a drain electrode, a source electrode, and a semiconductor layer that includes regions to be a channel of TFT and partially overlaps with the source and drain electrodes. Respective parts of a first conductor layer forming the drain electrode and a second conductor layer forming the source electrode are arranged in an alternating manner along a prescribed direction, and the region to be the channel is sandwiched between the part of the first conductor layer and the part of the second conductor layer. | 2022-08-04 |
20220246704 | DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - A display apparatus includes a plurality of pixels. Each pixel of the pixels includes a thin film transistor, a first insulating pattern positioned on the thin film transistor, a pixel electrode positioned on the first insulating pattern, and a second insulating pattern covering an edge of the pixel electrode and contacting an edge of the first insulating pattern. | 2022-08-04 |
20220246705 | TRANSISTOR AND DISPLAY DEVICE INCLUDING THE SAME - A transistor may include an active layer including a first end area, a middle area adjacent to the first end area, and a second end area spaced from the first end area by the middle area, a first electrode on the active layer, overlapping the first end area, and connected to the first end area through a first contact hole, an upper gate electrode on the active layer, overlapping the middle area, at a same layer as the first electrode, and to receive a gate signal and a lower gate electrode under the active layer, overlapping the first contact hole and the middle area, and to receive the gate signal. | 2022-08-04 |
20220246706 | DISPLAY DEVICE - A display device includes a substrate, a semiconductor layer on the substrate and including a channel area of a first transistor, a first insulating layer on the semiconductor layer, a first conductive layer on the first insulating layer and including a plurality of split patterns which overlap with the channel area of the first transistor, a second insulating layer on the first conductive layer, a shield pattern on the second insulating layer and having a constant voltage applied thereto, a third insulating layer on the second conductive layer, and a third conductive layer on the third insulating layer and including a scan connecting pattern which electrically connects the split patterns to each other and overlaps with the semiconductor layer in an overlapping area different from the channel area. | 2022-08-04 |
20220246707 | ORGANIC LIGHT-EMITTING ELEMENT AND ORGANIC LIGHT-EMITTING DISPLAY DEVICE INCLUDING THE SAME - Provided is an organic light-emitting element including a substrate, a thin film transistor provided on the substrate, a first insulating layer provided on the substrate and the thin film transistor, a reflective layer provided on the first insulating layer, the reflective layer being electrically connected to a first portion of the thin film transistor, a second insulating layer provided on the first insulating layer and the reflective layer, an anode provided on the second insulating layer, the anode being electrically connected to a second portion of the thin film transistor that is different from the first portion of the thin film transistor, an emission layer provided on the anode, and a cathode provided on the emission layer, wherein the reflective layer and the anode overlap each other with the second insulating layer interposed therebetween to form a storage capacitor. | 2022-08-04 |
20220246708 | METHOD OF MANUFACTURING METAL OXIDE FILM AND DISPLAY DEVICE INCLUDING METAL OXIDE FILM - A method of manufacturing a metal oxide film includes injecting a reaction gas and metal precursors into a chamber, forming a first metal precursor film on a substrate in a plasma OFF state, forming a first sub-metal oxide film by oxidizing the first metal precursor film in a plasma ON state, and forming a second metal precursor film on the first sub-metal oxide film in the plasma OFF state, where the metal oxide film has an amorphous phase, a thickness of about 20 nanometer (nm) to about 130 nm, and a dielectric constant of about 10 to about 50. | 2022-08-04 |
20220246709 | OLED DISPLAY SUBSTRATE AND METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE - The present disclosure provides an OLED display substrate, a method for preparing the same, and a flexible display device, and belongs to the technical field of display. The OLED display substrate includes a base substrate, and a thin film transistor, a first electrode and a light emitting layer sequentially arranged on the base substrate, the thin film transistor including an active layer, in which the OLED display substrate further includes a light shielding layer arranged between the active layer and the first electrode, and the light shielding layer also serves as an insulating layer of the OLED display substrate. The technical solution of the present disclosure is capable of ensuring the display effect of the display device. | 2022-08-04 |
20220246710 | LIGHT EMITTING DISPLAY DEVICE - An embodiment provides a light emitting display device, including a display panel including a display area, wherein the display area of the display panel includes: a transparent display area; an intermediate display area that is disposed at one side or both sides of the transparent display area along a first direction and includes a pixel circuit part for a transparent display area; and a normal display area, and wherein the transparent display area includes: a first anode; and a transmission transistor that transmits an emission current outputted from the pixel circuit part for the transparent display area to the first anode. | 2022-08-04 |
20220246711 | DISPLAY PANEL, METHOD FOR REPAIRING DISPLAY PANEL, AND DISPLAY APPARATUS - A display panel, a method for repairing the same, and a display apparatus are provided. The display panel includes pixels, signal lines, and pixel repair structures. The pixel includes a first pixel circuit and a light-emitting device. The signal line extends in a first direction and is coupled to the first pixel circuit. The pixel repair structures include second pixel circuits, first and second repair assemblies, and first compensation structures. The first compensation structures and the signal lines are in one-to-one correspondence. The first repair assembly partially overlaps at least one signal line. The second repair assembly partially overlaps at least one light-emitting device. The first repair assembly includes a first repair line coupled to a first input terminal of the second pixel circuit. An output terminal of the second pixel circuit is coupled to at least one second repair line of at least one second repair assembly. | 2022-08-04 |
20220246712 | DISPLAY DEVICE - A display device may include a display panel including a display area, a non-display area which may be disposed on a periphery of the display area, and a pad area which may be disposed on one side of the non-display area. The display panel may include data lines disposed in the display area of the display panel along a second direction which intersects a first direction, and connection lines disposed in the display area of the display panel along the first direction. A first data line among the data lines may be connected to a first connection line among the connection lines. | 2022-08-04 |
20220246713 | DISPLAY APPARATUS - A display apparatus includes a substrate, a wire having an inner edge including first and second portions, a first insulating layer covering a portion of the substrate, and a second insulating layer. The portion of the substrate covered by the first insulating layer is closer to a center of the substrate than the wire, the first insulating layer covers a part of the first portion of the wire and a part of the second portion of the wire, and a first end of the first insulating layer is disposed on the wire. The second insulating layer covers the first insulating layer and has a second end disposed on the wire. A distance between the first end and the second end covering the first portion of the wire is different from a distance between the first end and the second end covering the second portion of the wire. | 2022-08-04 |
20220246714 | LOW TEMPERATURE ROUTE FOR EPITAXIAL INTEGRATION OF PEROVSKITES ON SILICON - The present disclosure provides a layering structure that permits integration of epitaxially oriented perovskite oxides, such as bismuth ferrite (BiFeO | 2022-08-04 |
20220246715 | CAPACITOR UNIT AND MANUFACTURING PROCESS THEREOF - A capacitor unit and a manufacturing process thereof are provided. The manufacturing process includes: providing a carrier; forming a metallic layer on the carrier, defining a plurality of metallic blocks in the metallic layer, and forming a middle stacking structure on each of the metallic blocks, wherein the middle stacking structure includes a first capacitance conductive layer, a second capacitance conductive layer, and a capacitance insulation layer located between the first and second capacitance conductive layers, wherein the first capacitance conductive layer is electrically connected to the corresponding one of the metallic blocks; and removing the carrier to expose the metallic blocks so as to form a plurality of independent capacitor units, so as to fabricate double sided capacitor units with high capacitance. | 2022-08-04 |
20220246716 | CAPACITOR FOR DYNAMIC RANDOM ACCESS MEMORY, DRAM INCLUDING THE SAME AND METHODS OF FABRICATING THEREOF - Disclosed are a capacitor for DRAM, a DRAM including the same, and a method of fabricating the same. The DRAM capacitor according to an embodiment may include a first electrode of the DRAM; a second electrode spaced apart from the first electrode; and a dielectric layer including a HfZrO film disposed between the first electrode and the second electrode. The HfZrO film may have an intermediate state corresponding to a phase transition region between a first state in which a tetragonal crystalline phase with anti-ferroelectricity property or a tetragonal crystalline phase is dominant, and a second state in which the orthorhombic crystalline phase with anti-ferroelectricity property or the orthorhombic crystalline phase is dominant. The HfZrO film may include both of the tetragonal crystalline phase and the orthorhombic crystalline phase. The HfZrO film maintains an intermediate state corresponding to the phase transition region within the operating voltage range of the capacitor. | 2022-08-04 |
20220246717 | HIGH ASPECT RATIO NON-PLANAR CAPACITORS FORMED VIA CAVITY FILL - A method for forming non-planar capacitors of desired dimensions is disclosed. The method is based on providing a three-dimensional structure of a first material over a substrate, enclosing the structure with a second material that is sufficiently etch-selective with respect to the first material, and then performing a wet etch to remove most of the first material but not the second material, thus forming a cavity within the second material. Shape and dimensions of the cavity are comparable to those desired for the final non-planar capacitor. At least one electrode of a capacitor may then be formed within the cavity. Using the etch selectivity of the first and second materials advantageously allows applying wet etch techniques for forming high aspect ratio openings in fabricating non-planar capacitors, which is easier and more reliable than relying on dry etch techniques. | 2022-08-04 |
20220246718 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a metal layer, a semiconductor layer in electrical contact with the metal layer, a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure, and a metal compound layer disposed between the 2D material layer and the semiconductor layer. | 2022-08-04 |
20220246719 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A silicon carbide semiconductor device includes an electric field relaxation layer disposed in a drift layer. The electric field relaxation layer includes a first region having a second conductivity type and disposed at a position deeper than trenches, and a second region having the second conductivity type and disposed between the adjacent trenches to be away from a side surface of each of the adjacent trenches. Each of the first region and the second region is made of an ion implantation layer. The electric field relaxation layer further includes a double implantation region in which the first region and the second region overlap with each other, and the electric field relaxation layer has a peak of a second conductivity type impurity concentration in the double implantation region. | 2022-08-04 |
20220246720 | SUPERJUNCTION REVERSE CONDUCTING INSULATED GATE BIPOLAR TRANSISTOR AND ELECTRIC AUTOMOBILE MOTOR CONTROL UNIT - This application provides a superjunction reverse conducting insulated gate bipolar transistor and an electric automobile motor control unit. The superjunction reverse conducting insulated gate bipolar transistor includes: an N-type buffer layer; a superjunction structure layer formed on a first principal surface of the N-type buffer layer, where the superjunction structure layer includes P-type drift regions and N-type drift regions that are alternately arranged in a first direction; a front-side component formed on the superjunction structure layer; a collector layer formed on a second principal surface of the N-type buffer layer, where the collector layer includes P+ collectors and N+ collectors that are alternately arranged in the first direction; and a collector electrode layer formed on the collector layer. | 2022-08-04 |
20220246721 | CAVITY SPACER FOR NANOWIRE TRANSISTORS - A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain. | 2022-08-04 |
20220246722 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A layout structure of a standard cell using vertical nanowire (VNW) FETs is provided. A p-type transistor region in which VNW FETs are formed and an n-type transistor region in which VNW FETs are formed are provided between a power supply interconnect VDD and a power supply interconnect VSS. A local interconnect is placed across the p-type transistor region and the n-type transistor region. The top electrode of a transistor that is a dummy VNW FET is connected with the local interconnect. | 2022-08-04 |
20220246723 | SILICON CARBIDE VERTICAL CONDUCTION MOSFET DEVICE FOR POWER APPLICATIONS AND MANUFACTURING PROCESS THEREOF - A vertical conduction MOSFET device includes a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body. The source region has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level. | 2022-08-04 |
20220246724 | SEMICONDUCTOR DEVICE HAVING ASYMMETRICAL SOURCE/DRAIN - A semiconductor device includes a substrate, a first active fin on the substrate, the first active fin including a first side surface and a second side surface opposing the first side surface, a second active fin on the substrate, the second active fin including a third side surface facing the second side surface and a fourth side surface opposing the third side surface of the second active fin, a first isolation layer on the first side surface of the first active fin, a second isolation layer between the second side surface of the first active fin and the third side surface of the second active fin, a third isolation layer on the fourth side surface of the second active fin and a merged source/drain on the first and second active fins. | 2022-08-04 |
20220246725 | SEMICONDUCTOR DEVICES WITH GRADED DOPANT REGIONS - Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICs, improvement in refresh time for DRAMs, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFETs, and a host of other applications. | 2022-08-04 |
20220246726 | GERMANIUM TIN GATE-ALL-AROUND DEVICE - The present disclosure describes a semiconductor device includes a substrate, a buffer layer on the substrate, and a stacked fin structure on the buffer layer. The buffer layer can include germanium, and the stacked fin structure can include a semiconductor layer with germanium and tin. The semiconductor device further includes a gate structure wrapped around a portion of the semiconductor layer and an epitaxial structure on the buffer layer and in contact with the semiconductor layer. The epitaxial structure includes germanium and tin. | 2022-08-04 |
20220246727 | APPARATUSES INCLUDING PASSING WORD LINES COMPRISING A BAND OFFSET MATERIAL, AND RELATED METHODS AND SYSTEMS - An apparatus comprises active word lines extending within a semiconductive material, passing word lines extending adjacent to the active word lines within the semiconductive material, isolation regions adjacent to the passing word lines, and a band offset material adjacent to the passing word lines and the isolation regions. The semiconductive material exhibits a first bandgap and the band offset material exhibits a second, different bandgap. Related methods and systems are also described. | 2022-08-04 |
20220246728 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate including a peripheral region, a first active pattern on the peripheral region, the first active pattern having an upper portion including first semiconductor patterns and second semiconductor patterns, which are alternately stacked, a first gate electrode intersecting the first active pattern, a pair of first source/drain patterns provided at both sides of the first gate electrode, respectively, a first capping layer on the first active pattern, a second capping layer on the first capping layer, and a first gate insulating layer between the second capping layer and the first gate electrode. The first capping layer is between a sidewall of the first active pattern and the second capping layer. A concentration of germanium (Ge) of the first capping layer is greater than a concentration of germanium of the second capping layer. | 2022-08-04 |
20220246729 | SILICON CARBIDE VERTICAL CONDUCTION MOSFET DEVICE AND MANUFACTURING PROCESS THEREOF - A vertical conduction MOSFET device includes a body of silicon carbide, which has a first type of conductivity and a face. A superficial body region of a second type of conductivity has a first doping level and extends into the body to a first depth , and has a first width. A source region of the first type of conductivity extends into the superficial body region to a second depth, and has a second width. The second depth is smaller than the first depth and the second width is smaller than the first width. A deep body region of the second type of conductivity has a second doping level and extends into the body, at a distance from the face of the body and in direct electrical contact with the superficial body region, and the second doping level is higher than the first doping level. | 2022-08-04 |
20220246730 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device has a silicon carbide substrate, a first insulator, a first electrode, and a second electrode. The silicon carbide substrate includes a first impurity region, a second impurity region, a third impurity region, a first superjunction portion, a fourth impurity region, a fifth impurity region, a sixth impurity region, and a second superjunction portion. The first superjunction portion has a first region and a second region. The second superjunction portion has a third region and a fourth region. In a direction perpendicular to a second main surface, a bottom surface of a first trench is located between a second end surface and the second main surface and is located between a fourth end surface and the second main surface. | 2022-08-04 |
20220246731 | COMPOSITE OXIDE SEMICONDUCTOR AND TRANSISTOR - A novel material is provided. A composite oxide semiconductor includes a first region and a second region. The first region contains indium. The second region contains an element M (the element M is one or more of Ga, Al, Hf, Y, and Sn). The first region and the second region are arranged in a mosaic pattern. The composite oxide semiconductor further includes a third region. The element M is gallium. The first region contains indium oxide or indium zinc oxide. The second region contains gallium oxide or gallium zinc oxide. The third region contains zinc oxide. | 2022-08-04 |
20220246732 | RECESSED ACCESS DEVICE - A method of manufacturing a recessed access device includes the following operations. A first trench is formed in a substrate. A first gate oxide layer is formed on an inner surface of the first trench. A sacrificial layer is formed in a bottom of the first trench, in which a portion of the first gate oxide layer above the sacrificial layer is exposed from the first trench. The portion of the first gate oxide layer is removed to expose a sidewall of the first trench. The sidewall of the first trench is oxidized to form a second gate oxide layer within the substrate, in which the second gate oxide layer is in contact with the first gate oxide layer. The sacrificial layer is removed to form a second trench. | 2022-08-04 |
20220246733 | SEMICONDUCTOR DEVICE - An object of the disclosure is to provide a semiconductor device with low-loss and suppressed leakage current, which is particularly useful for power devices. A semiconductor device including a semiconductor layer, a dielectric film provided on the semiconductor layer and having an opening and provided over a distance of at least 0.25 μm from the opening, and an electrode layer provided over a part or all of the dielectric film from the inside of the opening, wherein the dielectric film has a thickness of less than 50 nm from the opening to a distance of 0.25 μm, and has relative permittivity of 5 or less. | 2022-08-04 |
20220246734 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a semiconductor part, first and second electrodes. The semiconductor part is provided between the first and second electrodes. A method of manufacturing the device includes forming the first electrode covering a back surface of a wafer after the second electrode is formed on a front surface of the wafer; forming a first groove by selectively removing the first electrode; and dividing the wafer by forming a second groove at the front surface side. The wafer includes a region to be the semiconductor part; and the first and second grooves are provided along a periphery of the region. The first groove is in communication with the first groove. The second groove has a width in a direction along the front surface of the wafer, the width of the first groove being narrower than a width of the first groove in the same direction. | 2022-08-04 |
20220246735 | BACK SIDE CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE AND CORRESPONDING MANUFACTURING PROCESS - Various embodiments provide a vertical-conduction semiconductor device that includes: a silicon substrate having a front face and a rear face; a front-side structure arranged on the front face of the substrate, having at least one current-conduction region at the front face; and a back side metal structure, arranged on the rear face of the substrate, in electrical contact with the substrate and constituted by a stack of metal layers. The back side metal structure is formed by: a first metal layer; a silicide region, interposed between the rear face of the substrate and the first metal layer and in electrical contact with the aforesaid rear face; and a second metal layer arranged on the first metal layer. | 2022-08-04 |
20220246736 | METHODS OF FORMING A MICROELECTRONIC DEVICE, AND RELATED MICROELECTRONIC DEVICES, MEMORY DEVICES, AND ELECTRONIC SYSTEMS - A microelectronic device comprises a conductive structure, a metal nitride material, and a metal silicide material. The conductive structure comprises a first portion having a first width, and a second portion under the first portion and extending into a semiconductive material. The second portion has a tapered profile defining additional widths varying from the first width at an upper boundary of the second portion to a second width less than the first width at a lower boundary of the second portion. The metal nitride material substantially surrounds outer surfaces of the first portion and the second portion of the conductive structure. The metal silicide material substantially covers outer surfaces of the metal nitride material within vertical boundaries of the second portion of the conductive structure. Related methods, memory devices, and electronic systems are also described. | 2022-08-04 |
20220246737 | OHMIC CONTACTS WITH DIRECT ACCESS PATHWAYS TO TWO-DIMENSIONAL ELECTRON SHEETS - An ohmic contact includes a first semiconductor layer a second semiconductor layer, and a heterointerface between the first semiconductor layer and the second semiconductor layer. The second semiconductor layer has a two-dimensional electron sheet region in which a two-dimensional electron sheet is formed. The ohmic contact further includes a metal terminal covering the first semiconductor layer and filling a plurality of direct access pathways that provide direct lateral contact with the two-dimensional electron sheet region. The semiconductor device is fabricated by providing the semiconductor layers, etching the direct access pathways, and depositing metal material to fill the direct access pathways and cover the semiconductor layers. The ohmic contact may be part of a high-electron-mobility transistor that achieves low contact resistance with either no annealing at all (as-deposited metal), or at an anneal temperature that is much lower than industry-standard anneal temperatures to achieve sufficiently low contact resistance. | 2022-08-04 |
20220246738 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device includes a plurality of gate structures each including a gate line extending on a fin-type active region and insulation spacers on sidewalls of the gate line; a source/drain contact between first and second gate structures, and having opposing sides that are asymmetric in the first horizontal direction; and an insulation liner on sidewalls of the source/drain contact. The source/drain contact includes a lower contact portion and an upper contact portion having a horizontal extension that extends on an upper corner of the first gate structure, the insulation liner includes a first local region between the upper corner and the horizontal extension and a second local region that is farther from the substrate than the first local region, and a thickness of the first local region is greater than that of the second local region. | 2022-08-04 |