31st week of 2022 patent applcation highlights part 70 |
Patent application number | Title | Published |
20220247340 | FAULT TOLERANT OPERATIONS OF A SIX-PHASE MACHINE - A method of operating a multi-phase electric machine includes operating a six-phase machine with six phases that are configured into a first group having a first neutral connection and a second group having a second neutral connection. The method also includes determining whether at least one of the six phases is experiencing a fault. In response to the determining, the method includes combining the first and second neutral connections to form a common neutral connection to continue operating the six-phase machine by using the remaining phase not experiencing the fault. | 2022-08-04 |
20220247341 | SYSTEMS AND METHODS FOR CONTROLLING FAN MOTORS WITH VARIABLE FREQUENCY DRIVES - A fan assembly is provided. The fan assembly includes a fan, a motor that is coupled to the fan, and a variable frequency drive (VFD) that is coupled to the motor. The motor includes a maximum rated speed that is greater than a maximum structural speed limit of the fan, and the VFD includes a current output limit configured to limit an operational speed of the motor to be less than or equal to the maximum structural speed limit of the fan. | 2022-08-04 |
20220247342 | Multi-tier Elevated Super-structural Novel Renewable Energy Infrastructures (MESNREI) - This invention is related to the field of Wind & Solar Energy applications and associated infrastructural facilities, which will be an environmental friendly set-up on a small land area for better utilisation of wind & solar resources available in that particular surroundings, harnessing increased efficiencies from the novel wind turbines plus the inventive solar shells. | 2022-08-04 |
20220247343 | THERMOELECTRIC ACTIVE STORAGE EMBEDDED HYBRID SOLAR THERMAL AND PHOTOVOLTAIC WALL MODULE - Solar collection and storage module systems as building blocks are provided to build walls or shingles of buildings to transform any buildings into stabilized power generation stations and tie to power grid to form power grid-interactive efficient buildings. The solar collection and storage module system comprises a hybrid photovoltaic and thermal panel, thermoelectric modules, thermal storage package, control system, and battery storage. The incident sunlight is partially converted into electricity directly by the photovoltaic part of the system directly, and rest part is transformed into heat which is extracted, boosted to high temperature, and stored into the thermal storage package by the thermoelectric modules operating in cooler mode at this movement. At night or in cloudy days, the stored heat flow through the thermoelectric modules, which are switched to generator mode by the control system, generating electricity. In the module system, the cogenerated heat is stored in thermal energy format and outputted in electrical energy format; the total conversion efficiency of the module system is significantly improved. When the module systems are used as wall modules or shingles to build buildings, the encapsulation properties of the buildings are substantially improved. | 2022-08-04 |
20220247344 | PHOTOVOLTAIC MODULE AND ASSEMBLY - The invention relates to a photovoltaic assembly ( | 2022-08-04 |
20220247345 | SOLAR PANEL GUARD SYSTEM - A solar panel guard system includes a guard structure including an upper edge to be disposed proximate a solar panel and a lower edge to be disposed proximate a surface that is disposed under the solar panel. The solar panel guard system further includes a bracket including a clip that removably attaches to the solar panel. The bracket includes a leg extending from the clip towards the lower edge of the guard structure, the leg forming a threaded portion. The threaded portion is to removable connect to a fastening device to secure the guard structure to the leg. | 2022-08-04 |
20220247346 | SYSTEM AND METHOD FOR CLEANING COVER GLASSES OF PHOTOVOLTAIC MODULES - In a system for cleaning cover glasses ( | 2022-08-04 |
20220247347 | DRONE SYSTEMS FOR CLEANING SOLAR PANELS AND METHODS OF USING THE SAME - The present invention provides an unmanned aerial vehicle (“UAV”) operations system for cleaning one or more designated surfaces such as a solar panel installed on a roof, or the surface of a window, wall, billboard, scoreboard, etc., which may be too high or too far away from a position on the ground which is easily and safely accessible by a person. For solar panels, such cleaning is not only for aesthetic purposes, but must be performed regularly in order to keep the solar panel functioning at peak performance. The system may also include a ground companion vehicle such as an ATV, golf cart, or the like, which can follow an approximation of the UAV's flight path and provide cleaning media and power to the UAV via a tether, allowing the UAV to clean a large number of surfaces before returning to refill or recharge. | 2022-08-04 |
20220247348 | RECEIVER FOR FREE-SPACE OPTICAL POWER BEAMING - A free-space optical power beaming device may be configured to receive a light beam from an external source. The device may include a plurality of photovoltaic elements configured to convert light to electrical energy; a plurality of electrical charge storage elements, and a light reflector element configured to reflect a light beam toward one or more of the plurality of photovoltaic elements. Each electrical charge storage element may be coupled with at least of one of the plurality of photovoltaic elements and configured to store electrical energy output from the at least one of the plurality of photovoltaic elements. In some aspects a set of the plurality of photovoltaic elements may be configured in a tilted manner. In other aspects the light reflector element may be steerable to reflect a light beam toward one or more of the plurality of photovoltaic elements to provide a desired time-averaged light intensity distribution. | 2022-08-04 |
20220247349 | SOLAR POWER GENERATION SYSTEM - A solar power generation system includes a string, an inverter, and a first shut-off device. The string includes a plurality of solar cell modules connected in series. The inverter converts DC power output from the plurality of solar cell modules to AC power. The first shut-off device is connected to electrical paths connecting the plurality of solar cell modules to each other. The string includes a plurality of solar cell module groups each including the plurality of the solar cell modules. The plurality of solar cell module groups include at least a first group and a second group connected to the first group. The first shut-off device shuts off a first electrical path connecting the first group and the second group and a second electrical path connecting the plurality of solar cell modules belonging to the first group to each other in response to a control signal from the inverter. | 2022-08-04 |
20220247350 | HEATING HEAVY EQUIPMENT - A solar panel is electrically coupled to a battery and configured to convert solar energy to electricity to charge the battery. A heating element is electrically coupled to the battery. A thermal sensor is configured to detect an ambient temperature. The thermal sensor is configured to produce a temperature stream indicative of the detected ambient temperature. A humidity sensor is configured to detect an ambient humidity. The humidity sensor is configured to produce a humidity stream indicative of the detected ambient humidity. A controller is electrically couple to the thermal sensor the humidity sensor, and the heating element. The controller is configured to receive a profile that includes an initial designated duration and an initial temperature needed for a designated machine, and produce a current for the heating element to heat the designated machine for the designated duration and temperature. | 2022-08-04 |
20220247351 | REMOTE SITE SURVEY FOR PHOTOVOLTAIC SYSTEM SITE - Remotely surveying a photovoltaic system site includes receiving a photograph uploaded by a user device; analyzing the photograph using a trained machine learning model; receiving a confidence score from the trained machine learning model; determining if the photograph includes predetermined information, the predetermined information being used to perform a remote photovoltaic (PV) system site survey remotely; and in response to a determination that the photograph does not include the predetermined information, provide specific instructions regarding the missing information, wherein the specific instructions include guidance on how to retake the photograph to capture the predetermined information. | 2022-08-04 |
20220247352 | Circuit Device And Oscillator - A circuit device includes an oscillation circuit and a processing circuit that generates capacitance control data. The oscillation circuit includes a variable capacitance circuit whose capacitance value is variably controlled based on the capacitance control data, and an oscillation frequency thereof is controlled based on the capacitance value of the variable capacitance circuit. The variable capacitance circuit includes a capacitor array. The capacitor array includes a plurality of capacitors each having a binary-weighted capacitance value, and a plurality of switches that are on-off controlled based on the capacitance control data. The processing circuit outputs the capacitance control data, which is subjected to dithering, so as to switch the capacitance value of the variable capacitance circuit between a first capacitance value and a second capacitance value in a time division manner. | 2022-08-04 |
20220247353 | MULTI-ELEMENT RESONATOR - A resonant tank includes a first capacitor formed on a semiconductor substrate, a first inductor formed on the semiconductor substrate, a second capacitor formed on the semiconductor substrate, and a second inductor formed on the semiconductor substrate. The first capacitor, the first inductor, the second capacitor, and the second inductor are connected in a ring configuration, with each capacitor connected between a pair of the inductors and with each inductor connected between a pair of the capacitors. An amplifier circuit is coupled to the resonant tank and configured to amplify a signal in the resonant tank. | 2022-08-04 |
20220247354 | OSCILLATING CIRCUIT AND ELECTRONIC DEVICE - The present disclosure provides an oscillating circuit and an electronic device; the oscillating circuit includes a capacitor charging and discharging circuit unit, a voltage comparison circuit unit and a threshold voltage generation circuit unit; the oscillating circuit uses the capacitor charging and discharging and the hysteresis effect of the capacitor charging and discharging circuit unit to achieve oscillation based on the negative feedback regulation constituted by the voltage comparison circuit unit and the threshold voltage generation circuit unit, which is different from the traditional oscillating circuit based on capacitance and inductance; the oscillating circuit does not adopts inductors, has relatively low power consumption, and outputs oscillation signals with frequencies that vary with currents., and when the oscillating circuit is used to provide clock signals for the sensor, it can be integrated with a sensor signal processing circuit to realize the miniaturization and integration of the sensor system. | 2022-08-04 |
20220247355 | ACCELERATED CHANNEL SCANNING WITH A TWO-POINT-MODULATED PHASE-LOCKED LOOP - A receiver is provided having a two-point-modulated phase-locked loop for the rapid scanning of the signal strength of a plurality of frequency channels. The two-point modulation includes a modulation of a frequency gain by an oscillator in the phase-locked loop and a modulation of a frequency division by a divider in the phase-locked loop. | 2022-08-04 |
20220247356 | DEMODULATOR AND WIRELESS RECEIVER INCLUDING THE SAME - There is provided a demodulator that makes it possible to reduce or avoid deterioration in demodulation performance due to nonlinearity of input amplitude-frequency characteristics of a variable capacitive element included in an analog control signal input section of a frequency variable oscillator, while suppressing an influence of noise. The demodulator includes: a low-resolution A/D converter that performs analog-digital conversion of a first phase difference signal, which represents a phase difference between a digitally modulated modulation signal and an oscillation signal, with a resolution lower than at least a resolution of a digital demodulation signal, which is a final output, to generate a second phase difference signal that is digital; a low-resolution D/A converter that performs digital-analog conversion of the second phase difference signal to generate a third phase difference signal that is analog; an analog subtractor that subtracts the third phase difference signal from the first phase difference signal to generate a first control signal; an ADPLL that generates a second control signal on the basis of a reference signal and the oscillation signal; and an FVO that generates the oscillation signal on the basis of the first control signal and the second control signal. | 2022-08-04 |
20220247357 | Combined Mixer and Filter Circuitry - A combined mixer and filter circuitry is disclosed. The combined mixer and filter circuitry comprises a mixer comprising a first input, a second input and an output. The combined mixer and filter circuitry further comprises a filter comprising an active inductor and a first capacitor. The active inductor comprises a transistor having a first terminal, a second terminal and a third terminal and a resistor connected between the first terminal of the transistor and a voltage potential. The first capacitor is connected between the third terminal and a signal ground and the second terminal of the transistor is connected to the second input of the mixer. | 2022-08-04 |
20220247358 | Power Amplifier Equalizer - Circuits and methods for achieving good AM-AM and AM-PM metrics while achieving good power, PAE, linearity, and EVM performance in an amplifier. Embodiments provide an equalization approach which compensates for AM-AM and AM-PM variations in an amplifier by controlling bias voltage versus output power to alter the AM-AM and AM-PM profiles imposed by the amplifier. Differential amplifier embodiments include cross-coupled common-gate transistors that generate an equalization voltage that alters the gate bias voltage of respective main FETs in proportion to a power level present at the respective drains of the main FETs. Single-ended amplifier embodiments include an equalization circuit that alters the bias voltage to the gate of a main FET in proportion to a power level present at the main FET drain. Embodiments may also include a linearization circuit which alters the AM-PM profile of an input signal to compensate for the AM-PM profile imposed by a coupled amplifier. | 2022-08-04 |
20220247359 | ANALOG BIAS CONTROL OF RF AMPLIFIERS - Examples provide methods and apparatus for controlling a DC bias current in an RF amplifier. In one example where the RF amplifier is implemented on an amplifier die, a reference voltage is produced across a reference resistor implemented on the amplifier die, the DC bias current is measured, and a current controller, which is implemented on a controller die that is separate from the amplifier die, operates a feedback loop using the reference voltage to control a level of the DC bias current. | 2022-08-04 |
20220247360 | TRANSMITTING AND RECEIVING DEVICE HAVING A WIDE-BAND HF POWER AMPLIFIER, IN PARTICULAR AN N-WAY DOHERTY AMPLIFIER HAVING ACTIVE LOAD MODULATION - A transmitting and receiving device having a module (GSZ) with a configurable HF high-power amplifier (HPA) that includes a main power amplifier (DM) with a main amplifier core and at least one peak power amplifier (DP | 2022-08-04 |
20220247361 | Power Amplifier Linearizer - Circuits and methods for achieving good amplifier AM-AM and AM-PM metrics while achieving good power, PAE, linearity, and EVM performance. Embodiments compensate for a non-linear distortion profile (e.g., an AM-PM and/or AM-AM profile) in an amplifier by pre-processing an input signal, such as a radio-frequency signal, to alter the non-linear distortion profile of the input signal so as to compensate for the non-linear distortion profile imposed by a coupled device, such as an amplifier. An inventive aspect includes linearizing an output from an amplifier having a first non-linear distortion profile, including passing an input signal having a second non-linear distortion profile through a reflective hybrid coupler to a non-linear termination circuit, and reflecting a modified input signal from the non-linear termination circuit back through the reflective hybrid coupler as an output signal, the output signal having a third non-linear distortion profile shaped to compensate for the first non-linear distortion profile. | 2022-08-04 |
20220247362 | HIGH-SPEED, LOW DISTORTION RECEIVER CIRCUIT - A receiver circuit has a first stage circuit having a first stage input and a first stage output, the first stage output setting a first stage common mode voltage; a second stage circuit having a second stage input connected to the first stage output, and a second stage output setting a second stage common mode voltage; and a buffer circuit having a trip point voltage, connected to the second stage output. The first stage circuit can include circuit elements configured to establish the first stage common mode voltage so that the second stage common mode voltage matches the trip point voltage. The second stage circuit can include a self-biased amplifier. | 2022-08-04 |
20220247363 | AMPLIFIER ASSEMBLY AND METHOD OF AMPLIFICATION PARTICULARLY FOR PORTABLE DEVICE - A sound system includes a sound source having an analogue audio signal output and a sound volume control; signal amplifier apparatus ( | 2022-08-04 |
20220247364 | MULTI-MODE BROADBAND LOW NOISE AMPLIFIER - Multi-mode broadband low noise amplifiers (LNAs) are disclosed herein. In certain embodiments, an LNA includes a first amplification stage and a second amplification stage having a lower gain than the first amplification stage. The LNA is operable in a plurality of operating modes including a first mode in which the first amplification stage and the second amplification stage operate in a cascade to amplify a radio frequency (RF) receive signal, and a second mode in which the first amplification stage amplifies the RF receive signal and the second amplification stage is bypassed. | 2022-08-04 |
20220247365 | STACKED POWER AMPLIFIERS WITH DC CURRENT REUSE - Apparatus and the methods for stacked power amplifiers are provided. In certain embodiments, a mobile device includes a transceiver that generates a first radio frequency input signal and a second radio frequency input signal, and a front end system including a stacked power amplifier that receives power from a power high supply voltage and a power low supply voltage. The stacked power amplifier includes a first power amplifier that amplifies the first radio frequency input signal and a second power amplifier that amplifies the second radio frequency input signal. The first power amplifier and the second power amplifier are electrically connected in a stack between the power high supply voltage and the power low supply voltage and operate with a shared DC bias current. | 2022-08-04 |
20220247366 | OPTICAL AMPLIFYING MODULE AND MANUFACTURING METHOD THEREOF - An optical amplifying module and a manufacturing method are provided. The optical amplifying module includes a current amplifying element, a light emitting element and a light receiving element. A main substrate of the current amplifying element has a first surface and a second surface, which are opposed to each other. Moreover, plural first main electrodes are installed on the first surface, and plural second main electrodes are installed on the second surface. The light emitting element is installed beside the first surface of the current amplifying element. The light emitting units of the light emitting element are electrically coupled with the corresponding first main electrodes. The light receiving element is installed beside the second surface of the current amplifying element. The light receiving units of the light receiving element are electrically coupled with the corresponding second main electrodes. | 2022-08-04 |
20220247367 | ZERO-CROSSING MANAGEMENT IN CLASS-D AUDIO AMPLIFIERS - Class-D amplifier circuits provide operation with low-distortion zero crossings outside of a unipolar power supply voltage range. The amplifiers include a first H-bridge driver circuit and a second H-bridge driver circuit. The class-D amplifier circuits also include a control circuit having an input for receiving an input signal to be reproduced by the class-D amplifier circuit. The control circuit has outputs coupled to inputs of the first and second H-bridge drivers, and includes one or more modulators. The control circuit selects between actively operating a selected one of the driver circuits or both, according to the signal to be reproduced, while setting an unselected driver circuit to turn either a high-side switch or a low-side switch of the unselected one of the first driver circuit or the second driver circuit fully on for at least some cycles of the one or more modulators. | 2022-08-04 |
20220247368 | GAIN CONTROL CIRCUIT FOR TRANSMITTER AND METHOD THEREOF - A gain control circuit utilized in a transmitter is disclosed. The transmitter is configured to amplify an input signal according to a gain via a digital amplifier, an analog amplifier and a power amplifier, to generate an output signal. The gain control circuit includes a correction unit configured to calculate a correction power according to an elapsed time since a current packet transmission duration of the transmitter is completed. The gain control circuit adjusts the gain according to the correction power, a transmitter signal strength indication of the input signal and an environment temperature of the transmitter. | 2022-08-04 |
20220247369 | CIRCUITRY FOR REDUCING DISTORTION OVER A WIDE FREQUENCY RANGE - A combination amplifier can include a “main amplifier circuit” for signal amplification, and a matching “compensation amplifier circuit” to monitor distortion in the main amplifier output signal. The compensation amplifier circuit provides a compensation signal to the main amplifier circuit to compensate for and servo out distortion therein. The compensation amplifier circuit includes a passive input network and an amplifier. The passive input network can connect to both the input and output nodes of the main amplifier circuit such that the input and output signals cancel within the passive input network, leaving only the low level distortion component introduced in the main amplifier. Thus, the compensation amplifier is then only operating on the low-level distortion introduced in the main amplifier to generate the compensation signal. Because the compensation amplifier is then only operating on the very low distortion signal, any distortion it introduces into the compensation signal is negligible. | 2022-08-04 |
20220247370 | APPARATUS AND METHODS FOR ADAPTIVE POWER AMPLIFIER BIASING - Apparatus and methods for adaptive power amplifier biasing are provided. In certain embodiments, a power amplifier system includes a power amplifier that provides amplification to a radio frequency (RF) signal, and a power amplifier bias control circuit that generates a bias signal of the power amplifier based on a bandwidth signal indicating a bandwidth of the RF signal. The power amplifier bias control circuit has a bandwidth that adapts to the bandwidth of the RF signal as indicated by the bandwidth signal. | 2022-08-04 |
20220247371 | SWITCHING POWER SUPPLY, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND DIFFERENTIAL INPUT CIRCUIT - This switching power source | 2022-08-04 |
20220247372 | CURRENT SENSING CIRCUITRY - A system may include a front end differential amplifier having two input terminals, two input resistors, each of the two input resistors coupled to a respective one of the two input terminals, and an input common mode biasing circuit for an output stage of the front end differential amplifier, the input common mode biasing circuit comprising two current sources configured to generate currents for biasing the output stage of the front end differential amplifier. | 2022-08-04 |
20220247373 | TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATORS WITH MULTIPLE PIEZOELECTRIC MEMBRANE THICKNESSES ON THE SAME CHIP - An acoustic resonator is fabricated with multiple piezoelectric plate thicknesses on a single chip. After conductor patterns are formed on a piezoelectric plate, the plate is bonded to a sacrificial substrate, with the conductor patterns facing the sacrificial substrate. The piezoelectric plate is then thinned to a desired thickness for shunt resonators. A mask is applied to the surface of the plate and selected areas of the piezoelectric plate are further thinned to a desired thickness for series resonators to form a thinned piezoelectric plate. A substrate with swimming pool cavities is bonded to the thinned piezoelectric plate, and the sacrificial substrate is removed. | 2022-08-04 |
20220247374 | METHOD FOR MANUFACTURING A STRUCTURE COMPRISING A THIN LAYER TRANSFERRED ONTO A SUPPORT PROVIDED WITH A CHARGE TRAPPING LAYER - A method for manufacturing a structure comprising a thin layer transferred onto a support provided with a charge trapping layer, the method comprising the following steps: —preparing the support comprising forming the trapping layer on a base substrate, the trapping layer having a hydrogen concentration of less than 10{circumflex over ( )}18 at/cm{circumflex over ( )}; —joining the support to a donor substrate by way of a dielectric layer having a hydrogen concentration of less than 10{circumflex over ( )}20 at/cm{circumflex over ( )}3 or comprising a barrier preventing the diffusion of hydrogen toward the trapping layer or having low hydrogen diffusivity; —removing part of the donor substrate to form the thin layer; the manufacturing method exposing the structure to a temperature below a maximum temperature of 1000° C. The present disclosure also relates to a structure obtained at the end of this method. | 2022-08-04 |
20220247375 | COMPOSITE SUBSTRATE FOR MANUFACTURING ACOUSTIC WAVE RESONATOR AND SURFACE ACOUSTIC WAVE RESONATOR, AND MANUFACTURING METHOD THEREOF - The present invention discloses a composite substrate for manufacturing an acoustic wave resonator and a Surface Acoustic Wave (SAW) resonator, and a manufacturing method thereof. The manufacturing method of the composite substrate includes: providing a base, wherein the base includes a first surface and a second surface that are opposite to each other; and a first groove sunken towards the second surface is formed on the first surface; and providing a piezoelectric plate, wherein the piezoelectric plate is matched with the first groove in shape, and a bottom of the first groove is integrated with the piezoelectric plate by bonding; and the composite substrate includes: a base, wherein the base includes a first surface and a second surface that are opposite to each other; and a first groove sunken towards the second surface is provided on the first surface; and a piezoelectric plate, wherein the piezoelectric plate is embedded into the first groove, and a top of the piezoelectric plate is higher than the first surface or flush with the first surface. | 2022-08-04 |
20220247376 | DIFFERENTIAL AMPLIFICATION CIRCUIT - A differential amplification circuit includes a differential amplifier configured to output a signal including harmonics and first and second filters configured to reduce level of an even harmonic included in output from the differential amplifier. The first and second filters are connected to output of the differential amplifier. The first filter includes a resonant circuit composed of a capacitor and an inductor and a resonant circuit composed of a capacitor and the inductor. The second filter includes a resonant circuit composed of a capacitor and an inductor and a resonant circuit composed of a capacitor and the inductor. A center frequency of the first filter is lower than a center frequency of the even harmonic. A center frequency of the second filter is higher than the center frequency of the even harmonic. | 2022-08-04 |
20220247377 | ACOUSTIC WAVE DEVICE - An acoustic wave device includes a piezoelectric substrate and an electrode on the piezoelectric substrate and including first and second layers. The first layer includes Al and Cu. The second layer is on a side opposite to a piezoelectric substrate side of the first layer and includes Al. The first layer includes an Al crystal and at least a portion of CuAl | 2022-08-04 |
20220247378 | LAMB WAVE RESONATOR AND METHOD OF FABRICATING THE SAME - A Lamb wave resonator includes a piezoelectric material layer, a first finger electrode, a second finger electrode, at least two floating electrodes, and at least two gaps. The first finger electrode is disposed on one side of the piezoelectric material layer and includes a first main portion and first fingers. The second finger electrode is disposed on the side of the piezoelectric material layer and includes a second main portion and second fingers. The first fingers are parallel to and alternately arranged with the second fingers. The floating electrodes are disposed between each first finger and each second finger, and the gaps are disposed at two ends of each floating electrode, respectively. | 2022-08-04 |
20220247379 | SURFACE ACOUSTIC WAVE RESONATOR WITH PISTON MODE DESIGN AND ELECTROSTATIC DISCHARGE PROTECTIONS - Certain aspects of the present disclosure provide a surface acoustic wave (SAW) resonator with piston mode design and electrostatic discharge (ESD) protections. An example electroacoustic device generally includes a piezoelectric material and a first electrode structure disposed above the piezoelectric material. The first electrode structure comprises first electrode fingers arranged within an active region having a first region and a second region. At least one of the first electrode fingers has at least one of a different width or a different height in the first region than in the second region, and the first electrode fingers comprise a first electrode finger that has a width or height in the second region that is less than a corresponding width or height of the at least one of the first electrode fingers in the second region. | 2022-08-04 |
20220247380 | ACOUSTIC WAVE DEVICE - An acoustic wave device includes a piezoelectric substrate, first and second signal electrodes, and a first ground electrode on a first main surface of the piezoelectric substrate, at least one insulation layer on a second main surface of the piezoelectric substrate, first and second signal terminals provided indirectly on the second main surface with the insulation layer interposed therebetween, and a ground terminal on the second main surface. An acoustic wave filter is provided on the piezoelectric substrate. The first signal electrode and the first signal terminal are electrically coupled, the second signal electrode and the second signal terminal are electrically coupled, and the first ground electrode and the ground terminal are electrically coupled. The ground terminal includes a contact portion in contact with the second main surface of the piezoelectric substrate. | 2022-08-04 |
20220247381 | TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATORS WITH MULTIPLE PIEZOELECTRIC MEMBRANE THICKNESSES ON THE SAME CHIP - A filter device with multiple piezoelectric plate thicknesses if fabricated on a single chip by bonding a piezoelectric plate to a surface of a substrate having swimming pool shunt and series cavities. Non-selected areas of the plate have a thickness for shunt resonators and form shunt membranes of the plate that span the swimming pool shunt cavities. Selected areas of a back surface of the plate have a thickness for series resonators and form series membranes of the plate that span the swimming pool series cavities but not the swimming pool shunt cavities. The thickness for series resonators is thinner than that for shunt resonators. Shunt interdigital transducers (IDTs) are on a front surface of the plate over the swimming pool shunt cavities; and series IDTs are on a front surface of the plate over the swimming pool series cavities. | 2022-08-04 |
20220247382 | BANDPASS FILTERS USING TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATORS - Bandpass filters for a target communications band extending between a lower band edge and an upper band edge are disclosed. A bandpass filter includes one or more shunt resonators and one or more series resonators connected in a ladder filter circuit, wherein a relative difference between the anti-resonance and resonance frequencies of each acoustic resonator is greater than a fractional bandwidth of the target communications band. A first capacitor is connected in parallel with a first shunt resonator from the one or more shunt resonators, and a second capacitor connected in parallel with a first series resonator from the one or more series resonators. | 2022-08-04 |
20220247383 | WIDEBAND FILTER USING TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATORS AND INDUCTIVE CANCELLATION - There are disclosed acoustic filter circuits. A filter circuit includes a first capacitor connected between an input and a first node, a first inductor coupled between the first node and ground, a series resonant circuit comprising a first acoustic resonator and a second inductor connected between the first node and a second node, and a shunt resonant circuit comprising a second acoustic resonator and a third inductor connected between the second node and ground. The first inductor and the third inductor are inductively coupled with a negative mutual inductance. | 2022-08-04 |
20220247384 | TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATOR WITH MULTI-MARK INTERDIGITAL TRANSDUCER - Acoustic resonator devices and acoustic filter devices. An acoustic resonator includes a piezoelectric plate having front and back surfaces. The back surface is attached to a surface of a substrate, and a portion of the piezoelectric plate forms a diaphragm spanning a cavity in the substrate. A conductor pattern is formed on the front surface. The conductor pattern includes a multi-mark interdigital transducer (IDT), with fingers of the IDT on the diaphragm. | 2022-08-04 |
20220247385 | ELECTROACOUSTIC FILTER WITH LOW PHASE DELAY FOR MULTIPLEXED SIGNALS - Aspects of the disclosure relate to wireless communication, and high-frequency filters with resonators configured to systematically modify phase characteristics of an antenna reflection coefficient. One aspect is a wireless communication apparatus comprising an acoustic resonator having a first resonator side and a second resonator side, the first resonator side coupled to a first signal connection port, a first capacitor including a first side coupled to the first resonator side and the first signal connection port, the first capacitor further including a second side coupled to a ground connection port, and a second capacitor including a first side coupled to the ground connection port, the second capacitor further including a second side, the second resonator side and the second side of the second capacitor coupled to an output port. | 2022-08-04 |
20220247386 | NOISE MITIGATION CIRCUITRY FOR QUANTUM COMPUTERS AND CORRESPONDING METHODS - Various embodiments provide methods, apparatuses, systems, or computer program products for providing a signal to an electrode of a quantum computer. In an example embodiment, the system comprises noise mitigation circuitry comprising a signal generator, a gain stage, and a filter stage. The signal generator may be comprised of a plurality of voltage sources. The controller causes the signal generator to generate a signal, and the signal is provided to the electrode through the noise mitigation circuitry to cause at least a portion of the system to perform a function. | 2022-08-04 |
20220247387 | Semiconductor Device - A semiconductor device includes first and second insulated-gate transistors in parallel with each other, a charger-discharger, and a gate voltage correction circuit. The charger-discharger can perform first control to charge both of the gates of the first and second transistors, second control to discharge both of the gates of the first and second transistors, and third control to charge one of the gates of the first and second transistors. The gate voltage correction circuit corrects the gate voltages of the first and second transistors to eliminate the difference between those voltages in at least one of the first control, the second control, and protection operation in which the first and second transistors are forcibly kept off. | 2022-08-04 |
20220247388 | LOW POWER FLIP-FLOP - A low power flip-flop includes first to fourth signal generation circuits and an inverter. The first signal generation circuit receives the clock signal, the data input signal, and a first internal signal that is an output of the second signal generation circuit and generates a second internal signal. The inverter receives the first internal signal and generates an inverted first internal signal. The second signal generation circuit receives the first internal signal and the output signal that is an output of the third signal generation circuit, and generates the inverted output signal. The third signal generation circuit receives the clock signal and the inverted output signal and generates the output signal. The fourth signal generation circuit receives the inverted first internal signal, the second internal signal, and the clock signal and generates the first internal signal. | 2022-08-04 |
20220247389 | DIGITAL PULSE-WIDTH MODULATION (PWM) MODULATOR WITH DYNAMICALLY SWITCHABLE CODE SET FOR REDUCED TOTAL HARMONIC DISTORTION AND NOISE (THDN) - A digital PWM modulator modulates a digital input signal to drive a PWM signal to a PWM DAC susceptible to introducing inter-symbol interference (ISI) in small PWM edge separation presence causing audio THDN degradation. A multi-bit quantizer switches from a first to second mode when the input signal rises above a threshold. The quantizer quantizes the input signal into a quantized output signal, each sample of which has a code selected from respective first and second quantization code sets. The second set, relative to the first set, causes the digital PWM signal to have increased edge separation to reduce the ISI at high input levels. The first set includes small magnitude codes relative to the second set to reduce quantization noise at low input levels. The threshold is sufficiently low to cause the quantized output signal to be dominated by small codes when operating in the first mode. | 2022-08-04 |
20220247390 | SIGNAL GENERATION CIRCUIT HAVING MINIMUM DELAY, SEMICONDUCTOR APPARATUS USING THE SAME, AND SIGNAL GENERATION METHOD - A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value. | 2022-08-04 |
20220247391 | TRUE SINGLE PHASE CLOCK (TSPC) BASED LATCH ARRAY - A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch the data from the master latch, and an inverter including an input coupled to the AOI gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data. | 2022-08-04 |
20220247392 | SYSTEM AND METHOD FOR GENERATING SUBHARMONIC LOCKED FREQUENCY DIVISION AND PHASE INTERPOLATION - A system for generating a sub-harmonically injection locked phase interpolated output signal. The system comprises ring oscillator (RO) circuitry to generate an output oscillator signal in response to a periodic input signal. The RO circuitry includes a plurality of differential delay RO stages interconnected in cascade within a closed loop, where each RO stage is configured to establish a corresponding delayed version of the output oscillator signal successively shifted in phase by a predetermined phase difference based on a predetermined interpolation mapping scheme. The system further comprises signal injection circuitry coupled to the RO circuitry to apply a first signal having a first input phase and a second signal having a second input phase to the plurality of differential delay RO stages based on the predetermined interpolation mapping scheme to lock a frequency of the output oscillator signal at one half the frequency of the periodic input signal. | 2022-08-04 |
20220247393 | HIGH ACCURACY LOW POWER SMALL AREA CMOS CURRENT STARVED RING OSCILLATOR WITH NOVEL COMPENSATION TECHNIQUES FOR SUPPLY, TEMPERATURE AND PROCESS DEPENDENCY - An apparatus includes a poly current generator circuit, which includes a fractional bandgap circuit, or a bandgap voltage reference circuit and a current reference generator, an adaptive bias current generator, a frequency generator to generate an output clock signal having a select frequency, wherein the frequency generator includes a current starved ring oscillator that comprises n identical cascaded stages connected in a shape of a ring, wherein an output of the nth cascaded stage is fed back as an input of the first cascaded stage, wherein n is an odd number greater than or equal to 3; and clock buffers configured to buffer the output clock signal generated by the frequency generator for distribution. | 2022-08-04 |
20220247394 | LATCH - A circuit includes cross coupled invertors including a first invertor and a second inventor. The first invertor and the second invertor are cross coupled at a first data node and a second data node. An input unit is coupled between the cross-coupled invertors and a power node. The input unit controls the cross-coupled invertors in response to a first input signal received at a first input terminal of the input unit and a second input signal received at a second input terminal of the input unit. A first transistor is connected between the power node and a supply node. The first transistor connects the power node to the supply node in response to an enable signal changing to a first value. A second transistor is connected between the power node and ground. The second transistor connects the power node to the ground in response to the enable signal changing to a second value. | 2022-08-04 |
20220247395 | Attack-resistant ring oscillators and random-number generators - An oscillator circuit includes a plurality of inverters connected in a cascade, at least first and second feedback taps, and alternation circuitry. The at least first and second feedback taps are configured to feed-back at least respective first and second output signals taken from at least respective first and second points in the cascade. The alternation circuitry is configured to derive an input signal from at least the first and second output signals by alternating between at least the first and second feedback taps, and to apply the input signal to an input of the cascade. | 2022-08-04 |
20220247396 | RTWO-BASED FREQUENCY MULTIPLIER - Rotary traveling wave oscillator-based (RTWO-based) frequency multipliers are provided herein. In certain embodiments, an RTWO-based frequency multiplier includes an RTWO that generates a plurality of clock signal phases of a first frequency, and an edge combiner that processes the clock signal phases to generate an output clock signal having a second frequency that is a multiple of the first frequency. The edge combiner can be implemented as a logic-based combining circuit that combines the clock signal phases from the RTWO. For example, the edge combiner can include parallel stacks of transistors operating on different clock signal phases, with the stacks selectively activating based on timing of the clock signal phases to generate the output clock signal of multiplied frequency. | 2022-08-04 |
20220247397 | CHAINED PROGRAMMABLE DELAY ELEMENTS - Delay elements and multiplexers are in programmable delay elements. Each programmable delay element has a chain of delay elements to produce successive delays of a clock of the programmable delay element. Each programmable delay element has a first multiplexer to select among an input clock and delay element outputs in the chain of delay elements to produce a skewed clock output of the programmable delay element. In at least a subset of the programmable delay elements, each programmable delay element has a second multiplexer to select among clocks that include a first clock, and a second clock that is from one of the delay elements of another programmable delay element to produce the clock of the programmable delay element. | 2022-08-04 |
20220247398 | DUTY CYCLE ADJUSTMENT CIRCUIT WITH INDEPENDENT RANGE AND STEP SIZE CONTROL - Duty cycle adjustment circuitry includes a first stage, a second stage, and decoder circuitry. The first stage includes a first strength tuning circuit having first inverter branches, and a first fine tuning circuit having second inverter branches. The first strength tuning circuit and the first fine tuning circuit are coupled in parallel. The second stage includes a second strength tuning circuit having third inverter branches, and a second fine tuning circuit having fourth inverter branches. The second strength tuning circuit and the second fine tuning circuit are coupled in parallel. Further, the second stage is electrically coupled to the first stage. The decoder circuitry is electrically coupled to the first stage and the second stage. The decoder circuitry controls the first strength tuning circuit independently from the first fine tuning circuit to adjust the duty cycle of an input signal received by the duty cycle adjustment circuitry. | 2022-08-04 |
20220247399 | RELIABILITY DETECTION DEVICE AND RELIABILITY DETECTION METHOD - A reliability detection device includes a control circuit, oscillator circuits, and an output circuit. The control circuit is configured to generate enable signals according to a mode signal. The oscillator circuits output oscillating signals, in which each of the oscillator circuits is configured to generate a corresponding oscillating signal in the oscillating signals according to a switching signal when the mode signal has a first logic value, and generate the corresponding oscillating signal according to a corresponding enable signal in the enable signals when the mode signal has a second logic value, and the switching signal is associated with a functional circuit. The output circuit is configured to output a detection signal according to the oscillating signals when the mode signal has the second logic value, in which the detection signal is to indicate a reliability of the functional circuit. | 2022-08-04 |
20220247400 | LOAD DRIVE CONTROL DEVICE - A predriver circuit that controls driver elements includes a slope control circuit that separately controls inclination of slope of current from the driver elements, and inclination of slope of voltage from a driver circuit. A controller outputs, to the predriver circuit, a current control signal selected from a plurality of current control signals and a voltage control signal selected from a plurality of voltage control signals, to control the slope of current from the driver elements and the slope of voltage from the driver circuit. | 2022-08-04 |
20220247401 | High-Speed Switch with Accelerated Switching Time - A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch. | 2022-08-04 |
20220247402 | TERMINATION CIRCUIT - A termination circuit, including a termination resistor, a first switch circuit, a second switch circuit, and a control circuit, is provided. A first end of the termination resistor is coupled to a signal pad. A first end of the first switch circuit is coupled to a second end of the termination resistor. A first end of the second switch circuit is coupled to a second end of the first switch circuit. A second end of the second switch circuit is coupled to a reference voltage line. During a period when the second switch circuit is turned on, the control circuit turns on the first switch circuit with a bias voltage. During a period when the second switch circuit is turned off, the control circuit turns off the first switch circuit with a voltage of the first end of the first switch circuit. | 2022-08-04 |
20220247403 | SMART SWITCH APPARATUS - A smart switch apparatus is coupled between a live wire of an indoor power and two output terminals of a SPDT (Single Pole Double Throw) switch. Two ends of a load are respectively connected to a neutral wire of the indoor power and an input terminal of the SPDT switch. The smart switch apparatus includes an on-off status detector, a switch position detector, a controller, an on-off controller and a power circuit. The on-off status detector is coupled to the live wire of the indoor power for generating an on-off status signal. The switch position detector is coupled to the two output terminals of the SPDT switch for generating a switch position signal. The controller is coupled to the on-off status detector and the switch position detector for receiving the on-off status signal and the switch position signal. The on-off controller is coupled to the two output terminals of the SPDT switch and the live wire of the indoor power to selectively turn on or turn off the target power loop according to the on-off control signal. | 2022-08-04 |
20220247404 | POWER SWITCH DRIVE CIRCUIT AND DEVICE - An apparatus includes a capacitor coupled to a gate of a power switch, and a negative voltage adjustment device connected to a common node of the capacitor and the gate of the power switch, wherein the negative voltage adjustment device is configured such that after a turn-off signal is applied to the gate of the power switch, a voltage across the capacitor is maintained at a predetermined voltage level through a negative current provided by the negative voltage adjustment device. | 2022-08-04 |
20220247405 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention includes: a P-type output transistor configured to have a source to which a power supply voltage is applied, and a drain connected to an external connection pad; a gate wiring configured to be connected to a gate of the output. transistor; a signal transmitting portion configured to transmit an input signal to the gate wiring; and a voltage-breakdown protecting portion configured to apply the power supply voltage to a back gate of the output transistor if a voltage on the external connection pad is equal to or lower than the power supply voltage, or the voltage-breakdown protecting portion bringing the signal transmitting portion into a disconnection state and applies the voltage on the external connection pad to the gate and the back gate of the output transistor if the voltage applied on the external connection pad is higher than the power supply voltage. | 2022-08-04 |
20220247406 | SWITCH LINEARIZATION WITH ASYMMETRICAL ANTI-SERIES VARACTOR PAIR - Described herein are switches with asymmetrical anti-series varactor pairs to improve switching performance. The disclosed switches can include asymmetrical varactor pairs to reduce distortions. The asymmetry in the varactor pairs can be associated with geometry of each varactor in the pair. The disclosed switches can stack both symmetrical and asymmetrical varactor pairs. The disclosed switches with asymmetrical anti-series varactor pairs can be configured to improve both H2 and H3 simultaneously. | 2022-08-04 |
20220247407 | RESONATOR, OSCILLATOR, AND QUANTUM COMPUTER - A resonator, an oscillator, and a quantum computer in which the area occupied by the circuit can be reduced is provided. A resonator ( | 2022-08-04 |
20220247408 | Electrical switch - A switch device includes a main module, which includes at least one main electronic control circuit, connections to the electrical system of a building and/or to equipment or devices to be controlled, one or more touch sensors or contacts connected to the at least one main electronic control circuit, a main box-shaped housing element for the preceding components, and one or more systems that provide a reversible electric or electronic and mechanical connection of the main module to an accessory module. | 2022-08-04 |
20220247409 | USER INTERFACE SYSTEM FOR CONTROLLING A VEHICLE OPERATION - A user interface system for controlling a vehicle operation including a printed circuit board (PCB) that has a front side and a back side. A top layer that is electrically conductive defines the front side of the PCB. A plurality of indicia are etched into the top layer. An applique overlies the front side of the PCB. At least one proximity sensor is integrated into the front side of the PCB for detecting user object adjacent to the associated indicia and outputting a corresponding detection signal. The PCB further includes a base layer under the top layer. The base layer is at least partially formed of an optically transparent material. At least one light emitting device is positioned on the back side of the PCB for illuminating the indicia. A controller unit is coupled to the at least one proximity sensor and the at least one light emitting device. | 2022-08-04 |
20220247410 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a pad; a control circuit; a plurality of high-potential-side circuit regions having distances to the pad different from each other, each including a gate drive circuit, a SET-side level shifter, a RESET-side level shifter, and a circular wire; a SET-side wire electrically connects the pad with the SET-side level shifters; and a RESET-side wire electrically connects the pad with the RESET-side level shifters, wherein the circular wire located closer to the pad is electrically connected to the SET-side wire and the RESET-side wire via the circular wire 8 | 2022-08-04 |
20220247411 | CLOCK-GATING SYNCHRONIZATION CIRCUIT AND METHOD OF CLOCK-GATING SYNCHRONIZATION - A clock-gating synchronization circuit is provided. The clock-gating synchronization circuit includes a synchronization circuit and clock-gating circuit. The synchronization circuit is configured to perform a synchronization operation to convert a first control signal in a first clock domain into a second control signal in a second clock domain, transmit the second control signal to an electronic circuit, and determine whether the first control signal and the second control signal are the same to generate a first signal. The clock-gating circuit is configured to perform clock gating on the clock signal from a clock generator in the second clock domain according to the first signal to generate a gated clock signal, and transmit the gated. clock signal to the electronic circuit and the synchronization circuit, wherein the synchronization operation performed by the synchronization circuit is controlled by the gated clock signal. | 2022-08-04 |
20220247412 | FAST FPGA INTERCONNECT STITCHING FOR WIRE HIGHWAYS - A field programmable gate array (FPGA) has non-highway wire segments for connection to logic blocks, and highway wire segments in a highway network of highways. Each highway has sets of highway wire segments in successive connection. Each successive connection is through a multiplexer. Multiplexers of highways have on-ramps, off-ramps, or both, for programmable connection to wire segments in accordance with programming the FPGA. | 2022-08-04 |
20220247413 | ADDING LUT FRACTURABILIY TO FPGA 4-LUTS USING EXISTING ADDER CIRCUITRY - A field programmable gate array (FPGA) has a 4-LUT (lookup table) that has four stages of multiplexers. The 4-LUT is fracturable. The 4-LUT being fracturable includes the capability to implement multiple LUTs in an instance of FPGA programming for functions from a group that includes adder functions and further functions. The 4-LUT has outputs exposed to programmable connection in accordance with FPGA programming. Outputs of the 4-LUT include an output of a first multiplexer in the third stage, an output of a multiplexer in the second stage, and an output of a multiplexer in the second or third stage of the 4-LUT. | 2022-08-04 |
20220247414 | REFERENCE-LESS CLOCK AND DATA RECOVERY DEVICE AND METHOD - A reference-less clock and data recovery device includes a CDR circuit, an oscillator circuit, and a processor. The CDR circuit is configured to generate a first clock signal through synchronization according to a data signal having a first frequency in a first time period. The oscillator circuit is configured to output an oscillating clock signal according to the first clock signal. A frequency of the oscillating clock signal is substantially identical to that of the first clock signal. The processor oversamples the data signal having a second frequency in a second time period to generate a simulated preparation signal conforming to the second frequency. The CDR circuit is configured to generate a second clock signal through synchronization according to the simulated preparation signal. Before generating the second clock signal, the CDR circuit is synchronized to the oscillating clock signal to maintain outputting of the first clock signal. | 2022-08-04 |
20220247415 | PHASE-LOCKED LOOP CAPABLE OF COMPENSATING POWER NOISE - A phase-locked loop includes a bias circuit controlling a first bias current between a first power source and a first node according to a bias control signal; an oscillation circuit coupled between the first node and a second power source and generating an oscillation signal according to a current from the first node; a duplicate bias circuit controlling a second bias current between the first power source and a second node according to the bias control signal; an equivalent impedance circuit coupled between the second node and the second power source; a comparator circuit comparing voltages of the first node and the second node; a first variable current circuit controlling a current between the first node and the second power source; and a second variable current circuit controlling a current between the second node and the second power source. | 2022-08-04 |
20220247416 | CAN TRANSMITTER - The disclosure relates to a Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter ( | 2022-08-04 |
20220247417 | Method and Apparatus for Controlling Clock Cycle Time - A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit. | 2022-08-04 |
20220247418 | MAGNETORESISTIVE ASYMMETRY COMPENSATION - Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit. | 2022-08-04 |
20220247419 | ADC Apparatus and Control Method - A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2 | 2022-08-04 |
20220247420 | CALIBRATION SCHEME FOR FILLING LOOKUP TABLE IN AN ADC - In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC. | 2022-08-04 |
20220247421 | LOOKUP TABLE FOR NON-LINEAR SYSTEMS - In described examples, a circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value. | 2022-08-04 |
20220247422 | Successive Approximation Register using Switched Unit Elements - An Analog to Digital Converter (ADC) for a multiplier accumulator generates a digital output associated with a charge transfer bus made of weighted charge transfer lines with capacitance associated with each charge transfer line, the charge transfer bus connected to groups of ADC unit elements (UE) which add or remove charge from each line of the charge transfer line, each group of ADC unit elements having a sign bit input and a step size input and controlled by an ADC controller which switches the groups of ADC UE in a successive approximation according to a comparison of a summed charge from the weighted charge transfer lines until the ADC UE charge equals the charge transfer line capacitance, each comparison generating a bit value of the digital output. | 2022-08-04 |
20220247423 | SAR ADC AND SAMPLING METHOD BASED ON SINGLE-CHANNEL TIME-INTERLEAVED-SAMPLING - SAR ADC and sampling method based on single-channel TIS. The SAR ADC comprises: a capacitor array comprising a weight capacitor and a compensation capacitor, a first switch array, a second switch array, a channel switch group and a sampling switch; when in a sampling state: a lower plate of the weight capacitor is connected to an input voltage by means of the first switch array, and an upper plate of the capacitor array is connected to a common mode voltage by the sampling switch and the channel switch group; when in a successive approximation state: the lower plate of the weight capacitor is connected to a reference voltage by the second switch array. Input signals are sampled by using a unified to sampling switch, which solves the problem in the traditional technology that sampling moments are mismatched due to different sampling signals in each time-interleaved channel. | 2022-08-04 |
20220247424 | METHOD FOR OUTPUTTING A CURRENT AND CURRENT OUTPUT CIRCUIT - A method for outputting a current includes performing a sorting operation on a plurality of current sources according to intensities of currents generated by the current sources, dividing the plurality of current sources into N current source sets according to a result of the sorting operation and a predetermined selection order, and enabling at least one current source set of the N current source sets to output the current according a target output value. The plurality of current sources have a same target current value. Each of the N current source sets includes at least one current source. In the N current source sets, a total quantity of current sources of the n | 2022-08-04 |
20220247425 | Architecture for Multiplier Accumulator using Unit Elements for multiplication, bias, accumulation, and analog to digital conversion over a shared Charge Transfer Bus - An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspects of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in AND-groups, each AND gate coupled to a charge transfer bus through a charge transfer capacitor Cu to form an analog multiplication product. Each UE transfers differential charge to the charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result. | 2022-08-04 |
20220247426 | DELTA-SIGMA MODULATOR, DELTA-SIGMA DIGITAL- ANALOG CONVERTER, AND METHOD FOR OPERATING A DELTA-SIGMA MODULATOR AND A DELTA-SIGMA DIGITAL- ANALOG CONVERTER - A delta-sigma modulator which receives an input signal. The input signal is combined with a feedback signal and the combined signal is filtered by the delta-sigma modulator. The filtered signal is quantized, wherein the feedback signal is generated on the basis of the quantized signal. The quantized signal is output as an output signal. The input signal and/or the filtered signal and/or the feedback signal are filtered in such a way that at least one frequency in an out-of-band frequency range of the input signal is amplified in order to suppress out-of-band quantization noise at the at least one frequency. | 2022-08-04 |
20220247427 | OCCUPANCY INFORMATION PREDICTION METHOD, ENCODER, DECODER, AND STORAGE MEDIUM - Embodiments of the present application provide an occupancy information prediction method, an encoder, a decoder, and a storage medium. The occupancy information prediction method comprises: when an encoder encodes geometrical information on the basis of an octree, determining encoding information corresponding to a neighboring node of a node to be predicted, and a distance parameter between a child node of the node to be predicted and the neighboring nodes; wherein the encoding information corresponding to the neighboring node comprises occupancy information; determining an occupancy weight corresponding to the child node of the node to be predicted according to the distance parameter, and the encoding information corresponding to the neighboring node; performing a prediction processing on the child node according to the occupancy weight and a preset occupancy threshold set to obtain a node type corresponding to the child node. | 2022-08-04 |
20220247428 | ERROR CORRECTION BIT FLIPPING SCHEME - Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component). | 2022-08-04 |
20220247429 | TRANSMITTER AND PUNCTURING METHOD THEREOF - A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode outer-encoded bits to generate an LDPC codeword including LDPC information bits and parity bits; a puncturer configured to puncture some of the parity bits included in the LDPC codeword; and a mapper configured to map the LDPC codeword except the punctured parity bits to symbols for transmission to a receiver, wherein the puncturer calculates a number of parity bits to be punctured among the parity bits included in the LDPC codeword based on a number of the outer-encoded bits, a number of the LDPC information bits, and a minimum number of parity bits to be punctured among the parity bits included in the LDPC codeword. | 2022-08-04 |
20220247430 | APPARATUSES AND METHODS FOR PIPELINING MEMORY OPERATIONS WITH ERROR CORRECTION CODING - Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed. | 2022-08-04 |
20220247431 | SOFTWARE-DEFINED COMMUNICATION SYSTEM AND DEVICE - Systems, methods and devices to generate tailored antenna radiation patterns for particular purposes are provided. The software-defined communication devices and systems dynamically reconfigure an antenna in a controlled and reversible manner, transmit and receive signals to a plurality of endpoints simultaneously without requiring moving elements, and control radiation patterns, making them useful and more versatile for many applications, especially in implementations concerning satellite communications. Communication links may be established with multiple endpoints simultaneously, and the position of the endpoints may be learned without knowing it in advance. The configurations described in the embodiments provide great versatility due to the possibility of processing the signal at each antenna element of the antenna. | 2022-08-04 |
20220247432 | CROSS ANTENNA CONFIGURATION IN FREQUENCY DIVISION DUPLEX (FDD) DUAL-BAND RADIO - A multi-band radio, comprising a first antenna; a second antenna that is physically separate from the first antenna; one or more transmitters configured to: transmit a first transmit signal in a first transmit frequency band via the first antenna; and transmit a second transmit signal in a second transmit frequency band via the first antenna; and one or more receivers configured to: receive a first receive signal in a first receive frequency band via the second antenna; and receive a second receive signal in a second receive frequency band via the second antenna. | 2022-08-04 |
20220247433 | DIGITAL TRANSMITTER WITH DUTY CYCLE CORRECTION - Disclosed herein are related to systems and methods for correcting non-linearity due to duty cycle error. In one aspect, a system includes a mixer configured to up-convert transmission (Tx) data, a coefficient calibrator configured to select a target value of a coefficient based on a measurement of an interference signal due to non-linearity of the mixer, and an interference canceller coupled to the coefficient calibrator and the mixer. In some embodiments, the interference canceller is configured to generate compensated Tx data based on the Tx data and the selected target value of the coefficient and provide the compensated Tx data to the mixer. In some embodiments, the compensated Tx data corrects for the non-linearity of the mixer. | 2022-08-04 |
20220247434 | SUPPORT PLATE AND PORTABLE COMMUNICATION DEVICE INCLUDING THE SAME - Disclosed is a portable communication device including a housing, a printed circuit board seated in the housing and mounted to a communication circuit, and a least one position adjusting groove, wherein the housing includes a support plate having at least one antenna unit operatively connected with the communication circuit, and an injection molded member surrounding at least a portion of the at least one antenna unit, wherein the support plate includes a main body in which at least a portion of the printed circuit board is seated, and at least one lead connecting the at least one antenna unit with the main body, and wherein the at least one position adjusting groove is formed at a position at which the at least one lead makes contact with the injection molded member. | 2022-08-04 |
20220247435 | SWITCHED CURRENT-STEERING DIGITAL TRANSMITTER WITH ENCODER BASED UP-CONVERSION - Disclosed herein are related to systems and methods for selectively disabling current steering circuitries. In one aspect, the system includes a balun including a first inductor and a second inductor, a first current steering circuit coupled to the first inductor, a second current steering circuit coupled to the first inductor, and a controller coupled to the first current steering circuit and the second current steering circuit. In one aspect, the controller is configured to, based on input data having a first state, apply a first signal and a second signal having a first level to the first current steering circuit and a third signal and a fourth signal having the first level to the second current steering circuit to disable a first current through the second inductor, a second current through the first current steering circuit, and a third current through the second current steering circuit. | 2022-08-04 |
20220247436 | METHOD FOR IMPROVING ANTENNA MATCHING AND NODE - A method improves antenna matching for a node, in particular a sensor apparatus and/or actuator apparatus, of a communications network. The node is capable of radio communication and has a radio module equipped with an antenna and a transmit path and/or receive path for radio signals to be emitted and/or received. The node has a power supply apparatus, which is preferably energy self-sufficient, in particular a battery. The antenna has an impedance and in the receive situation and/or in the transmit situation in the case of adjustable matchings, preferably by use of adjustable matching networks, the signal to noise ratio associated with each matching is estimated, and a matching is selected from the different matchings for the receive mode and/or the transmit mode. | 2022-08-04 |
20220247437 | THz Impulse and Frequency Comb Generation Using Reverse Recovery of PIN Diode - Many embodiments provide a frequency comb receiver that includes a PIN diode, a THz pulse generator block that generates THz tones (LO) for coherent frequency comb detection, an on-chip antenna for broadband detection and a driver stage switched by a series of buffers, where a repetition rate of the LO tones are tunable over a range and determines a spacing between two adjacent tones in the corresponding frequency comb. | 2022-08-04 |
20220247438 | CIRCUIT CONFIGURED TO COMPENSATE FOR TIMING SKEW AND OPERATION METHOD THEREOF - An electronic circuit converts a receive signal being analog into reception data being digital. The electronic circuit includes a delay circuit that receives a first receive signal and outputs a reference signal, the reference signal being generated by delaying the first receive signal as much as one of a plurality of different timing delays respectively set to a plurality of loops, a sampler that receives a second receive signal and samples the second receive signal based on the reference signal in each of the plurality of loops, a timing skew estimation circuit that outputs a compensation signal for compensating for a timing skew by extracting a statistical characteristic of a plurality of sample data sampled through the sampler and estimating the timing skew based on the statistical characteristic, and a controller that controls an operation of the timing skew estimation circuit. | 2022-08-04 |
20220247439 | METHOD AND APPARATUS FOR PHASE ERROR COMPENSATION HAVING TOLERANCE TO CYCLIC SLIP - Disclosed is a method and apparatus for phase error compensation having tolerance to a cyclic slip. The method includes determining first phase error candidates based on symbol phases of a first block of a received signal, determining an initial estimation error according to the first phase error candidates, determining second phase error candidates based on symbol phases of a second block of the received signal, determining a final estimation error according to the initial estimation error and the second phase error candidates, and compensating for a phase of the received signal according to the final estimation error. | 2022-08-04 |