32nd week of 2009 patent applcation highlights part 18 |
Patent application number | Title | Published |
20090195261 | IMPEDANCE MEASURING INSTRUMENT - A measurement instrument for measuring the impedance of a device under test (DUT) includes a first source of either a voltage or a current and a second source of either a voltage or a current, wherein the first source is connectable in a first feedback relationship with the DUT and the second source is connectable in a second feedback relationship with both the DUT and the first source. The first and second sources are operated respectively as a current source responsive to the current through the DUT and a voltage source responsive to the voltage across the DUT or operated respectively as a voltage source responsive to the voltage across the DUT and a current source responsive to the current through the DUT. The second feedback relationship has a narrower bandwidth than the first feedback relationship. The resulting voltage across the DUT and the current through the DUT establish the measured impedance of the DUT. | 2009-08-06 |
20090195262 | IN-LINE ELECTRON BEAM TEST SYSTEM - A method and apparatus for testing a plurality of electronic devices formed on a large area substrate is described. In one embodiment, the apparatus performs a test on the substrate in one linear axis in at least one chamber that is slightly wider than a dimension of the substrate to be tested. Clean room space and process time is minimized due to the smaller dimensions and volume of the system. | 2009-08-06 |
20090195263 | PROBE APPARATUS, PROBING METHOD AND STORAGE MEDIUM - A probe apparatus includes a first stage, a second stage, a third stage and an image pickup. A Z position measuring unit measures a Z direction position of the mounting table and has a Z scale extending in the Z direction and a reading unit for reading the Z scale. A computation unit obtains a calculated contact position between the probes and the electrode pads of the substrate to be inspected based on images picked up by the image pickup with respect to a coordinate position on coordinates of a driving system which includes a Z direction position and X and Y direction positions measured by a measuring unit for measuring X and Y direction positions of the mounting table. A correcting unit corrects the Z direction position of the contact position based on the change amount thereof for a next contact operation. | 2009-08-06 |
20090195264 | High temperature test system - A high temperature test system is adapted for testing a device under test (DUT) under a high temperature environment. The high temperature test system includes a preheating unit, a first moving unit, a testing unit, and a second moving unit. The preheating unit is adapted for preheating the DUT. The first moving unit is adapted for removing the preheated DUT from the preheating unit. The testing unit is adapted for placement of the DUT removed by the first moving unit, for testing the DUT, and for providing the high temperature environment to the DUT during testing. The second moving unit is adapted for removing the DUT that has passed testing from the testing unit. | 2009-08-06 |
20090195265 | DEVICE AND METHOD FOR TESTING INTEGRATED CIRCUITS - A method and device for testing an integrated circuit. The method includes selecting between a shadow latch data retention mode and a shadow latch test mode; performing first test of an integrated circuit; storing, at the shadow latch if the shadow latch test mode is selected, information representative of a first test-imposed state; performing a second test of the integrated circuit; and generating a test equipment detectable signal if the first test-imposed state differs from a second test-imposed state of the tested latch. | 2009-08-06 |
20090195266 | HIGH VOLTAGE STRESS TEST CIRCUIT - A high voltage stress test circuit includes an internal data generation unit for generating internal data and inverted internal data, and a level shifter for receiving the internal data and the inverted internal data and for generating digital data and inverted digital data. In a normal mode, the internal data and the inverted internal data have logic states corresponding to input data, while the digital data and the inverted digital data have logic states corresponding to the internal data and the inverted internal data. In a high voltage stress test mode, the internal data and the inverted internal data have predetermined logic states regardless of a logic state of the input data, while the digital data and the inverted digital data have predetermined logic states regardless of logic states of the internal data and the inverted internal data. | 2009-08-06 |
20090195267 | High-Voltage tolerant output driver - A high-voltage tolerant output driver for use in a switching regulator is provided herein. The driver allows the switching regulator to regulate supply voltages that exceed device breakdown limits for the process technology from which the high-voltage tolerant output driver is fabricated. Unregulated supply voltages can vary over a wide range. The regulator only needs two intermediate voltages. | 2009-08-06 |
20090195268 | Level Shifting Circuit and Method - In a particular embodiment, a method includes receiving an input voltage at an input to a level shifting circuit that includes voltage pull-up logic. The method includes providing an output signal from the level shifting circuit. The method also includes selectively activating the voltage pull-up logic circuit of the level shifting circuit. | 2009-08-06 |
20090195269 | INPUT STAGE FOR MIXED-VOLTAGE-TOLERANT BUFFER WITH REDUCED LEAKAGE - A mixed-voltage buffer circuit coupled between a first circuit operative at a first power supply voltage and a second circuit operative at a second power supply voltage. The buffer circuit is connectable to the second power supply voltage and a third power supply voltage and includes an input circuit coupled to the first circuit through a first node and to the second circuit through a second node. The input circuit includes a first part coupled to the first node and an inverter coupled to the second node. The first part provides a signal having a voltage level approximately equal to the third power supply voltage to the inverter in response to a first signal on the first node, and provides a signal having a voltage level approximately equal to the second power supply voltage to the inverter in response to a second signal on the first node. | 2009-08-06 |
20090195270 | OUTPUT BUFFER DEVICE - A controlling output buffer slew rate method and an output buffer circuit for a memory device is provided. The output buffer include an output stage formed by a PMOS transistor and a NMOS transistor electrically connected in series, a pre-driver for respectively controlling each gate terminal of the PMOS transistor and the NMOS transistor in order to bring these transistors to the turning-on threshold, a first wire, for transmitting a pull-up signal, coupled between the output stage and the pre-driver, and a second wire, for transmitting a pull-down signal, coupled between the output stage and the pre-driver. After a DATA signal transition (logic state is changed from “H” to “L” or “L” from to “H”), the PMOS or NMOS transistor is turned off first, and then the NMOS or PMOS transistor is turned on due to the time difference between the pull-up signal and the pull-down signal. | 2009-08-06 |
20090195271 | FREQUENCY MODE SELECTION DISCRIMINATOR AND LOW PASS FILTER - A circuit is described that detects high and low frequencies and additional clock frequencies and outputs a signal that indicates a high, a low frequency or an additional mode. When in the low frequency low frequency mode signals are regenerated free of any high frequency signals from appearing on the filtered low frequency clock line. The rising and falling edges of the input clock are low pass filtered separately and then combined to generate a low frequency clock or the additional input clock and that retains the input clock pulse width and duty cycle. | 2009-08-06 |
20090195272 | Data transmission system for exchanging multi-channel signals - A receiver circuit is provided with: a plurality of input terminals; a plurality of hold circuits holding reception signals received by the plurality of input terminals; a detector circuit detecting clock bits from selected one of the reception signals to recover a clock signal in response to the detected clock bits; and a clock circuit connected to the detector circuit and generating one or more internal clock signals from the clock signal. The hold circuits commonly receive the internal clock signal(s) and perform sampling of the reception signals commonly in synchronization with the internal clock signal(s). | 2009-08-06 |
20090195273 | START-UP CIRCUIT FOR SMIA INPUT CLOCK BUFFER - A circuit for a buffer includes input and output nodes, in which the buffer provides a high level voltage output at the output node for a low level input leakage condition at the input node. The circuit includes a pull-up circuit, coupled to the input node, for providing a pull-up voltage to raise a common voltage level of an input signal. The buffer includes a transistor coupled to the input node, in which the transistor is turned on, in response to the pull-up voltage. A detector is coupled to the output node for detecting presence of the input signal. Upon the transistor turning on, the output node provides a buffered output signal corresponding to the input signal, and upon the detector detecting the presence of the input signal, the pull-up circuit is configured to remove the pull-up voltage. The input signal is an AC coupled signal having a peak-to-peak voltage excursion about a common DC voltage value. The input signal is an AC coupled clock signal adopted for standard mobile architecture (SMIA). | 2009-08-06 |
20090195274 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to the present invention comprises a clock tree circuit for delay-adjusting a clock signal using various delay amounts, and a clock synchronizing circuit to which the delay-adjusted clock signal is supplied. The clock tree circuit comprises a first clock tree cell provided in a poststage of a clock signal introducing terminal, a second clock tree cell provided in a prestage of the clock synchronizing circuit and a poststage of the first clock tree cell, and a clock ramification point provided in a prestage of the second clock tree cell. The clock synchronizing circuit comprises a first clock synchronizing circuit to which the clock signal delay-adjusted by the second clock tree cell and thereafter outputted from the clock tree circuit is supplied, and a second clock synchronizing circuit to which the clock signal outputted from the clock tree circuit at the clock ramification point is supplied. | 2009-08-06 |
20090195275 | TECHNIQUE FOR EFFICIENTLY MANAGING BOTH SHORT-TERM AND LONG-TERM FREQUENCY ADJUSTMENTS OF AN ELECTRONIC CIRCUIT CLOCK SIGNAL - A control system for generating an electronic circuit clock signal that can optimize operating frequency margins by responding to short term effects by quickly varying the clock frequency and long term effects by finding an optimal frequency point. A sensor indicates frequency margins associated with safe use of the clock signal, and these frequency margins are input into a frequency compensator and used to determine whether the system is operating within acceptable margins, or alternatively to modify the operating clock frequency on a short-term basis in order to achieve acceptable operating margins. The requests for frequency adjustment by the frequency compensator are provided to a frequency filter, which combines such request with a maintained/accumulated history of previous short-term frequency requests that have previously been made in order to determine whether an update needs to be made to the target frequency to provide long-term frequency control. | 2009-08-06 |
20090195276 | System and method for implementing a digital phase-locked loop - An apparatus for implementing a digital phase-locked loop includes a voltage-controlled oscillator that generates a primary clock signal in response to a VCO control voltage. Detection means generates counter control signals, including count up signals and count down signals, to indicate a current relationship between the primary clock signal and a reference signal. An up/down counter then either increments or decrements a counter value in response to corresponding counter control signals. The counter value is then converted by a digital-to-analog converter into the VCO control voltage for adjusting the frequency of the primary clock signal generated by the voltage-controlled oscillator. In alternate embodiments, the foregoing up/down counter may be utilized to adjust the frequency of the voltage-controlled oscillator in proportion to the counter value by utilizing appropriate techniques other than generating a VCO control voltage with a digital-to-analog converter. | 2009-08-06 |
20090195277 | SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLK | 2009-08-06 |
20090195278 | METHOD AND CIRCUIT FOR CONTROLLING CLOCK FREQUENCY OF AN ELECTRONIC CIRCUIT WITH NOISE MITIGATION - A technique to mitigate noise spikes in an electronic circuit device such as an integrated circuit. The clock frequency of a clock signal used by the electronic circuit is controlled such that instantaneously large changes to the clock frequency are avoided by use of a frequency filter that is capable of generating frequency ramps having a linear slope which is used as a feedback signal in a digital phase-locked loop clock circuit in lieu of a discrete, stair-stepped feedback control signal. | 2009-08-06 |
20090195279 | DELAY LOCKED LOOP CIRCUIT AND METHOD - Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference. A low pass filter may filter an output from the charge pump. The delay locked loop may further include a delay line having a plurality of delay elements, the plurality of delay elements including a first selectable group and a second selectable group that is larger than the first selectable group. A first clock signal from the first group of delay elements may be provided to the phase detector to first synchronize the delay locked loop, and following the synchronization, a second clock signal from the second group may be employed to synchronize the delay locked loop. | 2009-08-06 |
20090195280 | INTEGRATED CIRCUIT HAVING A MEMORY WITH A PLURALITY OF STORAGE CELLS OF SYNCHRONOUS DESIGN AND CONNECTED TO CLOCK GATING UNITS - In a memory area having portions of predictable access frequency, such as in a memory area of a real time clock unit, a synchronous design may be implemented by associating storage cells of identical access frequency with a clock gating mechanism, thereby reducing power consumption. Hence, the synchronous design of the real time clock unit may provide reduced implementation effort and enhanced verification capability. | 2009-08-06 |
20090195281 | Timing Signal Generating Circuit, Semiconductor Integrated Circuit Device and Semiconductor Integrated Circuit System to which the Timing Signal Generating Circuit is Applied, and Signal Transmission System - A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period. | 2009-08-06 |
20090195282 | Semiconductor integrated circuit device having standard cell including resistance element - A standard cell includes an input terminal, an output terminal, first and second inverters coupled in series between the input and output terminals, the first inverter including a first transistor of a first conductivity type and a second transistor of a second conductivity type, the first transistor being coupled between a first power source terminal and a first node, and the second transistor being coupled between a second node and a second power source terminal, and a plurality of resistance elements which are used to provide a conductivity path between the first and second nodes, in order to adjust a duty ratio of a signal which passes the standard cell. | 2009-08-06 |
20090195283 | DELAY LOCKED LOOP - The digital duty cycle correction circuit according to the present invention includes a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock. | 2009-08-06 |
20090195284 | SEMICONDUCTOR DEVICE EQUIPPED WITH A PULL-DOWN CIRCUIT - Provided is a semiconductor device equipped with a pull-down circuit capable of reducing its area. The pull-down circuit is formed of a depletion type NMOS transistor in which a gate thereof is connected to a ground potential, and an enhancement type NMOS transistor in which a gate and a drain thereof are connected to a source of the depletion type NMOS transistor and a source thereof is connected to the ground potential. An overdrive voltage of the depletion type NMOS transistor is reduced by a threshold voltage of the enhancement type NMOS transistor, whereby a size of the depletion type NMOS transistor can be reduced. Accordingly, an area of the pull-down circuit can be reduced. | 2009-08-06 |
20090195285 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit is provided with one or more flip-flop circuits ( | 2009-08-06 |
20090195286 | PHASE SHIFTING USING ASYMMETRIC INTERPOLATOR WEIGHTS - Illustrative embodiments provide an apparatus for phase shifting to produce uniform phase steps in a predictable manner to improve the linearity of conversion. The apparatus comprises a phase selector for selecting two or more phases to create selected phases and a phase interpolator capable of receiving the selected phases. The apparatus further comprises a set of digital to analog converter cells connected to the phase interpolator, wherein interpolator weight distribution among the set of digital to analog converter cells is non-linear, and a thermometer code in communication with the set of digital to analog converter cells, wherein the thermometer code adjusts output of the set of digital to analog converter cells to phase shift the selected phases. | 2009-08-06 |
20090195287 | APPARATUS AND METHOD FOR EXTERNAL TO INTERNAL CLOCK GENERATION - A phase recombination circuit includes a first phase input and a first one-shot pulse generator adapted to receive the first phase input and produce a first signal to pull a signal to a first state. The phase recombination circuit also includes a second phase input in phase relationship with the first phase input, and a second one-shot pulse generator adapted to receive the second phase input and produce a second signal to pull a signal to a second state. | 2009-08-06 |
20090195288 | SERIAL LINK TRANSMITTER - The invention provides a serial link transmitter coupled to a serial link receiver through a pair of transmission lines and having a pair of transmitting terminals respectively coupled to one of the transmission lines. The serial link transmitter comprises a differential amplifier and a voltage clamping circuit. The differential amplifier generates a pair of differential output voltages on the transmitting terminals according to a pair of differential input voltages for transmitting data to the serial link receiver, and the differential output voltages are transmitted with a common mode voltage to the serial link receiver during data transmission. The voltage clamping circuit clamps the pair of differential output voltages of the transmitting terminals to the common mode voltage before the serial link transmitter transmits data to the serial link receiver. | 2009-08-06 |
20090195289 | Process-Variation Tolerant Diode, Standard Cells Including the Same, Tags and Sensors Containing the Same, and Methods for Manufacturing the Same - Process variation-tolerant diodes and diode-connected thin film transistors (TFTs), printed or patterned structures (e.g., circuitry) containing such diodes and TFTs, methods of making the same, and applications of the same for identification tags and sensors are disclosed. A patterned structure comprising a complementary pair of diodes or diode-connected TFTs in series can stabilize the threshold voltage (V | 2009-08-06 |
20090195290 | METHOD AND APPARATUS FOR OVERSHOOT AND UNDERSHOOT ERRORS CORRECTION IN ANALOG LOW DROPOUT REGULATORS - The present invention provides a method and apparatus for dynamically correcting overshoot and undershoot errors in an analog integrated circuit by improving the reaction time (Δt) of the analog integrated circuit. Equivalently, an error correction circuit is disclosed present invention is only activated to reduce overshoot and undershoot errors by increasing the bandwidth of the integrated circuit when either undershoot or overshoot errors are detected. | 2009-08-06 |
20090195291 | Level shift circuit, and driver and display system using the same - Disclosed is a level shift circuit that includes a first level shifter which is connected between an output terminal and a first power supply terminal that supplies a first voltage and sets the output terminal to a level of the first voltage when an input signal received at an input terminal assumes a first value; a second level shifter which is connected between the output terminal and a second power supply terminal that supplies a second voltage and sets the output terminal to a level of the second voltage when the input signal assumes a complementary value of the first value; and a feedback control unit that performs control of deactivating the first level shifter during a predetermined time interval including a point of time when the input signal is supplied when it is detected that the output terminal immediately before the input signal is received at the input terminal assumes the first voltage level. When the input signal supplied in the predetermined time interval assumes a value that sets the output terminal to the second voltage level, the second level shifter sets the output terminal to the second voltage level with the first level shifter deactivated. | 2009-08-06 |
20090195292 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost. | 2009-08-06 |
20090195293 | EMITTER-SWITCHED BIPOLAR TRANSISTOR - The invention relates to a power circuit with a emitter-switched bipolar transistor (ESBT) (T | 2009-08-06 |
20090195294 | Method and System for Signal Generation via a Temperature Sensing Crystal Integrated Circuit - Aspects of a method and system for signal generation via a temperature sensing crystal integrated circuit are provided. In this regard, a temperature sensing crystal integrated circuit (TSCIC) comprising a memory and a crystal or crystal oscillator may generate a signal indicative of a measured temperature. The generated signal and data stored in the memory may be utilized to configure one or more circuits communicatively coupled to the TSCIC. The data stored in the memory may characterize behavior of the TSCIC as a function of temperature and/or time. The data characterizing the behavior of the TSCIC may indicate variations in frequency of the crystal or crystal oscillator as a function of temperature and/or time. The data characterizing the behavior of the TSCIC may comprise one or both of a frequency value and a frequency correction value. | 2009-08-06 |
20090195295 | Semiconductor device having power supply system - A semiconductor device is provided which includes: a first semiconductor integrated circuit; a ground line and a power supply line trough which electric power is supplied to the first semiconductor integrated circuit; and a variable impedance component which is connected between the ground line and the power supply line. | 2009-08-06 |
20090195296 | Method for Recovering an On-State Forward Voltage and, Shrinking Stacking Faults in Bipolar Semiconductor Devices, and the Bipolar Semiconductor Devices - In a bipolar semiconductor device such that electrons and holes are recombined in a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate at the time of on-state forward bias operation; an on-state forward voltage increased in a silicon carbide bipolar semiconductor device is recovered by shrinking the stacking fault area enlarged by on-state forward bias operation. In a method of this invention, the bipolar semiconductor device in which the stacking fault area enlarged and the on-state forward voltage has been increased by on-state forward bias operation, is heated at a temperature of higher than 350° C. | 2009-08-06 |
20090195297 | CCD DEVICE AND METHOD OF DRIVING SAME - Disclosed is a CCD device in which a charge transfer register of a CCD structure is connected to a charge detector via an output gate and has a reset gate between the charge detector and a reset drain, and an output gate pulse opposite in phase from a reset pulse applied to the reset gate is applied to the output gate. A dummy charge detector and an amplitude adjusting circuit are provided. On the basis of detection of the potential of a diffusion layer in the dummy charge detector, the amplitude adjusting circuit controls the amplitude of the output gate pulse applied to the output gate. | 2009-08-06 |
20090195298 | CHARGE PUMP CIRCUIT AND ELECTRONIC APPARATUS PROVIDED WITH THE SAME - A pumping circuit includes: a pumping capacitance; a first drive transistor connected between an input node for receiving an input voltage and one terminal of the pumping capacitance; and a second drive transistor connected between an output node for outputting an output voltage and the one terminal of the pumping capacitance. In a charge storing mode, the first drive transistor is turned ON to store charge in the pumping capacitance, while in a charge transfer mode, the second drive transistor is turned ON to transfer the charge stored in the pumping capacitance to the output node. The protection circuit puts at least one of the first and second drive transistors in a high-resistance state in which the resistance value is higher than when the transistor is ON, based on whether the output voltage is higher or lower than a predetermined judgment voltage. | 2009-08-06 |
20090195299 | APPARATUS AND METHOD FOR PREVENTING EXCESSIVE INCREASE IN PUMPING VOLTAGE WHEN GENERATING PUMPING VOLTAGE - A device for generating a pumping voltage and preventing an excessive increase in the pumping voltage includes a pumping voltage output unit that outputs a pumping voltage and adjusts the level of the pumping voltage in order to maintain a target voltage. The level of the pumping voltage is adjusted in response to a change in the level of the pumping unit. A release unit is included to detect an excessive pumping voltage. The release unit adjusts the level of the pumping voltage when the pumping voltage reaches a predetermined excessive level by compulsively decreasing the pumping voltage to prevent damage in the DRAM. | 2009-08-06 |
20090195300 | Gate controlled atomic switch - The invention relates to a method for producing a switch element. The invention is characterised in that the switch element comprises three electrodes that are located in an electrolyte, two of which (source electrode and drain electrode) are interconnected by a bridge consisting of one or more atoms that can be reversibly opened and closed. The opening and closing of said contact between the source and drain electrodes can be controlled by the potential that is applied to the third electrode (gate electrode). The switch element is produced by the repeated application of potential cycles between the gate electrode and the source or drain electrode. The potential is increased and reduced during the potential cycles until the conductance between the source and drain electrode can be switched back and forth between two conductances, as a result of said change in potential in the gate electrode, as a reproducible function of the voltage of the gate electrode. | 2009-08-06 |
20090195301 | BAND-GAP REFERENCE VOLTAGE DETECTION CIRCUIT - Methods, devices, modules, and systems for a band-gap reference voltage detection circuit are provided. One embodiment for a band-gap reference voltage detection circuit includes a Brokaw cell having a band-gap reference voltage, and a circuit portion for indicating the magnitude of an input voltage signal with respect to the band-gap reference voltage. The input voltage is applied to transistor bases of the Brokaw cell. | 2009-08-06 |
20090195302 | REFERENCE BUFFER - A reference buffer is disclosed. The reference buffer includes a main source follower stage, a replica source follower stage, and a low-pass filter. The main source follower stage provides a first main voltage according to a first driving voltage. The replica source follower stage duplicates the first main voltage to generate a first reference voltage. The low-pass filter is coupled between the main source follower stage and the replica source follower stage. | 2009-08-06 |
20090195303 | Method of Reducing Common Mode Current Noise in Power Conversion Applications - A transformer and filter circuit for reducing common mode noise current in isolated power conversion circuits, comprising a series connection of: a first transformer having an N:1 turns ratio, a common mode current filter, and a second transformer having a 1:M turns ratio. The overall effect being a transformer with N:M turns ratio and with low capacitive coupling from the primary N turns to the secondary M turns thus providing a high impedance to common mode currents crossing the isolation. The series connection of two transformers allows one to be bridged with additional common mode filter components without significant reduction in isolation impedance. | 2009-08-06 |
20090195304 | TRANSADMITTANCE AND FILTER HAVING A GAIN FUNCTION - Disclosed are a circuit and a method for tuning a programmable filter including input terminals, output terminals, a filter network and a transadmittance stage. The input terminals can receive input signals, and the output terminals output a filtered signal. The transadmittance stage, coupled to the input terminals, generates a current at its output based on the input signals. The output of the transadmittance stage can be coupled to the output terminals. The filter network can be a resistive-capacitive network connected to the input terminals. The RC network can include a capacitance respectively coupling the input terminals to output terminals, and a voltage divider network coupling the input and output terminals together. The transadmittance stage output terminals can be connected to the voltage divider, and the output terminals of the programmable filter circuit are coupled to respective intermediate nodes of the voltage divider network to provide a filtered output signal. | 2009-08-06 |
20090195305 | Analog Switch Controller - Methods and systems for implementing an analog switch controller to improve linearity of analog switches are described. | 2009-08-06 |
20090195306 | SWITCHED-CAPACITOR CIRCUIT HAVING SWITCH-LESS FEEDBACK PATH - A switched-capacitor circuit includes a plurality of cascaded differential-input, single-ended-output amplifiers. A negative feedback path, from an output terminal of a last of the cascaded amplifiers to an input terminal of a first of the cascaded amplifiers, is configured to exclude, and not be shorted out by, any switches. | 2009-08-06 |
20090195307 | MULTIPLE-PATH POWER AMPLIFIER - An amplifier circuit and method for amplifying a signal efficiently over a plurality of power ranges. The amplifier circuit including a strong amplifier which is efficient over a first power range and a weak amplifier which is efficient over a second power range. An impedance transformation circuit is used for generating a higher potential and providing increased efficiency when the second range of power is present. A circuit biases active the strong amplifier when the first power range of is present and biases active the weak amplifier when the second power range is present. | 2009-08-06 |
20090195308 | AUTOMATIC GAIN CONTROL CIRCUIT - An automatic gain control circuit includes a first voltage dividing resistor, a filter circuit, a switch circuit, and an amplifying circuit. The first voltage dividing resistor divides a voltage of the automatic gain control circuit using an internal impedance of the audio device to produce a divided DC voltage, wherein the first voltage dividing resistor is connected between a first power source and an output of the audio device. The filter circuit filters audio signals outputted from the audio device to produce filtered audio signals, and wherein the filter circuit receives the divided DC voltage, wherein the filter circuit is connected to the output of the audio device. The switch circuit outputs controlling signals according to the divided DC voltage from the filter circuit. The amplifying circuit amplifies the filtered audio signals according to the controlling signals. An electronic device using the automatic gain control circuit is also provided. | 2009-08-06 |
20090195309 | DISTORTION COMPENSATOR APPARATUS, AMPLIFIER APPARATUS, TRANSMITTER, AND METHOD OF COMPENSATING DISTORTION - This distortion compensator apparatus is a distortion compensator apparatus compensating nonlinearity of an amplifier and includes: a memory storing a compensation parameter used for correcting an input signal of the amplifier; a compensator correcting the input signal of the amplifier based on the compensation parameter; and an update controller updating the compensation parameter according to an operation state of the amplifier. | 2009-08-06 |
20090195310 | LNA HAVING A POST-DISTORTION MODE AND A HIGH-GAIN MODE - A differential low noise amplifier (LNA) is operable in a selectable one of two modes. The LNA includes a first transistor, a second transistor, a third transistor and a fourth transistor. In the first mode (PDC mode), the four transistors are configured to operate as a post-distortion cancellation (PDC) LNA. The third and fourth transistors operate as cancel transistors that improve linearity, but reduce LNA gain somewhat. In the second mode (high gain mode), the third and fourth transistors are configured so that amplified versions of the LNA input signal that they output are added to amplified versions of the LNA input signal that are output by the first and second main transistors, resulting in increased gain. Multiplexing circuits are provided within the LNA so that the LNA is configurable into a selectable one of the two modes by controlling a digital mode control signal supplied to the LNA. | 2009-08-06 |
20090195311 | INDEPENDENT DOMINANT POLE COMPENSATION OF TWO LOOPS USING ONE COMPENSATION ELEMENT - Disclosed is a differential amplifier system that maintains high speed characteristics of the differential amplifier while providing stability from a common-mode loop by using dominant pole compensation. The disclosed system includes a first and second transconductance stage, a circuit having high impedance, and a compensation circuit. | 2009-08-06 |
20090195312 | DIFFERENTIAL AMPLIFIER - A differential amplifier comprises a left amplifier having transistors, a right amplifier having transistors, a negative feedback network having a resistor, and a negative feedback network having a transformer with a center tap. Phase compensation networks comprising a capacitor and a resistor, a capacitor and a resistor, and a capacitor and a resistor are further added to the amplifier. Both ends of a secondary winding of the transformer are connected to the output terminals of the right and left amplifiers, and the center tap of the secondary winding is grounded, so that a differential amplified output signal can be fed back to a single-phase input using one transformer, thereby reducing a cost and an area. | 2009-08-06 |
20090195313 | BOOSTED TAIL-CURRENT CIRCUIT - A circuit includes a pair of input transistors configured as a differential pair and having input terminals configured to receive an input voltage. The circuit also includes a first current source connected to and configured to provide a first tail current to the pair of input transistors, the first tail current being a class-A current having a non-zero quiescent value. The circuit also includes a second current source connected to and configured to provide a second tail current to the pair of input transistors, the second tail current being a class-B current having a zero quiescent value and a non-zero non-quiescent value. The second current source is configured to provide the second tail current as a function of the input voltage. | 2009-08-06 |
20090195314 | DEVICE AND METHOD FOR AMPLIFYING PULSED RF SIGNALS - Device and method are described for amplifying pulsed RF signals, comprising one or more transistors, each comprising a drain, a gate and a source. A device synchronizes the supply for the drain with an RF pulse. | 2009-08-06 |
20090195315 | SAMPLE-AND-HOLD AMPLIFIERS - A sample-and-hold amplifier is provided. The sample-and-hold amplifier comprises a sample-and-hold circuit and a buffer circuit. The sample-and-hold circuit receives an input signal and transmits the input signal to a first node according to a control signal. The buffer circuit is coupled between a supply voltage source and a ground and controlled by the first node to provide an output signal at an output node. The buffer circuit comprises a native MOS transistor coupled to the output node. | 2009-08-06 |
20090195316 | RE-CONFIGURABLE LOW NOISE AMPLIFIER UTILIZING FEEDBACK CAPACITORS - A re-configurable low noise amplifier utilizing feedback capacitors is disclosed. The low noise amplifier has output transistors, capacitor switch cells, and capacitance distributors all in an output terminal. The output transistors are for controlling selection of a specific frequency band in a wide band of frequencies. The capacitor switch cells are for adjusting a harmonic frequency for the specific frequency band. The capacitance distributor is for determining an amount of gain, and according to the gain, an output impedance feeds back to an input terminal of the low noise amplifier for input matching. Since the output terminal is at high impedance and suitable for a wide band of frequencies, input matching not only makes the low noise amplifier applicable to kinds of wireless communication standards, but also fulfills high gain and low noise figure. | 2009-08-06 |
20090195317 | Multi-Mode High Efficiency Linear Power Amplifier - A power amplifier includes a plurality of amplification paths in which at least one amplification path is selectively enabled and disabled, wherein each amplification path includes an output impedance modification element and an output phase shift element that is operable independently from the output impedance modification element, and wherein the output impedance modification element in each amplification path provides selective impedance for each amplification path. | 2009-08-06 |
20090195318 | Self Regulating Biasing Circuit - A disclosed self regulating biasing circuit (SRBC) includes an unregulated node that couples to an unregulated power supply that produces a supply voltage. An impedance element of the SRBC carries an unregulated current having a nominal component and a variance component between an unregulated node and a regulated node. A detection circuit connected between the unregulated node and a third node detects a variance component of a supply voltage and generates a detection current based on the variance component. A compensation circuit connected to the third node draws a compensation current, based on the detection current, from the regulated node. The SRBC is designed wherein the compensation current is approximately equal to the variance component of the unregulated current. The regulated node may be connected to a control terminal of a transistor to be biased. | 2009-08-06 |
20090195319 | Large Time Constant Steering Circuit and Instrumentation Amplifier Implementing Same - The present invention relates to a large time constant steering circuit for slowly changing a voltage on a node between at least two discrete voltage levels. The present invention further relates to a slow steering current DAC comprising said large time constant steering circuit. The present invention further relates to an instrumentation amplifier device comprising a current balancing instrumentation amplifier for amplifying an input signal to an amplified output signal and a DC servo-loop for removing a DC-component from the input signal. The present invention further relates to an EEG acquisition ASIC comprising said instrumentation amplifier device. | 2009-08-06 |
20090195320 | IMPLEMENTING LAYOUT OF INTEGRATED CIRCUIT CONTAINING OPERATIONAL AMPLIFIER - A method for implementing a layout of an integrated circuit containing an OP (operational amplifier) is disclosed. The method includes constructing an output path connecting an output terminal of the OP to an output pad of the OP; and constructing a feedback path connecting an input terminal of the OP to an element of the OP, the element lying in an area covering the output pad, in which a minimum distance between the element and the output pad is less than a tenth of length of the feedback path. The present invention also provides an integrated circuit device produced through the method. | 2009-08-06 |
20090195321 | INTEGRATED FREQUENCY CALIBRATION ARCHITECTURE - In an exemplary embodiment, a free running VCO has two modes: a normal operating mode and a calibration mode. In the calibration mode, the free running VCO is phase lock looped with itself instead of a calibration VCO. Furthermore, in an exemplary embodiment, a tuning voltage for the free running VCO is adjusted to offset any tuning error. In addition, in various embodiments a reference crystal oscillator used in the phase lock loop is located on a DSP module instead of on the RF module. In yet another exemplary embodiment, the free running VCO is the only high frequency VCO on a radio frequency module. | 2009-08-06 |
20090195322 | CRYSTAL OSCILLATOR FREQUENCY CALIBRATION - Techniques are disclosed for estimating a frequency of a crystal oscillator based on temperature. In an embodiment, the oscillator frequency is computed using a polynomial approximation. Techniques are disclosed for deriving and periodically updating the coefficients used in the polynomial approximation. | 2009-08-06 |
20090195323 | SURFACE-MOUNT TYPE CRYSTAL OSCILLATOR - A surface-mount type crystal oscillator includes: a container body including a base wall and a frame wall, the frame wall being arranged on one principal surface of the base wall as including an opening; a crystal blank hermetically encapsulated inside a recess of the container body, the recess being formed by the opening of the frame wall; and an IC chip in which an oscillation circuit that uses the crystal blank is integrated. A flat portion which is a part of the base wall protrudes outwardly from an outer circumference of the frame wall. The IC chip is fixed to the one principal surface of the base wall at the flat portion. A testing terminal which is electrically connected with the crystal blank is provided on the one principal surface of the base wall at the flat portion. | 2009-08-06 |
20090195324 | BALUN TRANSFORMER WITH IMPROVED HARMONIC SUPPRESSION - An electronic assembly includes a substrate ( | 2009-08-06 |
20090195325 | DIFFERENTIAL INTERNALLY MATCHED WIRE-BOND INTERFACE - In wireless communication devices, internally matching impedance in millimeter wave packaging enables better signal retention at high frequencies in the range of 15 GHz and above. Through the use of differential wire bond signal transmission, the inherent inductance of a millimeter wave package can be matched by the capacitance of the package wire bonds if the capacitance is tailored. The capacitance can be tailored by calculating a suitable distance between wire bonds and tuning the dielectric constant of the over-mold material. A differential set of wire bonds act like a differential transmission line whose characteristic impedance can be tuned by configuring the dielectric constant of the over-mold of the millimeter wave package. | 2009-08-06 |
20090195326 | DUAL-FREQUENCY MATCHING CIRCUIT - The connection topology of input terminals | 2009-08-06 |
20090195327 | TRANSMITTING RADIO FREQUENCY SIGNAL IN SEMICONDUCTOR STRUCTURE - A semiconductor device for transmitting a radio frequency signal along a signal line includes a signal line that extends along a principal axis. On one side of the signal line is a first dielectric, and on the opposite side of the signal line is a second dielectric. First and second ground lines are proximate to the first and second dielectrics, respectively, and the ground lines are approximately parallel to the signal line. The device has a transverse cross-section that varies along the principal axis. | 2009-08-06 |
20090195328 | DELAY LINE, SIGNAL DELAY METHOD, AND TEST SIGNAL GENERATING APPARATUS - Provided is a delay line that prevents reflection signals output from a test signal generator from being superimposed as noise. The delay line delays an electrical signal input into a signal line and outputs the thus delayed signal, and includes three or more passive elements that are provided on the signal line and delay the signal. Each section of the signal line between pairs of adjacent passive elements has a different electrical length. The reflection signals reflected by the passive elements are superimposed on each other at different phases. It is desirable that the reflection signals reflected by adjacent passive elements differ by 180 degrees. | 2009-08-06 |
20090195329 | VARIABLE PHASE SHIFTER - Disclosed is a variable phase shifter The variable phase shifter includes a housing; a fixed board unit fixedly installed inside the housing, equipped with an input microstrip line with a via hole for receiving an input signal on one face thereof, and equipped with at least one circular arc-shaped output microstrip line outside the input microstrip line; and a rotating board unit rotatably installed inside the housing while being in contact with the one face of the fixed board unit, equipped with a transmission microstrip line on a face coming in contact with the one face of the fixed board unit, and for providing at least one output signal by making coupling even during rotation thereof. | 2009-08-06 |
20090195330 | VIBRATOR, RESONATOR USING THE SAME AND ELECTROMECHANICAL FILTER USING THE SAME - An object is to provide a resonator and a vibrator with a high Q value in which dissipation of vibration energy in vibration of the vibrator is small, and a thickness of a support part of the vibrator of a beam structure is made thicker than a thickness of the vibrator and the support part is formed in axisymmetry with respect to a length direction of a beam. By this configuration, brittleness of the support part is improved and loss of vibration energy from the support part is reduced and also loss of vibration energy resulting from surface roughness of a surface of the vibrator can be reduced, so that a resonator having a high Q value can be provided. | 2009-08-06 |
20090195331 | FILTER - A filter includes: a container; at least one barrier, an input device and an output device. The at least one barrier divide the container into at least two resonant cavities. Each resonant cavity has a harmonic oscillators disposed therein. At least one of the harmonic oscillators comprises a supporter and a carbon nanotube structure disposed on a surface of the supporter. | 2009-08-06 |
20090195332 | WIRELESS NON-RADIATIVE ENERGY TRANSFER - The electromagnetic energy transfer device includes a first resonator structure receiving energy from an external power supply. The first resonator structure has a first Q-factor. A second resonator structure is positioned distal from the first resonator structure, and supplies useful working power to an external load. The second resonator structure has a second Q-factor. The distance between the two resonators can be larger than the characteristic size of each resonator. Non-radiative energy transfer between the first resonator structure and the second resonator structure is mediated through coupling of their resonant-field evanescent tails. | 2009-08-06 |
20090195333 | WIRELESS NON-RADIATIVE ENERGY TRANSFER - The electromagnetic energy transfer device includes a first resonator structure receiving energy from an external power supply. The first resonator structure has a first Q-factor. A second resonator structure is positioned distal from the first resonator structure, and supplies useful working power to an external load. The second resonator structure has a second Q-factor. The distance between the two resonators can be larger than the characteristic size of each resonator. Non-radiative energy transfer between the first resonator structure and the second resonator structure is mediated through coupling of their resonant-field evanescent tails. | 2009-08-06 |
20090195334 | HIGH FREQUENCY MODULE PROVIDED WITH POWER AMPLIFIER - The present invention is provided with a high frequency module comprising a multilayered substrate, a power amplifier IC mounted on the upper surface of the multilayered substrate, first and second filters disposed substantially directly below the power amplifier IC in an inner layer of the multilayered substrate, and coupling-reducing ground vias disposed between the first filter and the second filter. At least the first filter is disposed substantially directly below the power amplifier IC. The coupling-reducing ground vias double as thermal vias for dissipating heat generated by the power amplifier IC. | 2009-08-06 |
20090195335 | SEMICONDUCTOR CONFIGURATION HAVING AN INTEGRATED COUPLER AND METHOD FOR MANUFACTURING SUCH A SEMICONDUCTOR CONFIGURATION - A semiconductor configuration having an integrated coupler is provided. The semiconductor configuration includes a coupler which is integrated in the substrate and which includes a first port and a second port. The coupler defines, in a plan view onto the substrate, an inner region of the substrate surrounded at least in sections by the coupler, and an outer region of the substrate arranged outside to the coupler. The coupler is at least a magnetic coupler, a capacitive coupler, or a combination of both. At least a circuit element is integrated in the inner region of the substrate and includes a port which is electrically connected to the second port of the coupler. | 2009-08-06 |
20090195336 | TUNABLE VOLTAGE-CONTROLLED OSCILLATOR - A multi-band VOC includes a plurality of oscillators, each oscillators having an oscillatory range respectively; a plurality of capacitor tanks is provided in each oscillators, and each capacitors is composed of a plurality of capacitors in series connection; a voltage detecting device is provided to detect a voltage signal, and to select an oscillator; one end of a logic controller is provided to electrically connect to the voltage detecting device, and another end is provided to electrically connect to the capacitor tank, which is provided a control signal to drive capacitance of the capacitor tank; and a multiple device is provided to output an oscillation frequency. | 2009-08-06 |
20090195337 | MANUALLY SELECTABLE INSTANTANEOUS CURRENT SETTINGS FOR A TRIP UNIT AND ELECTRICAL SWITCHING APPARATUS INCLUDING THE SAME - A circuit breaker includes separable contacts, an operating mechanism structured to open and close the separable contacts, and a trip mechanism cooperating with the operating mechanism to trip open the contacts. The trip mechanism includes a current transformer structured to sense a current flowing through the contacts and provide a signal representative of the current. A manually operable selector selects one of a plurality of predetermined current conditions by using a plurality of different zener diodes. Each of the predetermined current conditions is greater than an arc reduction maintenance current condition of four times the maximum rated current of the trip mechanism. An instantaneous trip circuit cooperates with the current transformer and the manually operable selector to compare the signal representative of the current with respect to the selected one of the predetermined current conditions. The instantaneous trip circuit responsively causes the operating mechanism to instantaneously trip open the contacts. | 2009-08-06 |
20090195338 | CONTACTLESS SWITCH - The invention relates to a contactless switch ( | 2009-08-06 |
20090195339 | Magnetized Casing String Tubulars - A stack of magnetized casing tubulars includes a plurality of magnetized wellbore tubulars each of which includes a plurality of north and south magnetic poles imparted to a corresponding plurality of longitudinal positions along the tubulars. The plurality of wellbore tubulars are arranged into a stack having at least two rows and at least two columns, the wellbore tubulars are stacked side by side and atop one another such that the magnetic poles on one tubular are radially aligned with magnetic poles of an opposite polarity on adjacent tubulars. Such a configuration advantageously substantially eliminates weakening of the imparted magnetic field due to interaction of the magnetic poles on adjacent tubulars. | 2009-08-06 |
20090195340 | Method for Magnetizing Casing String Tubulars - A method for magnetizing a wellbore tubular includes a positioning a wellbore tubular substantially coaxially in a plurality of longitudinally spaced magnetizing coils deployed on a frame. The coils are selectively connected and disconnected from electrical power such that a circumferential electrical current flows in each of the coils to impart a predetermined magnetic field pattern to the tubular. Exemplary embodiments of this invention provide for semi-automated control of tubular magnetization and thereby enable a repeatable magnetic pattern to be imparted to each of a large number of wellbore tubulars. | 2009-08-06 |
20090195341 | Coil Device for Antenna and Antenna System for Rear Window of Vehicle - In a coil device for an antenna, a wide surface of a connector connecting section and a mounting surface of a fixing section are substantially vertically arranged. A connecter terminal can take a first arrangement or a second arrangement to a resin member. In the first arrangement the connector terminal can take, the connector connecting section is positioned on one end side in the width direction of the resin member, and in the second arrangement, the connector connecting section is positioned on the other end side in the width direction of the resin member by turning the connector connecting section in the first arrangement 180 degrees. | 2009-08-06 |
20090195342 | COMMON MODE CHOKE COIL - A common mode choke coil includes a core, external electrodes, a pair of windings, and a top plate. The core includes a winding core portion and a pair of flanges disposed at respective ends thereof. The external electrodes are provided at lower portions of the flanges. The pair of the windings is wound around the winding core portion of the core, and ends thereof are connected to the external electrodes, respectively. A lower surface and a side surface of the top plate are covered with a metal film and are adhered to upper surfaces of the flanges with an adhesive. Preferably, magnetic powder is mixed in the adhesive. | 2009-08-06 |
20090195343 | Planar inductor - A planar inductor ( | 2009-08-06 |
20090195344 | CONTACTLESS DATA COMMUNICATIONS COUPLER - The embodiments of the present invention provide a non-contact data connection that is adaptable to transmit data across an air gap. The data connection includes a first substrate ( | 2009-08-06 |
20090195345 | MAGNETIC ELEMENT - A magnetic element including a first core and a second core each of which has a winding core provided with a flange portion having a flange surface at least at one end thereof; and an intermediate core to form a closed magnetic circuit which is disposed between said first core and said second core in a manner being integrally connected with said first core and said second core. | 2009-08-06 |
20090195346 | THERMAL AND/OR MAGNETIC OVERLOAD TRIP - A thermal and/or magnetic overload trip device for an electrical switching device having multiple poles includes a housing having a housing member configured to receive a plurality of functional elements and being at least partially closable, The overload trip device further including a conductor strap associated with each of the multiple poles, each conductor strap having an associated housing portion, and a rotatable trip shaft configured to rotate between a rest position and an actuating position so as to trip an associated switching mechanism. The overload trip device further including at least one rotatable adjusting element configured to set the at least one of the presettable thermal threshold and the presettable magnetic threshold. Further, the housing member is configured so that the functional elements is insertable therein and is couplable to the housing member. | 2009-08-06 |
20090195347 | Device for detecting the location of a compression point - The device has a first substrate on which an electrical resistive element is mounted, and a second substrate on which a contact electrode is mounted. The contact electrode is disposed opposite the resistive element at an electrically insulating distance. It can be brought into electrical contact with the resistive element by pressing the substrates together. The device is provided with electrical or electronic circuitry for detecting the location of the compression point. At least one of the substrates is equipped with a flat leaf spring of spring-grade sheet metal attached flush thereto, which leaf covers the compression zone of the substrates. | 2009-08-06 |
20090195348 | Resistor, and method for making same - A resistor includes a substantially cylindrical resistive element having a resistance of less than about 1 mΩ, a substantially cylindrical first termination electrically connected to the resistive element and a second termination electrically connected to the resistive element. The substantially cylindrical first termination is hollow to allow for accepting a connection such as from a battery cable. In addition there may be sense leads present on the resistor. A method of forming a substantially cylindrical resistor includes forming a hollow cylindrical resistor body by rolling a flat sheet comprising a resistive element and a first termination and a second termination joined on opposite ends of the resistive element. | 2009-08-06 |
20090195349 | SYSTEM AND METHOD FOR HOME ENERGY MONITOR AND CONTROL - The invention generally concerns systems and methods for monitoring and controlling the power consumption of a power-consuming device. The system and method may connect to a power source and a power-consuming device, connecting the power-consuming device to the power source. The power usage of the power-consuming device may then be measured and monitored. This monitoring data may then be stored and optionally sent to a controlling device on a data network. The location of the power-consuming device may also be determined, recorded, and sent to a controlling device. The system may also control the power usage of the power-consuming device. In some cases, a remote server may connect multiple energy monitoring systems in order to gain additional efficiencies and foster a community-based social network. | 2009-08-06 |
20090195350 | Situationally Aware and Self-Configuring Electronic Data And Communication Device - A self-configuring wearable electronic data and communication device comprising a self-contained module comprising means for self-configuring based on a user's activity and context an operational mode in a plurality of operational modes, wherein the self contained module further comprises intelligent situational awareness derived from at least one of pre-programmed criteria, a sensing ability, a user-specified lifestyle theme, a communication functionality, an accessory, and a user motion pattern. The self-contained module further comprises a display, a processor, a memory, and a battery, and is capable of configuring itself according to an accessory to which it is attached or connected. | 2009-08-06 |
20090195351 | INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD - A information processing device includes: a busy-level acquiring section for acquiring information on user's busy-level; a controller for determining a presentation form of information currently presented according to the user's busy-level acquired by the busy-level acquiring section; an information processor for performing a predetermined processing to the information under the control of the controller; and an output processor for outputting the information having been subjected to the processing by the information processor to an output section. | 2009-08-06 |
20090195352 | SYSTEM AND METHOD FOR HOME AUTOMATION AND SECURITY - A home automation and security system is provided in which a home automation and security controller in a customer premises is coupled with a remotely located central control facility using a continuous connectivity access line providing a data channel separate from a voice channel. The controller at the customer premises is responsible for monitoring and applying control signals to devices in the home and for supporting a human interface. The remotely located central control facility is responsible for providing the computational and database resources to the controller. By redistributing functionality, the network-based structure of this home automation and security system can overcome the disadvantages of conventional home automation and security systems. | 2009-08-06 |
20090195353 | CONTROL DEVICE AND CONTROLLED DEVICE - A control device being a control device communicating with a controlled device to control the controlled device includes: a first memory to store first authentication information for authenticating the controlled device; a second memory to store second authentication information for making the controlled device authenticate itself; a determination unit to compare third authentication information sent from the controlled device for specifying the controlled device with the first authentication information; a calculator to perform calculation processing on the first authentication information or the third authentication information using the second authentication information to generate a calculated value; a transmitter to transmit, when the determination unit determines that the first authentication information and the third authentication information are the same, the calculated value to the controlled device; and a memory controller to update the first authentication information. | 2009-08-06 |
20090195354 | Authenticating a signal based on an unknown component thereof - Authentication of a signal, signal | 2009-08-06 |
20090195355 | METHODS AND APPARATUS FOR PLACE SHIFTING CONTENT TO A VEHICLE ENTERTAINMENT SYSTEM - Apparatus, systems and methods are provided for transferring content from a home entertainment system to a vehicle entertainment system through a wireless connection. A user requests to experience content, through a vehicle entertainment system that is stored or otherwise made available through a content source that is located remotely with respect to the vehicle entertainment system. The vehicle entertainment system transmits a request to a base station communicatively coupled to the content source and the base station responsively retrieves the content from the content source and transmits the content over a wireless connection to the vehicle entertainment system. | 2009-08-06 |
20090195356 | Power Estimation of an Active RFID Device - Methods and apparatus, including computer program products, for power estimating of an active RFID device. A method includes, in a radio frequency identification (RFID) interrogator, interrogating a RFID device, receiving an identification code, times and temperature data from the RFID device in response to the interrogation, and estimating a remaining battery life of a battery in the RFID device. A system includes a radio frequency identification (RFID) device having a store of times and temperature data, and a RFID interrogator programmed to interrogate the RFID, receive the times and temperature data, and estimate a remaining battery life of a battery in the RFID device from the times and temperature data. | 2009-08-06 |
20090195357 | Active transmission architecture without battery and application - An active transmission architecture without battery and the application are proposed, which make use of an analog front-end circuit to convert a received carrier into a dc signal for providing power for the active transmission architecture without battery, and therefore actively produces a replying signal with the same or different frequencies from the carrier. It is not necessary to add an extra power circuit, hence accomplishing the advantage of no battery. The proposed active transmission architecture without battery can apply to RFID systems or be used in applications that require transmitter and receiver modules. | 2009-08-06 |
20090195358 | RFID System With A Mobile RFID Reader - An RFID system includes a pair of guide tracks located on opposite boundaries of at least one zone. A channel is movably attached to the guide tracks and is configured to move along the guide tracks through the at least one zone. A mobile RFID reader is movably attached to the channel and the mobile RFID reader is paused at a plurality of read points to scan for RFID tags located. The read points are determined by an arrangement of a plurality of hexagonal areas which are grouped together to create a combined area, where the combined area is aligned with the predefined area to define locations of the plurality of hexagonal areas, and where substantially central locations of each hexagonal area represent the plurality of read points. | 2009-08-06 |
20090195359 | SEMICONDUCTOR DEVICE - An object is to increase the reliability of a semiconductor device which is capable of wireless communication. The semiconductor device includes a plurality of functional circuits as redundant circuits, and each of the plurality of functional circuits includes an antenna and a semiconductor integrated circuit. The plurality of functional circuits is covered with one sealing layer in which a fibrous body is impregnated with resin. Further, the semiconductor integrated circuit is provided with a transmission/reception circuit electrically connected to the antenna, a power supply circuit electrically connected to the transmission/reception circuit, and a logic circuit electrically connected to the transmission/reception circuit and the power supply circuit. | 2009-08-06 |
20090195360 | RFID SYSTEM AND COMMUNICATION METHOD PERFORMED BY THE SAME - Provided is an RFID system and method for maintaining a constant strength of a signal transmitted from an RFID tag to an RFID reader, regardless of a distance between the reader and tag. The RFID signal strength measuring reader measures a signal strength received from the RFID tag, creates control information used to set an amplification amount of the RFID tag by using a value of the measured strength to include the control information in an output signal, and sends the output signal to the RFID tag. The RFID tag, if the signal sent from the RFID reader is received, extracts internal information from the received signal, sends the information to the RFID reader as an output signal, and extracts the control information included in the signal sent from the RFID reader to adjust a strength of the output signal according to a value of the control information. | 2009-08-06 |