32nd week of 2015 patent applcation highlights part 55 |
Patent application number | Title | Published |
20150221514 | Charged-Particle-Beam Patterning Without Resist - A process for fabricating an integrated circuit is provided. The process includes providing a substrate, forming a hard mask upon the substrate by one of atomic-layer deposition and molecular-layer deposition, and exposing the hard mask to a charged particle from one or more charged particle beams to pattern a gap in the hard mask. In the alternative, the process includes exposing the hard mask to a charged particle from one or more charged-particle beams to pattern a structure on the hard mask. | 2015-08-06 |
20150221515 | METHOD AND APPARATUS FOR COOLING WAFER IN ION IMPLANTATION PROCESS - Embodiments of method for cooling a wafer in an ion implantation process are provided. A method for cooling the wafer in the ion implantation process includes placing the wafer in a process module. The method also includes performing the ion implantation process on the wafer and simultaneously cooling the wafer in the process module. The method further includes removing the wafer from the process module. In addition, the method includes heating up the wafer. | 2015-08-06 |
20150221516 | PROCESS-COMPATIBLE SPUTTERING TARGET FOR FORMING FERROELECTRIC MEMORY CAPACITOR PLATES - A sputtering target for a conductive oxide, such as SrRuO | 2015-08-06 |
20150221517 | METHOD OF MANUFACTURING SEMICONDUCTOE DEVICE - A method of manufacturing a semiconductor device capable of thinning a semiconductor chip can be performed while preventing the semiconductor chip from being damaged. A method of manufacturing a semiconductor device includes: preparing a semiconductor substrate including a plurality of semiconductor chips, attaching the semiconductor substrate to a support substrate with an adhesive support film, removing an edge region of the semiconductor substrate together with a portion of the adhesive support film between the edge region of the semiconductor substrate and the support substrate and, thereafter, polishing the semiconductor substrate to thin the semiconductor substrate. | 2015-08-06 |
20150221518 | DRY ETCHING METHOD - In the present invention, a dry etching method for plasma etching a second laminated film in which a first laminated film in which a silicon-containing film and a silicon dioxide film are laminated is laminated in plurality and an inorganic film arranged over the second laminated film, includes etching the inorganic film and the second laminated film by a mixed gas of an NF | 2015-08-06 |
20150221519 | VACUUM-INTEGRATED HARDMASK PROCESSES AND APPARATUS - Vacuum-integrated photoresist-less methods and apparatuses for forming metal hardmasks can provide sub-30 nm patterning resolution. A metal-containing (e.g., metal salt or organometallic compound) film that is sensitive to a patterning agent is deposited on a semiconductor substrate. The metal-containing film is then patterned directly (i.e., without the use of a photoresist) by exposure to the patterning agent in a vacuum ambient to form the metal mask. For example, the metal-containing film is photosensitive and the patterning is conducted using sub-30 nm wavelength optical lithography, such as EUV lithography. | 2015-08-06 |
20150221520 | COMPOSITION AND METHOD FOR POLISHING MOLYBDENUM - The present invention provides compositions and methods for polishing a molybdenum metal-containing surface. A polishing composition (slurry) described herein comprises an abrasive concentration of an inorganic particulate abrasive material (e.g., alumina or silica) suspended in an acidic aqueous medium containing a water soluble surface active material and an oxidizing agent. The surface active material is selected based on the zeta potential of the particulate abrasive, such that when the abrasive has a positive zeta potential, the surface active material comprises a cationic material, and when the particulate abrasive has a negative zeta potential, the surface active material comprises an anionic material, a non-ionic material, or a combination thereof. | 2015-08-06 |
20150221521 | CMP METHOD FOR SUPPRESSION OF TITANIUM NITRIDE AND TITANIUM/TITANIUM NITRIDE REMOVAL - A chemical mechanical polishing (CMP) method for removal of a metal layer deposited over a titanium nitride (TiN) or titanium/titanium nitride (Ti/TiN) barrier layer is described herein. The method comprises abrading the metal layer with an acidic CMP composition to expose the underlying TiN or Ti/TiN layer, wherein the TiN or Ti/N layer is polished at a low rate due to the presence of a surfactant inhibitor. The acidic CMP composition comprises a particulate abrasive (e.g., silica, alumina) suspended in a liquid carrier containing a surfactant selected from the group consisting of an anionic surfactant, a nonionic surfactant, cation surfactants, and a combination thereof. | 2015-08-06 |
20150221522 | PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - A plasma processing method performs an etching process of supplying a fluorine-containing gas into a plasma processing space and etching a target substrate, in which a silicon oxide film or a silicon nitride film is formed on a surface of a nickel silicide film, with plasma of the fluorine-containing gas (process S | 2015-08-06 |
20150221523 | ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME - An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration. | 2015-08-06 |
20150221524 | SLOPED PHOTORESIST EDGES FOR DEFECT REDUCTION FOR METAL DRY ETCH PROCESSES - A method of etching a metal containing layer including a metal including material includes providing a substrate including a top semiconductor surface having the metal containing layer thereon. A photoresist pattern is formed from a photoresist layer on the metal containing layer including forming sloped edge regions of the photoresist layer, wherein the sloped edge regions have an average angle over a full length of the sloped edge regions of from ten (10) to fifty (50) degrees. The metal containing layer is dry etched using the photoresist pattern, wherein the sloped edge regions of the photoresist layer reduce deposition and growth of an etch byproduct including the metal including material into sidewalls of the photoresist layer (metal/polymer sidewall defect) as compared to a conventional vertical (or near-vertical) edge of the photoresist layer. | 2015-08-06 |
20150221525 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - A semiconductor device includes an insulating substrate, a wiring pattern formed on the insulating substrate, a semiconductor chip secured to the wiring pattern, a junction terminal formed of the same material as the wiring pattern and electrically connected to the semiconductor chip, one end of the junction terminal being secured to the insulating substrate, the other end of the junction terminal extending upward away from the insulating substrate, and a control circuit for transmitting a control signal for the semiconductor chip, the control circuit being electrically connected to the junction terminal. | 2015-08-06 |
20150221526 | SELECTIVE PLANISHING METHOD FOR MAKING A SEMICONDUCTOR DEVICE - In a method for fabricating semiconductor devices a leadframe pattern is formed from a flat tape of base metal. A plurality of additional metal layers is plated on the patterned tape of base metal. The surface of the metal layers is roughed. A plurality of sites for assembling semiconductor chips are created. The sites alternate with zones for connecting the leadframe pattern to molding compound runners A selected first set of leadframe areas are selectively planished creating flattened areas offsetting a second set of leadframe areas. A semiconductor chip is attached to each site. | 2015-08-06 |
20150221527 | ENCAPSULANT COMPOSITION - Compositions that have relatively high Tg, relatively low CTE, and relatively low modulus are suitable for use as encapsulants with stress-sensitive electronic assemblies, such as those containing low k dielectrics. These compositions are used in methods of die attachment, encapsulation, and solder bump reinforcement. | 2015-08-06 |
20150221528 | PROCESS FOR IMPROVING PACKAGE WARPAGE AND CONNECTION RELIABILITY THROUGH USE OF A BACKSIDE MOLD CONFIGURATION (BSMC) - A backside mold configuration (BSMC) process for manufacturing packaged integrated circuits includes applying a mold compound to a side of a packaging substrate opposite an attached die. The mold compound is deposited on a dielectric (such as photo resist). The mold compound and dielectric are patterned after coupling a die to the packaging substrate to expose a contact pad of the packaging substrate. After patterning the mold compound and dielectric, a packaging connection is coupled to contact pads through the mold compound and dielectric. The mold compound surrounding the packaging connection reduces warpage of the packaging substrate during processing. Additionally, patterning the dielectric after attaching the die improves reliability of the packaging connection. | 2015-08-06 |
20150221529 | GAS SUPPLY METHOD AND THERMAL TREATMENT METHOD - A gas supply apparatus including a raw material gas supply system supplying a raw material gas inside a raw material storage tank into the processing container by the carrier gas, the gas supply apparatus includes: a carrier gas passage introducing the carrier gas into the raw material storage tank, a raw material gas passage connecting the raw material storage tank and the processing container to supply the carrier gas and the raw material gas; a pressure control gas passage being connected to the raw material gas passage to supply the pressure control gas; and a valve control unit controlling an opening/closing valve to perform for starting a supply of the pressure control gas into the processing container and simultaneously starting supply of the raw material gas into the processing container from the raw material storage tank, and stopping the supply of the pressure control gas. | 2015-08-06 |
20150221530 | SUBSTRATE LIQUID PROCESSING APPARATUS, SUBSTRATE LIQUID PROCESSING METHOD AND COMPUTER READABLE RECORDING MEDIUM HAVING SUBSTRATE LIQUID PROCESSING PROGRAM RECORDED THEREIN - Disclosed is a method for performing a liquid processing on a substrate using an aqueous solution of a chemical agent at a predetermined concentration as a processing liquid. The method includes: storing the processing liquid in a processing liquid storage unit; and supplying an aqueous solution of the chemical agent at a different concentration from the concentration of the processing liquid to the processing liquid storage unit, discharging the processing liquid from the processing liquid storage unit so as to update the processing liquid stored in the processing liquid storage unit. The aqueous solution in a predetermined amount is supplied to the processing liquid storage unit, and the processing liquid is discharged from the processing liquid storage unit, the processing liquid containing the chemical agent in the same amount as the amount of the chemical agent contained in the aqueous solution supplied to the processing liquid storage unit. | 2015-08-06 |
20150221531 | SUBSTRATE CLEANING APPARATUS AND SUBSTRATE PROCESSING APPARATUS - The present invention relates to a substrate cleaning apparatus for performing scrub cleaning of a surface of a substrate by rotating both of the substrate and a roll cleaning member while keeping the roll cleaning member in contact with the surface of the substrate. The substrate cleaning apparatus includes a roll holder ( | 2015-08-06 |
20150221532 | SUBSTRATE PROCESSING APPARATUS, HEATING APPARATUS, CEILING HEAT INSULATOR, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A ceiling heat insulator installed above a side wall heat insulator of a heating apparatus for a substrate processing apparatus for processing a substrate is provided. The ceiling heat insulator includes a gas-flow path installed therein to allow a cooling gas to pass therethrough so that the ceiling heat insulator has a solid cross-sectional area in an outer edge side of the ceiling heat insulator that is smaller than that in a center side of the ceiling heat insulator. | 2015-08-06 |
20150221533 | HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS FOR HEATING SUBSTRATE BY IRRADIATING SUBSTRATE WITH LIGHT - A surface of a semiconductor wafer with a gate of a high dielectric constant film formed thereon is heated to a target temperature for a short time by irradiating the surface with a flash of light. This promotes the crystallization of the high dielectric constant film while suppressing the growth of an underlying silicon dioxide film. Subsequently, the temperature of the semiconductor wafer subjected to the flash heating is maintained at an annealing temperature by irradiating the semiconductor wafer with light from halogen lamps. An annealing process after the flash heating is performed in an atmosphere of a gas mixture of hydrogen gas and nitrogen gas. The annealing process is performed on the semiconductor wafer in the atmosphere of the hydrogen-nitrogen gas mixture, so that defects present near the interfaces of the high dielectric constant film are eliminated by hydrogen termination. | 2015-08-06 |
20150221534 | STACKED PROCESS MODULES FOR A SEMICONDUCTOR HANDLING SYSTEM - A substrate transport apparatus having a drive section, an articulated arm operably connected to the drive section, and an end effector connected to the articulated arm, the end effector being configured for holding a substrate thereon and transporting the substrate through articulation of the articulated arm. The end effector is a substantially flat and elongated member, depending from the articulated arm at a base end of the end effector, and extending longitudinally so that the end effector engages edges of the substrate on both proximal and distal sides with respect to the base end. The end effector has a lateral cross section that tapers in a longitudinal portion of the end effector extending between the base end and a distal end of the end effector, the lateral cross section being tapered, along the longitudinal portion, in at least two different directions that are angled and crossing each other. | 2015-08-06 |
20150221535 | TEMPERATURE MEASUREMENT USING SILICON WAFER REFLECTION INTERFERENCE - Temperature measurement of a silicon wafer is described using the interference between reflections off surfaces of the wafer. In one example, the invention includes a silicon processing chamber, a wafer holder within the chamber to hold a silicon substrate for processing, and a laser directed to a surface of the substrate. A photodetector receives light from the laser that is reflected off the surface directly and through the substrate and a processor determines a temperature of the silicon substrate based on the received reflected light. | 2015-08-06 |
20150221536 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE TRANSFER METHOD AND SUBSTRATE TRANSFER DEVICE - A substrate processing apparatus can prevent photo-corrosion of, e.g., copper interconnects due to exposure of a surface to be processed of a substrate to light, and can perform processing, such as cleaning, of a substrate surface while preventing photo-corrosion of, e.g., copper interconnects due to exposure to light. The substrate processing apparatus includes a plurality of processing areas housing therein processing units which have been subjected to light shielding processing; and at least one transfer area housing therein a transfer robot and disposed between two adjacent ones of the plurality of processing areas. A light shielding wall is provided between the transfer area and each of the two adjacent processing areas, and a light-shielding maintenance door is provided for the front opening of the transfer area. The processing units are coupled to the light shielding walls in a light-shielding manner. | 2015-08-06 |
20150221537 | CONTAINER INTERCHANGING METHOD - A container interchanging method is provided. The container interchanging method provides that a first container accommodating a processed substrate therein and a second container accommodating an unprocessed substrate therein are interchanged in a container connection mechanism of a substrate transfer chamber. The substrate transfer chamber includes the container connection mechanism to which the container accommodating the substrate is connected. The substrate transfer chamber is configured to unload the substrate from the container connected to the container connection mechanism. The substrate transfer chamber further includes a buffer configured to mount the container. When the first container and the second container are interchanged in the container connection mechanism, any one of the first container and the second container is temporarily stored in the buffer. | 2015-08-06 |
20150221538 | LOAD PORT AND EFEM - A load port provided adjacent to a wafer transport chamber for taking in and out a wafer W between the wafer transport chamber and a FOUP, includes a plate-shaped part that constitutes a part of a wall of the wafer transport chamber, and has an opening for opening the wafer transport chamber; a door part for opening and closing the opening; a mounting table that is configured to mount a wafer storage container so as to oppose a lid part for opening and closing an internal space to the door part, and to move to and from the plate-shaped part; and an elastic part that is provided on the mounting table side of the plate-shaped part along the peripheral edge of the opening, wherein the elastic part elastically contacts the periphery of the lid part in the wafer storage container by moving the mounting table toward the plate-shaped part. | 2015-08-06 |
20150221539 | COOLED TAPE FRAME LIFT AND LOW CONTACT SHADOW RING FOR PLASMA HEAT ISOLATION - Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a tape frame lift assembly for a plasma processing chamber includes a capture single ring having an upper surface for supporting a tape frame of a substrate support and for cooling the tape frame. The tape frame lift assembly also includes one or more capture lift arms for moving the capture single ring to and from transfer and processing positions. The tape frame assembly also includes one or more captured lift plate portions, one captured lift plate portion corresponding to one capture lift arm, the one or more captured lift plate portions for coupling the one or more capture lift arms to the capture single ring. | 2015-08-06 |
20150221540 | DEVICES, SYSTEMS AND METHODS FOR ELECTROSTATIC FORCE ENHANCED SEMICONDUCTOR BONDING - Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates. | 2015-08-06 |
20150221541 | AIR GAP PROCESS - Methods are described for forming “air gaps” between adjacent metal lines on patterned substrates. The common name “air gap” will be used interchangeably with the more technically accurate “gas pocket” and both reflect a variety of pressures and elemental ratios. The air gaps are produced within narrow gaps between copper lines while wide gaps retain dielectric material. Retention of the dielectric material within the wide gaps enables formation of a desirable planar top surface. Using a hardmask layer and a selective dry-etch process enables a wet processing step to be avoided right before the formation of the air gaps. The air gaps can have a dielectric constant approaching one, favorably reducing interconnect capacitance compared with typical low-k dielectric materials. | 2015-08-06 |
20150221542 | METHODS AND APPARATUS FOR SELECTIVE DEPOSITION OF COBALT IN SEMICONDUCTOR PROCESSING - Methods and apparatus for selective deposition of cobalt on copper lines in the presence of exposed dielectric in semiconductor processing are provided. Cobalt in its metallic form is selectively deposited onto copper in the presence of dielectric by contacting a prepared surface of the substrate with an organometallic cobalt compound in a presence of a reducing agent. Surface preparation involves H | 2015-08-06 |
20150221543 | Semiconductor structure and method of forming a harmonic-effect-suppression structure - A method of forming a harmonic-effect-suppression structure is disclosed. The method includes: providing a semiconductor substrate having a base semiconductor substrate, a buried dielectric on the base semiconductor substrate, and a surface semiconductor layer on the buried dielectric. Next, a deep trench is formed extending through the surface semiconductor layer and the buried dielectric into the base semiconductor substrate, a silicon layer is formed within a lower portion of the deep trench, the silicon layer allowed to have a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate, and a dielectric layer is formed within the deep trench and on the silicon layer. | 2015-08-06 |
20150221544 | METHOD FOR SEPARATING AT LEAST TWO SUBSTRATES ALONG A SELECTED INTERFACE - A process for separating at least two substrates comprising at least two separation interfaces along one of the interfaces includes, before inserting a blade between the substrate, damaging at least one portion of a peripheral region of a chosen one of the interfaces, then inserting the blade and partially parting the substrates, and applying a fluid in a space between the parted substrates while the blade remains inserted therebetween, and decreasing a rupture energy of the chosen interface by stress corrosion involving breaking of siloxane bonds present at the interface. | 2015-08-06 |
20150221545 | METHOD FOR REDUCING SURFACE ROUGHNESS WHILE PRODUCING A HIGH QUALITY USEFUL LAYER - A method for producing a high quality useful layer of semiconductor material on a substrate. The method includes implanting at least two different atomic species into a face of a donor substrate to a controlled mean implantation depth to form a weakened zone therein and to define a useful layer. The implanting step is conducted to minimize low-frequency roughness at the weakened zone. Next, the method includes bonding a support substrate to the face of the donor substrate, and detaching the useful layer from the donor substrate along the weakened zone. A structure is thus formed that includes the useful layer on the support substrate with the useful layer presenting a surface for further processing. The technique also includes thermally treating the structure to minimize high-frequency roughness of the surface of the useful layer. The result is a surface having sufficient smoothness so that chemical-mechanical polishing (CMP) is not needed. | 2015-08-06 |
20150221546 | Semiconductor Diodes Fabricated by Aspect Ratio Trapping with Coalesced Films - A method of forming a photonic device that comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The method may further include forming a top diode material and an active diode region between the top and bottom diode materials. | 2015-08-06 |
20150221547 | HARDMASK FACETING FOR ENHANCING METAL FILL IN TRENCHES - A stack of an interlevel dielectric (ILD) layer, a dielectric cap layer, and a metallic hard mask layer is formed on a substrate. The metallic hard mask layer can be patterned with a first pattern. A photoresist layer is formed over the metallic hard mask layer and is patterned with a second pattern. A combination of the first pattern and the second pattern is transferred into the ILD layer to form a dual damascene trench, which includes an undercut underneath the patterned dielectric cap layer. The metallic hard mask layer is removed and the dielectric cap layer is anisotropically etched to form faceted edges and removal of overhanging portions. A metallic material can be deposited into the dual damascene trench without formation of voids during a metal fill process. | 2015-08-06 |
20150221548 | SEMICONDUCTOR DEVICES HAVING BIT LINE CONTACT PLUGS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device including active regions defined in a semiconductor substrate to be non-parallel with a first direction and a second direction which are perpendicular to each other, word lines intersecting active regions and extending in first directions to be spaced apart from each other in the second direction, bit lines crossing over word lines and extending in second directions to be spaced apart from each other in the first direction, first impurity regions disposed in respective ones of central portions of active regions to non-overlap with the word lines, second impurity regions disposed in both ends of each of the active regions to non-overlap with the word lines, and bit line contact plugs disposed between the first impurity regions and the bit lines. The bit line contact plugs having longish shapes including major axes substantially parallel with the second direction and minor axes substantially parallel with the first direction. | 2015-08-06 |
20150221549 | PROCESS METHODS FOR ADVANCED INTERCONNECT PATTERNING - Methods for achieving advanced patterning of an interconnect dielectric material layer are provided in which the dimension, i.e., width, of an opening that is formed into a metallic hard mask layer is shrunk prior to extending the opening into the interconnect dielectric material layer. The shrinking of the dimension of the opening that is formed into the metallic hard mask layer can be achieved in the present application by forming at least a metallic hard mask spacer portion on a sidewall surface of each patterned metallic hard mask layer. The aforementioned basic principle can be applied to forming a line opening, a via opening and/or a combined via and line opening within an interconnect dielectric material layer, wherein each of the openings (line, via and/or via and line) has a reduced dimension as compared to that obtainable utilizing conventional lithography. | 2015-08-06 |
20150221550 | INTEGRATION OF ALD BARRIER LAYER AND CVD Ru LINER FOR VOID-FREE Cu FILLING - Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal. | 2015-08-06 |
20150221551 | NON-LITHOGRAPHIC FORMATION OF THREE-DIMENSIONAL CONDUCTIVE ELEMENTS - A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate. | 2015-08-06 |
20150221552 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes a groove portion formation process of forming a groove portion in a base body, a bather layer formation process of forming a barrier layer covering at least the inner wall surface of the groove portion, a seed layer formation process of forming a seed layer covering the barrier layer, and a seed layer melting process of causing the seed layer to be melted using the reflow method. The seed layer is made of Cu. | 2015-08-06 |
20150221553 | COOLED TAPE FRAME LIFT AND LOW CONTACT SHADOW RING FOR PLASMA HEAT ISOLATION - Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a tape frame lift assembly for a plasma processing chamber includes a capture single ring having an upper surface for supporting a tape frame of a substrate support and for cooling the tape frame. The tape frame lift assembly also includes one or more capture lift arms for moving the capture single ring to and from transfer and processing positions. The tape frame assembly also includes one or more captured lift plate portions, one captured lift plate portion corresponding to one capture lift arm, the one or more captured lift plate portions for coupling the one or more capture lift arms to the capture single ring. | 2015-08-06 |
20150221554 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device that includes steps of: (1) adhering a support substrate to a first surface of a wafer using an adhesive, the wafer including first and second scribe lines extending along first and second directions, respectively, (2) thinning the wafer, (3) forming a groove in a first scribe line excluding a region located in an outer peripheral portion of the wafer, the groove piercing the wafer from the first surface to a second surface opposite to the first surface to expose the adhesive, the first scribe line and the second scribe line demarcating chip regions; and (4) removing the adhesive by immersing the wafer adhered to the support substrate in a solvent such that the solvent permeates into the groove. | 2015-08-06 |
20150221555 | INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - An integrated circuit structure is provided including a substrate, a low voltage device and a high voltage device. The low voltage device has a first beeline distance from a first epitaxial structure to an adjacent gate stack; and the high voltage structure has a second beeline distance from a second epitaxial structure to an adjacent gate stack. The second beeline distance of the high voltage device is greater than the first beeline distance of the low voltage device, so that the leakage current in the high voltage device may be decreased under high voltage operation. Further, a method for manufacturing the integrated circuit structure also provides herein. | 2015-08-06 |
20150221556 | METHOD TO FORM TRENCH STRUCTURE FOR REPLACEMENT CHANNEL GROWTH - Embodiments may include a method of semiconductor patterning including forming a first trench bordered by a first spacer material. The method may involve forming a second trench bordered by a second spacer material formed conformally around the first spacer material. The method may include filling the second trench with a semiconductor material. | 2015-08-06 |
20150221557 | WIRING STRUCTURES AND METHODS OF FORMING THE SAME - In a method of forming a wiring structure, a carbon-containing layer may be formed on a substrate. A conductive layer may be formed on the carbon-containing layer, and the conductive layer may be formed to include a metal. The conductive layer and an upper portion of the carbon-containing layer may be etched to form a wiring and a carbon-containing layer pattern, respectively. | 2015-08-06 |
20150221558 | POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR - A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions. | 2015-08-06 |
20150221559 | SEMICONDUCTOR DEVICE WITH TRANSISTOR AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device that includes forming a gate stack layer including a metal-containing layer on a semiconductor substrate having an NMOS region and a PMOS region, introducing arsenic to the gate stack layer in the NMOS region, introducing aluminum to the gate stack layer in the PMOS region, and etching the gate stack layers, where the arsenic and the aluminum are introduced, to form a first gate structure and a second gate structure in the NMOS region and the PMOS region, respectively. | 2015-08-06 |
20150221560 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region. | 2015-08-06 |
20150221561 | Method for Monitoring Ion Implantation - A method comprises placing a wafer and a ring-shaped beam profiler on a wafer holder, wherein the ring-shaped beam profiler is adjacent to the wafer, moving a first sensor and a second sensor simultaneously with the wafer holder, receiving a first sensed signal and a second sensed signal from the first sensor and the second sensor respectively and adjusting an ion beam generated by an ion beam generator based upon the first sensed signal and the second sensed signal. | 2015-08-06 |
20150221562 | POLISHING METHOD AND POLISHING APPARATUS - A polishing method and a polishing apparatus for performing a measurement of a film thickness of a substrate, such as a wafer, if an error has occurred during polishing of the substrate. The polishing method includes polishing a plurality of substrates, measuring a film thickness of at least one substrate, which has been designated in advance, of the plurality of substrates that have been polished, and if a polishing error has occurred during polishing of any one of the plurality of substrates, measuring a film thickness of that substrate. | 2015-08-06 |
20150221563 | APPLICATION OF IN-LINE GLASS EDGE-INSPECTION AND ALIGNMENT CHECK IN DISPLAY MANUFACTURING - Methods and apparatus for determining substrate integrity and alignment are described. Devices as described herein can include a transfer chamber, one or more process chambers, a loadlock chamber a first optical device, a second optical device and a radiation source positioned outside and above an opening for the loadlock chamber. Methods as described herein can include delivering a substrate to an opening in a process chamber, activating the optical device and the radiation source and capturing a plurality of images, extracting a substrate edge pattern from the plurality of images, comparing the substrate edge pattern to an expected edge pattern to determine a level of edge variance and adjusting or stopping a process if the level of edge variance is outside of an edge variation range. | 2015-08-06 |
20150221564 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: forming a semiconductor wafer including a plurality of semiconductor devices sandwiching a dicing region and an inline inspection monitor arranged in the dicing region; after forming the semiconductor wafer, conducting an inline inspection of the semiconductor device by using the inline inspection monitor; and after the inline inspection, dicing the semiconductor wafer along the dicing region to separate the semiconductor devices individually. The step of forming the semiconductor wafer includes: simultaneously forming a first diffusion layer of the semiconductor device and a second diffusion layer of the inline inspection monitor; forming a metal layer on the first and second diffusion layer; and at least partly removing the metal layer on the second diffusion layer. When the semiconductor wafer is diced, a portion from which the metal layer has been removed is cut by a dicing blade on the second diffusion layer. | 2015-08-06 |
20150221565 | LAYOUT FOR RETICLE AND WAFER SCANNING ELECTRON MICROSCOPE REGISTRATION OR OVERLAY MEASUREMENTS - A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and registration monitoring structures including BEOL interconnections, respectively. Embodiments include forming an active monitoring structure having first and second edges separated by a first distance in an active layer on a semiconductor substrate; forming a poly monitoring structure having first and second edges separated by a second distance in a poly layer; and forming one or more contact monitoring structures in a contact layer, collectively exposing at least the first and second edges of each of the active and poly monitoring structures; wherein the active, poly, and contact monitoring structures are formed in an area which includes no IC patterns in the active, the poly, and the contact layers, respectively. | 2015-08-06 |
20150221566 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate on which plural gate electrodes are juxtaposed to each other, plural gate wirings formed on the semiconductor substrate, plural gate pads, a first pad, and a second pad. The adjacent gate electrodes define plural cells, and the plural cells include plural transistor cells. The plural gate electrodes are partitioned into plural types by the plural gate wirings. The plural transistor cells are partitioned into plural types according to a combination of the defined gate electrodes. | 2015-08-06 |
20150221567 | ALTERNATING OPEN-ENDED VIA CHAINS FOR TESTING VIA FORMATION AND DIELECTRIC INTEGRITY - Kerf areas are located between the integrated circuit chips on a wafer. Via chain test structures are located in the kerf areas or test chips. The via chain test structures comprise a first conductor in a first area of the wafer. First via chains are connected at individual points to the first conductor. Each of the first via chains comprises an open-ended electrical circuit beginning at the first conductor and ending in an insulated region of a second area of the wafer. The via chain test structures comprise a second conductor in the second area. Second via chains are connected at individual points to the second conductor. Each of the second via chains comprises an open-ended electrical circuit beginning at the second conductor and ending in an insulated region of the first area. | 2015-08-06 |
20150221568 | Semiconductor Test Structure For Mosfet Noise Testing - The present invention provides a semiconductor test structure for MOSFET noise testing. The semiconductor test structure includes: a MOSFET device having a first conductivity type formed on a first well region of a semiconductor substrate; a metal shielding layer formed on the MOSFET device, the metal shielding layer completely covering the MOSFET device and extending beyond the circumference of the first well region; a deep well region having a second conductivity type formed in the semiconductor substrate close to the bottom surface of the first well region, the deep well region extending beyond the circumference of the first well region; wherein a vertical via is formed between the portion of the metal shielding layer extending beyond the first well region and the portion of the deep well region extending beyond the first well region to couple the metal shielding layer to the deep well region. The metal shielding layer is used to be connected to the ground terminal of a testing machine during testing, and the first conductivity type and the second conductivity type are opposite conductivity types. | 2015-08-06 |
20150221569 | Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate - Electronic module ( | 2015-08-06 |
20150221570 | THIN SANDWICH EMBEDDED PACKAGE - Methods and systems for a thin sandwich embedded package are disclosed and may include bonding a semiconductor die to a first surface of a substrate, dispensing a bond line on the first surface of the substrate and the die, and bonding an interposer to the substrate and die using the dispensed bond line. The bond line may fill the volume between the interposer and the substrate or may fill the volume between the interposer and the die but not between the interposer and the substrate. A cavity structure may be formed on the interposer and/or substrate, wherein the die may be situated within a cavity formed by the cavity structure when the interposer is bonded to the substrate and die. The cavity structure may comprise solder resist. Contacts may be formed on the cavity structure using low volume pad finish metals to electrically couple the interposer to the substrate. | 2015-08-06 |
20150221571 | METHODS AND APPARATUS FOR PROVIDING AN INTERPOSER FOR INTERCONNECTING SEMICONDUCTOR CHIPS - Methods and apparatus are provide for an interposer for interconnecting one or more semiconductor chips with an organic substrate in a semiconductor package, the interposer including: a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1); a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2); and an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate, where CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the organic substrate. | 2015-08-06 |
20150221572 | METHOD OF LIMITING CAPILLARY ACTION OF GEL MATERIAL DURING ASSEMBLY OF PRESSURE SENSOR - A method for applying a pressure-sensitive gel material during assembly of an array of pre-singulated packaged semiconductor devices. In the method, pressure-sensitive gel material is dispensed onto a first semiconductor device of the array, where the first semiconductor device is disposed within a first cavity. A first curing process is performed to partially cure the pressure-sensitive gel material in the first cavity. Pressure-sensitive gel material is then dispensed onto another semiconductor device of the array, where the other semiconductor device is disposed within another cavity. The first curing process is initiated before the dispensing of the pressure-sensitive gel material inside of the other cavity is completed and initially cures pressure-sensitive gel material for fewer than all of the pre-singulated packaged semiconductor devices of the array. | 2015-08-06 |
20150221573 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate. | 2015-08-06 |
20150221574 | STRESS MITIGATION FOR THIN AND THICK FILMS USED IN SEMICONDUCTOR CIRCUITRY - A semiconductor device is configured to reduce stress in one or more film layers in the device. According to one embodiment, the semiconductor device includes a substrate, a discontinuous dielectric layer on a first surface of the substrate, and a substantially continuous encapsulation layer over the first surface of the substrate and the discontinuous dielectric layer. Notably, the dielectric layer may be broken into one or more dielectric sections in order to relieve stress in the semiconductor device. | 2015-08-06 |
20150221575 | TRANSFERRING HEAT THROUGH AN OPTICAL LAYER OF INTEGRATED CIRCUITRY - A computer program product or hardware description language (“HDL”) design structure in a computer-aided design system for generating a functional design model of an integrated circuitry structure including generating a functional representation of at least first and second regions of the integrated circuitry structure, generating a functional representation of an optical layer comprising optical waveguides, and generating a functional representation of a heat-conductive material for transferring heat from at least the second region through the optical layer to a heat sink. | 2015-08-06 |
20150221576 | Heat Dissipation Structure for Semiconductor Element - A heat dissipation structure for semiconductor element includes a semiconductor element and a covering. The covering has a first side and an opposite second side and is formed on the second side with a heat radiation layer. The covering is externally covered on one side of the semiconductor element with the first side of the covering attached to the covered side of the semiconductor. By attaching the covering to one side of the semiconductor element, heat emitted by the semiconductor element during operation can be more quickly absorbed by the covering and radiated from the heat radiation layer into ambient environment to avoid heat accumulation on the semiconductor element. | 2015-08-06 |
20150221577 | PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE - Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed. | 2015-08-06 |
20150221578 | SEMICONDUCTOR PACKAGE AND METHOD FOR PRODUCING A SEMICONDUCTOR - A device includes a die and at least one of an encapsulant at least partly encapsulating the die and a carrier to which the die is attached. The at least one of the encapsulant and the carrier includes a thermoplastic polymer that includes metallic particles. | 2015-08-06 |
20150221579 | HEAT DISSIPATION DEVICE AND SEMICONDUCTOR DEVICE - In a laminating direction of first to fifth ceramic sheets, a first slit and a second slit are positioned closer to a first mounting section and a second mounting section than a first communication hole, a second communication hole, a third communication hole and a fourth communication hole. Moreover, an overlapping section where each first slit and the first communication hole overlap, and an overlapping section where each second slit and the third communication hole overlap, are positioned in the vicinity of an area where the first mounting section and the second mounting section are disposed when viewed from the laminating direction of the first to fifth ceramic sheets. | 2015-08-06 |
20150221580 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a semiconductor chip having a front surface electrode, a metal lead frame having a bed portion on a front surface of which the semiconductor chip is mounted and a post portion disposed separately from the bed portion, a resin sealing portion formed so as to cover the semiconductor chip, and a metal connector. The metal connector includes a chip junction portion joined to the front surface of the semiconductor chip, a post junction portion joined to a front surface of the post portion of the lead frame, and a connecting portion connecting the chip junction portion and the post junction portion. The chip junction portion has a thickness larger than a thickness of each of the post junction portion and the connecting portion. At least a part of the chip junction portion is exposed from a front surface of the sealing part. | 2015-08-06 |
20150221581 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a first frame includes a first thin plate section and a first thick plate section. A second frame includes a second thin plate section and a second thick plate section. A semiconductor chip includes a first electrode bonded to a first inner surface of the first thin plate section of the first frame, and a second electrode bonded to a second inner surface of the second thick plate section of the second frame. A resin layer seals the semiconductor chip, but leaves exposed the first outer surface of the first frame and the second outer surface of the second frame. | 2015-08-06 |
20150221582 | CONNECTOR FRAME AND SEMICONDUCTOR DEVICE - According to one embodiment, a connector frame includes a frame part, a first connector projected from the frame part and integrated with the frame part, and a second connector projected from the frame part and integrated with the frame part. The first connector includes a first portion and a second portion provided between the first portion and the frame part. The second portion is thinner than the first portion. The second connector is as thick as the second portion of the first connector. | 2015-08-06 |
20150221583 | MAGNETICALLY COUPLED GALVANICALLY ISOLATED COMMUNICATION USING LEAD FRAME - An integrated circuit package includes an encapsulation and a lead frame. A portion of the lead frame is disposed within the encapsulation. The lead frame includes a first conductor forming a first conductive loop. A second conductor is galvanically isolated from the first conductor. The second conductor forms a second conductive loop proximate to and magnetically coupled to the first conductive loop to provide a magnetic communication link between the first and second conductors. A signal that is transmitted from a transmit circuit coupled to the first conductor is coupled to be received through the magnetic communication link by a receive circuit coupled to the second conductor. | 2015-08-06 |
20150221584 | Stacked Synchronous Buck Converter Having Chip Embedded in Outside Recess of Leadframe - A power supply system ( | 2015-08-06 |
20150221585 | HOUSING FOR AN ELECTRONIC COMPONENT, ELECTRONIC ASSEMBLY, METHOD FOR PRODUCING A HOUSING FOR AN ELECTRONIC COMPONENT AND METHOD FOR PRODUCING AN ELECTRONIC ASSEMBLY - A housing includes a lead frame formed from electrically conductive material having first and second sides, a contact section contacting an electronic component at the first side, and at least one receiving section arranging the electronic component at the first side, wherein the contact and receiving sections are separated and the contact section is formed thinner than the receiving section in a direction perpendicular, a molding material having an opening, the receiving and contact regions exposed in the opening, and into which the leadframe is embedded such that part of the molding material is formed between the contact and receiving sections and the second side is covered by the molding material in the contact section, and the second side is free of molding material in the receiving section, wherein the molding material at the second side has at least one opening filled with the electrically insulating material. | 2015-08-06 |
20150221586 | SEMICONDUCTOR DEVICE WITH REDUCED THICKNESS - A semiconductor device with reduced thickness is disclosed and may include forming a back end of line (BEOL) comprising a redistribution layer on a dummy substrate. A first semiconductor die may be bonded to a first surface of the BEOL and a second semiconductor die may be bonded to the first semiconductor die. The first and second semiconductor dies may be electrically coupled to the BEOL. The first and second semiconductor dies and the BEOL may be encapsulated utilizing a first encapsulant. The dummy substrate may be removed thereby exposing a second surface of the BEOL opposite to the first surface. A solder ball may be placed on the exposed second surface of the BEOL. The second semiconductor may be stacked stepwise on the first semiconductor and may be flip-chip bonded. The semiconductor dies may be electrically coupled to the BEOL utilizing a lateral plating layer or conductive wires. | 2015-08-06 |
20150221587 | Device and Method of Manufacturing the Same - A device includes a substrate having a base member and an insulation film formed on a surface of the base member, a first semiconductor chip mounted over a surface of the substrate on which the insulation film are formed, a second semiconductor chip stacked over the first semiconductor chip so that an overhang portion is formed, and a sealing member formed on the substrate so that the first semiconductor chip and the second semiconductor chip are covered with the sealing member. The insulation film has a first opening portion in a first area of the substrate that overlaps the overhang portion. The base member has an air passage communicating with the first opening portion. | 2015-08-06 |
20150221588 | Surface Mountable Power Components - According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically coupled to the component substrate. The power component also includes at least one first peripheral contact and at least one second peripheral contact situated on the component substrate. A power semiconductor device is situated between the at least one first peripheral contact and the at least one second peripheral contact. The at least one first peripheral contact, the at least one second peripheral contact, and a surface electrode of the power semiconductor device are configured for surface mounting. The at least one first peripheral contact can be electrically coupled to the power semiconductor device. | 2015-08-06 |
20150221589 | DISTRIBUTED ON-CHIP DECOUPLING APPARATUS AND METHOD USING PACKAGE INTERCONNECT - An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry. | 2015-08-06 |
20150221590 | SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT PLUGS - A semiconductor device includes subsurface structures extending from a main surface into a semiconductor portion, each subsurface structure including a gate electrode dielectrically insulated from the semiconductor portion. The semiconductor device further includes alignment plugs in a vertical projection of the subsurface structures, contact spacers extending along sidewalls of the alignment plugs tilted to the main surface, and contact plugs directly adjoining semiconductor mesas between the subsurface structures. The contact plugs are provided between opposing ones of the contact spacers. | 2015-08-06 |
20150221591 | OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE - A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal. | 2015-08-06 |
20150221592 | SEMICONDUCTOR DEVICE WITH PACKAGE-LEVEL DECOUPLING CAPACITORS FORMED WITH BOND WIRES - A decoupling capacitor (decap) for circuitry (e.g., an I/O interface) in a semiconductor die is formed using one or more pairs of (parallel) bond wires wire-bonded to bond pads on a top surface of the die. Depending on the implementation, the pairs of bond wires may be horizontally or vertically aligned and may be bonded to I/O and/or array bond pads. | 2015-08-06 |
20150221593 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, in a semiconductor device, a plurality of first wiring lines is provided in a first insulating film on a semiconductor substrate and is adjacent in a direction parallel to the semiconductor substrate. A second insulating film is provided on the first wiring lines and the first insulating film. A plurality of vias is provided in the second insulating film and is electrically connected to the first wiring lines. A third insulating film is provided on the vias and the second insulating film. Adjacent second wiring lines are provided in the third insulating film and are electrically connected to the vias. A fourth insulating film is provided on a sidewall of each of the adjacent second wiring lines, the sidewalls face each other. A conductive film abuts on the adjacent second wiring lines with the fourth insulating film interposed therebetween. | 2015-08-06 |
20150221594 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a fuse element that can be cut by a laser, which has a corrosion resistance. A fuse element ( | 2015-08-06 |
20150221595 | Impedance Controlled Electrical Interconnection Employing Meta-Materials - A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss. Alternative embodiments of the meta-material overlay provide, the enhancements for conventional discrete wire bonds whilst also facilitating single integrated designs compatible with tape implementation. | 2015-08-06 |
20150221596 | DIELECTRIC/METAL BARRIER INTEGRATION TO PREVENT COPPER DIFFUSION - An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber. The substrate has an exposed copper surface and an exposed low-k dielectric surface. A metal layer is formed over the copper surface but not over the low-k dielectric surface. A metal-based dielectric layer is formed over the metal layer and the low-k dielectric layer. | 2015-08-06 |
20150221597 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Performance of a semiconductor device is improved. In one embodiment, for example, deposition time is increased from 4.6 sec to 6.9 sec. In other words, in one embodiment, thickness of a tantalum nitride film is increased by increasing the deposition time. Specifically, in one embodiment, deposition time is increased such that a tantalum nitride film provided on the bottom of a connection hole to be coupled to a wide interconnection has a thickness within a range from 5 to 10 nm. | 2015-08-06 |
20150221598 | PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - There is provided a package substrate including: a body unit including a plurality of base substrates and having a mounting region allowing at least one semiconductor device to be mounted thereon; and a plurality of magnetic field shielding units including a ferromagnetic material and provided within the body unit, wherein the plurality of magnetic field shielding units may be respectively disposed on the plurality of different base substrates such that a magnetic field shielding region defined by the plurality of magnetic field shielding units corresponds to the mounting region. | 2015-08-06 |
20150221599 | Semiconductor Device - A semiconductor device includes a wiring substrate. The wiring substrate includes a first surface, a second surface located at an opposite side of the first surface, a cavity formed in the first surface, an electrode pad formed on the first surface surrounding the cavity, and a high frequency wire exposed on the first surface. A semiconductor element is accommodated in the cavity. A bonding wire connects the semiconductor element and the electrode pad. A first protection film is arranged on the first surface of the wiring substrate to cover the first surface, the semiconductor element, the electrode pad, the bonding wire, and the high frequency wire. | 2015-08-06 |
20150221600 | HIGH-FREQUENCY MODULE - A high-frequency module includes a laminate, a bottom surface electrode, and internal electrodes that provide grounding. The bottom surface electrode is provided on a bottom surface of the laminate. The laminate includes a wiring region through which wiring of a high-frequency circuit passes. The internal electrodes that provide grounding are provided between layers of the laminate and connected to the bottom surface electrode, respectively. The internal electrodes that provide grounding each include a line including ends extending outside of the wiring region along an outer edge of the laminate. The internal electrodes that provide grounding are endlessly continuous with each other when seen in a lamination direction of the laminate. | 2015-08-06 |
20150221601 | SEMICONDUCTOR DEVICE WITH REDISTRIBUTION LAYERS FORMED UTILIZING DUMMY SUBSTRATES - A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form. | 2015-08-06 |
20150221602 | Flip-Chip Hybridisation Of Two Microelectronic Components Using A UV Anneal - A method of manufacturing a microelectronic device including a first component hybridized with a second component via electric interconnects, involves the steps of: (i) forming the first and second components, the second component being transparent to ultraviolet radiation at least in line with locations provided for the interconnects; (ii) forming interconnection elements including copper oxide on the second component at the locations provided for the interconnects; (iii) placing the first and second components on each other; and (iv) applying the ultraviolet radiation through the second component on the elements including copper oxide to implement an ultraviolet anneal converting copper oxide into copper. | 2015-08-06 |
20150221603 | Microbump and Sacrificial Pad Pattern - Embodiments described herein generally relate to connections for integrated circuit (IC) dies. For example, in an embodiment an integrated circuit (IC) die is provided. The IC die includes a plurality of clusters of pads formed on a surface of the IC die, each cluster being associated with a respective circuit formed in the IC die. Each cluster includes a plurality of micropads each electrically coupled to the circuit associated with the cluster through a respective via and a sacrificial pad coupled to the circuit through the plurality of micropads, the sacrificial pad being larger than each of the micropads. | 2015-08-06 |
20150221604 | SEMICONDUCTOR DEVICE - In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively. | 2015-08-06 |
20150221605 | ETCHING OF UNDER BUMP METTALLIZATION LAYER AND RESULTING DEVICE - Methods for wet etching a UBM layer and the resulting devices are disclosed. Embodiments may include patterning metal bumps on a wafer that has at least two metal layers thereon; exposing the wafer to a first acid solution to remove a portion of a first of the two metal layers exposed by the patterning of the metal bumps; and exposing the wafer to a second acid solution to remove a portion a second of the two metal layers exposed by the patterning of the metal bumps and the exposure of the wafer to the first acid solution, wherein an undercut below the metal bumps, formed by removal of the portions of the first and second metal layers, is less than 1.5 microns. | 2015-08-06 |
20150221606 | Lead-Free Solder Ball - A lead-free solder ball is provided which suppresses interfacial peeling in a bonding interface of a solder ball, fusion defects which develop between the solder ball and solder paste, and which can be used both with Ni electrodes plated with Au or the like and Cu electrodes having a water-soluble preflux applied atop Cu. The lead-free solder ball for electrodes of BGAs or CSPs consists of 1.6-2.9 mass % of Ag, 0.7-0.8 mass % of Cu, 0.05-0.08 mass % of Ni, and a remainder of Sn. It has excellent resistance to thermal fatigue and to drop impacts regardless of the type of electrodes of a printed circuit board to which it is bonded, which are Cu electrodes or Ni electrodes having Au plating or Au/Pd plating as surface treatment. The composition may include at least one element selected from Fe, Co, and Pt in a total amount of 0.003-0.1 mass % or at least one element selected from Bi, In, Sb, P, and Ge in a total emount of 0.003-0.1 mass %. | 2015-08-06 |
20150221607 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Surfaces of a semiconductor chip and a circuit board are made to face each other, and upper portions of stoppers of the circuit board are fit into regions between adjacent stoppers of rail grooves of the semiconductor chip, and upper portions of the stoppers of the semiconductor chip are fit into regions between the adjacent stoppers of rail grooves of the circuit board, whereby side surfaces of first terminals of the semiconductor chip and side surfaces of second terminals of the circuit board are electrically connected. | 2015-08-06 |
20150221608 | PROCESSES OF MAKING PAD-LESS INTERCONNECT FOR ELECTRICAL CORELESS SUBSTRATE - A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug. | 2015-08-06 |
20150221609 | METHODS OF FORMING ULTRA THIN PACKAGE STRUCTURES INCLUDING LOW TEMPERATURE SOLDER AND STRUCTURES FORMED THERBY - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure. | 2015-08-06 |
20150221610 | SEPARATING BONDED WAFERS - Separating bonded wafers. A bonded wafer pair is mounted between first and second bonding chucks having flat chuck faces, the first bonding chuck face including adjustable zones capable of movement relative to each other, at least a component of the relative movement is along an axis that is perpendicular to the flat first bonding chuck face. The adjustable zones of the first face are moved relative to each other in a coordinated manner such that a widening gap is formed between the bonding faces of the wafer pair. | 2015-08-06 |
20150221611 | Methods of Packaging Semiconductor Devices and Packaged Semiconductor Devices - Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes coupling integrated circuit dies to a substrate, and disposing a molding material around the integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies. | 2015-08-06 |
20150221612 | THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS - Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures. | 2015-08-06 |
20150221613 | LARGE CHANNEL INTERCONNECTS WITH THROUGH SILICON VIAS (TSVS) AND METHOD FOR CONSTRUCTING THE SAME - An electrical device that includes at least two active wafers having at least one through silicon via, and at least one unitary electrical communication and spacer structure present between a set of adjacently stacked active wafers of the at least two active wafers. The unitary electrical communication and spacer structure including an electrically conductive material core providing electrical communication to the at least one through silicon via structure in the set of adjacently stacked active wafers and a substrate material outer layer. The at least one unitary electrical communication and spacer structure being separate from and engaged to the adjacently stacked active wafers, wherein coolant passages are defined between surfaces of the adjacently stacked active wafers and the at least one unitary electrical communication and spacer structure. | 2015-08-06 |