32nd week of 2022 patent applcation highlights part 62 |
Patent application number | Title | Published |
20220254704 | SEMICONDUCTOR PACKAGE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated. | 2022-08-11 |
20220254705 | LEAD FRAME STRUCTURE AND MANUFACTURING METHOD THEREOF - The present disclosure is related to a lead frame structure. The lead frame structure includes a bottom board and a blocking wall. The bottom board has a first conductive portion and a second conductive portion. The first conductive portion separates from the second conductive portion. The first and second conductive portions are configured to electrically connect to a light source. The blocking wall is located on the bottom board, and the blocking wall surrounds an opening. The first and the second conductive portions are exposed from the opening. The first and the second conductive portions each have an extending portion. The extending portion extends beyond an external surface of the blocking wall in a horizontal direction. | 2022-08-11 |
20220254706 | SEMICONDUCTOR DEVICE - Provided a semiconductor device which is covered by an encapsulating resin into a cuboid shape, and has a plurality of lead portions partially exposed from side surfaces and a bottom surface thereof, the semiconductor device having cutout portions formed in the encapsulating resin along edges formed by the side surfaces and the bottom surface, each of the plurality of lead portions having a first exposed surface which is coplanar with one of the side surfaces, and is exposed from the one of the side surfaces; and second exposed surfaces which are surfaces that are adjacent to and on both sides of the first exposed surface, and are exposed from the one of the cutout portions. | 2022-08-11 |
20220254707 | WIREBONDABLE INTERPOSER FOR FLIP CHIP PACKAGED INTEGRATED CIRCUIT DIE - A variety of methods and arrangements to convert a flip chip IC die package into a wirebondable component using an interposer are described. The interposer has an insulating layer and a patterned metal layer attached to one side of the insulating layer. The patterned metal layer is electrically connected to the IC die using solder bumps. The interposer has wirebond pads on a side of the interposer opposed to the side of the interposer having the electrical connection between the IC die and solder bumps. The interposer may be a thin organic laminate or a flexible printed circuit board. | 2022-08-11 |
20220254708 | INTERPOSER AND MANUFACTURING METHOD THEREOF - A manufacturing method of an interposer for disposing a semiconductor chip and an external terminal at two opposing sides includes the following steps. An active device is bonded to a first redistribution structure, wherein an active surface of the active device is in electrical contact with the first redistribution structure. A dielectric layer is formed on the first redistribution structure to encapsulate the active device. A second redistribution structure is formed over the dielectric layer to be electrically coupled to the first redistribution structure, wherein the first conductive pattern of the first redistribution structure is formed according to a first design rule to be finer than a second conductive pattern of the second redistribution structure formed according to a second design rule, the semiconductor chip and the external terminal are configured to be respectively disposed on the first conductive pattern and the second conductive pattern. | 2022-08-11 |
20220254709 | PACKAGE SUBSTRATE AND SEMICONDUCTOR STRUCTURE WITH PACKAGE SUBSTRATE - A package substrate and a semiconductor structure with the package substrate are provided. The package substrate includes a body and a conductive layer. The body includes an opening region. The conductive layer is disposed at the opening region. The conductive layer includes a first conductive bridge and a second conductive bridge. The first conductive bridge and the second conductive bridge are disposed at intervals. The first conductive bridge is provided with at least one first via. The first conductive bridge and the second conductive bridge are disposed at intervals in the opening region. | 2022-08-11 |
20220254710 | PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING THE PACKAGE SUBSTRATE, AND SEMICONDUCTOR PACKAGE INCLUDING THE PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A package substrate may include first conductive patterns, a first insulation layer and a second insulation layer. The first conductive patterns may be electrically connected with a semiconductor chip. The first insulation layer may be on an upper surface and side surfaces of each of the first conductive patterns. The first insulation layer may include at least one opening under at least one of side surfaces of the semiconductor chip. The second insulation layer may be on a lower surface of each of the first conductive patterns. Thus, a gas generated from the DAF may be readily discharged through the opening. A spreading of a crack, which may be generated at the interface between the side surface of the semiconductor chip and the molding member, toward the conductive patterns of the package substrate may be limited and/or suppressed. Adhesion between the semiconductor chip and the molding member may be reinforced. | 2022-08-11 |
20220254711 | SIGNAL ROUTING IN INTEGRATED CIRCUIT PACKAGING - In some implementations, a substrate for coupling to an integrated circuit includes multiple layers. Each of the multiple layers has, in a particular region of the substrate, a repeating pattern of regions corresponding to power and ground. The multiple layers include (i) a top layer having, in the particular region, power contacts and ground contacts for coupling to an integrated circuit and (ii) a bottom layer having, in the particular region, power contacts and ground contacts for coupling to another device. At least one layer of the multiple layers has a repeating pattern of signal traces that extend along and are located between the regions corresponding to ground in the at least one layer. | 2022-08-11 |
20220254712 | REDUCING INTERNAL NODE LOADING IN COMBINATION CIRCUITS - Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other. | 2022-08-11 |
20220254713 | SEMICONDUCTOR DEVICE WITH POLYMER-BASED INSULATING MATERIAL AND METHOD OF PRODUCING THEREOF - A semiconductor device includes a semiconductor substrate having a first main surface and a metal structure above the first main surface. The metal structure has a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness. A polymer-based insulating material contacts and covers at least the periphery region of the metal structure. A thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section. An average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure. | 2022-08-11 |
20220254714 | CAPACITOR AND METHOD FOR PRODUCING THE SAME - The present application provides a capacitor and a method for producing the same The capacitor includes: a multi-wing structure, including N groups of wing structures and N support structures, each group of the wing structures includes M wing structures arranged in parallel, M limit slots are formed on an outer side wall of the support structure, the M wing structures are fixed on outside of the support structure through the M limit slots, respectively, and M and N are positive integers; a laminated structure, covering the multi-wing structure and including at least one dielectric layer and a plurality of conductive layers; at least one first external electrode, electrically connecting to part or all of the odd-number conductive layers in the plurality of conductive layers; and at least one second external electrode, electrically connecting to part or all of even-number conductive layers in the plurality of conductive layers. | 2022-08-11 |
20220254715 | LOCAL INTERCONNECT LAYER WITH DEVICE WITHIN SECOND DIELECTRIC MATERIAL, AND RELATED METHODS - Embodiments of the disclosure provide an integrated circuit (IC) structure, including a device layer including a device on a substrate. A local interconnect layer is over the device layer, and includes a first dielectric material over the substrate. The first dielectric material has a first effective dielectric constant. A second dielectric material is over the device and adjacent the first dielectric material. The second dielectric material has a second effective dielectric constant less than the first effective dielectric constant. | 2022-08-11 |
20220254716 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, and a method of manufacturing the same, includes a first conductive pattern, a second conductive pattern configured to overlap a first line component of the first conductive pattern and to leave exposed a first pad component of the first conductive pattern. The semiconductor device also includes an interlayer insulating layer between the first conductive pattern and the second conductive pattern. The semiconductor device further includes a first conductive contact and a first insulating pillar extending from the first pad component of the first conductive pattern in opposite directions. | 2022-08-11 |
20220254717 | Semiconductor Device And Manufacturing Method Therefor - A semiconductor device and a manufacturing method therefor are provided. The semiconductor device includes a substrate and an inductor, where a shield layer may be formed between the substrate and the inductor, and the shield layer is used to shield an electrical coupling between the substrate and the inductor. In this way, a coupling current in the substrate can be reduced, an energy loss in the inductor is reduced, a quality factor of the inductor is improved, and performance of the semiconductor device is improved. | 2022-08-11 |
20220254718 | METHOD FOR FUSING AND FILLING SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR STRUCTURE - A method for fusing and filling a semiconductor structure includes: a semiconductor structure body is provided, a plurality of fuse array groups is formed in the semiconductor structure body; at least one of interconnection structures of the fuse array groups is fused to form at least one notch in the semiconductor structure body; a shielding layer is formed on the semiconductor structure body, at least one through hole exposing the at least one notch is formed in the shielding layer; and a sealing material layer is formed in the notch. | 2022-08-11 |
20220254719 | CHIP REDISTRIBUTION STRUCTURE AND PREPARATION METHOD THEREOF - The present invention provides a chip redistribution structure and a preparation method thereof. The chip redistribution structure includes a chip body, and a first distribution layer and a second distribution layer which are connected to the chip body. A first pin and a second pin are disposed on the surface of the chip body. The chip redistribution structure further includes a dielectric layer disposed on the surface of the chip body, wherein the dielectric layer is recessed downwards to form a first window, a second window, and a groove communicated with the first window. The first window and the second window respectively correspond to the first pin and the second pin. The first distribution layer extends along the groove and is communicated with the first pin, and the second distribution layer is disposed above the dielectric layer and is communicated with the second pin. In the present application, the first distribution layer and the second distribution layer are disposed in a staggered manner along the height direction through the dielectric layer provided with the groove, so that the size limitation problem of an existing redistribution process is overcome, the redistribution density can be improved, and the risk of short circuit is reduced. | 2022-08-11 |
20220254720 | PACKAGE SUBSTRATE AND SEMICONDUCTOR STRUCTURE WITH SAME - There is provided a package substrate and a semiconductor structure with the same. The package substrate includes a body and a plurality of conducive bridges. The body includes an opening region. The plurality of conductive bridges are disposed separately in the opening region, and adjacent conductive bridges have a respective distance value. At least two of the distance values are not equal. | 2022-08-11 |
20220254721 | HYBRID FAN-OUT ARCHITECTURE WITH EMIB AND GLASS CORE FOR HETEROGENEOUS DIE INTEGRATION APPLICATIONS - Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer. | 2022-08-11 |
20220254722 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure. | 2022-08-11 |
20220254723 | INTERPOSERS FOR MICROELECTRONIC DEVICES - Described are semiconductor interposer, and microelectronic device assemblies incorporating such semiconductor interposers. The described interposers include multiple redistribution structures on each side of the core; each of which may include multiple individual redistribution layers. The interposers may optionally include circuit elements, such as passive and/or active circuit. The circuit elements may be formed at least partially within the semiconductor core. | 2022-08-11 |
20220254724 | CHIP PACKAGE AND METHOD OF FORMING THE SAME - A chip package includes a semiconductor die laterally encapsulating by an insulating encapsulant, a first dielectric portion, conductive vias, conductive traces and a second dielectric portion. The first dielectric portion covers the semiconductor die and the encapsulant. The conductive vias penetrate through the first dielectric portion and electrically connected to the semiconductor die. The conductive traces are disposed on the first dielectric portion. The second dielectric portion is disposed on the first dielectric portion and covering the conductive traces, wherein a first minimum lateral width of a conductive trace among the conductive traces is smaller than a second minimum lateral width of a conductive via among the conductive vias. A method of forming the chip package is also provided. | 2022-08-11 |
20220254725 | SEMICONDUCTOR PACKAGE - A semiconductor package is disclosed. The semiconductor package includes a back-side wiring substrate and a front-side redistribution layer which are in parallel, and a connector, a semiconductor chip and an encapsulator which are between the back-side wiring substrate and the front-side redistribution layer. The encapsulator surrounds surfaces of the connector and the semiconductor chip. The back-side wiring substrate includes a core layer, a back-side via plug extending through the core layer, and a back-side redistribution layer on the back-side via plug. | 2022-08-11 |
20220254726 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Various aspects of the present disclosure provide a device that comprises an electronic device comprising a first device side, a second device side, and a first lateral device side. The example device may, for example, also comprise a substrate comprising a first substrate side, a second substrate side, and a first lateral substrate side. The substrate may, for example, comprise a first conductive pattern, a first barrier structure, and a second conductive pattern. The first conductive pattern may, for example, comprise a first side, a second side, and a first lateral side. The first barrier structure may, for example, be on the first lateral side of the first conductive pattern. The second conductive pattern may, for example, comprise a first side, a second side, and a first lateral side. The first lateral side of the second conductive pattern may, for example, be free of a metal barrier structure. | 2022-08-11 |
20220254727 | APPARATUSES INCLUDING A CONDUCTIVE CONTACT INCLUDING A DIELECTRIC MATERIAL SURROUNDED BY A CONDUCTIVE MATERIAL - An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed. | 2022-08-11 |
20220254728 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING BRIDGES FOR ENHANCED STRUCTURAL SUPPORT AND METHODS OF FORMING THE SAME - A three-dimensional memory device includes a first alternating stack of first word lines and first insulating layers, first memory stack structures vertically extending through the first alternating stack, a second alternating stack of second word lines and second insulating layers, second memory stack structures vertically extending through the second alternating stack, plural backside trench fill structures located between the first alternating stack and the second alternating stack, and a bridge region located between the plural backside trench fill structures and between the between the first alternating stack and the second alternating stack. At least one insulating layer extends continuously through the first alternating stack, the second alternating stack, and the bridge region. | 2022-08-11 |
20220254729 | REDUCTION IN SUSCEPTIBILITY OF ANALOG INTEGRATED CIRCUITS AND SENSORS TO RADIO FREQUENCY INTERFERENCE - An apparatus comprises a ground plane ( | 2022-08-11 |
20220254730 | SIGNAL ISOLATION FOR MODULE WITH BALL GRID ARRAY - Signal isolation for module with ball grid array. In some embodiments, a packaged module can include a packaging substrate having an underside, and an arrangement of conductive features implemented on the underside of the packaging substrate to allow the packaged module to be capable of being mounted on a circuit board. The arrangement of conductive features can include a signal feature implemented at a first region and configured for passing of a signal, and one or more shielding features placed at a selected location relative to the signal feature to provide an enhanced isolation between the signal feature and a second region of the underside of the packaging substrate. | 2022-08-11 |
20220254731 | SHIELDING PROCESS FOR SIP PACKAGING - Disclosed is a shielding process for SIP packaging, including: providing a circuit board; cutting the covering layer to form half-cut trenches separating different SIP packaging modules from each other, and to form grooves in each single SIP packaging module; forming a metal overlay, the metal overlay on an outer surface of the SIP packaging module and at positions where the half-cut trenches are located constituting a conformal shielding, the metal overlay at positions where the grooves are located constituting a compartment shielding; and cutting the half-cut trenches to obtain a plurality of SIP packaging modules that are separate from each other. | 2022-08-11 |
20220254732 | SEMICONDUCTOR DEVICE ASSEMBLIES WITH CONDUCTIVE UNDERFILL DAMS FOR GROUNDING EMI SHIELDS AND METHODS FOR MAKING THE SAME - A semiconductor device assembly is provided. The assembly includes a substrate including an upper surface having a plurality of internal contact pads and at least one grounding pad and a lower surface having a plurality of external contact pads. The assembly further includes a semiconductor die coupled to the plurality of internal contact pads, a conductive underfill dam coupled to the at least one grounding pad, and underfill material disposed at least between the semiconductor die and the substrate. The underfill material includes a fillet between the semiconductor die and the underfill dam. The assembly further includes a conductive EMI shield disposed over the semiconductor die, the fillet, and the conductive underfill dam. | 2022-08-11 |
20220254733 | THREE-DIMENSIONAL MEMORY DEVICE CONTAINING BRIDGES FOR ENHANCED STRUCTURAL SUPPORT AND METHODS OF FORMING THE SAME - A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region. | 2022-08-11 |
20220254734 | REINFORCED SEMICONDUCTOR DIE AND RELATED METHODS - Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die. | 2022-08-11 |
20220254735 | PACKAGE SUBSTRATE WITH CTE MATCHING BARRIER RING AROUND MICROVIAS - A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia. | 2022-08-11 |
20220254736 | PACKAGE STRUCTURE AND FABRICATING METHOD THEREOF - A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die. | 2022-08-11 |
20220254737 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a semiconductor device, a plurality of through semiconductor vias (TSV), a first seal ring, and a second seal ring. The TSVs are in the semiconductor device. Each of the TSVs has a first surface and a second surface opposite to the first surface. The first seal ring is located in proximity to an edge of the semiconductor structure and is physically connected to the first surface of each of the TSVs. The second seal ring is physically connected to the second surface of each of the TSVs. | 2022-08-11 |
20220254738 | POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto. | 2022-08-11 |
20220254739 | SPECIFICATDEVICES WITH THROUGH SILICON VIAS, GUARD RINGS AND METHODS OF MAKING THE SAME - A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate. | 2022-08-11 |
20220254740 | HIGH VOLTAGE ISOLATION BARRIER WITH ELECTRIC OVERSTRESS INTEGRITY - An electronic device comprises a multilevel metallization structure over a semiconductor layer and including a first region, a second region, a pre-metal level on the semiconductor layer, and N metallization structure levels over the pre-metal level, N being greater than 3. The electronic device also comprises an isolation component in the first region, the isolation component including a first terminal and a second terminal in different respective metallization structure levels, as well as a conductive shield between the first region and the second region in the multilevel metallization structure, the conductive shield including interconnected metal lines and trench vias in the respective metallization structure levels that at least partially encircle the first region. | 2022-08-11 |
20220254741 | PACKAGING STRUCTURE WITH ANTENNA AND MANUFACTURING METHOD THEREOF - A packaging structure with an antenna and a manufacturing method thereof are disclosed. The packaging structure includes a package, an antenna circuit, an interconnecting circuit, an outer-layer circuit, and a chip. The package is internally packaged with a first conducting through hole column and a second conducting through hole column. The antenna circuit is disposed on a first surface and a sidewall of the package. The interconnecting circuit is packaged in the package, and is connected to the antenna circuit by the first conducting through hole column. The outer-layer circuit is disposed on a second surface of the package, and is connected to the interconnecting circuit by the second conducting through hole column. The outer-layer circuit is further connected to a conductive pin. The chip is packaged in the package, and is connected to the interconnecting circuit or the outer-layer circuit. | 2022-08-11 |
20220254742 | SEMICONDUCTOR DEVICE - A semiconductor device is configured to include: a base member of a semiconductor material which forms a thin plate shape; a front face electrode which is placed on a front surface of the base member; a rear face electrode which covers a rear surface of the base member; and a via hole which forms a hole shape provided with the front face electrode as a bottom and being open onto the rear surface, and through which the front face electrode and the rear face electrode are electrically connected to each other; wherein, at a circumferential edge portion of the base member on its side where the rear surface is located, a protrusion portion which protrudes in a thickness direction is disposed. | 2022-08-11 |
20220254743 | AMPLIFIER DEVICE - Provided is an amplifier device including a semiconductor chip, a package, a first feedback circuit, and a second feedback circuit. The package includes a metal base, an insulating side wall, an input lead, and an output lead. The input lead is connected to a gate pad group of the semiconductor chip. The output lead is connected to a drain pad group of the semiconductor chip. Each of the feedback circuits includes a dielectric substrate disposed on the metal base, a feedback resistor located on the dielectric substrate, and a capacitor connected in series to the feedback resistor. Each of the feedback circuits is connected between the gate pad group and the drain pad group. The feedback circuits are located respectively on the base on one side and the other side of the semiconductor chip in an extension direction of a first and a second end edge. | 2022-08-11 |
20220254744 | FILM STRUCTURE FOR BOND PAD - The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure disposed over a substrate. The interconnect structure includes a plurality of interconnect layers disposed within a dielectric structure. A bond pad structure is disposed over the interconnect structure. The bond pad structure includes a contact layer. A first masking layer including a metal-oxide is disposed over the bond pad structure. The first masking layer has interior sidewalls arranged directly over the bond pad structure to define an opening. A conductive bump is arranged within the opening and on the contact layer. | 2022-08-11 |
20220254745 | SELECTIVE MICRO DEVICE TRANSFER TO RECEIVER SUBSTRATE - A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. Micro devices being attached to a donor substrate with a donor force. The donor substrate and receiver substrate are aligned and brought together so that selected micro devices meet corresponding contact pads. A receiver force is generated to hold selected micro devices to the contact pads on the receiver substrate. The donor force is weakened and the substrates are moved apart leaving selected micro devices on the receiver substrate. Several methods of generating the receiver force are disclosed, including adhesive, mechanical and electrostatic techniques. | 2022-08-11 |
20220254746 | CONDUCTIVE BARRIER DIRECT HYBRID BONDING - A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region. | 2022-08-11 |
20220254747 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes an interconnect structure, an insulating layer and a conductive layer. The interconnect structure includes a first surface and a second surface opposite to the first surface. The insulating layer contacts the interconnect structure. The insulating layer includes a third surface contacting the second surface of the interconnect structure and a fourth surface opposite to the third surface. The conductive layer is electrically coupled to the interconnect structure. The conductive layer has a continuous portion extending from the second surface to the fourth surface. | 2022-08-11 |
20220254748 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - An electronic device characterized by including a substrate, a bonding layer provided on the substrate, the bonding layer containing copper in an amount of greater than 0 mass % but 60 mass % or less, the copper having its crystal grain size of 50 nm or less, an electronic component provided on the bonding layer, and a coating film covering a side of the bonding layer, the coating film containing at least one compound selected from copper (I) oxide (Cu | 2022-08-11 |
20220254749 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device which suppresses poor bonding between a metal pattern and an electrode terminal due to insufficient temperature rise at the time of bonding the metal pattern and the electrode terminal. The electrode terminal is branched into a plurality of branch portions in a width direction on one end side of an extending direction thereof, of the plurality of branch portions, a first branch portion and a second branch portion are bonded on the metal pattern via a bonding material, respectively, the first branch portion has a wider width than that of the second branch portion, and the bonding material between the second branch portion and the metal pattern is thinner than the bonding material between the first branch portion and the metal pattern. | 2022-08-11 |
20220254750 | BALL BOND IMPEDANCE MATCHING - Methods and apparatus for providing an interconnection including a stack of wirebond balls having a selected impedance. The wirebond balls may have a size, which may comprise a radius, configured for the selected impedance. The stack may comprise a number of wirebond balls configured for the selected impedance and/or may comprise a material selected for the selected impedance. In embodiments, the selected impedance is primarily resistive (e.g., 50 Ohms), such that the overall reactance is minimized. | 2022-08-11 |
20220254751 | SEMICONDUCTOR DEVICE MANUFACTURING DEVICE AND MANUFACTURING METHOD - A semiconductor device manufacturing device ( | 2022-08-11 |
20220254752 | SENSOR PACKAGE STRUCTURE - A sensor package structure is provided. The sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of electrical connection members electrically connecting the sensor chip to the substrate, a supporting adhesive layer formed on the sensor chip, and a light-permeable sheet disposed on the supporting adhesive layer. Each of the electrical connection members includes a head solder disposed on a connecting pad of the sensor chip, a wire having a first end and a second end, and a tail solder. The first end of the wire extends from the head solder so as to connect the second end onto a soldering pad of the substrate, and the wire has a first bending portion arranged adjacent to the head solder. The head solder and the first bending portion of each of the electrical connection members are embedded in the supporting adhesive layer. | 2022-08-11 |
20220254753 | DIPOLE ALIGNMENT DEVICE, DIPOLE ALIGNMENT METHOD AND DISPLAY DEVICE MANUFACTURING METHOD - A dipole alignment device includes an electric field forming part including a stage, and a probe part which form an electric field on the stage; an inkjet printing apparatus including at least one inkjet head which sprays ink including dipoles and a solvent with the dipoles dispersed therein onto the stage; a transportation part comprising a first moving part which moves the electric field forming part in at least one direction; and a light irradiation apparatus including a light irradiation part which applies light to the ink sprayed onto the stage. | 2022-08-11 |
20220254754 | MICROELECTRONIC ASSEMBLIES - Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die. | 2022-08-11 |
20220254755 | FLIP-CHIP STACKING STRUCTURES AND METHODS FOR FORMING THE SAME - The present disclosure includes a semiconductor package including a redistribution layer (RDL) having a first surface in contact with input/output (I/O) contacts and a second surface opposite to the first surface. The semiconductor package also includes a staircase interconnect structure formed on the second surface of the RDL and electrically connected with the RDL. The staircase interconnect structure includes staircase layers including a first staircase layer and a second staircase layer stacked on a top surface of the first staircase layer. The second staircase layer covers a portion of the top surface of the first staircase layer such that a remaining portion of the top surface of the first staircase layer is exposed. Integrated circuit (IC) chips are electrically connected to the RDL via the staircase interconnect structure. A first IC chip of the IC chips is electrically connected to the RDL through the remaining portion of the top surface of the first staircase layer. | 2022-08-11 |
20220254756 | SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS - A semiconductor package includes: a first semiconductor chip stack including a plurality of first semiconductor chips which are stacked in a vertical direction; a bridge die stack disposed to be spaced apart from the first semiconductor chip stack in a horizontal direction and including a plurality of bridge dies which are stacked in the vertical direction, wherein the bridge dies include through electrodes, respectively, and the through electrodes aligned in the vertical direction are connected to each other through a connection electrode between the bridge dies; a redistribution layer disposed over the first semiconductor chip stack and the bridge die stack; a second semiconductor chip disposed over the redistribution layer and configured to receive a voltage through the through electrodes aligned in the vertical direction, the connection electrode, and the redistribution layer; and a voltage regulator configured to adjust the voltage. | 2022-08-11 |
20220254757 | INTEGRATED CIRCUIT PACKAGE WITH GLASS SPACER - Apparatuses, systems and methods associated with integrated circuit (IC) package design are disclosed herein. In embodiments, an IC package may include a first die and a second die. The IC package may include a spacer located between the first die and the second die, the spacer includes glass, and a molding compound that at least partially encompasses the first die, the second die, and the spacer. Other embodiments may be described and/or claimed. | 2022-08-11 |
20220254758 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element, a first terminal, a second terminal, a first conductor, a first connecting member, and a second connecting member. The semiconductor element includes a first electrode, a second electrode, and a third electrode, and is configured to perform on/off control between the first electrode and the second electrode based on a drive signal inputted to the third electrode. The first terminal and the second terminal are separated apart from each other and electrically connected to the first electrode. The first conductor is electrically connected to the first terminal. The first connecting member electrically connects the first electrode and the first conductor. The second connecting member electrically connects the first conductor and the second terminal. | 2022-08-11 |
20220254759 | Light Emission System with MicroLED Device Isolation - A light emission system includes an array of micro light-emitting diodes (microLED)s. The array of microLEDs includes a semiconductor substrate, a prep layer formed on at least a portion of the semiconductor substrate, and an active region formed on the prep layer. The array of microLEDs also include a plurality of thick sub-structures forming an array on the active region, and a plurality of thin sub-structures formed on the active region, each one of the thin sub-structures being located between each adjacent pair of thick substructures. Each one of the thick sub-structures defines a shape and size of a corresponding one of the microLEDs. Each one of the thin sub-structures is configured for preventing mobility of free electron carriers therethrough to electrically isolate each one of the thick sub-structures from every other one of the thick sub-structures. Further, the plurality of microLEDs share the active region. | 2022-08-11 |
20220254760 | METHODS, APPARATUSES, AND MATERIALS FOR PRODUCING MICRO-PIXELATED LEDS USING ADDITIVE MANUFACTURING - Methods, systems, and materials for producing micro-pixelated LEDs capable of achieving a full-color spectrum through stereolithography techniques are provided. The techniques include depositing a photocurable nanophosphor ink composition onto a substrate, projecting a pattern onto the substrate and ink composition, and then curing at least a portion of the ink composition based on the projected pattern. The ink composition includes at least one photocurable polymer, a plurality of nanophosphors (e.g., QDs), and at least one light-scattering additive. The resulting cured ink composition and substrate component can be a pixelated LED that is configured to fully convert blue light-emitting pixels to red and green light-emitting pixels. Printing systems for performing these methods and producing these LEDs are also disclosed, as are various, non-limiting examples of ink composition formulations. | 2022-08-11 |
20220254761 | LIGHTING-EMITTING DEVICE FILAMENT - A light emitting device filament includes a substrate, a plurality of light emitting diodes, two electrode pads, and a plurality of connection lines. The substrate includes a first surface and a second surface opposite to the first surface. The substrate extending in a first direction and having a width in a second direction. The plurality of light emitting diodes is disposed on the first surface of the substrate. The two electrode pads are disposed on the substrate. The plurality of connection lines electrically connects the plurality of light emitting diodes and the two electrode pads. The plurality of connection lines includes a first connection line and a second connection line. The first connection line, the second connection line, or both are formed in a direction inclined or curved with respect to the first direction or the second direction. | 2022-08-11 |
20220254762 | DEVICE PACKAGES WITH UNIFORM COMPONENTS AND METHODS OF FORMING THE SAME - A semiconductor device package includes a first and a second input lead and a plurality of uniform transistor-based components, the plurality of uniform transistor-based components comprising a first subset of the uniform transistor-based components coupled to the first input lead and a second subset of the uniform transistor-based components coupled to the second input lead. The first subset and the second subset are arranged in an asymmetric configuration with respect to one another. | 2022-08-11 |
20220254763 | ELECTRONIC DEVICE - The disclosure provides an electronic device, including a substrate, a first conductor layer, a first insulating layer, an electronic component, and a driving structure. The first conductor layer is arranged on the substrate. The first insulating layer is disposed on the first conductor layer. The electronic component is arranged on the first insulating layer and coupled to the first conductor layer. The driving structure is coupled to the electronic component. The electronic device in the disclosure can have improved structural reliability. | 2022-08-11 |
20220254764 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device comprising: a semiconductor element; a supporting board supporting the semiconductor element; a wiring unit electrically connected to the semiconductor element; and a resin member sealing the semiconductor element. The resin member is provided with a first driving-side opening part, a second driving-side opening part, a first control-side opening part, and a second control-side opening part, in which a part of the wiring unit is exposed and on which electronic parts electrically connected to the wiring unit can be mounted. | 2022-08-11 |
20220254765 | POWER STRUCTURE, PREPARATION METHOD, AND DEVICE - Embodiments of this application disclose a power structure, a preparation method, and a device, to provide a power structure with a high integration degree, to meet a requirement of the high-frequency and high-power field. The embodiments of this application provide a power structure, including a first substrate, a second substrate, a driver chip, a power chip, and a conductive part. A first surface of the first substrate and a second surface of the second substrate are disposed opposite to each other; a first end of the conductive part is connected to the first surface, and a second end of the conductive part is connected to the second surface; the driver chip is disposed on the first substrate; and the power chip is disposed on the second substrate. | 2022-08-11 |
20220254766 | DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - A display apparatus, including a circuit substrate, a driving unit and a light-emitting unit is provided. The driving unit is disposed on the circuit substrate. The light-emitting unit is disposed on the circuit substrate. A thickness of the driving unit is substantially the same as a thickness of the light-emitting unit. | 2022-08-11 |
20220254767 | MANUFACTURING METHOD OF PACKAGE ON PACKAGE STRUCTURE - A manufacturing method of a package-on-package structure includes at least the following steps. Top packages are mounted on a top side of a reconstructed wafer over a flexible tape, where conductive bumps at a bottom side of the reconstructed wafer is attached to the flexible tape, and during the mounting, a shape geometry of the respective conductive bump changes and at least a lower portion of the respective conductive bump is embraced by the flexible tape. The flexible tape is released from the conductive bumps after the mounting. | 2022-08-11 |
20220254768 | APPARATUSES INCLUDING SEMICONDUCTOR LAYOUT TO MITIGATE LOCAL LAYOUT EFFECTS - Apparatuses including semiconductor layout to mitigate local layout effects arc disclosed. An example apparatus includes a plurality of standard cells each including an active region, an isolation region adjacent the active region, and a first gate structure disposed on the active region and the isolation region. The first gate structure includes a first gate portion disposed on the active region, and a first contact portion disposed on the isolation region. The apparatus further includes a second gate structure disposed on the active region and the isolation region. The second gate structure includes a second gate portion disposed on the active region, and a second contact portion disposed on the isolation region. In the apparatus, a distance between a first contact point and the first gate portion is substantially equal to a distance between a second contact point and the second gate portion. | 2022-08-11 |
20220254769 | INTEGRATED CIRCUIT AND MANUFACTURING METHOD OF THE SAME - An integrated circuit includes a driver cell and at least one transmission cell. The driver cell includes a first active area and a second active area, and a first conductive line coupled to the first active area and the second active area on a back side of the integrated circuit. The at least one transmission cell having a second cell height includes a third active area and a fourth active area, a second conductive line coupled to the third active area and the fourth active area on the back side of the integrated circuit, and a conductor coupled to the third active area and the fourth active area. The integrated circuit further includes a third conductive line coupled between the first conductive line and the second conductive line on the back side to transmit a signal between the driver cell and the at least one transmission cell. | 2022-08-11 |
20220254770 | BACKSIDE CONDUCTING LINES IN INTEGRATED CIRCUITS - An integrated circuit includes a first-type active-region structure, a second-type active-region structure on a substrate, and a plurality of gate-conductors. The integrated circuit also includes a backside horizontal conducting line in a backside first conducting layer below the substrate, a backside vertical conducting line in a backside second conducting layer below the backside first conducting layer, and a pin-connector for a circuit cell. The pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line. The backside horizontal conducting line extends across a vertical boundary of the circuit cell. | 2022-08-11 |
20220254771 | SEMICONDUCTOR CIRCUIT AND MANUFACTURING METHOD FOR THE SAME - A semiconductor circuit and a manufacturing method for the same are provided. The semiconductor circuit includes an electrostatic discharge protection circuit. The electrostatic discharge protection circuit includes an N-type region, a P-type well, a first P-type element and a first N-type element. The P-type well is in the N-type region. The first P-type element is in the N-type region. The N-type region is continuously connected between the P-type well and the first P-type element. The first N-type element is in the P-type well. | 2022-08-11 |
20220254772 | PNP CONTROLLED ESD PROTECTION DEVICE WITH HIGH HOLDING VOLTAGE AND SNAPBACK - An ESD protection device protects a circuit from TLPs between a first terminal and a second terminal. The device includes an NPN discharge structure and a PNP triggering device. The first terminal is coupled to the p-doped emitter and the n-doped base of the PNP triggering device and also the n-doped emitter of the NPN discharge structure. The second terminal is coupled to the n-doped collector of the NPN discharge structure. The p-doped collector of the PNP triggering device is coupled to the p-doped base of the NPN discharge structure. A TLP causes base-collector junction breakdown in the PNP triggering device, which results in a current through the PNP triggering device. That current is injected into the base of the NPN discharge structure, which results in a larger discharge current through the NPN discharge structure. The device provides high holding voltage ESD protection device with snapback. | 2022-08-11 |
20220254773 | ELECTROSTATIC DISCHARGE DEVICES - The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge devices and methods of manufacture. The structure includes: a plurality of regions of a first dopant type; insulator material separating each region of the plurality of regions of the first dopant type; and a substrate contacting the plurality of regions of the first dopant type, the substrate comprising a base region of a second dopant type different than the first dopant type and an outer segment surrounding the plurality of regions of the first dopant type, the outer segment comprises an electrical resistivity higher than the second dopant type. | 2022-08-11 |
20220254774 | INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR BIPOLAR TRANSISTOR STACK WITHIN SUBSTRATE - Aspects of the disclosure provide an integrated circuit (IC) structure with a bipolar transistor stack within a substrate. The bipolar transistor stack may include: a collector, a base on the collector, and an emitter on a first portion of the base. A horizontal width of the emitter is less than a horizontal width of the base, and an upper surface of the emitter is substantially coplanar with an upper surface of the substrate. An extrinsic base structure is on a second portion of the base of the bipolar transistor stack, and horizontally adjacent the emitter. The extrinsic base structure includes an upper surface above the upper surface of the substrate. | 2022-08-11 |
20220254775 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device, wherein a straight line extending from an end portion E | 2022-08-11 |
20220254776 | Hybrid Semiconductor Device - Semiconductor devices and method of forming the same are provided. In one embodiment, a semiconductor device includes a first transistor and a second transistor. The first transistor includes two first source/drain features and a first number of nanostructures that are stacked vertically one over another and extend lengthwise between the two first source/drain features. The second transistor includes two second source/drain features and a second number of nanostructures that are stacked vertically one over another and extend lengthwise between the two second source/drain features. | 2022-08-11 |
20220254777 | DEVICES AND METHODS FOR LAYOUT-DEPENDENT VOLTAGE HANDLING IMPROVEMENT IN SWITCH STACKS - Devices and methods for layout-dependent voltage handling improvement in switch stacks. In some embodiments, a switching device can include a first terminal and a second terminal, a radio-frequency signal path implemented between the first terminal and the second terminal, and a plurality of switching elements connected in series to form a stack between the second terminal and ground. The stack can have an orientation relative to the radio-frequency signal path, and the switching elements can have a non-uniform distribution of a first parameter based in part on the orientation of the stack. | 2022-08-11 |
20220254778 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first gate structure of a first gate pitch, a first channel region under the first gate electrode, a first source/drain (S/D) feature contacting the first channel region and having a first S/D depth. The second transistor includes a second gate structure of a first gate pitch, a second channel region under the first gate electrode, a second S/D feature contacting the second channel region and having a second S/D depth. The second gate pitch is larger than the first gate pitch. The second S/D depth is larger than the first S/D depth. | 2022-08-11 |
20220254779 | INTEGRATED CIRCUITS AND METHOD OF MANUFACTURING THE SAME - An integrated circuit (IC) device includes first and second fin-type semiconductor active regions on a substrate. A plurality of first semiconductor patterns are provided, which are stacked on the first fin-type active region as a first plurality of spaced-apart channel regions of a first FINFET. A plurality of second semiconductor patterns are provided, which are stacked on the second fin-type active region as a second plurality of spaced-apart channel regions of a second FINFET. A first gate structure is provided on the plurality of first semiconductor patterns. This first gate structure includes a first material region, which at least partially fills spaces between the first plurality of spaced-apart channel regions. A second gate structure is also provided on the plurality of second semiconductor patterns. The second gate structure includes second and third material regions, which at least partially fill spaces between the second plurality of spaced-apart channel regions. | 2022-08-11 |
20220254780 | METHOD (AND RELATED APPARATUS) FOR FORMING A SEMICONDUCTOR DEVICE WITH REDUCED SPACING BETWEEN NANOSTRUCTURE FIELD-EFFECT TRANSISTORS - Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a semiconductor fin projecting from a substrate. Semiconductor nanostructures are disposed over the semiconductor fin. A gate electrode is disposed over the semiconductor fin and around the semiconductor nanostructures. A dielectric fin is disposed over the substrate. A dielectric structure is disposed over the dielectric fin. An upper surface of the dielectric structure is disposed over the upper surface of the gate electrode. A dielectric layer is disposed over the substrate. The dielectric fin laterally separates both the gate electrode and the semiconductor nanostructures from the dielectric layer. An upper surface of the dielectric layer is disposed over the upper surface of the gate electrode structure and the upper surface of the dielectric structure. A lower surface of the dielectric layer is disposed below the upper surface of the dielectric fin. | 2022-08-11 |
20220254781 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed are semiconductor devices and their fabricating methods. The semiconductor device comprises first and second active patterns, a first channel pattern including first semiconductor patterns, a second channel pattern including second semiconductor patterns, a gate electrode on the first and second channel patterns, and a gate dielectric layer between the gate electrode and the first and second channel patterns. The gate electrode includes a first inner gate electrode between the first semiconductor patterns, a second inner gate electrode between the second semiconductor patterns, and an outer gate electrode outside the first and second semiconductor patterns. The first and second inner gate electrodes are on bottom surfaces of uppermost first and second semiconductor patterns. The outer gate electrode is on top surfaces and sidewalls of the uppermost first and second semiconductor patterns. The first and second inner gate electrodes have different work functions. | 2022-08-11 |
20220254782 | METHOD FOR MANUFACTURING MEMORY AND MEMORY - A method for manufacturing a memory and a memory is provided. The method for manufacturing a memory includes: providing a substrate; stacking an electrode support structure, a protective layer and a first mask layer in sequence on the substrate; patterning the first mask layer on an array region, and etching the protective layer, the electrode support structure and the substrate by using the patterned first mask layer as a mask, to form capacitor holes penetrating the protective layer and the electrode support structure and extending into the substrate; removing the first mask layer; and forming a first electrode layer on side walls and bottom walls of the capacitor holes, a top surface of the first electrode layer being flush with a top surface of the electrode support structure. | 2022-08-11 |
20220254783 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases. | 2022-08-11 |
20220254784 | EPITAXIAL SILICON WITHIN HORIZONTAL ACCESS DEVICES IN VERTICAL THREE DIMENSIONAL (3D) MEMORY - Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by epitaxially grown channel regions. Gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from a channel regions by a gate dielectrics. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and digit lines coupled to the first source/drain regions. | 2022-08-11 |
20220254785 | Electrical Contact Structure - Provided are an electrical contact structure. Through enabling at least the first contact plug closest to a peripheral area to be formed above an isolation structure of a boundary area between a core area and the peripheral area and in contact with the isolation structure, and enabling a bottom portion of the first contact plug to be completely overlapped on the isolation structure, or, enabling a part of the bottom portion to be overlapped with the isolation structure, enabling the other part of the bottom portion to be overlapped with an active area (AA) of the core area next to the isolation structure, and even enabling a top portion of the first contact plug to be at least connected with a top portion of the contact plug above the AA of the core area next to the isolation structure. | 2022-08-11 |
20220254786 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE - Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate, and forming bit lines extending in a first direction and trenches between the adjacent bit lines on the substrate; forming a dielectric layer and a contact layer filling the trenches, parts of the dielectric layer and parts of the contact layer being arranged at intervals in the first direction, both the dielectric layer and the contact layer being in contact with the substrate, and the contact layer having first gaps; removing part of the contact layer, to expose the first gaps; forming a filling layer to fill the first gaps; and etching the contact layer and the filling layer back. | 2022-08-11 |
20220254787 | SSEMICONDUCTOR DEVICES - A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region. | 2022-08-11 |
20220254788 | MEMORY SUBWORD DRIVER LAYOUT - Semiconductor devices including active regions and gate electrodes are disclosed. An example semiconductor device according to the disclosure includes a gate electrode extending in a first direction, and first and second active regions extending in a second direction. The gate electrode has a side extending in the first direction. The first active region includes: a first center portion having a first width in the first direction; and a first end portion disposed at a first end of the first center portion, and having a second width in the first direction that is greater than the first width. The second active region includes: a second center portion having a third width in the first direction. The gate electrode overlaps along the side with portions of the first end portion and the second center portion. | 2022-08-11 |
20220254789 | SRAM STRUCTURE AND METHOD FOR FORMING THE SAME - SRAM structures are provided. An SRAM structure includes a substrate, a P-type well region over the substrate, an N-type well region over the substrate, a PMOS transistor in the N-type well region, an NMOS transistor in the P-type well region, an isolation region over the boundary between the P-type well region and the N-type well region, and a dielectric structure formed in the isolation region and extending from the isolation region to the boundary between the P-type well region and the N-type well region. The depth of the dielectric structure is greater than that of the isolation region. The PMOS transistor is separated from the NMOS transistor by the isolation region. | 2022-08-11 |
20220254790 | PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A bottom portion of a Ta pillar serving as a contact portion is connected to an N | 2022-08-11 |
20220254791 | THREE-DIMENSIONAL MEMORY ARRAY WITH LOCAL LINE SELECTOR - The present disclosure relates to an integrated chip including a three-dimensional memory array. The three-dimensional memory array includes a first local line and a second local line that are elongated vertically, a first memory cell extending between the first local line and the second local line, and a second memory cell directly under the first memory cell, extending between the first local line and the second local line, and coupled in parallel with the first memory cell. The first memory cell is coupled to a first word line and the second memory cell is coupled to a second word line. The first word line and the second word line are elongated horizontally. A first global line is disposed at a first height and is elongated horizontally. A first selector extends vertically from the first local line to the first global line. | 2022-08-11 |
20220254792 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor memory device includes: a gate electrode stack vertically stacked over a substrate with bent gate pads, the bent gate pads portion of the gate electrode stack having a step-shaped structure; an inter-layer dielectric layer covering the bent gate pads; and a plurality of contact plugs respectively coupled to the bent gate pads by penetrating the inter-layer dielectric layer, wherein the bent gate pads include angled corner portions of different sizes. | 2022-08-11 |
20220254793 | COCKTAIL LAYER OVER GATE DIELECTRIC LAYER OF FET FERAM - In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode arranged over a substrate. A gate dielectric layer is arranged over the gate electrode, and an active structure is arranged over the gate dielectric layer. A source contact and a drain contact are arranged over the active structure. The active structure includes a stack of cocktail layers alternating with first active layers. The cocktail layers include a mixture of a first material and a second material. The first active layers include a third material that is different than the first and second materials. The bottommost layer of the active structure is one of the cocktail layers. | 2022-08-11 |
20220254794 | CAPPING LAYER OVER FET FERAM TO INCREASE CHARGE MOBILITY - In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material. | 2022-08-11 |
20220254795 | FERROELECTRIC DEVICE BASED ON HAFNIUM ZIRCONATE AND METHOD OF FABRICATING THE SAME - A ferroelectric device, for instance, a metal-ferroelectric-metal (MFM) capacitor, a ferroelectric random access memory (Fe-RAM), or a ferroelectric field effect transistor (FeFET), is provided. In one aspect, the ferroelectric device is based on hafnium zirconate (HZO). The ferroelectric device can include a first electrode and a second electrode, and a doped HZO layer, which is arranged between the first electrode and the second electrode. The doped HZO layer can include a ferroelectric layer and at least two non-zero remnant polarization charge states. The doped HZO layer can be doped with at least two different elements selected from the lanthanide series, or with a combination of at least one element selected from the lanthanide series and at least one rare earth element. | 2022-08-11 |
20220254796 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines disposed over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed between the first lines and the second lines at intersection regions of the first lines and the second lines; first liner layer patterns positioned on both sidewalls of each memory cell in the second direction; a first insulating layer pattern positioned between adjacent first liner layer patterns in the second direction; second liner layer patterns positioned on both sidewalls of each memory cell in the first direction; a second insulating layer pattern positioned between adjacent second liner layer patterns in the first direction; and a third insulating layer positioned between adjacent second liner layer patterns in the second direction. | 2022-08-11 |
20220254797 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING MULTI-BIT CHARGE STORAGE ELEMENTS AND METHODS FOR FORMING THE SAME - A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from and is electrically isolated from the first memory material portion by at least one blocking dielectric material portion. | 2022-08-11 |
20220254798 | THREE-DIMENSIONAL MEMORY ARRAY INCLUDING DUAL WORK FUNCTION FLOATING GATES AND METHOD OF MAKING THE SAME - A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures extending through the alternating stack, where each of the memory opening fill structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements is located at a level of a respective one of the electrically conductive layers between the respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from the first memory material portion. The second memory material portion has a different material composition from the first memory material portion. | 2022-08-11 |
20220254799 | SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF - A semiconductor device is provided. The semiconductor device includes a first vertical stack, a first vertical channel line, a first data storage structure, and a first gate dielectric structure. The first vertical stack includes a first conductive line and a second conductive line. The first vertical channel line vertically passes through the first conductive line and the second conductive line, and the first vertical channel line is a P-type channel. The first data storage structure is disposed between the first conductive line and the first vertical channel line. The first gate dielectric structure is disposed between the second conductive line and the first vertical channel line. | 2022-08-11 |
20220254800 | SEMICONDUCTOR STORAGE DEVICE - A device includes a first region including first semiconductor pillars extending through first conductive layers; a second region including second semiconductor pillars extending through second conductive layers; and a third region disposed between the first region and the second region and including insulator columns extending through third conductive layers. The third region includes a fourth region and a fifth region. In the fourth region, one third conductive layer electrically connects one first conductive layer and one second conductive layer to each other, and in the fifth region, one third conductive layer is connected to a contact plug. A first diameter of a first subset of the insulator columns provided in the fourth region is smaller than a second diameter of a second subset of the insulator columns provided in the fifth region. | 2022-08-11 |
20220254801 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a semiconductor substrate comprising a first region, a second region, and a third region provided therebetween. The first region comprises: first conductive layers; a first semiconductor layer facing the first conductive layers; and a second semiconductor layer connected to the first semiconductor layer. The second region comprises: a third semiconductor layer and fourth semiconductor layer; and a second conductive layer electrically connected to the third semiconductor layer, the fourth semiconductor layer, and the semiconductor substrate. The third region comprises a fifth semiconductor layer and sixth semiconductor layer that are formed continuously with the second semiconductor layer and the third semiconductor layer or fourth semiconductor layer, and extend in a second direction. The third region comprises first and second portions aligned alternately in the second direction. In the second portions, the fifth and the sixth semiconductor layers are electrically connected. | 2022-08-11 |
20220254802 | SEMICONDUCTOR DEVICE, AN ELECTRONIC SYSTEM INCLUDING THE SAME, AND A METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes an upper-level layer having a cell array region, a cell contact region and a dummy region on a substrate. The upper-level layer includes a semiconductor layer, a cell array structure including first and second stack structures sequentially stacked on the semiconductor layer of the cell array region, the first and second stack structures comprising stacked electrodes, a first staircase structure on the semiconductor layer of the cell contact region, the electrodes extending from the cell array structure into the first staircase structure such that the cell array structure is connected to the first staircase structure, a vertical channel structure penetrating the cell array structure, a dummy structure in the dummy region, the dummy structure at the same level as the second stack structure, the dummy structure including stacked first layers, and cell contact plugs in the cell contact region and connected to the first staircase structure. | 2022-08-11 |
20220254803 | CURVED CHANNEL 3D MEMORY DEVICE - A vertical memory structure comprises a stack of alternating layers of insulator material and word line material with a vertical opening through the alternating layers. One of the layers of insulating material and layers of word line material have recessed inside surfaces facing the opening. First and second conductive pillars are disposed inside the vertical opening. A data storage structure is disposed on the inside surfaces of the layers of word line material, including on the recessed inside surfaces. A semiconductor channel layer is disposed on the data storage structures around a perimeter of the vertical opening, and having first and second source/drain terminals at contacts with the first and second conductive pillars | 2022-08-11 |