32nd week of 2022 patent applcation highlights part 64 |
Patent application number | Title | Published |
20220254904 | SILICON CARBIDE SEMICONDUCTOR DEVICE, POWER CONVERTER, AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A drift layer has a first conductivity type and is provided on a silicon carbide substrate. A well region has a second conductivity type and is provided on the drift layer. A source region has the first conductivity type and is provided on the well region. A gate trench has an inner surface with a bottom located at a deeper position than the well region and a lateral part continuous with the bottom. An electric field relaxation region has the second conductivity type and has at least a part located below the bottom of the gate trench. A surge relaxation region has the first conductivity type, contacts at least a part of the bottom of the gate trench, and is separated from the drift layer by the electric field relaxation region. | 2022-08-11 |
20220254905 | INTEGRATED CIRCUIT COMPRISING A JUNCTION FIELD EFFECT TRANSISTOR (JFET) AND METHOD FOR MANUFACTURING SUCH AN INTEGRATED CIRCUIT - An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate. | 2022-08-11 |
20220254906 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND POWER CONVERTER - An object of the present invention is to suppress the passage of bipolar current in a silicon carbide semiconductor device by reducing a voltage applied to a terminal well region during reflux operations. An SiC-MOSFET includes a plurality of first well regions, a second well region, a third well region in a surface layer of a drift layer, the first, second, and third well regions being of a second conductivity type. The third well region is provided on the side of the second well region opposite to the first well regions. A unit cell that includes the first well regions includes a unipolar diode. The SiC-MOSFET includes a source electrode connected to the unipolar diode and the ohmic electrode and not having ohmic connection with the second well region and the third well region. | 2022-08-11 |
20220254907 | INSULATED GATE BIPOLAR FIELD-EFFECT TRANSISTOR, GROUP, AND POWER CONVERTER - An insulated gate bipolar field-effect transistor (IGBT) includes a semiconductor chip, a gate pin disposed around the semiconductor chip, and an emitter region and n gate regions that are disposed on the semiconductor chip, where n is an integer greater than or equal to 2; x gate regions in the n gate regions are connected to the gate pin, where x is greater than or equal to 1 and less than or equal to n; when there is a different quantity x of gate regions connected to the gate pin, the IGBT is correspondingly applicable to a scenario in which there is a different switching frequency and a different switching loss; and n−x gate regions in the n gate regions are connected to the emitter region. | 2022-08-11 |
20220254908 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a drift layer provided on an upper surface side of the substrate, a base layer provided on the upper surface side of the drift layer, an upper semiconductor layer provided on the upper surface side of the base layer, a first electrode provided on the upper surface of the substrate, a second electrode provided on a rear surface of the substrate, a trench extending to the drift layer from the upper surface of the substrate and a gate electrode provided inside the trench, wherein an inner side surface of the trench has a first surface and a second surface provided below the first surface, the second surface tilts inward of the trench with respect to the first surface, and an intersection point of the first surface and the second surface is provided below the base layer. | 2022-08-11 |
20220254909 | Tunnel Field-Effect Transistor and Method for Manufacturing the Same - A channel layer has a quantum well structure including InGaAs or InGaAsSb, and includes a first barrier layer, a well layer, and a second barrier layer. A first intermediate layer is provided between the first barrier layer and the well layer, and a second intermediate layer is provided between the second barrier layer and the well layer. The first and second intermediate layers include InGaAs or InGaAsSb having an In composition ratio greater than that of the first and second barrier layers and smaller than that of the well layer. | 2022-08-11 |
20220254910 | BIDIRECTIONAL SWITCHES WITH ACTIVE SUBSTRATE BIASING - Structures for a bidirectional switch and methods of forming such structures. A substrate contact is formed in a trench defined in a substrate. A substrate includes a trench and a substrate contact in the trench. A bidirectional switch, which is on the substrate, includes a first source/drain electrode, a second source/drain electrode, an extension region between the first source/drain electrode and the second source/drain electrode, and a gate structure. A substrate-bias switch, which is on the substrate, includes a gate structure, a first source/drain electrode coupled to the substrate contact, a second source/drain electrode coupled to the first source/drain electrode of the bidirectional switch, and an extension region laterally between the gate structure and the first source/drain electrode. | 2022-08-11 |
20220254911 | NORMALLY-CLOSED DEVICE AND FABRICATION METHOD THEREOF - The present disclosure relates to the technical field of semiconductors, and provides a normally-closed device and a fabrication method thereof. The normally-closed device comprises a substrate; an epitaxial layer connected to the substrate, wherein the epitaxial layer comprises a first P-type nitride layer and a modified layer, the modified layer is located on two sides of the first P-type nitride layer, the modified layer is formed by modifying a second P-type nitride layer in a preset region, and the first P-type nitride layer and the second P-type nitride layer are formed by epitaxially growing synchronously; a barrier layer connected to the first P-type nitride layer and the modified layer; and a gate electrode connected to the barrier layer, and a source electrode and a drain electrode connected to the modified layer. | 2022-08-11 |
20220254912 | AN ENHANCEMENT MODE METAL INSULATOR SEMICONDUCTOR HIGH ELECTRON MOBILITY TRANSISTOR - An enhancement mode metal insulator semiconductor high electron mobility transistor (HEMT) is presented herein. By using a polarization stack to replace the traditional barrier layer, a thinner barrier layer (e.g., a thinner layer of AlGaN) may be formed during fabrication to effectuate a low-sheet-resistance two-dimensional electron gas. Advantageously, the thinner (.i.e., less-than-ten nanometers) barrier layer mitigates reactive ion etching (RIE) induced surface damage. This in turn allows the formation of a recessed gate. Additionally, a dual dielectric gate stack may be deposited to further reduce leakage currents and to improve subthreshold slope. | 2022-08-11 |
20220254913 | Semiconductor Device and Method of Fabricating a Semiconductor Device - A semiconductor device includes a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposing the first surface, at least one mesa positioned on the first surface, each mesa including an epitaxial III-V semiconductor-based multi-layer structure on the first surface of the support substrate, the III-V semiconductor-based multi-layer structure forming a boundary with the first surface and a parasitic channel suppression region positioned laterally adjacent the boundary. | 2022-08-11 |
20220254914 | MOSFET TRANSISTORS WITH HYBRID CONTACT - A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region. | 2022-08-11 |
20220254915 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, gate insulating films, gate electrodes, a first electrode, and a second electrode. When a current flows from the first electrode to the second electrode, a peak light emission intensity at a wavelength close to 390 nm is lower than a peak light emission intensity at a wavelength close to 500 nm. | 2022-08-11 |
20220254916 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SILICON CARBIDE SEMICONDUCTOR DEVICE - Back-surface roughness of a back surface of a silicon carbide semiconductor device having a MOS gate structure in a first region that is a region within 30 μm of a cross section (lateral surface) of the device is at most 4 μm while the back-surface roughness in a second region other than the first region is at most 2 μm, the back surface of the silicon carbide semiconductor device is the back surface of the second electrode. In a method of manufacture, the back-surface roughness of the device is specified to meet a predetermined condition. Then, ON voltages of the device before and after a forward current is passed through body diodes of the device are measured, and a rate of change of the ON voltage while the forward current is passed through body diodes is calculated, and then the device having a calculated rate of change less than 3% is identified. | 2022-08-11 |
20220254917 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device being capable of operating at least 100 degree C., includes a semiconductor substrate having an active region, the semiconductor substrate having first and second surfaces opposite to each other, a first semiconductor region of an n type, provided in the semiconductor substrate, a second semiconductor region of a p type, provided in the active region, between the first surface of the semiconductor substrate and the first semiconductor region, and a device element structure including a pn junction between the second and first semiconductor regions that forms a body diode through which a current flows when the semiconductor device is turned on. A stacking fault area that is a sum of areas that contain stacking faults within an entire active region of the first surface of the semiconductor substrate in the first surface is set to be greater, the higher a breakdown voltage is set. | 2022-08-11 |
20220254918 | METHODS AND SYSTEMS FOR FABRICATION OF VERTICAL FIN-BASED JFETS - A vertical FET device includes a semiconductor structure comprising a semiconductor substrate, a first semiconductor layer coupled to the semiconductor substrate, and a second semiconductor layer coupled to the first semiconductor layer. The vertical FET device also includes a plurality of fins. Adjacent fins of the plurality of fins are separated by a trench extending into the second semiconductor layer and each of the plurality of fins includes a channel region disposed in the second semiconductor layer. The vertical FET also includes a gate region extending into a sidewall portion of the channel region of each of the plurality of fins, a source metal structure coupled to the second semiconductor layer, a gate metal structure coupled to the gate region, and a drain contact coupled to the semiconductor substrate. | 2022-08-11 |
20220254919 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, third semiconductor regions of the second conductivity type, provided in the second semiconductor layer at positions facing the first semiconductor regions in a depth direction and having an impurity concentration higher than an impurity concentration of the second semiconductor layer, trenches, gate insulating films, gate electrodes, a first electrode, a second electrode, and third electrodes. The third electrodes form Schottky junctions with the second semiconductor layer and are provided on the surface of portions of the second semiconductor layer free of the third semiconductor regions. | 2022-08-11 |
20220254920 | Electronic Device Including a Non-Volatile Memory Cell and a Process of Forming the Same - An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time. | 2022-08-11 |
20220254921 | SEMICONDUCTOR DEVICE HAVING JUNCTION TERMINATION STRUCTURE AND METHOD OF FORMATION - A power semiconductor device may include a junction termination region, bounded by a side edge of a semiconductor substrate. The junction termination region may include a substrate layer of a first dopant type, a well layer of a second dopant type, a conductive trench assembly having a first set of conductive trenches, in the junction termination region, and extending from above the substrate layer through the well layer; and a metal layer, electrically connecting the conductive trench assembly to the well layer. The metal layer may include a set of inner metal contacts, electrically connecting a set of inner regions of the well layer to a first set of trenches of the conductive trench assembly; and an outer metal contact, electrically connecting an outer region of the well layer to a second set of conductive trenches of the conductive trench assembly, wherein the outer region borders the side edge. | 2022-08-11 |
20220254922 | LDMOS TRANSISTORS INCLUDING VERTICAL GATES WITH MULTIPLE DIELECTRIC SECTIONS, AND ASSOCIATED METHODS - A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances. | 2022-08-11 |
20220254923 | HIGH VOLTAGE DEVICE - A high-voltage device includes a first frame-like isolation and a second frame-like isolation separated from each other, a first frame-like gate structure covering the first frame-like isolation, a second frame-like gate structure covering the second frame-like isolation, a first drain region enclosed by the first frame-like isolation, a second drain region enclosed by the second frame-like isolation, a first frame-like source region surrounding the first frame-like gate structure, a second frame-like source region surrounding the second frame-like gate structure, a first doped region surrounding the first and second frame-like gate structures, and a second doped region disposed between the first and second frame-like gate structures. The first and second drain regions, and the first and second frame-like source regions include a first conductivity type. The first and the second doped region include a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. | 2022-08-11 |
20220254924 | TRANSISTOR STRUCTURE AND METHOD FOR FABRICATING THE SAME - A transistor structure includes a substrate, having a gate region and a first trench in the substrate at a first side of the gate region. Further, a first gate insulating layer is disposed on a first portion of the gate region, opposite to the first trench. A second gate insulating layer is disposed on a second portion of the gate region and a first portion of the first trench abutting to the gate region, wherein the second gate insulating layer is thicker than the first gate insulating layer. A gate layer is disposed on the first and second gate insulating layers, having a downward protruding portion corresponding to the first trench. A first doped region is in the substrate at least under the first trench. A second doped region is in the substrate at a second side of the gate region. | 2022-08-11 |
20220254925 | 3D DEVICES WITH 3D DIFFUSION BREAKS AND METHOD OF FORMING THE SAME - A semiconductor device is provided. The semiconductor device includes a first layer including a first semiconductor material. Shell structures are positioned above and electrically isolated from the first layer. The shell structures include at least one type of semiconductor material. Each shell structure is configured to include a channel region oriented in a vertical direction perpendicular to the first layer and have a current flow path in the vertical direction. The semiconductor device also includes an inner structure positioned on an inner sidewall of a respective channel region of each shell structure. The semiconductor device further includes gate structures including an outer gate structure positioned on an outer sidewall of a respective channel region of each shell structure. | 2022-08-11 |
20220254926 | METHOD OF MAKING A FIN FIELD-EFFECT TRANSISTOR AVOIDING SKEWING AND BENDING OF THE FINS - A method of making a Fin Field-effect transistor includes: providing a substrate and a plurality of fin structures on a surface of the substrate; forming a shallow trench isolation structure between the plurality of fin structures; forming a stress layer on a side of the shallow trench isolation structure away from the substrate; heat treating the stress layer and the plurality of fin structures; and removing the stress layer. The fin structures are spaced apart from each other. The stress layer covers a part of the fin structures away from the substrate. | 2022-08-11 |
20220254927 | GATE CONTACT AND VIA STRUCTURES IN SEMICONDUCTOR DEVICES - A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed within the gate capping structure and a first via structure disposed on the first contact structure. | 2022-08-11 |
20220254928 | SEMICONDUCTOR DEVICES - Semiconductor devices may include a substrate, an active region that is on the substrate and extends in a first direction, a gate structure that traverses the active region and extends in a second direction that may be different from the first direction, a source/drain region on the active region adjacent a side of the gate structure, an insulating layer on the substrate, the gate structure and the source/drain region, and a contact structure that is in the insulating layer and is connected to the source/drain region. In the source/drain region, a contact region that is in contact with the contact structure includes first and second side regions spaced apart from each other in the second direction and a central region between the first and second side regions, and at least one of the first and second side regions may include a recess. | 2022-08-11 |
20220254929 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and a sidewall of the first portion of the gate dielectric layer extends beyond a sidewall of the filling layer. | 2022-08-11 |
20220254930 | Transistors with Enhanced Dopant Profile and Methods for Forming the Same - A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor. | 2022-08-11 |
20220254931 | THIN FILM TRANSISTOR INCLUDING A DIELECTRIC DIFFUSION BARRIER AND METHODS FOR FORMING THE SAME - A semiconductor device includes an insulating layer embedding a gate electrode and overlying a substrate, a stack of a gate dielectric including a gate dielectric material, a dielectric diffusion barrier liner including a dielectric diffusion barrier material, and an active layer overlying a top surface of the gate electrode, and | 2022-08-11 |
20220254932 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device for high power consumption is provided. The semiconductor device includes a substrate, a first conductor over the substrate, a first metal oxide over the first conductor, a first oxide over the first metal oxide, a second oxide over the first oxide, a first insulator over the second oxide, a second conductor over the first insulator, a second insulator over the second conductor, a third insulator in contact with a side surface of the second conductor, a side surface of the first insulator, and a side surface of the second insulator, a second metal oxide over the second oxide, the second insulator, and the third insulator, and a third conductor over the second metal oxide. The second conductor includes a region overlapping with the second oxide. The third conductor includes a region in contact with the second metal oxide. The second metal oxide includes a region in contact with the second oxide. The carrier concentration of the second oxide is lower than the carrier concentration the first oxide. | 2022-08-11 |
20220254933 | ACTIVE DEVICE SUBSTRATE AND FABRICATION METHOD OF ACTIVE DEVICE SUBSTRATE - An active device substrate includes a substrate, an active device and a barrier layer. The active device is located on the substrate. The barrier layer is located on the active device. The barrier layer includes a first hydrogen atom distribution region and a second hydrogen atom distribution region. The first hydrogen atom distribution region includes silicon nitride and hydrogen atom. The first hydrogen atom distribution region is located between the second hydrogen atom distribution region and the substrate. The second hydrogen atom distribution region includes silicon nitride and hydrogen atom. The concentration of nitrogen atom in the first hydrogen atom distribution region is less than the concentration of nitrogen atom in the second hydrogen atom distribution region. The highest concentration of hydrogen atom in the first hydrogen atom distribution region is greater than the highest concentration of hydrogen atom in the second hydrogen atom distribution region. | 2022-08-11 |
20220254934 | ELECTRONIC CIRCUIT - An electronic circuit is disclosed. The electronic circuit includes: a first transistor device integrated in an inner region of a first semiconductor body; a level shifter integrated in a level shifter region of the first semiconductor body, the level shifter region located in an edge region surrounding the inner region of the semiconductor body; and a drive circuit integrated in a drive circuit region in the edge region of the first semiconductor body, the drive circuit configured to receive a first input signal from a first input and drive the first transistor device based on the first input the drive circuit region arranged closer to the inner region than the level shifter region. | 2022-08-11 |
20220254935 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer, a charge storage layer disposed on the surface of the semiconductor layer via a first insulating film, and an electrode layer disposed on the surface of the charge storage layer via a second insulating film. The charge storage layer includes a first layer containing elemental aluminum and elemental nitrogen, a second layer containing elemental silicon and elemental nitrogen, and a third layer containing elemental oxygen. | 2022-08-11 |
20220254936 | STACKED III-V SEMICONDUCTOR DIODE - A stacked III-V semiconductor diode comprising or consisting of GaAs, with a heavily n-doped cathode layer, a heavily p-doped anode layer, and a drift region arranged between the cathode layer and the anode layer with a dopant concentration of at most 8·10 | 2022-08-11 |
20220254937 | STACKED III-V SEMICONDUCTOR DIODE - A stacked III-V semiconductor diode comprising or consisting of GaAs with a highly n-doped cathode layer, a highly p-doped anode layer and a drift region arranged between the cathode layer and the anode layer, wherein the drift region has a low n-doped drift layer and a low p-doped drift layer, the n-doped drift layer is arranged between the p-doped drift layer and the cathode layer, both drift layers each have a layer thickness of at least 5 μm and, along the respective layer thickness, have a dopant concentration maximum of not more than 8·10 | 2022-08-11 |
20220254938 | STACKED III-V SEMICONDUCTOR DIODE - A semiconductor having a n-doped cathode layer, a p-doped anode layer, and a drift region, arranged between the cathode layer and the anode layer, with a dopant concentration of at most 8·10 | 2022-08-11 |
20220254939 | EPITAXIAL WAFER, METHOD OF MANUFACTURING THE EPITAXIAL WAFER, DIODE, AND CURRENT RECTIFIER - An epitaxial wafer, a method of manufacturing the epitaxial wafer, a diode, and a current rectifier are provided. The epitaxial wafer comprises a Si substrate layer; an insulating layer formed on the Si substrate layer; and a nitride semiconductor layer formed on a surface of the insulating layer facing away from the Si substrate layer; wherein the insulating layer has a thickness configured such that under a forward bias voltage, the insulating layer may allow electrons and holes to pass from one side to the other side of the insulating layer via quantum tunneling so as to allow a forward current flow. | 2022-08-11 |
20220254940 | LIGHT-RECEIVING DEVICE AND METHOD OF MANUFACTURING LIGHT-RECEIVING DEVICE - A light-receiving device includes a first semiconductor layer having a first conductivity type, an optical waveguide structure on a first region of the first semiconductor layer, and a photodiode structure on a second region adjacent to the first region of the first semiconductor layer. The optical waveguide structure includes a core layer on the first semiconductor layer, and a cladding layer on the core layer. The photodiode structure includes a light-absorbing layer optically coupled with the core layer, and a second semiconductor layer having a second conductivity type on or above the light-absorbing layer. The light-absorbing layer includes a third semiconductor layer having a p-type, and a fourth semiconductor layer having a n-type or an i-type. The third semiconductor layer is disposed between the fourth semiconductor layer and a p-type layer that is one of the first semiconductor layer and the second semiconductor layer. | 2022-08-11 |
20220254941 | OPTOELECTRONIC DEVICES WITH NON-RECTANGULAR DIE SHAPES - An optoelectronic module may include one or more non-rectangular optoelectronic dies e.g., light emitting diodes and photodiodes, arranged to maximize the usage of surface area when mounted to a base circuit board. Multi-axis and non-orthogonal axis dicing processes can be used to form the dies which have non-rectangular shapes. | 2022-08-11 |
20220254942 | PHOTOVOLTAIC MODULE - The embodiments of the present disclosure provide a photovoltaic module including a base plate, a cell string and a cover plate stacked in order; a first packaging layer located between the base plate and the cover plate and surrounding the cell string, the first packaging layer, the base plate and the cover plate defining a sealed space; and a moisture treatment layer located in the sealed space. The moisture treatment layer includes at least one of a functional layer and a moisture detection layer. The functional layer is adaptive to absorb moisture and be converted into a solidified layer, the solidified layer has a degree of cross linking greater than a degree of cross linking of the functional layer. The moisture detection layer is adaptive to detect and determine whether there is moisture in the sealed space through response information of the moisture detection layer. | 2022-08-11 |
20220254943 | HALF-CELL PHOTOVOLTAIC MODULES - The present invention relates a photovoltaic module comprising 126, 138 or 150 back-contact half-cells. In an embodiment, the half-cells are divided into 3 groups of each 2 parallel strings with each string containing ⅙ of the total number of half-cells. The module comprises an additional row of 6 back-contact half-cells, relative to known half-cell modules. | 2022-08-11 |
20220254944 | HIGH RADIATION DETECTION PERFORMANCE FROM PHOTOACTIVE SEMICONDUCTOR SINGLE CRYSTALS - Methods and devices for detecting incident radiation are provided. The methods and devices use high quality single-crystals of photoactive semiconductor compounds in combination with metal anodes and metal cathodes that provide for enhanced photodetector performance. | 2022-08-11 |
20220254945 | LOW-POWER PHOTONIC DEMODULATOR - A photo-detector for detecting photons generated by a received light is disclosed. The photo-detector includes a semiconductor substrate, two or more guided regions, a photo sensing region, and two or more detection regions. The semiconductor substrate and the guided regions are doped with the first conductive type of dopant. The photo sensing region is disposed between the two or more guided regions for an impinging photon from the received light to generate photo carriers. The detection regions are doped with a second conductive type of dopant. The guided regions are respectively connected to power sources to apply an electric potential across the guided regions for controlling a detectivity of the impinging photon. The photo sensing region is provided to form at least a pn junction between the guided regions that is reverse biased so as to reduce or prevent a leakage path between the guided regions. | 2022-08-11 |
20220254946 | SINGLE PHOTON AVALANCHE DIODE - A single photon avalanche diode may include a substrate and a plurality of junction structures supported by the substrate. The substrate may have an upper surface and a lower surface that are opposite to each other. The junction structures may support by the substrate to make contact with the upper surface of the substrate. The junction structures may include portions that overlap with each other in a vertical direction perpendicular to the substrate. Each of the junction structures may include a first impurity region having a first conductive type and disposed to make contact with the upper surface of the substrate, and a second impurity region having a second conductive type and disposed to make contact with the upper surface of the substrate and a bottom surface of the first impurity region. The first impurity region and the second impurity region in each of the junction structures may be configured to receive a bias voltage through the upper surface of the substrate. | 2022-08-11 |
20220254947 | METHOD FOR STRUCTURING AN INSULATING LAYER ON A SEMICONDUCTOR WAFER - A method for structuring an insulating layer on a semiconductor wafer, at least comprising the steps of: Provision of a semiconductor wafer with a top, a bottom and comprising multiple solar cell stacks, wherein each solar cell stack is a Ge substrate, which forms the bottom of the semiconductor wafer, a Ge subcell and at least two III-V subcells, in the above order, and at least one passage opening, which extends from the top to the bottom of the semiconductor wafer and has a connected side wall, an insulating layer two-dimensionally deposited on the top of the semiconductor wafer, on the side wall of the passage opening and/or on the bottom of the semiconductor wafer, and the deposition of an etch-resistant filling material by means of a printing process on an area of the top which comprises the passage opening, and into the passage opening. | 2022-08-11 |
20220254948 | INVERTED METAMORPHIC MULTIJUNCTION SOLAR CELL - A solar cell comprising an epitaxial sequence of layers of semiconductor material thrilling at least a first and second solar subcells; a semiconductor contact layer disposed on the bottom surface of the second solar subcell; a reflective metal layer disposed below the semiconductor contact layer such that the reflectivity of the reflective metal layer is greater than 80% in the wavelength range 850 to 2000 nm, for reflecting light back into the second solar subcell. | 2022-08-11 |
20220254949 | TRANSFER RESIN FOR TRANSFERRING AN LED CHIP, AND AN APPARATUS FOR TRANSFERRING AN LED CHIP BY USING THE SAME - The present invention relates to a transfer technology using a technique of transferring LED chips formed on a wafer to another carrier substrate and display panel, a transfer resin, and an apparatus for transferring an LED chip and a display panel using a resin which expands when light is applied. An apparatus for transferring an LED chip in accordance with an embodiment of the present invention, comprises: a substrate and a resin layer, formed on the substrate, which forms a photo-deteriorating layer and expands at a predetermined temperature. An LED chip is disposed on the resin layer and a lower part of the LED chip is placed in a state of being embedded in the resin layer by a clip-up structure. An adhesive force of the LED chip located in the photo-deteriorating layer is offset so that the LED chip is peeled off or transferred. | 2022-08-11 |
20220254950 | SELECTIVE RELEASE AND TRANSFER OF MICRO DEVICES - A method of selectively transferring micro devices from a donor substrate to contact pads on a receiver substrate. The method may comprise: providing a donor substrate comprising the plurality of micro devices, transferring the plurality of micro devices to an intermediate substrate, aligning a selected set of micro devices on the intermediate substrate proximal to the system substrate, providing a photo-sensitive layer between the selected set of micro devices and the system receiver; turning on the selected micro devices, curing the photo-sensitive layer in between the selected set of micro devices and the system substrate by light emitted by the selected micro devices; and bonding the selected set of micro devices to the corresponding contact pads on the system substrate. | 2022-08-11 |
20220254951 | METHOD FOR MANUFACTURING DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE - The present disclosure relates to a method for manufacturing a display device capable of transferring semiconductor light emitting diodes formed at predetermined intervals on a growth substrate to a wiring board or an assembly board while maintaining the intervals when the semiconductor light emitting diodes are transferred from the growth substrate to the assembly board by self-assembly. | 2022-08-11 |
20220254952 | PROCESS FLOW FOR HYBRID TFT-BASED MICRO DISPLAY PROJECTOR - Disclosed herein are techniques for forming a thin-film circuit layer on an array of light-emitting diodes (LEDs). LEDs in the array of LEDs can be singulated by various processes, such as etching and ion implantation. Singulating LEDs can be performed before or after forming the thin-film circuit layer on the array of LEDs. The array of LEDs can be bonded to a transparent or non-transparent substrate. | 2022-08-11 |
20220254953 | PRECLEAN AND ENCAPSULTAION OF MICROLED FEATURES - Method for cleaning and encapsulating microLED features are disclosed. Some embodiments provide for a wet clean process and a dry clean process to remove contaminants from the microLED feature. Some embodiments provide for the encapsulation of a clean microLED feature. Some embodiments provide improved crystallinity of the microLED feature and the capping layer. Some embodiments provide improved EQE of microLED devices formed from the disclosed microLED features. | 2022-08-11 |
20220254954 | LIGHT-EMITTING ELEMENT - A light-emitting element includes a first n-type contact layer, a light-emitting layer that is located on the first n-type contact layer and emits light at a wavelength of not less than 210 nm and not more than 365 nm, a p-type layer that includes Al | 2022-08-11 |
20220254955 | LIGHT EMITTING DIODE STRUCTURE - A light emitting diode structure includes a metal reflective layer, a first transparent electrically-conductive layer, a dielectric layer, second transparent electrically-conductive layers, a first type semiconductor layer, an active layer and a second type semiconductor layer. The metal reflective layer has first concave sections. The first transparent electrically-conductive layer is conformally formed over the first concave sections of the metal reflective layer. The dielectric layer is formed over the first transparent electrically-conductive layer and has through holes to expose the first transparent electrically-conductive layer. The second transparent electrically-conductive layers are formed over the dielectric layer, and connected with the first transparent electrically-conductive layer via the through holes. Each second transparent electrically-conductive layer is connected to the first transparent electrically-conductive layer to form a T-shaped cross section in each first concave section. | 2022-08-11 |
20220254956 | EPITAXIAL STRUCTURE, LIGHT EMITTING DEVICE, AND METHOD FOR EPITAXIAL STRUCTURE MANUFACTURE - An epitaxial structure, a light emitting device, and a method for epitaxial structure manufacture are provided. The epitaxial structure includes a buffer layer and a stress releasing layer that are sequentially formed on a substrate. The stress releasing layer includes a first stress releasing layer. The first stress releasing layer is made of aluminum gallium nitride (AlGaN) in which Al component accounts for 50%-90%. | 2022-08-11 |
20220254957 | Method for Manufacturing A Semiconductor Device and Optoelectronic Device - In an embodiment a method for manufacturing a semiconductor device include providing a growth substrate, depositing an n-doped first layer, depositing an active region on the n-doped first layer, depositing a second layer onto the active region, depositing magnesium (Mg) in the second layer and subsequently to depositing Mg, depositing zinc (Zn) in the second layer such that a concentration of Zn in the second layer decreases from a first value to a second value in a first area of the second layer adjacent to the active region, the first area being in a range of 5 nm to 200 nm. | 2022-08-11 |
20220254958 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device and a method of manufacturing the same are provided. The display device includes a first alignment electrode and a second alignment electrode spaced apart from each other, a light emitting element between the first alignment electrode and the second alignment electrode, a first auxiliary electrode at a first side of the light emitting element in a plan view, and separated from the first alignment electrode, and a second auxiliary electrode at a second side of the light emitting element in a plan view, and separated from the second alignment electrode, wherein an alignment signal is configured to be applied to the first alignment electrode, and wherein a first auxiliary signal of a phase that is different from a phase of the alignment signal is configured to be applied to the first auxiliary electrode. | 2022-08-11 |
20220254959 | LIGHT EMITTING ELEMENT, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE COMPRISING THE LIGHT EMITTING ELEMENT - A light emitting element having a shape extending in a direction includes a first semiconductor layer and a second semiconductor layer, an active layer between the first and second semiconductor layers, a first electrode layer on a second surface opposite to a first surface of the first semiconductor layer facing the active layer, a second electrode layer on a second surface opposite to a first surface of the second semiconductor layer facing the active layer, and an insulating film surrounding a side surface of the active layer, a side surface of the first electrode layer, and a side surface of the second electrode layer, wherein a first area including the insulating film adjacent to a side surface of the active layer has a thickness larger than a thickness of a second area including the insulating film adjacent to a side surface of the first electrode layer. | 2022-08-11 |
20220254960 | LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE - A light emitting element includes a support substrate, and first and second light emitting portions. Each of the first light emitting portion and the second light emitting portion includes a semiconductor layered body, an insulating film, first and second electrodes and first and second external connection portions. The first external connection portion provided in the first light emitting portion includes a first portion provided adjacent to the second external connection portion of the first light emitting portion in a first direction and provided adjacent to the first external connection portion of the second light emitting portion in a second direction, and the first portion has an inclined portion inclined with respect to one side of the semiconductor layered body on a side facing the first external connection portion provided in the second light emitting portion in the second direction. | 2022-08-11 |
20220254961 | DISPLAY DEVICE USING MICRO LED, AND MANUFACTURING METHOD THEREFOR - Provided in the present specification is a novel structured semiconductor light-emitting element capable of preventing an electrode forming failure due to an arrangement error occurring during assembly or transfer of semiconductor light-emitting elements on a substrate, when a display device is implemented using the semiconductor light-emitting elements, wherein at least one of a plurality of semiconductor light-emitting elements according to one embodiment of the present disclosure comprises: a first conductive type semiconductor layer; a second conductive type semiconductor layer located on the first conductive type semiconductor layer; an active layer arranged between the first conductive type semiconductor layer and the second conductive type semiconductor layer; a second conductive type electrode located on the second conductive type semiconductor layer; and a first conductive type electrode located on at least a one-side stepped portion of the first conductive type semiconductor layer exposed by etching a portion of the second conductive type semiconductor layer and the active layer. | 2022-08-11 |
20220254962 | OPTICAL ARRANGEMENTS IN COVER STRUCTURES FOR LIGHT EMITTING DIODE PACKAGES AND RELATED METHODS - Optical arrangements in cover structures for packaged light-emitting diode (LED) devices are disclosed. LED packages may include a cover structure arranged over one or more LED chips. The cover structure may include arrangements of one or more sublayers or regions configured with different optical arrangements for tailoring emission characteristics for the LED package. The one or more sublayers or regions may include one or more arrangements of optical materials, including lumiphoric materials, materials with different indexes of refraction, light-scattering materials, and light-diffusing materials individually or in various combinations with one another to provide one or more of improved light output, increased light extraction, improved emission uniformity, and improved emission contrast for the LED package. Related methods include providing individual sheets of precursor materials that include different optical arrangements and firing the sheets together to form cover structures. | 2022-08-11 |
20220254963 | CHIP-ON-BOARD TYPE PHOTOELECTRIC DEVICE - A COB type photoelectric device is provided. The COB type photoelectric device includes: a metallic substrate including a photoelectric element fixing area; a dam disposed on the metallic substrate and surrounding the photoelectric element fixing area; first photoelectric elements disposed on the metallic substrate and in the photoelectric element fixing area; a KSF phosphor based layer disposed on the first photoelectric elements and being not in contact with the metallic substrate; and an isolation layer disposed in the dam and covering the KSF phosphor based layer. The KSF phosphor based layer includes a KSF phosphor. The COB type photoelectric device can make full use of high luminous efficiency performance of the KSF, and improve luminous efficiency of the COB type photoelectric device while maintaining stability of the KSF. | 2022-08-11 |
20220254964 | LIGHT SOURCE APPARATUS AND PROJECTOR - A light source apparatus includes a light source, a wavelength conversion layer, a substrate, a first optical member having a first optical layer that transmits first light and reflects second light, second and third optical members having second and third optical layers that reflect the first light and the second light and intersect with the first optical layer, and a fourth optical layer reflects the first light and transmits the second light. The first optical member includes a fifth optical layer that transmits the first light polarized is a first direction. The first optical layer reflects part of the first light emitted from the wavelength conversion layer. First area of a light incident surface of the wavelength conversion layer is greater than second area of a light incident region of the light incident surface. The second area of the light incident region is greater than third area of an aperture. | 2022-08-11 |
20220254965 | SEMICONDUCTOR COMPONENT WITH RADIATION CONVERSION ELEMENT, AND METHOD FOR PRODUCING RADIATION CONVERSION ELEMENTS - The invention relates to a semiconductor component with a semiconductor chip and a radiation conversion element which is arranged on the semiconductor chip. The semiconductor chip has an active region which is designed to generate a primary radiation with a peak wavelength, the radiation conversion element has a quantum structure, the peak wavelength of the primary radiation lies in the infrared spectral range, and the quantum structure at least partly converts the primary radiation into a secondary radiation, wherein the emission wavelength of an emission maximum of the secondary radiation is greater than the peak wavelength. The invention additionally relates to a method for producing radiation conversion elements. | 2022-08-11 |
20220254966 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING SAME - A light emitting device including a fluorescent material with reduced hue, and a method of manufacturing the light emitting device are provided. | 2022-08-11 |
20220254967 | COLOR UNIFORMITY IN CONVERTED LIGHT EMITTING DIODE USING NANO-STRUCTURES - A nano-structure layer is disclosed. The nano-structure layer includes an array of nano-structure material configured to receive a first light beam at a first angle of incidence and to emit the first light beam at a second angle greater than the first angle, the nano-structure material each having a largest dimension of less than 1000 nm. | 2022-08-11 |
20220254968 | ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - An electronic device, including an active device substrate, an insulation film, a vertical wire, and an anisotropic conductive adhesive, is provided. The active device substrate includes a substrate, a first wire, and a second wire. The first wire is configured on a first surface of the substrate, the second wire is configured on a second surface of the substrate, and a side surface connects the first surface to the second surface that is opposite to the first surface. The insulation film is configured on the side surface of the substrate. The vertical wire is configured on a surface of the insulation film and is located between the insulation film and the side surface of the substrate. The anisotropic conductive adhesive is configured between the vertical wire and the side surface of the substrate and electrically connects the vertical wire to the first wire and the second wire. | 2022-08-11 |
20220254969 | Light-emitting Chip and Light-emitting Substrate - A light-emitting chip and a light-emitting substrate are provided. The light-emitting chip includes a base substrate and at least two sub-light-emitting chips disposed on a side of the base substrate, wherein each sub-light-emitting chip includes a first semiconductor layer, a second semiconductor layer and an light-emitting layer located between the first semiconductor layer and the second semiconductor layer which are stacked. | 2022-08-11 |
20220254970 | DISPLAY DEVICE - A display device includes a first electrode and a second electrode disposed on a substrate, the first and second electrodes extending in a first direction in parallel to each other, a first insulating layer disposed on the first and second electrodes, light-emitting elements disposed on the first insulating layer, the light-emitting elements including first end portions disposed on the first electrode and second end portions disposed on the second electrode, an oxide semiconductor layer disposed on the first insulating layer and the light-emitting elements, the oxide semiconductor layer including a first conductive portion electrically contacting the first end portions of the light-emitting elements, a second conductive portion electrically contacting the second end portions of the light-emitting elements, and a semiconductive portions disposed between the first and second conductive portions, and a second insulating layer disposed on the oxide semiconductor layer. | 2022-08-11 |
20220254971 | INORGANIC ULTRAVIOLET LED DEVICE AND PREPARATION METHOD - An inorganic ultraviolet LED device, includes a bracket, a curved lens, a press ring, a wire and an ultraviolet chip. A “T”-shaped recess is formed on the upper end of the bracket. The ultraviolet chip is fixed within the recess and connected to a welding layer at the lower end of the bracket through the wire. The curved lens is placed on a step of the recess. An inclined surface is formed on a contact surface of the step contacting with the curved lens. One end of the press ring is connected to the bracket, and the other end thereof presses against the curved lens. Deformation of the press ring is implemented under a pressure action of a pressure head, thereby implementing high-strength bonding of the device. Self-positioning is achieved through a curved surface of the lens and the contact with the inclined surface of the bracket. | 2022-08-11 |
20220254972 | DRIVING SUBSTRATE, MANUFACTURTION METHOD THEREOF AND DISPLAY DEVICE - The present disclosure provides a driving substrate, including: a flexible substrate including a display region and a bendable region; a first conductive layer on the flexible substrate and including a first wire in the display region, and a connection wire at least partially in the bendable region; a flexible insulating layer including a first insulation pattern in the display region, and a second insulation pattern in the bendable region; a second conductive layer at a side of the flexible insulating layer far away from the flexible substrate; and a planarization layer at a side of the second conductive layer far away from the flexible substrate and having a hollow structure in the bendable region, wherein a thickness of a portion of the second insulating pattern covering the connection wire is d | 2022-08-11 |
20220254973 | LIGHT EMITTING ELEMENT PACKAGE, DISPLAY DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICE - A light emitting element package includes a first substrate, at least one light emitting element, an encapsulation layer, and a plurality of conductive pads. The first substrate has an upper surface and a lower surface opposite to each other, in which an edge of the lower surface has a notch. The at least one light emitting element is disposed on the upper surface of the first substrate, in which the light emitting element has a positive electrode and a negative electrode. The encapsulation layer covers the light emitting element. The plurality of conductive pads are disposed on the lower surface of the first substrate and electrically connected to the positive electrode and the negative electrode of the light emitting element, respectively. | 2022-08-11 |
20220254974 | BONDING INTERFACE FOR HYBRID TFT-BASED MICRO DISPLAY PROJECTOR - For small, high-resolution, light-emitting diode (LED) displays, such as for a near-eye display in an artificial-reality headset, LEDs are spaced closely together. A backplane can be used to drive an array of LEDs in an LED display. A plurality of interconnects electrically couple the backplane with the array of LEDs. The backplane can have a different coefficient of thermal expansion (CTE) than the array of LEDs. During bonding of the backplane to the array of LEDs, CTE mismatch can cause misalignment of bonding sites. The higher the bonding temperature, the greater the misalignment of bonding sites. Lower temperature bonding, using materials with lower melting or bonding temperatures, can be used to mitigate misalignment during bonding so that interconnects can be more closely spaced, which can allow LEDs to be more closely spaced, to enable a higher-resolution display. | 2022-08-11 |
20220254975 | SEMICONDUCTOR STRUCTURE AND SUBSTRATE THEREOF, AND MANUFACTURING METHODS FOR SEMICONDUCTOR STRUCTURES AND SUBSTRATES THEREOF - The present disclosure provides a semiconductor structure and substrate thereof, and manufacturing methods for semiconductor structure and substrate thereof. In the method for manufacturing the substrate, at least one of groove is provided in each subunit region on a surface of a premanufactured substrate, and the premanufactured substrate includes at least one unit region, each of the at least one unit region includes at least two subunit regions, the at least one of groove is filled with heat conduction materials to form a substrate; in one of the at least one unit region, the at least two subunit regions respectively have different heat conduction coefficients. | 2022-08-11 |
20220254976 | BISMUTH TELLURIDE-BASED THERMOELECTRIC NANOCOMPOSITES WITH DISPERSED NANO-SIZED SILICON CARBIDE BASED ON THE RECYCLING OF BISMUTH TELLURIDE PROCESSING SCRAPS AND PREPARATION METHOD THEREOF - Disclosed are a bismuth telluride-based thermoelectric nanocomposite with dispersed nano-sized silicon carbide based on the recycling of bismuth telluride processing scraps, wherein the method comprises: (1) Under a protective atmosphere, mixing bismuth telluride processing scraps and nano-sized silicon carbide, and then performing ball milling; (2) Subjecting the ball-milled powders to spark plasma sintering to obtain a bismuth telluride-based thermoelectric nanocomposite with dispersed nano-sized silicon carbide. The method can significantly improve the utilization rate of bismuth telluride processing scraps and avoid the waste of precious materials. Moreover, the process has the characteristics of simple and easy operation, and low energy consumption. The obtained bismuth telluride-based thermoelectric nanocomposite with dispersed nano-sized silicon carbide has high thermoelectric performance, which can be widely used in the fields of thermoelectric power generation and refrigeration. | 2022-08-11 |
20220254977 | PARABOLIC TROUGH SOLAR GENERATION WITH UNDERGROUND COOLING - A system, a thermoelectric generator, and a method for generating electricity are provided. The system includes a thermoelectric generator, a cooling system, and a heating system. The cooling system includes a cold side module configured to hold a predetermined volume of air, a subterranean heat exchanger including an underground conduit, the underground conduit having a first end configured to receive ambient air and a second end coupled to the inlet of the cold side module, and an air exhaust coupled to the outlet of the cold side module and having one or more valves configured to control an airflow from the subterranean heat exchanger towards the air exhaust. The heating system includes a first solar concentrator to collect light rays, a hot side module, and a fiber optic cable to transport the collected light rays to the hot side module. | 2022-08-11 |
20220254978 | THERMOELECTRIC GENERATOR MODULE - A thermoelectric generator module includes a first base material that is formed into a sheet and that has a thermoplastic layer, a second base material that is formed into a sheet and that has a thermoplastic layer, a plurality of thermoelectric conversion elements arranged between the first base material and the second base material, a plurality of first electrodes arranged between the first base material and the thermoelectric conversion elements, a plurality of second electrodes arranged between the second base material and the thermoelectric conversion elements, and a joint that joins the first base material to the second base material. The thermoelectric conversion elements, the plurality of first electrodes, and the plurality of second electrodes are sealed by the joint. | 2022-08-11 |
20220254979 | HEAT GENERATOR - A thermoelectric generation device includes a first thermoelectric generation module having at least one heat utilization power generation element and a first housing that accommodates the heat utilization power generation element, a second thermoelectric generation module having at least one heat utilization power generation element and a second housing that accommodates the heat utilization power generation element, and an electroconductive member electrically connecting the first and second thermoelectric generation modules, wherein an outer surface of the first housing is in contact with an outer surface of the second housing. The heat utilization power generation element includes at least an electrolyte layer and a thermoelectric conversion layer. | 2022-08-11 |
20220254980 | DRIVER CIRCUITRY - Circuitry for driving a transducer for an object detection system, the circuitry comprising drive circuitry configured to generate a drive waveform for the transducer, current monitor circuitry for monitoring a current through the transducer, and system identification circuitry. The system identification circuitry is configured to determine a characteristic of the transducer based on a first signal indicative of a drive voltage for the transducer and a second signal indicative of the current through the transducer. The circuitry is operative to adjust the drive waveform based on the determined characteristic of the transducer. | 2022-08-11 |
20220254981 | PIEZOELECTRIC ACTUATOR - A piezoelectric actuator includes a piezoelectric element, and a case accommodating the piezoelectric element. The case is deformable to conform with expansion or contraction of the piezoelectric element. The case includes a cylinder including a first end portion being open, and a first cap including a first end plate being circular and a first protrusion being annular. The first protrusion is located on a first surface of the first end plate and protrudes perpendicularly to the first surface. The cylinder includes the first end portion receiving the first protrusion on the first cap. The first end portion includes an inner peripheral surface joined to an outer peripheral surface of the first protrusion. The first end portion includes an edge located nearer an edge of the first protrusion than the first surface of the first end plate in an axial direction of the cylinder. | 2022-08-11 |
20220254982 | TECHNOLOGIES FOR MICROELECTROMECHANICAL SYSTEMS WITH COMPOSABLE PIEZOELECTRIC ACTUATORS - In at least one illustrative embodiment, a microelectromechanical system (MEMS) includes a composable piezoelectric actuator electrically coupled to a terminal. In response to a voltage applied across electrodes of the actuator, a piezoelectric rod moves from an initial position to a displaced position. In an embodiment, the MEMS includes two terminals, a resistive element is coupled between the terminals, and when in the displaced position the rod contacts one of the terminals. In an embodiment, the MEMS includes three terminals, and when a threshold voltage is applied to one of the terminals, the rod moves to the displaced position and allows current to flow between the other two terminals. In an embodiment, the MEMS includes a primary set of actuators that are mechanically but not electrically connected to a secondary set of actuators. An output terminal is coupled to the second set of actuators. Other embodiments are described and claimed. | 2022-08-11 |
20220254983 | ULTRASONIC ACTUATOR, AND MOTOR HAVING SUCH AN ULTRASONIC ACTUATOR - The disclosure relates to an ultrasonic actuator formed of a plate having a base, a cover surface which is geometrically similar to the base, and a lateral surface which interconnects the base and the cover surface, wherein the plate includes an electromagnetic material. Electrodes for inciting periodic deformations of the plate are arranged on the base of the plate and on the cover surface of the plate opposite the base. The base includes at least two faces which are arranged in parallel with one another and form contact portions of the lateral surface, and the two faces of the base arranged in parallel with one another, together with connecting lines which interconnect the respective end points of the faces arranged in parallel, form a parallelogram inscribed in the base, in which parallelogram an angle different from 90° is enclosed between adjacent faces. A motor having such an ultrasonic actuator is also disclosed. | 2022-08-11 |
20220254984 | Multi-Element Piezo Sensors for Physiological Measurements - Disclosed herein are monitoring systems and sensors for physiological measurements. The sensors can be multi-element piezo sensors capable of generating multiple electrical signals, whereby the monitoring systems can receive the multiple electrical signals to analyze the user's vital signs along multiple regions of the user's body. In some examples, the piezo sensor can include one or more corrugations, such as peaks and valleys, to create localized regions with increased mechanical response to force. The sensitivity and resolution of the piezo sensor can be enhanced by further locating electrode sections at the corrugations, where the electrode sections can be electrically isolated and independently operable from other electrode sections. Traces electrically connecting an electrode section to, e.g., an off-panel controller can be routed over and/or around other electrode sections by including an insulator to electrically insulate from the other electrode sections, or by using vias to route through one or more layers. | 2022-08-11 |
20220254985 | 3D-Printed Ferroelectric Metamaterial with Giant Piezoelectricity and Biomimetic Mechanical Toughness - An in-situ poled ferroelectric prints with true 3D geometry is provided with an intercalated electrode design where soft polymer matrixes are selected for the ferroelectric layers, and rigid polymer matrixes are selected for the electrode layers, thus mimicking nacre architecture with a ceramic-like piezoelectric property and bone-like fracture toughness. Lithium-doped potassium sodium niobite (Li-KNN) microparticles may be used to produce ferroelectric properties and to create strong interfacial bonding with the interfacing electrode layers. Polylactic acid (PLA) in the electrode layers may be used to facilitate strong interfacial bonding with the Li-KNN microparticles. | 2022-08-11 |
20220254986 | NOVEL PIEZOELECTRIC COMPOSITION AND FILMS WITH HIGH D33 VALUES AND IMPROVED ADHESION AND FLEXIBILITY - Disclosed are piezoelectric compositions and films with high D33 values and improved surface smoothness, scratch resistance and/or adhesion. The compositions and films can have a combination of benefits over the prior art compositions and films by having two different polymers (i.e., EVA and PVDF-TrFE-CFE) blended into a polymer matrix, to which is added piezoelectric additives like PZT, BaTiO3, etc. at greater than 70-90 wt. % loading. Devices utilizing the compositions and films are also disclosed. Such devices can include sensors, transducers, actuators, or wearable devices. | 2022-08-11 |
20220254987 | PIEZOELECTRIC FILM AND PIEZOELECTRIC ELEMENT - A piezoelectric film contains iron-containing potassium sodium niobate represented by General Formula (1) and granular crystal particles having an average aspect ratio of 3 or less. | 2022-08-11 |
20220254988 | PIEZOELECTRIC FILM, PIEZOELECTRIC LAYERED BODY, PIEZOELECTRIC ELEMENT, AND METHOD FOR MANUFACTURING PIEZOELECTRIC LAYERED BODY - A piezoelectric stack including: a substrate; an electrode film; and a piezoelectric film as a poly-crystal film comprising an alkali niobium oxide of a perovskite structure represented by a composition formula of (K | 2022-08-11 |
20220254989 | PIEZOELECTRIC POLYMERS WITH HIGH POLYDISPERSITY - A piezoelectric polymer article may be characterized by a Young's modulus of 5 GPa or greater along at least one dimension thereof. The piezoelectric polymer article may include polyvinylidene fluoride, for example, and may have a polydispersity index of at least 2. A piezoelectric coefficient of the polymer article, which may be a thin film or fiber, may be at least 20 pC/N. | 2022-08-11 |
20220254990 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device includes a substrate including a first region and a second region, data storage patterns on the first region and spaced apart from each other in a first direction, an upper insulating layer on the first and second regions and on the data storage patterns , a cell line structure penetrating the upper insulating layer on the first region, extending in the first direction, and electrically connected to the data storage patterns, and an upper connection structure penetrating the upper insulating layer on the second region. The upper connection structure includes an upper conductive line, and upper conductive contacts arranged along a bottom surface of the upper conductive line. The bottom surface of the upper conductive line is located at a height higher than a bottom surface of the cell line structure. A side surface of the cell line structure has a straight line shape continuously-extended. | 2022-08-11 |
20220254991 | MAGNETIC MEMORY USING SPIN-ORBIT TORQUE - Spin-orbit-torque (SOT) segments are provided along the sides of free layers in magnetoresistive devices that include magnetic tunnel junctions. Current flowing through such SOT segments injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used as an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction in order to improve the efficiency of the switching current applied to the magnetoresistive device. | 2022-08-11 |
20220254992 | MAGNETIC DEVICE - A magnetic device includes a stacked body including a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer sandwiched between the first ferromagnetic layer and the second ferromagnetic layer; a first insulating layer which covers side surfaces of the stacked body; and a radiator located outside the first insulating layer with respect to the stacked body, in which a distance between the stacked body and the radiator differs depending on a position of the stacked body in a stacking direction. | 2022-08-11 |
20220254993 | MAGNETIC RANDOM-ACCESS MEMORY CELL, MEMORY AND DEVICE - The present disclosure provides a magnetic random-access memory cell, a memory and a device. The magnetic random-access memory cell comprises: a spin-orbit coupling layer and a first magnetic tunnel junction and a second magnetic tunnel junction disposed on the spin-orbit coupling layer, the first magnetic tunnel junction and the second magnetic tunnel junction having at least two symmetrical axes with different lengths; an angle between an easy magnetization symmetrical axis direction of a free layer of the first magnetic tunnel junction and a length direction of the spin-orbit coupling layer is a preset first angle, and an angle between an easy magnetization symmetrical axis direction of a free layer of the second magnetic tunnel junction and the length direction of the spin-orbit coupling layer is a preset second angle; neither of the first angle and the second angle is zero degree, 90 degrees or 180 degrees. | 2022-08-11 |
20220254994 | MAGNETIC MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a magnetic memory device comprises forming, on a substrate, a data storage structure including a bottom electrode, a magnetic tunnel junction pattern, and a top electrode, forming a first capping dielectric layer conformally covering lateral and top surfaces of the data storage structure, and forming a second capping dielectric layer on the first capping dielectric layer. The forming the first capping dielectric layer is performed by PECVD in which a first source gas, a first reaction gas, and a first purging gas are supplied. The forming the second capping dielectric layer Is performed by PECVD in which a second source gas, a second reaction gas, and a second purging gas are supplied. The first and second reaction gases are different from each other. The first and second purging gases are different from each other. | 2022-08-11 |
20220254995 | EMBEDDED HEATER IN A PHASE CHANGE MEMORY MATERIAL - A phase change memory cell for a semiconductor device that includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom portion of the spacer surrounding the heater element and a second dielectric layer on the first dielectric layer surrounding a top portion of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on the second dielectric material. | 2022-08-11 |
20220254996 | RESISTIVE RANDOM-ACCESS MEMORY CELL AND MANUFACTURING METHOD THEREOF - An resistive random-access memory (RRAM) device including an first crystalline semiconductor layer disposed adjacent to a crystalline semiconductor substrate, a crystal lattice edge-dislocation segment disposed at an interface of the first crystalline semiconductor layer and crystalline semiconductor substrate, the lattice edge-dislocation segment including first and second segment ends, a first ion-source electrode disposed upon the electrically isolating spacer, adjacent to the crystalline substrate and first crystalline semiconductor layer, and further disposed in contact with the first segment end of the lattice edge-dislocation segment, and a second electrode disposed upon the electrically isolating spacer, adjacent to the crystalline substrate and first crystalline semiconductor layer, and further disposed in contact with the second segment end of the lattice edge-dislocation segment. | 2022-08-11 |
20220254997 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device may include a first electrode, a second electrode, an insulating layer interposed between the first electrode and the second electrode and including an opening having an inclined sidewall, a variable resistance layer formed in the opening, and a liner interposed between the variable resistance layer and the insulating layer and between the variable resistance layer and the first electrode. The variable resistance layer includes a first surface and a second surface, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area. The variable resistance layer maintains an amorphous state during a program operation. | 2022-08-11 |
20220254998 | CONDUCTIVE BRIDGE MEMORY DEVICE, MANUFACTURING METHOD THEREOF, AND SWITCHING DEVICE - A conductive bridge memory device includes a memory cell including a first metal layer; a second metal layer; a first insulator layer having a first surface facing the first metal layer and a second surface facing the second metal layer and being a surface opposite to the first surface, and having a through hole penetrating between the first surface and the second surface; and a liquid layer being formed of liquid containing a liquid electrolyte impregnated in the through hole. | 2022-08-11 |
20220254999 | MEMORY DEVICE WITH INCREASED ELECTRODE RESISTANCE TO REDUCE TRANSIENT SELECTION CURRENT - A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell. | 2022-08-11 |
20220255000 | MEMORY CELL, METHOD OF FORMING THE SAME, AND SEMICONDUCTOR DEVICE HAVING THE SAME - Provided are a memory cell and a method of forming the same. The memory cell includes a bottom electrode, a top electrode, and a storage element layer. The storage element layer is disposed between the bottom and top electrodes. The storage element layer has a first inclined sidewall, the top electrode has a second inclined sidewall, and an angle of the first inclined sidewall is greater than an angle of the second inclined sidewall. A semiconductor device having the memory cell is also provided. | 2022-08-11 |
20220255001 | SELECTED-AREA DEPOSITION OF HIGHLY ALIGNED CARBON NANOTUBE FILMS USING CHEMICALLY AND TOPOGRAPHICALLY PATTERNED SUBSTRATES - Methods for forming films of aligned carbon nanotubes are provided. Also provided are the films formed by the methods and electronic devices that incorporate the films as active layers. The films are formed by flowing a suspension of carbon nanotubes over a substrate surface that is chemically and topographically patterned. The methods provide a rapid and scalable means of forming films of densely packed and aligned carbon nanotubes over large surface areas. | 2022-08-11 |
20220255002 | PROCESS FOR PRODUCING INVERTED POLYMER PHOTOVOLTAIC CELLS - A Process for producing an inverted polymer photovoltaic cell (or solar cell) includes the following steps
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20220255003 | LIGHT EMITTING ELEMENT AND AMINE COMPOUND FOR THE SAME - A light-emitting element includes a first electrode, a second electrode, and at least one functional layer disposed between the first electrode and the second electrode and including an amine compound represented by Formula 1. The light-emitting element may exhibit high emission efficiency and improved service life characteristics: | 2022-08-11 |