33rd week of 2009 patent applcation highlights part 18 |
Patent application number | Title | Published |
20090201020 | MAGNETIC RESONANCE APPARATUS UTILIZING TIME-VARYING RATE OF MAGNETIC RESONANT FREQUENCY - The present invention provides a magnetic resonance imaging system capable of performing spectrum measurement even when a magnetic resonant frequency changes during MRS measurement. A time-varying rate of a water magnetic resonant frequency is measured in advance before the MRS measurement. The amount of change in water magnetic resonant frequency during the MRS measurement is predicted from the measured time-varying rate. With the predicted value as the reference, a transmission frequency of an RF magnetic field irradiated in a signal suppression pulse sequence, a transmission frequency of an RF magnetic field for excitation and inversion and a received frequency at the detection of a magnetic resonance signal in a sequence of the MRS measurement are respectively set. A high-precision spectrum measurement is hence enabled. | 2009-08-13 |
20090201021 | PHASE CORRECTION METHOD - A method corrects for a phase error in an MR image, in which MR signals of an examination subject are acquired, complex images of the examination subject are generated, phase differences of the phase values for various image points of the complex images are established with an averaged phase value of image points from a first surrounding region of a respective image point, and a phase correction is executed dependent on how well the phase differences correspond to a predetermined phase value, where the order of the image points in which the phase correction is implemented is dependent on how well the phase values in the image points correspond to the predetermined phase value. | 2009-08-13 |
20090201022 | CONTROL APPARATUS FOR A MAGNETIC RESONANCE IMAGING ANTENNA ARRANGEMENT - An apparatus to control an antenna arrangement in a magnetic resonance apparatus has an amplifier with an input connected to a radio-frequency transmission signal to be amplified. The antenna arrangement has at least one antenna element for emission of the amplified transmission signal. The antenna element has an infeed point with two terminals, wherein the amplified transmission signal is connected at the terminals. The amplifier is connected on the output side with two terminals of the infeed point. The antenna element has at the infeed point, a mounting surface to accommodate the amplifier. | 2009-08-13 |
20090201023 | Pre-Amplifier and Mixer Circuitry for a Locator Antenna - A pre-amplifier circuit for connection to an antenna of a human-portable locator includes a differential amplifier/mixer pair and means for allowing a common-mode “phantom” signal to modulate a transfer function of the differential amplifier/mixer pair. The common-mode phantom signal modulates the transfer function of the differential pre-amplifier “onboard” the antenna without the usual requirement for onboard power supply and signal oscillator. This technique uses the same electronic components to provide both pre-amplification and mixing functions, thereby improving circuit performance-to-cost ratio, reducing mixer power consumption, situating the necessary signal oscillator remotely from the mixer, and greatly improving the available system bandwidth by limiting spectral transmission demands to the mixed signal bandwidth alone. | 2009-08-13 |
20090201024 | Ground Conductivity Meter with Automatic Calibration - A ground conductivity meter that includes a transmitter coil and a receiver coil that are horizontally spaced apart from each other, and a conductivity meter controller connected to the transmitter and receiver coils and including an electronic storage element and at least one processor, the conductivity meter controller being operative to: determine a first conductivity reading in dependence on signals from the receiver coil when the transmitter coil and receiver coil are positioned a predetermined distance above a ground surface in one of a vertical dipole orientation or a horizontal dipole orientation; determine a second conductivity reading in dependence on signals from the receiver coil when the transmitter coil and receiver coil are positioned the predetermined distance above the ground surface in the other of the vertical dipole orientation or horizontal dipole orientation; calculate a correction factor in dependence on the first and second conductivity readings and store the correction factor in the storage element; and determine a plurality of further conductivity readings in dependence on signals from the receiver coil during a site survey, and apply the stored correction factor to the further conductivity readings to produce corrected conductivity readings for the site survey. | 2009-08-13 |
20090201025 | Magnetization of Target Well Casing String Tubulars for Enhanced Passive Ranging - A method for magnetizing a wellbore tubular is disclosed. The method includes magnetizing a wellbore tubular at three or more discrete locations on the tubular. In exemplary embodiments the magnetized wellbore tubular includes at least one pair of opposing magnetic poles located between longitudinally opposed ends of the tubular. Wellbore tubulars magnetized in accordance with this invention may be coupled to one another to provide a magnetic profile about a section of a casing string. Passive ranging measurements of the magnetic field about the casing string may be utilized to survey and guide drilling of a twin well. Such an approach advantageously obviates the need for simultaneous access to both wells. | 2009-08-13 |
20090201026 | Method of Magnetizing Casing String Tubulars for Enhanced Passive Ranging - A method for magnetizing a wellbore tubular includes magnetizing the tubular at three or more discrete locations on the tubular. In exemplary embodiments the magnetized wellbore tubular includes at least one pair of opposing magnetic poles located between longitudinally opposed ends of the tubular. Wellbore tubulars magnetized in accordance with this invention may be coupled to one another to provide a magnetic profile about a section of a casing string. Passive ranging measurements of the magnetic field about the casing string may be utilized to survey and guide drilling of a twin well. Such an approach advantageously obviates the need for simultaneous access to both wells. | 2009-08-13 |
20090201027 | ELECTRICAL SAFETY DEVICES AND SYSTEMS FOR USE WITH ELECTRICAL WIRING, AND METHODS FOR USING SAME - Disclosed are systems and methods for monitoring an electrical wire. An appropriate safety device is utilized to monitor the electrical wire. The safety device includes a line side input configured to connect a line side power source and receive an electrical power signal from the line side power source. Additionally, the safety device includes a wire connection configured to connect to an electrical wire. The safety device further includes at least one relay or other suitable disconnection component configured to control the communication of the electrical power signal onto the electrical wire. The safety device also includes a control unit configured to test the electrical wire for at least one of miswires, wire faults, or abnormal conditions and, based at least in part on the results of the testing, to control the actuation of the at least one relay. | 2009-08-13 |
20090201028 | EVALUATION METHOD OF INSULATING FILM AND MEASUREMENT CIRCUIT THEREOF - Provided is a method of evaluating dielectric breakdown by applying a current to an insulating film, in which measurement for a forward direction current and measurement for a backward direction current are performed in a short period of time. For this purpose two MOS diodes in which an electrode of one MOS diode and a base of another MOS diode are short-circuited respectively are prepared to form a circuit to which the current is applied, providing current flow in one insulating film reverse to current flow in another insulating film, which enables the application of both the forward direction current and the backward direction current. | 2009-08-13 |
20090201029 | Electronic component device testing apparatus - An electronic component device testing apparatus includes first contacts arrayed so that first ends of the first contacts positionally correspond to electrode pads arrayed on a surface of an electronic component device; base electrodes in contact with second ends of the first contacts; and one or more second contacts each being in contact with one of the first contacts at a position which is between the first end and the second end of the one of the first contacts and closer to the first end of the one of the first contacts. | 2009-08-13 |
20090201030 | Method and apparatus for inspecting an object using terahertz electromagnetic wave - An inspection apparatus including a transmission line for propagating an electromagnetic wave; an electromagnetic wave supply unit for supplying a terahertz wave to the transmission line; an electromagnetic wave detection unit for detecting the terahertz wave from the transmission line; a conductive region; an inspection object supply unit; and a deposition unit. The conductive region is arranged at a site including at least a part of the range to which an electric field distribution of the electromagnetic wave propagating through the transmission line extends. The inspection object supply unit holds and supplies the inspection object to the outside, and the deposition unit deposits the inspection object selectively on the conductive region by electrostatic force. The electromagnetic wave supplied from the electromagnetic wave supply unit and propagated through the transmission line is detected by the electromagnetic wave detection unit to obtain information on the inspection object. | 2009-08-13 |
20090201031 | CAPACITANCE TYPE SENSOR - A capacitance type sensor good in operability and less in erroneous operation is provided. Switches SW | 2009-08-13 |
20090201032 | SENSOR CIRCUITS - A circuit for operating an amperometric sensor having a reference electrode, a counter electrode and a work electrode. The circuit comprises an amplifier having a positive input and a negative input and an output. The positive input is coupled to a reference voltage source, and the negative input and the output are coupled together via a negative feedback loop. The circuit includes means for coupling the amperometric sensor into said negative feedback loop of the amplifier wherein, in a first configuration, the counter electrode is coupled to said output and the reference electrode is coupled to said negative input and, in a second configuration, the work electrode is coupled to said output and the reference electrode is coupled to said negative input. | 2009-08-13 |
20090201033 | METHODS FOR MEASUREMENT AND CHARACTERIZATION OF INTERFEROMETRIC MODULATORS - Various methods are described to characterize interferometric modulators or similar devices. Measured voltages across interferometric modulators may be used to characterize transition voltages of the interferometric modulators. Measured currents may be analyzed by integration of measured current to provide an indication of a dynamic response of the interferometric modulator. Frequency analysis may be used to provide an indication of a hysteresis window of the interferometric modulator or mechanical properties of the interferometric modulator. Capacitance may be determined through signal correlation, and spread-spectrum analysis may be used to minimize the effect of noise or interference on measurements of various interferometric modulator parameters. | 2009-08-13 |
20090201034 | METHODS FOR MEASUREMENT AND CHARACTERIZATION OF INTERFEROMETRIC MODULATORS - Various methods are described to characterize interferometric modulators or similar devices. Measured voltages across interferometric modulators may be used to characterize transition voltages of the interferometric modulators. Measured currents may be analyzed by integration of measured current to provide an indication of a dynamic response of the interferometric modulator. Frequency analysis may be used to provide an indication of a hysteresis window of the interferometric modulator or mechanical properties of the interferometric modulator. Capacitance may be determined through signal correlation, and spread-spectrum analysis may be used to minimize the effect of noise or interference on measurements of various interferometric modulator parameters. | 2009-08-13 |
20090201035 | Contactless detection cell with reduced detection channel cross-section - A contactless detection cell ( | 2009-08-13 |
20090201036 | Oil Monitoring System - An embodiment of the present invention provides for a sensing element comprising a non-conductive housing with three chambers for detecting oil conductivity, additive depletion and oxidation, and water contamination, respectively. Through the monitoring of an array of oil sensors, an early warning of oil degradation due to oxidation is provided. The monitoring system further detects excess soot, water and other contaminants in the oil. The oil sensor array and related monitoring system decrease the likelihood of catastrophic engine failure through the early detection and warning of a decrease in oil quality thereby reducing vehicle owner outlays for servicing and disposal fees while further aiding in the satisfaction of environmental protection regulations. | 2009-08-13 |
20090201037 | SYSTEM AND METHOD FOR AUTOMATICALLY DISCOVERING TOTAL TRANSISTOR RESISTANCE IN A HYBRID POWER OVER ETHERNET ARCHITECTURE - A system and method for automatically discovering total transistor resistance in a hybrid power over Ethernet (PoE) architecture. A critical factor for a PoE system is the total resistance of the power FET. Typical PoE systems consist of a single power FET that may be integrated with the controller or external to the controller. In a hybrid architecture the PoE system consists of both an internal power FET and an external power FET. The external power FET can be used to customize a design to meet a particular application or need. The total resistance in the hybrid architecture can be automatically determined using voltage and current measurements of the internal and external power FETs. | 2009-08-13 |
20090201038 | TEST HEAD FOR FUNCTIONAL WAFER LEVEL TESTING, SYSTEM AND METHOD THEREFOR - A test head, system and method allowing functional wafer level testing of a test wafer, a die under test or a wafer under test, including at least one chip. The test head includes a semiconductor wafer and a series of protrusions in the semiconductor wafer. Each protrusion of the series of protrusions includes an electrical interconnection on a bottom surface of the semiconductor wafer, and a corresponding probe tip protruding from a top surface of the semiconductor wafer for establishing an electrical connection with a solder bump of the test wafer. The series of protrusion probe tips includes a pitch range of about 1 μm to about 100 μm. | 2009-08-13 |
20090201039 | PROBING SYSTEM FOR INTEGRATED CIRCUIT DEVICE - A probing system for integrated circuit device, which transmits testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system comprising a test head having a first transceiving module; a test station having a test unit couple to the test head to perform test operation; a communication module having a second transceiving module configured to exchange data with the first transceiving module; an integrated circuit device having at least one core circuit being tested; and at least one test module having a self-test circuit couple to the core circuit and the communication module for performing the core circuit self-testing. | 2009-08-13 |
20090201040 | COMPONENT TEST APPARATUS - A component test apparatus performing a test on an electronic component is disclosed. The component test apparatus includes a component loading device, a transport hand, and a component unloading device. The transport hand includes a plurality of index units each one of which is capable of holding the electronic component and operating independently from the other ones of the index units. The index units are aligned adjacently in a transport direction of the electronic component extending from a loading position at which the component loading device loads the electronic component toward a test position at which a test socket is provided. | 2009-08-13 |
20090201041 | Vertical Probe Array Arranged to Provide Space Transformation - Improved probing of closely spaced contact pads is provided by an array of vertical probes having all of the probe tips aligned along a single contact line, while the probe bases are arranged in an array having two or more rows parallel to the contact line. With this arrangement of probes, the probe base thickness can be made greater than the contact pad spacing along the contact line, thereby advantageously increasing the lateral stiffness of the probes. The probe tip thickness is less than the contact pad spacing, so probes suitable for practicing the invention have a wide base section and a narrow tip section. | 2009-08-13 |
20090201042 | THIN FILM TRANSISTOR ARRAY HAVING TEST CIRCUITRY - A thin film transistor (TFT) array having test circuitry includes a thin film transistor array body having a plurality of pixels. Test circuitry is integrally formed with the body. The test circuitry includes a power supply for supplying power via the test circuitry to the body; and a plurality of wireless switches to activate selected pixels. | 2009-08-13 |
20090201043 | Crack Sensors for Semiconductor Devices - Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimeter of an integrated circuit. The conductive structure is formed in at least one conductive material layer of the integrated circuit. The conductive structure includes a first end and a second end. A first terminal is coupled to the first end of the conductive structure, and a second terminal is coupled to the second end of the conductive structure. | 2009-08-13 |
20090201044 | LOGIC PERFORMANCE IN CYCLIC STRUCTURES - Apparatus, systems, and methods may operate to identify state holding elements and functional logic elements in an original cyclic structure, and to insert additional state holding elements or initial tokens in series with the identified functional logic elements to create a modified cyclic structure, wherein the additional state holding elements or initial tokens have substantially identical functionality to the original state holding elements. Other activities may include coupling additional functional logic elements to output nodes of the modified cyclic structure, wherein the additional functional logic elements have substantially identical functionality to the original functional logic elements. Additional apparatus, systems, and methods are disclosed. | 2009-08-13 |
20090201045 | INPUT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT COMPRISING THE INPUT CIRCUIT - A control signal input circuit for supplying control signals to a plurality of controlled circuits comprises N pieces of control signal preservation/output circuits provided one by one corresponding to plural-bit signals for delivering input data as it is when a trigger signal is at a first level, and holding previously delivered output data when the trigger signal is at a second level, and a controlled circuit selector circuit for setting the trigger signal for S pieces of the control signal preservation/output circuits to the first level, and setting the trigger signal for the rest of the control signal preservation/output circuits to the second level. | 2009-08-13 |
20090201046 | OUTPUT BUFFER AND METHOD HAVING A SUPPLY VOLTAGE INSENSITIVE SLEW RATE - An output buffer includes a final driver formed by first and second MOSFET transistors that alternately couple an output terminal to respective supply voltages. The output terminal is biased to a bias voltage intermediate the supply voltages. The slew rate at which the MOSFET transistors transition the output terminal to the supply voltages is affected by the magnitude of at least one of the supply voltages. The output buffer is driven by a pre-driver coupling first and second control signals to the first and second MOSFET transistors, respectively. The pre-driver adjusts the delay between generating one of the control signals to turn off the MOSFET transistor and generating the other of the control signals to turn on the other MOSFET transistor as a function of the supply voltage magnitude to make the slew rate of the resulting transition substantially insensitive to variations in power supply voltage. | 2009-08-13 |
20090201047 | Output Impedance Calibration Circuit with Multiple Output Driver Models - A method and circuitry for calibration of the output impedance of output driver circuits in an integrated circuit is disclosed. The output drivers within an area on the integrated circuit are defined as a group, and an output model indicative of the operation of the output drivers and used to calibrate their output impedances is provided proximate to the output drivers. A state machine is used to query each output model, and to set the proper output enable signals for the enable transistors in the output drivers in each group so as to calibrate their output impedances. By decentralizing the output models, the process used to form the output models will, due to proximity to the output drivers in each group, be indicative of the process used to form the output drivers. Thus, when each group of output drivers is calibrated, the output models used for each will compensate for process variations as may occur across the surface of the integrated circuit. Each group of output drivers is thus separately calibrated, with the result that the output impedances are made more uniform across the various output drivers despite process variations. | 2009-08-13 |
20090201048 | REDUCING ERRORS IN DATA BY DYNAMICALLY CALIBRATING TRIGGER POINT THRESHOLDS - Methods, systems, computer readable media and means for reducing errors in data caused by noise are provided. In some embodiments of the present invention, circuitry of the device receives timing data from one or more other circuitries and identifies noiseless periods from the timing data. The circuitry then actively adjusts the trigger point threshold of data being transmitted to and/or from the circuitry only during the noiseless periods. The circuitry subsequently monitors the timing data to identify noise periods. In response to identifying a noise period, the device ceases to adjust the trigger point threshold until the noise period is over. | 2009-08-13 |
20090201049 | INTEGRATED CIRCUIT WITH INPUT AND/OR OUTPUT BOLTON PADS WITH INTEGRATED LOGIC - An input and/or output pad (P) is dedicated to an integrated circuit comprising a core with input and/or output pins. This pad (P) comprises a pad cell (PC) comprising a pad block (PB) connected to an input buffer (IB | 2009-08-13 |
20090201050 | FAULT DETECTION AND ISOLATION OF REDUNDANT SIGNALS - A method of detecting signal faults comprises sampling at least three redundant signals; calculating a difference signal for each unique pair-wise comparison of the at least three sampled redundant signals; comparing each difference signal to an expected distribution for the difference signals; and determining if one of the at least three redundant signals is faulty based on the comparison of each difference signal to the expected distribution. | 2009-08-13 |
20090201051 | Sample-and-Hold Circuit and Pipeline Ad Converter Using Same - A switched capacitor sample-and-hold circuit using a source grounded input operational amplifier, wherein a feed forward circuit or a feedback circuit is provided in the operational amplifier and connected to the feedback capacitor of the operational amplifier via switches, an input common voltage or a middle point voltage of outputs is detected, and a difference of the same from a reference voltage is previously charged in the feedback capacitor, thereby suppressing fluctuation of an output operation point at the time of amplification of the operational amplifier. | 2009-08-13 |
20090201052 | LOW VOLTAGE, HIGH-SPEED OUTPUT-STAGE FOR LASER OR MODULATOR DRIVING - The present invention provides a driving circuit ( | 2009-08-13 |
20090201053 | LAYOUT STRUCTURE OF SOURCE DRIVER AND METHOD THEREOF - A layout structure of a source driver having a plurality of driving channels, and a method thereof are provided herein. The layout structure of the source driver includes a plurality of pads and a plurality of routings. The pads are used for making electric contact between the source driver and an external circuit. The routings are respectively coupled between the driving channels and the pads for transmitting the signal. Besides, the routings respectively includes a plurality of resistance units, and each of the resistance units is used for adjusting the resistance of the respective routing so as to minimize a variation of the driving ability between the pads. | 2009-08-13 |
20090201054 | DRIVING CIRCUITS IN ELECTRONIC DEVICE - In driving circuits, signal enhancing circuits are used to enhance driving ability of driving signals. Further, source follower transistors may further enhance driving ability of the driving circuits by conducting more current to loading, so that output signals of the driving circuits may transit more rapidly. In other words, the pull high ability of the driving circuits is enhanced. | 2009-08-13 |
20090201055 | Methods and Apparatus For Managing LSI Power Consumption and Degradation Using Clock Signal Conditioning - Methods and apparatus for distributing clock signals to an integrated circuit provide for: producing, in a slow mode of operation, a first clock signal having at least first and second on-pulses of differing first and second on-times each period, respectively, where a sum of the first and second on-times is approximately equal to a sum of off-times each period; distributing the first clock signal through a distribution tree and terminating at a plurality of final buffer circuits that produce respective distributed clock signals from which respective second clock signals are produced to supply at least a portion of the integrated circuit; deleting the second on-pulse from each of the distributed clock signals each period to produce the respective second clock signals, the second clock signals each including at least a portion of the first on-pulse, but none of the second on-pulse each period. | 2009-08-13 |
20090201056 | Preset Circuit of Audio Power Amplifier - A preset circuit of an audio power amplifier includes an inverter and a voltage drop device. The inverter receives an input signal to output an output signal, and includes a first switch and a second switch. The first switch is controlled with the input signal, and has a first terminal coupled to a power voltage and a second terminal for outputting the output signal. The second switch is controlled with the input signal, and has a third terminal for outputting the output signal and a fourth terminal coupled to a low reference voltage. The voltage drop device is coupled between the first terminal of the first switch and the power voltage and configured to lower the power voltage. The output signal is kept at a low level when the voltage drop device and the first switch are de-actuated due to the power voltage having a level below a first threshold. | 2009-08-13 |
20090201057 | METHOD AND APPARATUS TO GENERATE SYSTEM CLOCK SYNCHRONIZATION PULSES USING A PLL LOCK DETECT SIGNAL - Method and apparatus for generating system clock synchronization pulses using a Phase Locked Loop (PLL) lock detect signal are provided. The method includes utilizing a clock lock detect signal indicative that a system clock is synchronized with an internal clock, and determining an initial count value. Then, start counting beginning at a first rising edge of the system clock after the clock lock detect signal is generated, the counting starting with the initial count value. The method further includes generating a synchronization pulse (syncnp) when the counting ends, where the syncnp indicates the beginning of the next system clock cycle, and continue generating syncnps separated by one system clock cycle so as to continue indicating the beginning of the next system clock cycle. The method further guarantees stopping the syncnp generation when the lock detect is inactive indicating that the internal clock and the system clock are not synchronized. | 2009-08-13 |
20090201058 | CHARGE PUMP FOR PLL/DLL - A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operations amplifier also mitigates the effects of low power supply voltage. | 2009-08-13 |
20090201059 | System and Method for Signal Adjustment - Embodiment of the present invention relate to a method for receiving a first signal, determining a first characteristic of the first signal, the characteristic being a time based characteristic, receiving a second signal and processing the second signal through a predetermined range of delay elements, an initial minimum number of delay elements in the predetermined range being adjustable, the processed second signal having a second characteristic substantially corresponding to the first characteristic of the first signal. | 2009-08-13 |
20090201060 | CLOCK SYNCHRONIZING CIRCUIT - A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit. | 2009-08-13 |
20090201061 | Electronic apparatus having display portion and oscillator and manufacturing method of the same - A method for manufacturing a quartz crystal unit comprises the steps of forming a quartz crystal tuning fork resonator vibratable in a flexural mode of an inverse phase and having a quartz crystal tuning fork base and first and second quartz crystal tuning fork tines connected to the quartz crystal tuning fork base, forming at least one groove having at least three stepped portions in at least one of opposite main surfaces of each of first and second quartz crystal tuning fork tines, disposing an electrode on a surface of one of the at least three stepped portions of the at least one groove and an electrode on one of opposite side surfaces of each of the first and second quartz crystal tuning fork tines, mounting the quartz crystal tuning fork resonator on a mounting portion of a case, and connecting a lid to the case to cover an open end of the case, wherein the step of forming the quartz crystal tuning fork base and the first and second quartz crystal tuning fork tines is performed before the step of forming the at least one groove having the at least three stepped portions. | 2009-08-13 |
20090201062 | Electronic apparatus having display portion and oscillator and manufacturing method of the same - A method for manufacturing a quartz crystal unit comprises the steps of adjusting an oscillation frequency of a quartz crystal tuning fork resonator that is vibratable in a flexural mode of an inverse phrase and that has first and second quartz crystal tuning fork tines, forming at least one groove in each of two of opposite main surfaces of each of first and second quartz crystal tuning fork tines, disposing an electrode on a surface of the at least one groove formed in each of two of the opposite main surfaces and each of two of opposite side surfaces of each of the first and second quartz crystal tuning fork tines so that the electrodes of the grooves of the first quartz crystal tuning fork tine are connected to the electrodes of the side surfaces of the second quartz crystal tuning fork tine and the electrodes of the grooves of the second quartz crystal tuning fork tine are connected to the electrodes of the side surfaces of the first quartz crystal tuning fork tine, the quartz crystal tuning fork resonator having a series resistance R | 2009-08-13 |
20090201063 | DYNAMIC SEMICONDUCTOR DEVICE - A dynamic semiconductor device is provided with a plurality of master step sections having hatch sections for temporarily storing input data and dynamic gate sections; a plurality of slave step sections, which are alternately connected with master step sections and provided with dynamic gate sections or with latch sections and dynamic gate sections; and a timing signal generating section for generating a signal for controlling operation of the master step sections and the slave step sections. The timing signal generating section supplies the latch sections with signals for storing data of the previous step before the data is erased. | 2009-08-13 |
20090201064 | Phase Interpolator System and Associated Methods - A phase interpolator system is disclosed that may include a clock to provide a clock signal, and a control section in communication with the clock to regulate the strength of the clock signal. The system may also include a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from the control section. | 2009-08-13 |
20090201065 | Local signal generation circuit - A local signal generation circuit in accordance with one aspect of the present invention includes a phase comparator that detects a phase difference between a reference signal and a feedback signal and outputs a error signal, a charge-pump circuit that receives the error signal and generates a step-up voltage, a loop filter that generates a tuning voltage by changing the shape of the step-up voltage, a voltage control oscillator that generates a first output signal having a predefined frequency based on the tuning voltage, and a prescaler that outputs a second output signal generated by dividing the frequency of the first output signal to a predefined frequency and also outputs a frequency-division signal generated by dividing the frequency of the first output signal to the predefined frequency to a frequency divider that generates the feedback signal. | 2009-08-13 |
20090201066 | Digitally Clock with Selectable Frequency and Duty Cycle - A system and method are provided for controlling the duty cycle and frequency of a digitally generated clock. The method accepts a first clock signal having a fixed first frequency. A frequency control word with a first pattern is loaded into a first plurality of serially-connected registers. A duty cycle control word with a second pattern is loaded into a second plurality of serially-connected registers. A register clock signal is generated in response to the first clock and the first pattern. Then, a digital clock signal is generated having a frequency and duty cycle responsive to the register clock signal and the second pattern. | 2009-08-13 |
20090201067 | REFERENCE VOLTAGE GENERATING CIRCUIT, INTEGRATED CIRCUIT DEVICE, AND SIGNAL PROCESSING APPARATUS - A reference voltage generating circuit that generates a reference voltage includes: a first pn junction that generates a first voltage; a second pn junction that has a different current density from the first pn junction; a first resistor that generates a first current having a positive temperature coefficient based on a voltage equivalent to a difference between a forward voltage of the first pn junction and a forward voltage of the second pn junction; a second resistor that generates a first voltage having a positive temperature coefficient based on the first current, wherein the first voltage having the positive temperature coefficient and a voltage having a negative temperature coefficient are added to generate the reference voltage; and a third resistor that generates a temperature-dependent voltage based on the first current having the positive temperature coefficient, wherein the reference voltage and the temperature-dependent voltage are outputted in parallel from first and second output nodes, respectively, and a resistance value of the first resistor and a resistance value of the third resistor are adjusted in the same proportion by a trimming signal. | 2009-08-13 |
20090201068 | Output circuit with overshoot-reducing function - Output circuit with reduced overshoot includes input end, output end, a circuit composed of PMOS and NMOS, rising and falling edge trigger bias circuits. The rising and falling edge trigger bias circuits output biasing voltages to the output end for clamping the voltage of the output signals respectively according to the rising edge and the falling edge of the input signal. In this way, the overshoot of the output signal is reduced. | 2009-08-13 |
20090201069 | LEVEL SHIFTING CIRCUIT - A level shifting circuit includes a first level shifting unit including a plurality of signal transfer units; a first operation control unit inactivating some of signal transfer units of the first level shifting unit in response to a clamping signal; a second level shifting unit connected in parallel to the first level shifting unit and comprising a plurality of signal transfer units; a second operation control unit inactivating some of signal transfer units of the second level shifting unit in response to the clamping signal; a signal output unit connected to output ends of the first and second level shifting units; and a clamping unit fixing the output ends of the first and second level shifting units to a predetermined voltage level in response to the clamping signal. | 2009-08-13 |
20090201070 | PRE-DRIVER CIRCUIT USING TRANSISTORS OF A SINGLE CHANNEL TYPE - A serial interface apparatus comprises a driver for generating a differential communication signal and a pre-driver for driving the driver circuit. The pre-driver receives an input signal that alternates between VDD and ground and produces an output signal that alternates between a lower limit that is greater than ground and an upper limit that is less than VDD. The pre-driver comprises input circuitry and actuation circuitry, and the actuation circuitry comprises transistors of a single channel type. | 2009-08-13 |
20090201071 | Bootstrap circuit - Disclosed herein is a bootstrap circuit configured to employ first, second and third transistors of the same conduction type wherein: a node section connecting a gate electrode of the first transistor and a specific one of the source and drain areas of a third transistor to each other is put in a floating state when the third transistor is put in a turned-off state; a gate electrode of the second transistor is connected to a clock supply line which conveys the other one of the two clock signals; and a voltage-variation repression capacitor is provided between the node section and a first voltage supply line. | 2009-08-13 |
20090201072 | BRIDGE CIRCUITS AND THEIR COMPONENTS - A half bridge is described with at least one transistor having a channel that is capable in a first mode of operation of blocking a substantial voltage in at least one direction, in a second mode of operation of conducting substantial current in one direction through the channel and in a third mode of operation of conducting substantial current in an opposite direction through the channel. The half bridge can have two circuits with such a transistor. | 2009-08-13 |
20090201073 | Pump Control Unit with Decelerometer Switch - A pump control unit incorporates an accelerometer as a sensor. Responsive to outputs from the sensor, electrical load driving signals can be provided to energize a pump motor to reduce a fluid level in an enclosure. | 2009-08-13 |
20090201074 | Method and Circuit for Implementing Efuse Sense Amplifier Verification - A method and circuit for implementing Efuse sense amplifier verification, and a design structure on which the subject circuit resides are provided. A first predefined resistor value is sensed relative to a reference resistor. A second predefined resistor value is sensed relative to a reference resistor. Responsive to identifying a respective sense amplifier output resulting from the sensing steps of an unblown eFuse and a blown eFuse, valid operation of the sense amplifier is identified. | 2009-08-13 |
20090201075 | Method and Apparatus for MOSFET Drain-Source Leakage Reduction - A method and apparatus are taught for reducing drain-source leakage in MOS circuits. In an exemplary CMOS logic gate, a first transistor causes the body of an affected transistor to be at a first body potential. A second transistor brings the body potential of the affected transistor to a second body potential by providing an accurate body voltage from a body voltage source. The first transistor's gate is controlled by a digital voltage source having a same polarity as that of an output of the CMOS logic gate and the second transistor is controlled by a digital voltage source having a same polarity as that of an input to the CMOS logic gate. | 2009-08-13 |
20090201076 | SEMICONDUCTOR CHARGE PUMP USING MOS (METAL OXIDE SEMICONDUCTOR) TRANSISTOR FOR CURRENT RECTIFIER DEVICE - A semiconductor charge pump includes a plurality of P-channel MOS transistors being connected in series, a plurality of first pumping capacitors one electrode of each of which is connected to a connection point of each of the P-channel MOS transistors, a clock signal generating circuit which generates first and second clock signals whose phases are different from each other by 180 degrees, the first and second clock signals being alternately supplied to the other electrodes of the first pumping capacitors. The semiconductor charge pump further includes a plurality of dynamic level converter circuits each including a resistor element and a second pumping capacitor and connected to each of gates of the P-channel MOS transistors. | 2009-08-13 |
20090201077 | CLOCKED INVERTER, NAND, NOR AND SHIFT REGISTER - A threshold voltage of a transistor is fluctuated because of fluctuation in film thickness of a gate insulating film or in gate length and gate width caused by differences of used substrates or manufacturing steps. In order to solve the problem, according to the present invention, there is provided a clocked inverter including a first transistor and a second transistor connected in series, and a compensation circuit including a third transistor and a fourth transistor connected in series. In the clocked inverter, gates of the third transistor and the fourth transistor are connected to each other, drains of the third transistor and the fourth transistor are each connected to a gate of the first transistor, sources of the first transistor and the fourth transistor are each electrically connected to a first power source, a source of the second transistor is electrically connected to a second power source, and an amplitude of a signal inputted to a source of the third transistor is smaller than a potential difference between the first power source and the second power source. | 2009-08-13 |
20090201078 | Single-chip common-drain JFET device and its applications - A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation. | 2009-08-13 |
20090201079 | Single-chip common-drain JFET device and its applications - A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation. | 2009-08-13 |
20090201080 | CURRENT MIRROR CIRCUIT AND DIGITAL-TO-ANALOG CONVERSION CIRCUIT - A first switched capacitor circuit is connected to the source of one MOS transistor of a current mirror pair configured by a pair of MOS transistors and a second switched capacitor circuit is connected to the source of the other MOS transistor. Each of the first and second switched capacitor circuits includes a capacitor and a switch connected in parallel with the capacitor and the switch is on/off-controlled based on a clock signal of a preset cycle. Each of the first and second switched capacitor circuits equivalently functions as a resistor with large resistance and a variation in the output current of the current mirror circuit based on a variation in the threshold voltages of the pair of MOS transistors can be reduced even if the power source voltage is reduced. | 2009-08-13 |
20090201081 | Method and Apparatus for MOSFET Drain-Source Leakage Reduction - A method and apparatus is taught for reducing drain-source leakage in MOS circuits. In an exemplary CMOS inverter, a first transistor causes the body of an affected transistor to be at a first body potential. A second transistor brings the body potential of the affected transistor to a second body potential by providing an accurate body voltage from a body voltage source. Exemplary body bias voltage sources are further described that can drive one or more gate transistors of different gate circuits. | 2009-08-13 |
20090201082 | INTEGRATED CIRCUIT DEVICE HAVING POWER DOMAINS AND PARTITIONS BASED ON USE CASE POWER OPTIMIZATION - A programmable SoC (system on a chip) having optimized power domains and power islands. The SoC is an integrated circuit device including a plurality of power domains, each of the power domains having a respective voltage rail to supply power to the power domain. A plurality of power islands are included within the integrated circuit device, wherein each power domain includes at least one power island. A plurality of functional blocks are included within the integrated circuit device, wherein each power island includes at least one functional block. Each functional block is configured to provide a specific device functionality. The integrated circuit device adjusts power consumption in relation to a requested device functionality by individually turning on or turning off power to a selected one or more power domains, and for each turned on power domain, individually power gating one or more power islands. | 2009-08-13 |
20090201083 | AMPLIFIER DEVICE AND SYSTEM USING THE DEVICE - A device comprising: an input for an electric signal; an integrator stage connected to said input to provide an integrated signal; an amplifier stage electrically coupled to the integrator stage to receive said integrated signal and to provide an output signal. The device being characterized in that the integrator stage is such that the integrated signal is obtained by an individual signal integration operation. | 2009-08-13 |
20090201084 | MULTI-MODE POWER AMPLIFIERS - Multi-mode power amplifiers that can support multiple radio technologies and/or multiple frequency bands are described. In one exemplary design, a first linear power amplifier supporting multiple radio technologies may be used to amplify a first RF input signal (e.g., for low band) and provide a first RF output signal. A second linear power amplifier also supporting the multiple radio technologies may be used to amplify a second RF input signal (e.g., for high band) and provide a second RF output signal. Each linear power amplifier may include multiple (e.g., three) chains coupled in parallel. Each chain may be selectable to amplify an RF input signal and provide an RF output signal for a respective range of output power levels. An RF input signal may be a phase modulated signal or a quadrature modulated signal and may be pre-distorted to account for non-linearity of the power amplifier. | 2009-08-13 |
20090201085 | POWER AMPLIFYING APPARATUS AND MOBILE COMMUNICATION TERMINAL - A power amplifying apparatus includes an input terminal configured to receive an input signal, a first power amplifier biased for class A or class AB operation which is configured to amplify the input signal, an output terminal connected to an output of the first power amplifier, a second power amplifier biased for class C operation which is configured to receive and amplify a part of the input signal, and a switch connected between an output of the second power amplifier and the output terminal. | 2009-08-13 |
20090201086 | Current sense amplifier with extended common mode voltage range - A circuit includes an input stage configured to receive and amplify an input signal to produce an amplified signal, where the input signal is referenced to a higher voltage and is associated with a common mode voltage. The circuit also includes level shifter resistors configured to level shift the amplified signal to produce a shifted signal. The level shifter resistors are configured to provide a voltage drop so that the shifted signal is referenced to a lower voltage. The input stage may include multiple transistors floating in one or more isolated portions of a substrate, where the transistors perform amplification in the input stage. The circuit may also include circuitry configured to control current through the level shifter resistors so that the voltage drop depends on the common mode voltage of the input signal. In addition, the lower voltage may be between supply rails of the circuit. | 2009-08-13 |
20090201087 | DIFFERENTIAL INPUT AMPLIFIER - An amplifier comprises: first and second supply terminals intended to receive a DC supply voltage; a first branch coupled between the first and second supply terminals and including a first terminal of application of a differential signal to be amplified; a second branch coupled between the first and second supply terminals and including a second terminal of application of the differential signal to be amplified; a third branch coupled between the first and second supply terminals and including a first amplifier having an input terminal connected to the second branch and having an output terminal configured to be coupled to a load, and a measurement element configured to measure a current in the third branch; and a fourth branch coupled between the first and second supply terminals and including a second amplifier having an input terminal connected to the first branch, and a copying element configured to copy the current measured in the third branch. | 2009-08-13 |
20090201088 | Measuring Load Impedance Of An Amplifier Driving A Variable Load - According to an aspect of the present invention, the magnitude and phase angle of looking-in impedance driven by an amplifier are computed in digital domain during normal operation within a module containing the amplifier. In an embodiment, the computed magnitude and phase angle are used for impedance matching at a node driven by the amplifier. As a result, impedance matching may be obtained even in situations when the impedance changes during operation. | 2009-08-13 |
20090201089 | High frequency power amplifier - A high frequency power amplifier includes an amplifying device for amplifying an input high frequency signal, a harmonic reflection circuit for reflecting a harmonic outputted from the amplifying device, and a harmonic generating circuit provided at an input terminal of the amplifying device, the harmonic generating circuit including a divider for dividing an input signal of a fundamental wave into two parts, a harmonic generator for generating a second harmonic from one part of the fundamental wave signal, and a combiner for combining the second harmonic generated from the harmonic generator with the other part of the fundamental wave signal to offer a combined signal to the amplifying device, wherein the harmonic reflection circuit reflects the second harmonic. | 2009-08-13 |
20090201090 | SIGNALING SYSTEM WITH LOW-POWER AUT0MATIC GAIN CONTROL - An integrated circuit device includes a variable-gain amplifier, memory circuit and gain control update circuit. The variable-gain amplifier generates an amplified signal having an amplitude according to a gain control value that is stored, at least during a first interval, within the memory circuit. The update circuit generates an updated gain control value based on the amplified signal during the first interval, and outputs the updated gain control value to the memory circuit to be stored therein at a conclusion of the first interval. | 2009-08-13 |
20090201091 | SYSTEM AND METHOD FOR CONTROLLING ATTENUATOR - An apparatus for setting an attenuation of an attenuator includes a control transistor, which includes a drain connected to a gate of a shunt transistor of the attenuator. A channel resistance of the shunt transistor corresponds to a current density of the control transistor, and the channel resistance of the shunt transistor determines the attenuation of the attenuator. The current density of the control transistor is based at least in part on a control voltage input to the apparatus. | 2009-08-13 |
20090201092 | COMMUNICATION SYSTEM AND OSCILLATION SIGNAL PROVISION METHOD - An embodiment of a communication system is provided, in which a high frequency oscillator generates a first high frequency signal upon receipt of no disable signal. The first high frequency signal is commonly shared by at least two modules. Each module coupled to the high frequency oscillator operates in either busy or idle mode, wherein the module operates at the first high frequency signal when in busy mode, and asserts a request signal when in idle mode. A disablement unit, coupled to the first and second modules, asserts the disable signal to the high frequency oscillator when all of the request signals are asserted, thereby forcing the high frequency oscillator to cease the generation of the first high frequency signal. | 2009-08-13 |
20090201093 | PHASE-LOCKED CIRCUIT EMPLOYING CAPACITANCE MULTIPLICATION - A phase-locked loop circuit. The phase-locked loop circuit comprises a phase detector, a proportional charge pump, a decimator, an integral charge pimp, and a voltage-controlled oscillator. The phase detector obtains an phase error information according to a phase difference between a reference signal and a clock signal input to the phase detector. The proportional charge pump coupled to the phase detector generates a first voltage according to the phase error information. The decimator generates a decimated version of the phase error information by a decimation factor of N. The integral charge pump generates a second voltage according to the decimated version of the phase error information. The voltage-controlled oscillator generating the clock signal according to a combination of the first and second voltages. | 2009-08-13 |
20090201094 | PHASE COMPARISON CIRCUIT AND PLL SYNTHESIZER USING THE SAME - The phase comparison circuit according to an embodiment of the present invention comprises a fractional frequency divider | 2009-08-13 |
20090201095 | OSCILLATOR DEVICE AND OPTICAL DEFLECTION DEVICE - An oscillator device includes an oscillation system including an oscillator and a resilient supporting member, a driving member configured to supply a driving force to the oscillation system based on a driving signal, and a driving frequency control unit configured to control a driving frequency of a driving signal to be outputted to the driving member, wherein, when an oscillation frequency of the oscillator is to be changed from a current oscillation frequency to a target oscillation frequency, the driving frequency control unit temporarily outputs, to the driving member, a driving signal having a driving frequency which is made different from the target oscillation frequency, being changed from the current driving frequency and beyond the target oscillation frequency, thereby to cause the driving member to drive the oscillation system. | 2009-08-13 |
20090201096 | OSCILLATOR - This invention relates to an oscillator having reduced sensitivity to acceleration. The oscillator includes a plurality of asymmetrically mounted resonator portions each having an active resonance region. The asymmetric mounting of the resonator portions means that each resonator portion has an axis passing through its active resonance region along which the acceleration sensitivity vector is dominant, i.e. the sensitivity to acceleration along the direction defined by one axis is much greater than the sensitivity to acceleration in other directions. The resonators are mounted in an oscillator such that their dominant axes are directed in different directions, e.g. an anti-parallel arrangement, which means that the dominant acceleration sensitivity vectors can cancel each other out. | 2009-08-13 |
20090201097 | CONTINUOUSLY TUNABLE INDUCTOR AND METHOD TO CONTINUOUSLY TUNE AN INDUCTOR - A continuously tunable inductor with an inductive-capacitive (LC) voltage controlled oscillator (VCO) having a primary coil. The inductor includes a separate isolated secondary coil, a set of transistors composing a closed loop with the secondary coil, a magnetic coupling between the primary coil of the LC VCO and the secondary coil, an electrical coupling between the LC VCO and the set of transistors composing a closed loop with the secondary coil, and means for electric current injection into the closed loop. Such an inductor can be tuned by modulating a mutual inductance, which is magnetically and electrically coupled with the LC VCO by injection of an electric current (I | 2009-08-13 |
20090201098 | ACTIVE NONLINEAR TRANSMISSION LINE - A system for propagating a non-dispersive signals includes a transmission line with a voltage dependent propagation constant and distributed gain elements to maintain the non-dispersive signal between a maximum propagating amplitude and a minimum propagating amplitude. | 2009-08-13 |
20090201099 | MULTI-BAND HIGH-FREQUENCY CIRCUIT, MULTI-BAND HIGH-FREQUENCY CIRCUIT COMPONENT AND MULTI-BAND COMMUNICATION APPARATUS USING SAME - A multi-band high-frequency circuit for performing wireless communications among pluralities of communication systems having different communication frequencies, comprising a high-frequency switch circuit comprising switching elements for switching the connection of pluralities of multi-band antennas to transmitting circuits and receiving circuits; a first diplexer circuit disposed between the high-frequency switch circuit and transmitting circuits for branching a high-frequency signal into frequency bands of the communication systems; a second diplexer circuit disposed between the high-frequency switch circuit and receiving circuits for branching a high-frequency signal into frequency bands of the communication systems; the first and second diplexer circuits each comprising a lower-frequency filter circuit and a higher-frequency filter circuit, a bandpass filter circuit being used as the lower-frequency filter circuit in the second diplexer circuit, or disposed between the lower-frequency filter circuit in the second diplexer circuit and the receiving circuit, the high-frequency switch circuit comprising first to fourth ports, the first port being connected to a first multi-band antenna, the second port being connected to a second multi-band antenna, the third port being connected to the first diplexer circuit, and the fourth port being connected to the second diplexer circuit; and the switching elements being controlled in an ON or OFF state to select a multi-band antenna for performing wireless communications and to switch the connection of the selected multi-band antenna to the transmitting circuit or the receiving circuit. | 2009-08-13 |
20090201100 | INDUCTOR COMBINING PRIMARY AND SECONDARY COILS WITH PHASE SHIFTING - An inductor including a primary coil coaxially arranged and operated in parallel with isolated secondary coils each including at least one loop winding with two open-circuited ports. At least one phase shifting device is arranged between open-circuited ports of at least one secondary coil. A method to operate an inductor by combining primary and secondary coils with phase shifting devices to get a wide tuning range is also provided. The method includes the step of phase shifting open-circuited ports of at least one secondary coil. | 2009-08-13 |
20090201101 | INDUCTOR AND METHOD OF OPERATING AN INDUCTOR BY COMBINING PRIMARY AND SECONDARY COILS WITH COUPLING STRUCTURES - An inductor and method of operating the inductor by combining primary and secondary coils with passive coupling, active parallel, or active cross-coupling structures. The first includes at least one passive coupling structure having at least one coupling coil arranged between a primary coil and at least one of the secondary coils and/or between two of the secondary coils. The second includes an active coupling structure arranged between a primary coil and at least one secondary coil and/or between at least two of the secondary coils, to selectively parallel couple the primary coil and one of the secondary coils and/or at least two of the secondary coils. The third includes an active coupling structure to selectively cross couple a primary coil and at least one of the secondary coils and/or to selectively cross couple at least two of the secondary coils. | 2009-08-13 |
20090201102 | BOUNDARY ACOUSTIC WAVE ELEMENT, BOUNDARY ACOUSTIC WAVE DEVICE, AND MANUFACTURING METHODS FOR THE SAME - A boundary acoustic wave element includes an IDT electrode arranged at the interface between a piezoelectric substance and a dielectric layer, a heat dissipation film is arranged on the outer side surface of the dielectric layer or on the outer side surface of a sound-absorbing film laminated on the outer side of the dielectric layer, the heat dissipation film is arranged to have a portion that overlaps the IDT electrode in plan view, and the heat dissipation film is connected to a bump provided on the outer side surface of the sound-absorbing film, and is connected to a via-hole conductor that extends through the sound-absorbing film. The boundary acoustic wave element and a boundary acoustic wave device are excellent in a heat dissipation property and hence can provide enhanced electric power resistance, without causing an increase in chip size and an increase in the area of the mounting space. | 2009-08-13 |
20090201103 | SURFACE ACOUSTIC WAVE FILTER DEVICE - A first and a second longitudinally coupled resonator-type surface acoustic wave filter are disposed on a piezoelectric substrate. One end of a first IDT arranged at the middle of the first longitudinally coupled resonator-type surface acoustic wave filter is connected to a first unbalanced terminal, and one end of a first IDT arranged at the middle of the second longitudinally coupled resonator-type surface acoustic wave filter is connected to a second unbalanced terminal. Signal terminals of second IDTs of the first and the second longitudinally coupled resonator-type surface acoustic wave filter are connected to each other with a first signal line. Third IDTs are connected to each other with a second signal line. A capacitor is connected between the first and the second signal line. The above arrangement provides a cascaded longitudinally coupled resonator-type surface acoustic wave filter device including an inter-stage capacitor is miniaturized. | 2009-08-13 |
20090201104 | ACOUSTIC WAVE DEVICE, DUPLEXER, COMMUNICATION MODULE, AND COMMUNICATION APPARATUS - An acoustic wave device includes a ladder-type filter in which resonators are connected in a ladder configuration. In the acoustic wave device, series-connected resonators are connected in a parallel line in the ladder-type filter, and the resonators connected in the parallel line have mutually different resonance frequencies. | 2009-08-13 |
20090201105 | ACOUSTIC WAVE DEVICE - An acoustic wave device includes first and second 3-IDT acoustic wave filters provided on a piezoelectric substrate. A second IDT in the first acoustic wave filter is electrically connected to a second IDT in the second acoustic wave filter and a third IDT in the first acoustic wave filter is electrically connected to a third IDT in the second acoustic wave filter to cascade the first acoustic wave filter with the second acoustic wave filter. An acoustic wave resonator is connected to a first IDT in the first acoustic wave filter. In the acoustic wave device, NA/NB is in a range from about 2.6 to about 3.5 and fB/fa is in a range from about 0.995 to about 1.010, where NA denotes the number of electrode fingers of the first IDT in the first acoustic wave filter, NB denotes the number of electrode fingers of each of the second and third IDTs in the first acoustic wave filter, fB denotes the end frequency of a stop band of each of reflectors in the first and second acoustic wave filters, and fa denotes an anti-resonant frequency of the acoustic wave resonator. | 2009-08-13 |
20090201106 | HARMONIC SUPPRESSION RESONATOR, HARMONIC PROPAGATION BLOCKING FILTER, AND RADAR APPARATUS - A harmonic suppression resonator comprises a plurality of waveguide resonators that resonate in TE mode, in which harmonic suppression resonator, adjoining resonators are coupled via a plurality of coupling windows. Four coupling windows | 2009-08-13 |
20090201107 | Waveguide Junction - A junction ( | 2009-08-13 |
20090201108 | Switched Length Match Transmission Path Instrument - A testing apparatus includes one or more trace banks. Each trace bank includes (1) an input switch operable to couple an input port to one of multiple output ports, (2) an output switch operable to couple one of multiple input ports to one output port, and (3) transmission lines of different lengths coupled between the output ports of the input switch and the input ports of the output switch. The trace banks can be cascaded using cables to connect their output and input ports. The input and output switches in the trace banks are controlled to provide a transmission path of the desired length. | 2009-08-13 |
20090201109 | CIRCUIT BREAKER - A circuit breaker of different interruption speeds, and a spring operation mechanism is standardized for designing and manufacturing the circuit breaker. The circuit breaker has a power transmission mechanism for driving a movable contact | 2009-08-13 |
20090201110 | SWITCH DEVICE - A movable contact positioned in a sealed case is moved together with a movable contact spring provided with an armature by a magnetic shunt body which is moved outside the sealed case. The movement of the movable contact (movement of the movable contact spring) due to the movement of the magnetic shunt body is based on the change of the magnetically attracting force of a magnet with respect to the armature through a pair of yokes. The movable contact spring is provided with a bent portion which is bent in spaced-apart relation to the armature, the bent portion being provided between a fulcrum portion at a time when the movable contact spring moves and a portion where the armature is provided. | 2009-08-13 |
20090201111 | GENERATING ELECTROMAGNETIC FORCES WITH FLUX FEEDBACK CONTROL - An electromagnetic actuator with flux feedback control includes two poles located on opposite sides of a soft-magnetic target. A bias flux is introduced that flows into both poles. Magnetic circuitry may be designed so that the total bias flux is independent or substantially independent of a position of the target with respect to the poles or the control flux. The electromagnetic actuator also includes flux sensors introduced into each gap between the poles and the target. The electromagnetic actuator further includes an actuator control circuit to command the current in the control coil to bring a difference between the readings of the two flux sensors to a targeted level. In some aspects, the force exerted on the actuator target in this arrangement may be proportional to the command signal regardless of the position of the actuator target, MMF drop in the soft-magnetic parts of the magnetic circuit, or the frequency. | 2009-08-13 |
20090201112 | METHOD OF ENCASING A MAGNET AND AN ENCASED MAGNET - A method of encasing a magnet to isolate the magnet from the environment is provided. The method includes introducing a magnet to a housing having at least one passage capable of passing a fluid from the environment to the magnet, introducing a hardenable fluid, for example, a resin, to the passage to obstruct the passage, and solidifying the hardenable fluid in the passage to provide a solid obstruction to the passage to isolate the magnet from environmental fluids. The housing may be provided as two mating housings and the passage may be provided by the mating surfaces between the two housings. An encased magnet is also disclosed. The encased magnet may be used in any environment that may be damaging to the magnet, for example, in surgical or prosthetic applications. | 2009-08-13 |
20090201113 | INTEGRATED INDUCTOR STRUCTURE AND METHOD OF FABRICATION - An inductor structure comprised of a magnetic section and a single turn solenoid. The single turn solenoid to contain within a portion of the magnetic section and circumscribed by the magnetic section. | 2009-08-13 |
20090201114 | BOBBIN ASSEMBLY - A bobbin assembly is disclosed that includes a first bobbin and a second bobbin. The second bobbin is configured substantially similar to the first bobbin. The first and second bobbins include a first flange and a second flange disposed at opposite ends of a central core. The first flanges include terminal receiving cavities and wire posts for terminate a wire wound around the central core. The bobbin assembly may be formed by mating either the first flanges or the second flanges together. | 2009-08-13 |
20090201115 | INDUCTANCE ELEMENT IN AN INTEGRATED CIRCUIT PACKAGE - An electronic circuit in an integrated circuit package comprises an inductance element. The inductance element further comprises a plurality of separated metal strips formed on a substrate and a ferrite core coupled to the substrate. The metal strip plurality is formed between the substrate and the ferrite core. The inductance element further comprises a plurality of wires coupled to the separated metal strips whereby the metal strips and wires form a continuous coil. The ferrite core is interposed between the metal strip plurality and the wire plurality. | 2009-08-13 |
20090201116 | ANTENNA CIRCUIT AND TRANSPONDER - A transponder is provided capable of having desired characteristics by a method for forming a resonance circuit, despite the fact that its cost is low and its structure is simple. An antenna circuit is provided in the transponder and comprises an antenna conductor having a predetermined conductor pattern formed on the front surface of a substrate and a sheet metal disposed on the rear surface of the substrate. A part of the sheet metal is provided with a slit so formed that its start end and terminal end are opened to the area at which the sheet metal does not exist. | 2009-08-13 |
20090201117 | CONTAINER WITH ELECTROMAGNETIC COUPLING MODULE - A container includes an electromagnetic coupling module on an inner surface of a container main body and a radiator made of a metal material on an outer surface of the container main body. The electromagnetic coupling module includes a feeder circuit board, on which a radio IC chip is mounted and in which a feeder circuit including a resonant circuit that has a predetermined resonant frequency and includes an inductance element is provided. The electromagnetic coupling module and the radiator preferably transmit and receive high-frequency signals through electromagnetic coupling. The container thus has an electromagnetic coupling module that includes a radio IC chip that is resistant to a shock applied from the outside and an environmental change, realizes an easy arrangement of a radiator and the electromagnetic coupling module, provides a preferable radiation characteristic, and is suitably used in an RFID system. | 2009-08-13 |
20090201118 | Electromagnetic current limiter device - An electromagnetic current limiter device comprising at least one ferromagnetic core having a central opening; at least one winding of electric conducting material wound on the core; a portion of said winding passing through said opening; an input terminal for receiving alternating current for supplying said alternating current to said winding; an output terminal for supplying current limited current to an external load; and a plurality of predetermined aligned magnetic domains defined in said core for limiting the current to said output terminal. | 2009-08-13 |
20090201119 | Hysteretic mems thermal device and method of manufacture - A MEMS hysteretic thermal actuator may have a plurality of beams disposed over a heating element formed on the surface of the substrate. The plurality of beams may be coupled to a passive beam which is not disposed over the heating element. One of the plurality of beams may be formed in a first plane parallel to the substrate, whereas another of the plurality of beams may be formed in a second plane closer to the surface of the substrate. When the heating element is activated, it heats the plurality of beams such that they move the passive beam in a trajectory that is neither parallel to nor perpendicular to the surface of the substrate. When the beams are cooled, they may move in a different trajectory, approaching the substrate before moving laterally across it to their initial positions. By providing one electrical contact on the distal end of the passive beam and another stationary electrical contact on the substrate surface, the MEMS hysteretic actuator may form a reliable electrical switch that is relatively simple to manufacture and operate. | 2009-08-13 |