33rd week of 2009 patent applcation highlights part 39 |
Patent application number | Title | Published |
20090203124 | MAGE-A3 PEPTIDES PRESENTED BY HLA-DR1 MOLECULES - The invention describes HLA class II binding peptides encoded by the MAGE tumor associated genes, as well as nucleic acids encoding such peptides and antibodies relating thereto. The peptides stimulate the activity and proliferation of CD4 | 2009-08-13 |
20090203125 | MIG-7 AS A SPECIFIC ANTICANCER TARGET - Aspects of the present invention provide novel Mig-7 encoding nucleic acids and Mig-7 polypeptides, recombinant DNA expression systems and host cells containing same, as well as methods of inhibiting expression of the subject nucleic acid molecules, inhibiting production of the encoded proteins or polypeptides, inhibiting metastasis of a carcinoma cell in a subject (including in humans), inhibiting migration/invasion of and mimicking of normal cells by carcinoma cells in a subject, detecting the presence of a cancer cell (e.g., a migrating/invading cancer cell or carcinoma cell mimic, and tumor neovascularization) in a sample of a subject's tissue or body fluids, and inhibiting the migration/invasion of or endothelial cell mimicking by a placental cell into the blood stream or vessels of a female mammal. Particular aspects relate to novel anti-Mig-7 antibodies, diagnostic and/or prognostic methods, and therapeutic methods comprising use of the inventive nucleic acids, polypeptides and antibodies or derivatives thereof. | 2009-08-13 |
20090203126 | CELL CULTURE ARRAY SYSTEM FOR AUTOMATED ASSAYS AND METHODS OF OPERATION AND MANUFACTURE THEREOF - A number of novel improved microfluidic configurations and systems and methods of manufacture and operation. In one embodiment, three wells are used for independent cell culture systems in a cell culture array. In a second aspect, artificial sinusoids with artificial epithelial barriers are provided with just one (optionally shared or multiplexed) fluidic inlet and one (optionally shared or multiplexed) fluidic output, where the medium output also functions as a cellular input. A pneumatic cell loader combined with other components provides a fully automated cell culture system. Magnetic alignment of plate molds provides advantages and ease of molded manufacture. | 2009-08-13 |
20090203127 | Nematode Fatty Acid Desaturase-Like Sequences - Nucleic acid molecules from nematodes encoding fatty acid desaturase polypeptides are described. Fatty acid desaturase-like polypeptide sequences are also provided, as arc vectors, host cells, and recombinant methods for production of fatty acid desaturase-like nucleotides and polypeptides. Also described are screening methods for identifying inhibitors and/or activators of fatty acid desaturase-like polypeptides, as well as methods for antibody production. | 2009-08-13 |
20090203128 | Nogo-Receptors and Methods of Use - Disclosed are compositions relating to the Nogo receptor (NgR) family as well as fragments, chimeras, and variants thereof. The invention provides polypeptides, nucleic acids, vectors, expression systems, and antibodies and antibody fragments related to the NgRs as well as uses thereof. Such uses include modulation neurite outgrowth in a subject and treatment of central nervous system disorders in a subject, as well as, methods of identifying and screening compounds that can be used for modulating neurite outgrowth in a subject or in treatment of central nervous system disorders in a subject. | 2009-08-13 |
20090203129 | MULTIPOTENT ADULT STEM CELLS AND METHODS FOR ISOLATION - The invention provides isolated stem cells of non-embryonic origin that can be maintained in culture in the undifferentiated state or differentiated to form cells of multiple tissue types. Also provided are methods of isolation and culture, as well as therapeutic uses for the isolated cells. | 2009-08-13 |
20090203130 | MULTIPOTENT ADULT STEM CELLS AND METHODS FOR ISOLATION - The invention provides isolated stem cells of non-embryonic origin that can be maintained in culture in the undifferentiated state or differentiated to form cells of multiple tissue types. Also provided are methods of isolation and culture, as well as therapeutic uses for the isolated cells. | 2009-08-13 |
20090203131 | Polyamides for nucleic acid delivery - The present invention describes reagents and methods for using concatermized double-stranded oligonucleotide molecules (CODN) for transcription factor decoys. In one embodiment, the concatemers consist of a variable number of end-to-end copies of a short dsDNA containing a sequence or sequences that act as transcription factor decoys. | 2009-08-13 |
20090203132 | PYRROLIDINYL GROUPS FOR ATTACHING CONJUGATES TO OLIGOMERIC COMPOUNDS - The present invention provides pyrrolidinyl compounds that are useful for preparing conjugated oligomeric compounds. The conjugated pyrrolidinyl compounds can be attached to support medium and provide a free hydroxyl for oligomer synthesis to prepare an oligmeric compound having a 3′-conjugate. Alternatively, the pyrrolidinyl compound can be prepared as a phosphoramidite which can be placed internally or at the 5′-position of an oligomeric compound. These two strategies can be used together to prepare oligomeric compounds having 2 or more conjugates at any selected positions. The present invention also provides methods for modulating gene expression using the conjugated oligomeric compounds. | 2009-08-13 |
20090203133 | Determinants of Sensitivity to Chemotherapeutic Agents - The present invention provides methods for determining the level of resistance of a tumour cell to one or more chemotherapeutic agents, comprising measuring the level of expression of a muscle ankyrin repeat protein in the tumour cell. The invention also provides methods for increasing the sensitivity of a tumour cell to one or more chemotherapeutic agents, comprising administering to the cell an effective amount of an antagonist of a muscle ankyrin repeat protein. The invention further provides compositions for use in accordance with methods of the invention. | 2009-08-13 |
20090203134 | REMEDY FOR NERVE CELL REGENERATION | 2009-08-13 |
20090203135 | Glycoconjugates of RNA Interference Agents - The present invention relates to agents, compositions and methods for inhibiting the expression of a target gene, comprising an RNAi agent bearing at least one galactosyl moiety. These are useful for delivering the gene expression inhibiting activity to cells, particularly hepatocytes, and more particularly in therapeutic applications. | 2009-08-13 |
20090203136 | MODULATING IMMUNE SYSTEM DEVELOPMENT AND FUNCTION THROUGH MICRORNA MIR-146 - The present disclosure relates to the finding that microRNA-146 plays a role in modulating the development and function of the immune system. Immune cell development and function can be modulated by delivery of microRNA-146 (miR-146) or antisense miR-146 to target immune cells or precursor cells. For example, in some embodiments, activity and/or proliferation of certain immune cells is regulated by administering miR-146 oligonucleotides or anti-miR-146 oligonucleotides. In other embodiments, pro-inflammatory cytokine expression in immune cells is regulated by administering a miR-146 oligonucleotide or anti-miR-146. In further embodiments, methods of regulating macrophage activity using antisense miR-146 are provided. Additional methods and compositions for regulating immune system function and development using miR-146 are disclosed. | 2009-08-13 |
20090203137 | COMPOUNDS FOR THE MODULATION OF BETA-CATENIN EXPRESSION - The invention relates to oligomer compounds (oligomers), which target beta-catenin mRNA in a cell, leading to reduced expression of beta-catenin. Reduction of beta-catenin expression is beneficial for a range of medical disorders, such as hyperproliferative disorders, such as cancer. The invention provides therapeutic compositions comprising oligomers and methods for modulating the expression of beta-catenin using said oligomers, including methods of treatment. | 2009-08-13 |
20090203138 | Small Interfering RNAs Targeting Feline Herpes Virus - The present application provides polynucleotides, compositions thereof and methods of treating feline herpes virus infections. In certain embodiments, the polynucleotides and compositions thereof can be used to reduce replication of feline herpes simplex virus 1 (FHV-1) in vivo and/or in vitro. | 2009-08-13 |
20090203139 | PRODUCTION OF FOUR CARBON ALCOHOLS USING IMPROVED STRAIN - Using screening of transposon random insertion mutants, genes involved in accumulation of (p)ppGpp were found to be involved in bacterial cell response to butanol. Reduced production of proteins with enzymatic activity for (p)ppGpp biosynthesis confers increased butanol tolerance. Bacterial strains with reduced (p)ppGpp accumulation and having a butanol or 2-butanone biosynthetic pathway are useful for production of butanol or 2-butanone. | 2009-08-13 |
20090203140 | Genomic editing in zebrafish using zinc finger nucleases - Disclosed herein are methods and compositions for genomic editing of one or more genes in zebrafish, using fusion proteins comprising a zinc finger protein and a cleavage domain or cleavage half-domain. Polynucleotides encoding said fusion proteins are also provided, as are cells comprising said polynucleotides and fusion proteins. | 2009-08-13 |
20090203141 | Generation of tumor-free embryonic stem-like pluripotent cells using inducible recombinant RNA agents - The present invention generally relates to a method for developing, generating and selecting tumor-free embryonic stem (ES)-like pluripotent cells using electroporation delivery of an inducible tumor suppressor mir-302 agent into mammalian cells. More particularly, the present invention relates to a method and composition for generating a Tet-On/Off recombinant transgene capable of expressing a manually re-designed mir-302 microRNA (miRNA)/shRNA agent under the control of doxycyclin (Dox) in human somatic/cancer cells and thus inducing certain specific gene silencing effects on the differentiation-associated genes and oncogenes of the cells, resulting in reprogramming the cells into an ES-like pluripotent state. | 2009-08-13 |
20090203142 | NUCLEOTIDE SEQUENCES OF A NEW CLASS OF DIVERGED DELTA-9 STEAROYL-ACP DESATURASE GENES - An isolated nucleic acid fragment encoding a diverged delta-9 fatty acid desaturase is disclosed. Also the construction of a chimeric gene encoding all or a portion of the diverged delta-9 fatty acid desaturase is disclosed, in sense or antisense orientation, wherein expression of the chimeric gene results in production of altered levels of the diverged delta-9 fatty acid desaturase in a transformed host cell. | 2009-08-13 |
20090203143 | TRANS-SPLICING MEDIATED PHOTODYNAMIC THERAPY - The present invention provides methods and compositions for conferring selective death on cells expressing a specific target precursor messenger RNA (selective target pre-mRNA). The compositions of the invention include pre-trans-splicing molecules (PTMs) designed to interact with a target precursor messenger RNA molecule (target pre-mRNA) expressed within a cell and mediate a trans-splicing reaction resulting in the generation of a novel chimeric mRNA molecule (chimeric mRNA) capable of encoding a light producing protein or enzyme. Cell death is further mediated by the presence of a photosensitizer which upon photoactivation produces cytotoxicity. | 2009-08-13 |
20090203144 | HIV-GAG CODON-OPTIMISED DNA VACCINES - The invention provides a nucleotide sequence that encodes an HIV- | 2009-08-13 |
20090203145 | METHODS FOR ANALYSIS OF VITAMINS - The invention relates to methods for determining the level of B vitamins in a test sample. The methods can include the steps of obtaining a water soluble vitamin fraction by extraction in acidic aqueous solution of a test sample, wherein the vitamin fraction comprises one or more B vitamins having at least a predetermined minimum concentration; adding a vitamin standard comprising one or more B vitamins of known quantity to a portion of the vitamin fraction of the test sample, wherein said vitamins in the vitamin standard comprise an isotope label and wherein the vitamin standard is added in an amount sufficient to determine the level of the corresponding vitamins in the test sample; and determining the level of one or more vitamins in the test sample corresponding to one or more of the vitamins in the vitamin standard using mass spectrometry. | 2009-08-13 |
20090203146 | NARROW BORE LAYER OPEN TUBE CAPILLARY COLUMN AND USES THEREOF - A polymer-based PLOT column prepared by in situ copolymerization of a functional monomer, which usually contains the retentive chemistries, and a crosslinking monomer, which enhances the strength of the polymer matrix, is disclosed. Styrenic based monomers such as styrene and divinylbenzene or meth/acrylic based monomers such as butyl or stearyl methacrylate and ethylene glycol dimethacrylate, are preferred. Columns of the invention can be prepared in a robust fashion with a very narrow i.d., e.g., 5-15 μm. Thus, they are suitable for commercial use in ultratrace LC/MS proteomic analysis. Columns according to the invention are characterized by high resolving power, high column-to-column reproducibility and relatively high loading capacity. When these columns are coupled on-line with, e.g., ESI-MS detection, the resulting systems provide high sensitivity for analysis of complex proteomic samples, even down to the low attomole to sub-attomole level. | 2009-08-13 |
20090203147 | BLOTTING DETECTION METHOD - It is an object of the present invention to provide a blotting detection method capable of quick detection of a very tiny amount of an analysis target. The present invention provides a blotting detection method which comprises moving an analyte held on a first carrier with a developing solution, and adsorbing the analyte onto a second carrier, wherein the analyte is labeled with metal fine particle and is detected by sensitization with use of a silver-containing compound and a reducing agent for silver ion, and the labeling substance having a size of not less than 1 μm and not more than 20 μm in the average particle size at the time of detection is detected. | 2009-08-13 |
20090203148 | Methods and Devices For Detection and Identification of Encoded Beads and Biological Molecules - The invention relates to methods and devices used in the sequencing, separation, detection, and identification of objects and biological molecules. In preferred embodiments, the invention relates to a DNA sequencing system based on cyclic sequencing by synthesis which is performed on beads in three-dimensional vessels and detected using monolithic multicapillary arrays. In other embodiments, the invention relates to a bead comprising two or more luminescent labels coupled to a nucleic acid sequence. In further embodiments, said luminescent labels are quantum dots. | 2009-08-13 |
20090203149 | ENHANCED METHODS FOR GAS AND/OR VAPOR PHASE ANALYSIS OF BIOLOGICAL ASSAYS - Processes for improved efficiencies as it relates to the analysis of small molecules whose concentration in the analysis solution is dependent upon the concentration of a target as determined through a liquid phase biological assays with vapor and/or gas phase analysis are disclosed. The process generally includes the competitive or non-competitive binding of target substances onto carrier particles functioning as substrates in the biological assay. Employing the carrier particles as substrates provides increased surface area for the reaction to occur; increased ease of washing steps; and allows for concentration of the increased surface area into a smaller reaction volume prior to introduction into the vapor and/or gas phase spectrometer such as an ion mobility spectrometer. | 2009-08-13 |
20090203150 | METHODS AND SYSTEMS FOR IDENTIFYING INSULIN MIMETICS - Methods are provided for identifying and selecting candidate molecules that activate glucose transport through binding of the insulin receptor at a site other than the insulin binding site. The methods include analyzing the properties of one or more candidate molecules in terms of the ability to bind the insulin receptor and activate glucose transport. Optionally the methods include, competitive assays in the presence of the glucose receptor, a candidate molecule, and one or more of insulin, alpha PGG and beta PGG. | 2009-08-13 |
20090203151 | IMMUNOASSAY METHOD - It is an object of the present invention to provide an immunoassay method which is capable of simultaneous quantification of a plurality of test substances under a same analysis condition, through adjustment of the measurement sensitivity/range by simply varying the size of particles for use as labels, without changing the spectra of these particles. The present invention provides an immunoassay method which comprises: simultaneously or step-by step developing respective of the plurality of the test substances and respective of labeling substance particles labeled with first binding substance against the respective of the plurality of the test substances on an insoluble carrier; capturing the test substances and the labeling substance particles in reaction portions on the insoluble carrier that has been immobilized with the respective of second binding substances against the respective of the plurality of the test substances at different positions; and measuring optical characteristic of the labeling substance particles, so as to simultaneously detect the plurality of the test substances, wherein the plurality of the test substances having different detection concentration ranges are simultaneously detected with use of the labeling substance particles which are different in the particle size corresponding to the test substances. | 2009-08-13 |
20090203152 | Method for Analyzing an Analyte Qualitatively and Quantitatively - A specific binding analysis method capable of controlling the amount of specific binding to freely setting the sensitivity, concentration range and the like in an analysis, and a device used therefore are provided. In order to optimize the amount of specific binding, the specific binding analysis method and the device used therefor restrain the amount and velocity of a sample passing, by capillarity, through a detection zone, by controlling the dimensions, ventilation resistance, hydrophilicity and the like in the portion of the device where the sample passes through. | 2009-08-13 |
20090203153 | METAL PARTICLE AND A TESTING METHOD USING THE SAME - An object of the present invention is to provide a metal particle with which a highly-sensitive testing method can be conducted, and a testing method using such metal particle. The present invention provides a metal particle, which is produced by coating a metal particle labeled with a molecule binding to an analyte with a mixture of two or more types of water-soluble polymer having a mercapto group, a dithiol group or a sulfide group and differing in molecular weight. | 2009-08-13 |
20090203154 | Method for Sensing a Chemical - This invention relates to a method for detecting an analyte in a sample. The method comprises the steps of exposing the sample to a transducer having a pyroelectric or piezoelectric element and electrodes which is capable of transducing a change in energy to an electrical signal, the transducer having at least one reagent proximal thereto, the reagent having a binding site which is capable of binding the analyte or a complex or derivative of the analyte, wherein at least one of the analyte or the complex or derivative of the analyte has a label attached thereto which is capable of absorbing the electromagnetic radiation generated by the radiation source to generate energy by non-radiative decay; irradiating the reagent with a series of pulses of electromagnetic radiation, transducing the energy generated into an electrical signal; detecting the electrical signal and the time delay between each pulse of electromagnetic radiation from the radiation source and the generation of the electric signal. The time delay between each of the pulses of electromagnetic radiation and the generation of the electric signal corresponds to the position of the analyte at any of one or more positions at different distances from the surface of the transducer. The label is a nanoparticle comprising a non-conducting core material and at least one metal shell layer. | 2009-08-13 |
20090203155 | LABELED PARTICLE OBTAINED BY IMMOBILIZING A FRAGMENTED ANTIBODY TO A LABELING SUBSTANCE - An object of the present invention is to provide a labeled particle having a high reactivity with an antigen and a suppressed non-specific adsorption, and an immunochromatographic method using the labeled particle. The present invention provides a labeled particle, wherein a fragmented antibody is immobilized to a labeling substance via a chemical bond. | 2009-08-13 |
20090203156 | METHODS FOR ACCURATELY MEASURING THE THICKNESS OF AN EPITAXIAL LAYER ON A SILICON WAFER - Methods for measuring thickness of an epitaxial layer of a wafer. An example method applies photoresist over the epitaxial layer, and then portions of the photoresist within a sacrificial region of the wafer are removed. Next, the epitaxial layer is isotropically etched through the removed portions of the photoresist until a portion of the silicon handle layer is exposed. The remaining photoresist layer is removed. Then, the silicon handle layer is anisotropically etched to form a well. Profile information of the epitaxial layer and the etched handle layer generated. Next, the thickness of the epitaxial layer is determined based on the profile information. The acceptability of the epitaxial layer may be determined based on the determined thickness of the epitaxial layer. If the epi layer is acceptable, then the geometry of devices that are to be etched into the epitaxial layer are determined based on the determined thickness. | 2009-08-13 |
20090203157 | DISPLAY APPARATUS - A configuration for decreasing the leakage electric current of a transistor for control for controlling an electric potential holding operation of a control electrode of a transistor for drive for flowing an electric current through a display device by adjusting the output electric potential of an electric potential source is disclosed. | 2009-08-13 |
20090203158 | METHOD FOR FABRICATING A PHOTONIC CRYSTAL OR PHOTONIC BANDGAP VERTICAL-CAVITY SURFACE-EMITTING LASER - The invention relates to fabrication of VCSELs. It provides a method for fabricating a VCSEL that contains a micro/nano-structured mode selective lateral layer, where the micro/nano-structured layer is obtained by well controlled local etching. The invention enables control of the micro/nano-structured layer thickness with very high precision. In particular, the invention relates to a method for fabricating a VCSEL with a micro/nano-structured mode selective layer for controlling the VCSELs transverse electromagnetic modes. | 2009-08-13 |
20090203159 | METHOD OF PRODUCING SEMICONDUCTOR OPTICAL DEVICE - The invention discloses a method of producing on a substrate a semiconductor optical device having a laser diode and an EA optical modulator. An etched side face of a first semiconductor portion is formed. Then, for example, a first optical confinement layer and an active layer both for the EA optical modulator are grown by the metal organic vapor phase epitaxy method. The first optical confinement layer is grown by supplying hydrogen chloride in addition to a material gas. When the first optical confinement layer is grown, the formation of a thick semiconductor layer along the etched side face, which is an abnormally grown semiconductor layer, is decreased. Subsequently, the active layer for the EA optical modulator is grown. This method can suppress the active layer for the EA optical modulator from bending caused by the abnormally grown semiconductor layer. | 2009-08-13 |
20090203160 | SYSTEM FOR DISPLAYING IMAGES INCLUDING THIN FILM TRANSISTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A system for displaying images. The system comprises a thin film transistor (TFT) device comprising a substrate comprising a driving circuit region and a pixel region. First and second active layers are disposed on the substrate in the driving circuit region and in the pixel region, respectively. The first active layer has a grain size greater than that of the second active layer. Two gate structures are disposed on the first and second active layers, respectively, in which each gate structure comprises a stack of a gate dielectric layer and a gate layer. A reflector is disposed on the substrate under the first active layer and insulated from the first active layer. A method for fabricating a system for displaying images including the TFT device is also disclosed. | 2009-08-13 |
20090203161 | SEMICONDUCTOR LASER DIODE WITH A RIDGE STRUCTURE BURIED BY A CURRENT BLOCKING LAYER MADE OF UN-DOPED SEMICONDUCTOR GROWN AT A LOW TEMPERATURE AND METHOD FOR PRODUCING THE SAME - The present invention provides a laser diode with a current blocking layer without a pn-junction. The laser diode includes a lower cladding layer, an active region and an upper cladding layer on the GaAs substrate in this order. The active region includes first and second regions. The upper cladding layer, which includes a ridge structure, locates on the first region, while, the current blocking region is on the second region of the active region so as to sandwich the ridge structure. The current blocking layer of the invention is made of one of un-doped GaInP and un-doped AlGaInP grown at a relatively low temperature and shows high resistance greater than 10 | 2009-08-13 |
20090203162 | OPTICAL ELEMENT, METHOD FOR MANUFACTURING OPTICAL ELEMENT AND SEMICONDUCTOR LASER DEVICE USING THE OPTICAL ELEMENT - The present invention provides an optical element which can reliably acquire a difference of refractive indices between a member under a photonic crystal layer and the crystal layer without using such a stacking technique as in conventional processes; a method for manufacturing the optical element; and a semiconductor laser device with the use of the optical element. The optical element has the first layer | 2009-08-13 |
20090203163 | METHOD FOR MAKING A TRANSDUCER - A method for forming a transducer including the step of providing a semiconductor-on-insulator wafer including first and second semiconductor layers separated by an electrically insulating layer. The method further includes depositing or growing a piezoelectric film or piezoresistive film on the wafer, depositing or growing an electrically conductive material on the piezoelectric or piezoresistive film to form at least one electrode, and depositing or growing a bonding layer including an electrical connection portion that is located on or is electrically coupled to the electrode. The method further includes the step of providing a ceramic substrate having a bonding layer located thereon, the bonding layer including an electrical connection portion and being patterned in a manner to generally match the bonding layer of the semiconductor-on-insulator wafer. The method also includes causing the bonding layer of the semiconductor-on-insulator wafer and the bonding layer of the substrate to bond together to thereby mechanically and electrically couple the semiconductor-on-insulator wafer and the substrate to form the transducer, wherein the electrical connection portions of the bonding layers of the semiconductor-on-insulator wafer and the substrate are fluidly isolated from the surrounding environment by the bonding layers. | 2009-08-13 |
20090203164 | ELECTROLYTE COMPOSITION FOR DYE-SENSITIZED SOLAR CELL, DYE-SENSITIZED SOLAR CELL INCLUDING SAME, AND METHOD OF PREPARING SAME - An electrolyte composition for a dye sensitized solar cell according to one embodiment includes a first polymer or a non-volatile liquid compound having a weight average molecular weight of less than or equal to 500, a second polymer having a weight average molecular weight of more than or equal to 2000, inorganic nano-particles, and a redox derivative. | 2009-08-13 |
20090203165 | METHOD TO IMPROVE FLEXIBLE FOIL SUBSTRATE FOR THIN FILM SOLAR CELL APPLICATIONS - A thin film solar cell including a Group IBIIIAVIA absorber layer on a defect free base including a stainless steel substrate is provided. The stainless steel substrate of the base is surface treated to remove the surface roughness such as protrusions that cause shunts. Before removing the protrusions, a thin protective ruthenium film is first deposited on the recessed surface portions of the substrate to protect these portions during the following protrusion removal. The protrusions on the surface receives very little or no ruthenium during the deposition. After the ruthenium film is formed, the protrusions are etched and removed by an etchant which only attacks the stainless steel but neutral to the ruthenium film. A contact layer is formed over the ruthenium layer and the exposed portions of the substrate to complete the base. | 2009-08-13 |
20090203166 | Zinc Oxide Materials and Methods for Their Preparation - A method for preparing p-type zinc oxide (ZnO) is described. The p-type ZnO is prepared by implanting low energy acceptor ions into an n-type ZnO substrate and annealing. In an alternative embodiment, the n-type ZnO substrate is pre-doped by implanting low energy donor ions. The p-type ZnO may have application in various optoelectronic devices, and a p-n junction formed from the p-type ZnO prepared as described above and a bulk n-type ZnO substrate is also described. | 2009-08-13 |
20090203167 | Method for Manufacturing Bonded Substrate - The present invention provides a method for manufacturing a bonded substrate that is a method for manufacturing a bonded substrate where an active layer wafer is bonded to a support substrate wafer, comprising: a first step of providing a groove on an inner side on a surface of the active layer wafer along an outer peripheral portion over an entire circumference; a second step of determining a surface where the groove is formed as a bonding surface and bonding the active layer wafer to the support substrate wafer; and a third step of reducing a film thickness of the active layer wafer and removing an unbonded portion on an outer side of the groove of the active layer wafer. As a result, there is provided the method for manufacturing a bonded substrate that can simplify processes, avoid breakage, cracks, or particle generation, and manage a shape of an edge portion of an active layer wafer when reducing a film thickness of the active layer wafer. | 2009-08-13 |
20090203168 | Manufacturing Method for a Secure-Digital (SD) Flash Card with Slanted Asymmetric Circuit Board - A flash-memory device has a printed-circuit board assembly (PCBA) with a PCB with a flash-memory chip and a controller chip. The controller chip includes an input/output interface circuit to an external computer over a Secure-Digital (SD) interface, and a processing unit to read blocks of data from the flash-memory chip. The PCBA is encased inside an upper case and a lower case, with SD contact pads on the PCB that fit through contact openings in the upper case. Supporting end ribs under each of the SD contact pads and middle ribs support the PCB at a slanted angle to the centerline of the device. The PCB slants upward at the far end to allow more thickness for the chips mounted to the bottom surface of the PCB, and slants downward at the insertion end to position the SD contact pads near the centerline. | 2009-08-13 |
20090203169 | FLIP CHIP MOUNTING BODY AND METHOD FOR MOUNTING SUCH FLIP CHIP MOUNTING BODY AND BUMP FORMING METHOD - In a flip chip mounted body in which a semiconductor chip ( | 2009-08-13 |
20090203170 | FLIP CHIP MOUNTING METHOD, FLIP CHIP MOUNTING APPARATUS AND FLIP CHIP MOUNTING BODY - A flip chip mounting method includes holding a circuit board ( | 2009-08-13 |
20090203171 | SEMICONDUCTOR DEVICE FABRICATING METHOD - A semiconductor device fabricating method includes forming a plurality of semiconductor devices that include one semiconductor chip and a metal plate having an opening portion that surrounds a region where the semiconductor chip is provided, by cutting, at regions where a frame portion exists, a plate-shaped member that includes: a wiring layer including a wiring portion and an insulating portion; a plurality of semiconductor chips disposed on one surface of the wiring layer; a metal plate disposed at a surface of the wiring layer at a side at which the semiconductor chips are provided, and having a plurality of opening portions that surround regions where the semiconductor chips are provided and the frame portion that forms the opening portions; and a sealing resin layer provided so as to seal at least gaps between the semiconductor chips and the metal plate. | 2009-08-13 |
20090203172 | Enhanced Die-Up Ball Grid Array and Method for Making the Same - Methods of assembling a ball grid array (BGA) package is provided. One method includes providing a tape substrate that has a first surface and a second surface, attaching a first surface of a stiffener to the first substrate surface, mounting an IC die to the second stiffener surface, mounting a heat spreader to the IC die, and attaching a plurality of solder balls to the second substrate surface. | 2009-08-13 |
20090203173 | MOLD CLEANING SHEET AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE USING THE SAME - A cleaning sheet with frame for cleaning a molding die comprising a cleaning heat main body that covers the entire mating surface of a molding die and a reinforcing frame which can be disposed along the peripheral edge to the outside of the plural cavities of the mating surface of the molding die, the cleaning sheet main body being formed with first through holes at positions corresponding to the cavities of the molding die, air vent slits and flow cavity recesses at positions corresponding to the air vents of the cavities, second through holes at positions corresponding to the pots of the molding die, and slits at positions corresponding to the runners of the molding die, thereby capable of improving the cleaning effect of the molding die and shortening the time for the cleaning operation to improve the productivity. | 2009-08-13 |
20090203174 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing an insulating film, which is used as an insulating film used for a semiconductor integrated circuit, whose reliability can be ensured even though it has small thickness, is provided. In particular, a method for manufacturing a high-quality insulating film over a substrate having an insulating surface, which can be enlarged, at low substrate temperature, is provided. A monosilane gas (SiH | 2009-08-13 |
20090203175 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - TFT structures optimal for driving conditions of a pixel portion and driving circuits are obtained using a small number of photo masks. First through third semiconductor films are formed on a first insulating film. First shape first, second, and third electrodes are formed on the first through third semiconductor films. The first shape first, second, third electrodes are used as masks in first doping treatment to form first concentration impurity regions of one conductivity type in the first through third semiconductor films. Second shape first, second, and third electrodes are formed from the first shape first, second, and third electrodes. A second concentration impurity region of the one conductivity type which overlaps the second shape second electrode is formed in the second semiconductor film in second doping treatment. Also formed in the second doping treatment are third concentration impurity regions of the one conductivity type which are placed in the first and second semiconductor films. Fourth and Fifth concentration impurity regions having the other conductivity type that is opposite to the one conductivity type are formed in the third semiconductor film in third doping treatment. | 2009-08-13 |
20090203176 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To suppress generation of dangling bonds, the present invention relates to a method for manufacturing a semiconductor device including the steps of: forming a semiconductor film; forming a gate insulating film and a gate electrode over the semiconductor film; forming an impurity region in the semiconductor film by addition of an impurity element having one conductivity type thereto; forming an insulating film containing fluorine with the semiconductor film, the gate insulating film, and the gate electrode covered therewith; heating the semiconductor film and the insulating film containing fluorine; and forming a wiring, which is electrically connected to the impurity region, over the insulating film containing fluorine. The insulating film containing fluorine is any one of a silicon oxide film containing fluorine, a silicon oxide film containing fluorine and nitrogen, or a silicon nitride film containing fluorine. | 2009-08-13 |
20090203177 | THIN-FILM SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method of manufacturing a thin-film semiconductor device, including forming a crystallized region on a transparent insulating substrate, implanting an impurity into the crystallized region and an amorphous semiconductor layer to form a source diffusion region and a drain diffusion region in the crystallized region, subjecting the resultant structure to heat treatment, thereby not only activating the impurity implanted in the crystallized region and the amorphous semiconductor layer but also restoring crystallinity of only a portion of the amorphous semiconductor layer which is formed on the crystallized region to thereby turn the portion into a polycrystalline semiconductor layer, and subjecting the resultant surface to selective etching to thereby leave only the polycrystalline semiconductor layer and to remove the amorphous semiconductor layer formed on other regions, thereby forming, in a self-aligned manner, a stacked source diffusion layer and a stacked drain diffusion layer. | 2009-08-13 |
20090203178 | Memory device and method of manufacturing the same - A example embodiment may provide a memory device that may include an active pattern on a semiconductor substrate, a first charge trapping layer pattern on the active pattern, a first gate electrode on the first charge trapping layer pattern, a second charge trapping layer pattern on a sidewall of the active pattern in a first direction, a second gate electrode on the second charge trapping layer pattern in the first direction, and/or a source/drain region in the active pattern. The memory device may have improved integration by forming a plurality of charge trapping layer patterns on the same active pattern. | 2009-08-13 |
20090203179 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In this invention, the semiconductor device is provided with a gate electrode formed on a gate insulating film in a region sectioned by an element isolation formed on a semiconductor layer of the first conduction type, and a source region and a drain region of the second conduction type. At least one of the source region and the drain region has a first low concentration region and a high concentration region. Also, the semiconductor device of the present invention is provided with a second low concentration region of the second conduction type between a channel stopper region formed below the element isolation and the source region, and between the channel stopper region and the drain region. The semiconductor layer immediately below the gate electrode projects to the channel stopper region side along the gate electrode, and the semiconductor layer and the channel stopper region make contact with each other. | 2009-08-13 |
20090203180 | MOS TRANSISTOR HAVING PROTRUDED-SHAPE CHANNEL AND METHOD OF FABRICATING THE SAME - A MOS transistor that has a protruding portion with a favorable vertical profile and a protruded-shape channel that requires no additional photolithography process, and a method of fabricating the same are provided. A first mask that defines an isolation region of a substrate is overall etched to form a second mask with a smaller width than the first mask. Then, the substrate is etched to a predetermined depth while using the second mask as an etch mask, thereby forming the protruding portion. Without performing a photolithography process, the protruding portion has a favorable profile and the protruding height of an isolation layer is adjusted to be capable of appropriately performing ion implantation upon the protruding portion. | 2009-08-13 |
20090203181 | Semiconductor device manufacturing method, wiring and semiconductor device - In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film. | 2009-08-13 |
20090203182 | Method of manufacturing transistor having metal silicide and method of manufacturing a semiconductor device using the same - In a method of manufacturing a transistor and a method of manufacturing a semiconductor device using the same, the method may include forming a preliminary metal silicide pattern on a single-crystalline silicon substrate and on a polysilicon pattern, and partially etching the preliminary metal silicide pattern to form a first metal silicide pattern on the substrate and a second metal silicide pattern on the polysilicon pattern, the second metal silicide pattern having a line width the same as or smaller than that of the polysilicon pattern. The method may include the transistor having no metal silicide residue on the spacer. Accordingly, an operation failure due to the residue may be prevented or reduced. | 2009-08-13 |
20090203183 | Method for integrating SIGE NPN and Vertical PNP Devices - According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device. | 2009-08-13 |
20090203184 | Self-Aligned Epitaxially Grown Bipolar Transistor - The illumination system has a light source ( | 2009-08-13 |
20090203185 | METHOD FOR FABRICATING DEVICE STRUCTURES HAVING A VARIATION IN ELECTRICAL CONDUCTIVITY - A method for forming device structures having a variation in electrical conductivity includes forming a device structure and a radiation absorbing layer overlying the device structure. The radiation absorbing layer has a spatial variation and radiation absorbing characteristics, such that upon irradiating the device structure, the radiation absorbing layer attenuates the intensity of the radiation so that a variation in dopant activation takes place within the device structure. Accordingly, device structures are formed having a variation in electrical resistance independent of the physical size of the device structures. | 2009-08-13 |
20090203186 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device, including: forming a first well of a second conduction type and a second well of a first conduction type on a semiconductor substrate of the first conduction type, forming a gate oxide corresponding to each element on a surface of the semiconductor substrate, forming trenches by etching at forming locations of first and second trench isolating regions respectively at a first depth larger than a depth of a diffusion layer formed in a memory-cell forming region within the second well and smaller than a depth of a diffusion layer of a transistor of a peripheral circuit region, executing additional etching at a forming location of the second trench isolating region so that a second depth larger than the first depth is obtained and doping the trenches at the forming locations of the first and second trench isolating regions respectively, with a doping agent, thereby executing a planarization process. | 2009-08-13 |
20090203187 | Method of Manufacturing SOI Substrate - To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. | 2009-08-13 |
20090203188 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches. | 2009-08-13 |
20090203189 | METHODS OF MANUFACTURING TRENCH ISOLATION STRUCTURES USING SELECTIVE PLASMA ION IMMERSION IMPLANTATION AND DEPOSITION (PIIID) - A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches. | 2009-08-13 |
20090203190 | Method of forming a mask stack pattern and method of manufacturing a flash memory device including an active area having rounded corners - A method of forming a mask stack pattern and a method of manufacturing a flash memory device including an active area having rounded corners are provided. The method of manufacture including forming a mask stack pattern defining an active region, the mask stack pattern having a pad oxide layer formed on a semiconductor substrate, a silicon nitride layer formed on the pad oxide layer and a stack oxide layer formed on the silicon nitride layer, oxidizing a surface of the semiconductor substrate exposed by the mask stack pattern and lateral surfaces of the silicon nitride layer such that corners of the active region are rounded, etching the semiconductor substrate having an oxidized surface to form a trench in the semiconductor substrate, forming a device isolation oxide layer in the trench, removing the silicon nitride layer from the semiconductor substrate, and forming a gate electrode in a portion where the silicon nitride layer is removed. | 2009-08-13 |
20090203191 | METHOD FOR MANUFACTURING SOI SUBSTRATE - A semiconductor substrate and a base substrate made from an insulator are prepared; an oxide film containing a chlorine atom is formed over the semiconductor substrate; the semiconductor substrate is irradiated with accelerated ions through the oxide film to form an embrittled region at a predetermined depth from a surface of the semiconductor substrate; plasma treatment of the oxide film is performed by applying a bias voltage; a surface of the semiconductor substrate and a surface of the base substrate are disposed opposite to each other to bond a surface of the oxide film and the surface of the base substrate to each other; and heat treatment is performed to cause separation along the embrittled region after bonding the surface of the oxide film and the surface of the base substrate to each other, thereby forming a semiconductor film over the base substrate with the oxide film interposed therebetween. | 2009-08-13 |
20090203192 | Crack Stop Trenches - Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels. | 2009-08-13 |
20090203193 | LASER PROCESSING METHOD - A laser processing method including a first step of forming a first groove and a second step of forming a second groove on the workpiece. In the first step, the laser beam is intermittently applied to the first street except the intersections between the first street and the second street, thereby forming a discontinuous groove as the first groove in such a manner that each intersection is not grooved. In the second step, the laser beam is continuously applied to the second street, thereby forming a continuous groove as the second groove intersecting the first groove in such a manner that each intersection is grooved by the second groove. In the second step, heat generated at a portion immediately before each intersection is passed through the intersection to be dissipated forward, thereby suppressing overheating at this portion. | 2009-08-13 |
20090203194 | TRANSPARENT CONDUCTIVE FILM DEPOSITION APPARATUS, FILM DEPOSITION APPARATUS FOR CONTINUOUS FORMATION OF MULTILAYERED TRANSPARENT CONDUCTIVE FILM, AND METHOD OF FORMING THE FILM - Raw materials are economized and a film deposition rate is improved while maintaining film evenness and high film quality. | 2009-08-13 |
20090203195 | Hybrid nanocomposite semiconductor material, and method of producing inorganic semiconductor therefor - Hybrid semiconductor materials have an inorganic semiconductor incorporated into a hole-conductive fluorene copolymer film. Nanometer-sized particles of the inorganic semiconductor may be prepared by mixing inorganic semiconductor precursors with a steric-hindering coordinating solvent and heating the mixture with microwaves to a temperature below the boiling point of the solvent. | 2009-08-13 |
20090203196 | Fabrication of metallic hollow nanoparticles - Metal and semiconductor nanoshells, particularly transition metal nanoshells, are fabricated using dendrimer molecules. Metallic colloids, metallic ions or semiconductors are attached to amine groups on the dendrimer surface in stabilized solution for the surface seeding method and the surface seedless method, respectively. Subsequently, the process is repeated with additional metallic ions or semiconductor, a stabilizer, and NaBH | 2009-08-13 |
20090203197 | NOVEL METHOD FOR CONFORMAL PLASMA IMMERSED ION IMPLANTATION ASSISTED BY ATOMIC LAYER DEPOSITION - Embodiments of the invention provide a novel apparatus and methods for forming a conformal doped layer on the surface of a substrate. A substrate is provided to a process chamber, and a layer of dopant source material is deposited by plasma deposition, atomic layer deposition, or plasma-assisted atomic layer deposition. The substrate is then subjected to thermal processing to activate and diffuse dopants into the substrate surface. | 2009-08-13 |
20090203198 | SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD USING THE SAME - A semiconductor manufacturing apparatus and method are disclosed in which the apparatus comprises a reaction tube configured to hold one or more wafers, a spray pipe coupled to the reaction tube for spraying reaction gas into the reaction tube, and a plurality of electrodes used to convert the reaction gas to a plasma state. The electrodes include a cathode and an anode plasma electrode arranged for exciting reaction gas exiting the spray pipe to a plasma state prior to entry into the reaction tube. A switching device is coupled to both the cathode and anode plasma electrode and configured to switch a polarity of a high voltage applied to each of the cathode and anode to prevent a build-up of positive plasma reaction gas ions on the cathode during repeated processing steps. | 2009-08-13 |
20090203199 | ION BEAM IRRADIATING APPARATUS, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - An ion beam irradiating apparatus has a field emission electron source | 2009-08-13 |
20090203200 | GATE PATTERNING SCHEME WITH SELF ALIGNED INDEPENDENT GATE ETCH - A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation. | 2009-08-13 |
20090203201 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a dielectric film containing a porogen material above a substrate; removing a portion of the porogen material contained in the dielectric film so as to make a concentration of the porogen material higher in a part on a lower side of the dielectric film than in another part on a higher side of the dielectric film; forming an opening halfway in the dielectric film from which a portion of the porogen material has been removed to leave the dielectric film below a bottom of the opening; removing or polymerizing a remainder of the porogen material contained in the dielectric film; and etching the bottom of the opening after removing or polymerizing the remainder of the porogen material. | 2009-08-13 |
20090203202 | Strained Gate Electrodes in Semiconductor Devices - Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode. | 2009-08-13 |
20090203203 | METHOD FOR THE FABRICATION OF A TRANSISTOR GATE THAT INCLUDES THE BREAKDOWN OF A PRECURSOR MATERIAL INTO AT LEAST ONE METALLIC MATERIAL, USING AT LEAST ONE - A microelectronic method for the fabrication of a transistor gate using a precursor material that is suitable for being broken down into at least one metallic material after having been exposed to an electron beam. The invention applies in particular to the fabrication of multi-channel transistors, of the FinFET, suspended-channel, ITS or GAA type. | 2009-08-13 |
20090203204 | Methods of manufacturing semiconductor device having recess channel array transistor - Methods of manufacturing a semiconductor device having an RCAT are provided. The method includes forming a first recess having a first depth formed in an active region of a semiconductor substrate, and a second recess having a second depth that is less than the first depth formed in an isolation layer. The depth of the second recess is decreased by removing the isolation layer from the upper surface of the isolation layer by a desired thickness. A gate dielectric layer is formed on an inner wall of the first recess and a gate is formed on the gate dielectric layer. | 2009-08-13 |
20090203205 | Method for producing a floating gate with an alternation of lines of first and second materials - A diblock copolymer layer comprising at least two polymers and having a lamellar structure perpendicularly to a substrate is deposited on a first gate insulator formed on the substrate. One of the polymers of the diblock copolymer layer is then eliminated to form parallel grooves in the copolymer layer. The grooves are filled by a first metallic or semi-conductor material and the rest of the copolymer layer is eliminated. A second dielectric material is deposited to form a second gate insulator. The second gate insulator of the floating gate then comprises an alternation of parallel first and second lines respectively of the first and second materials, the second material encapsulating the lines of the first material. | 2009-08-13 |
20090203206 | FABRICATION OF SEMICONDUCTOR DEVICES USING ANTI-REFLECTIVE COATINGS - Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface of a substrate. A layer which is transparent to a wavelength of light used during the photolithographic process is provided over the first anti-reflective coating, and a photosensitive material is provided above the transparent layer. The photosensitive material is exposed to a source of radiation including the wavelength of light. Preferably, the first anti-reflective coating extends beneath substantially the entire transparent layer. The complex refractive index of the first anti-reflective coating can be selected to maximize the absorption at the first anti-reflective coating to reduce notching of the photosensitive material. | 2009-08-13 |
20090203207 | Method for manufacturing semiconductor device - A contact hole, after hole etching, is subjected to light etching using a process gas containing a fluorocarbon-based gas and oxygen, with the oxygen being enriched, under condition without applying bias. Then, reaction products ( | 2009-08-13 |
20090203208 | COPPER ALLOY FOR WIRING, SEMICONDUCTOR DEVICE, METHOD FOR FORMING WIRING, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A wiring metal contains a polycrystal of copper (Cu) as a primary element and an additional element other than Cu, and concentration of the additional element is, at crystal grain boundaries composing the Cu polycrystal and in vicinities of the crystal grain boundaries, higher than that of the inside of the crystal grains. The additional element is preferably at least one element selected from a group consisting of Ti, Zr, Hf, Cr, Co, Al, Sn, Ni, Mg, and Ag. This Cu wiring is formed by forming a Cu polycrystalline film, forming an additional element layer on this Cu film, and diffusing this additional element from the additional element layer into the Cu film. This copper alloy for wiring is preferred as metal wiring formed for a semiconductor device. | 2009-08-13 |
20090203209 | Semiconductor device and method of manufacturing the same - A semiconductor device which is capable of avoiding an increase in pattern ratio and allowing wiring dummy patterns to improve global steps developed by CMP upon insertion of the dummy patterns which are different from an actual wiring pattern. The semiconductor device has a configuration wherein a gate wiring pattern is formed on a semiconductor substrate, a plurality of dummy patterns are provided therearound, and a BPSG oxide film which is flattened by CMP is formed on the gate wiring pattern and the dummy patterns as an interlayer insulating film. In the semiconductor device, the dummy patterns are formed so as to include pattern non-forming regions such as slits. | 2009-08-13 |
20090203210 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method of forming a metal interconnection that has a favorable cross-sectional shape is provided without the fear of side etching, even in a sparse arrangement of metal interconnections. The method, the following structure is employed. A region for placing a dummy metal interconnection is provided close to a region in which a metal interconnection is formed. A trench is formed in the dummy metal interconnection region and a resist pattern for the metal interconnection is then formed, giving the resist above the trench a large surface area per unit area. The metal interconnection is subsequently formed by dry etching in which an organic component from the resist above the trench forms a solid sidewall protection film, permitting anisotropic etching. The metal interconnection can thus have a favorable cross-sectional shape. | 2009-08-13 |
20090203211 | MULTI-CHAMBER SYSTEM HAVING COMPACT INSTALLATION SET-UP FOR AN ETCHING FACILITY FOR SEMICONDUCTOR DEVICE MANUFACTURING - A multi-chamber system of an etching facility for manufacturing semiconductor devices occupies a minimum amount of floor space in a clean room by installing a plurality of processing chambers in multi-layers and in parallel along a transfer path situated between the processing chambers. The multi-layers number | 2009-08-13 |
20090203212 | Surface Grinding Method and Manufacturing Method for Semiconductor Wafer - The present invention provides a surface grinding method for a semiconductor wafer, which performs surface grinding with respect to a semiconductor wafer sliced into a thin plate shape, wherein at least a cleaning process for removing a heavy metal is performed before carrying out surface grinding of the semiconductor wafer, and a surface grinding process is carried out after performing the cleaning process. As a result, there are provided the surface grinding method and a manufacturing method for a semiconductor wafer, which can effectively reduce a contaminant, which has adhered to a surface of the semiconductor wafer, e.g., a heavy metal such as Cu. | 2009-08-13 |
20090203213 | Slurry composition for chemical-mechanical polishing and method of chemical-mechanical polishing with the same - Provided may be a slurry composition for chemical mechanical polishing (CMP) and a CMP method using the same. For example, the slurry composition may include a first polishing inhibitor including at least one of PO | 2009-08-13 |
20090203214 | SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE OBTAINED BY SUCH A METHOD - The invention relates to a method of manufacturing a semiconductor device ( | 2009-08-13 |
20090203215 | METAL POLISHING SLURRY AND CHEMICAL MECHANICAL POLISHING METHOD - A metal polishing slurry which is capable of simultaneously realizing a high polishing speed and reduced dishing in the polishing of a subject to be polished is provided. The metal polishing slurry includes a compound represented by the following general formula (1): | 2009-08-13 |
20090203216 | PHOTOLITHOGRAPHIC SYSTEMS AND METHODS FOR PRODUCING SUB-DIFFRACTION-LIMITED FEATURES - Systems and methods for near-field photolithography utilize surface plasmon resonances to enable imaging of pattern features that exceed the diffraction limit. An example near-field photolithography system includes a plasmon superlens template including a plurality of opaque features to be imaged onto photosensitive material and a metal plasmon superlens. The opaque features and the metal superlens are separated by a polymer spacer layer. Light propagates through the superlens template to form an image of the opaque features on the other side of the superlens. An intermediary layer including solid or liquid material is interposed between the superlens and a photoresist-coated semiconductor wafer to reduce damage resulting from contact between the superlens template and the photoresist-coated semiconductor wafer. | 2009-08-13 |
20090203217 | NOVEL SELF-ALIGNED ETCH METHOD FOR PATTERNING SMALL CRITICAL DIMENSIONS - A method is disclosed for etching an integrated circuit structure within a trench. A layer to be etched is applied over the structure and within the trench. A CF-based polymer is deposited over the layer to be etched followed by deposition of a capping layer of SiOCl-based polymer. The CF-based polymer reduces the width of the trench to such an extent that little or no SiOCl-based polymer is deposited at the bottom of the trench. An O | 2009-08-13 |
20090203218 | PLASMA ETCHING METHOD AND COMPUTER-READABLE STORAGE MEDIUM - A plasma etching method includes etching an etching target layer formed on a substrate to be processed by a plasma of a processing gas by using an ArF photoresist as a mask. The etching target layer is a silicon nitride layer or silicon oxide layer, and the processing gas contains at least a CF | 2009-08-13 |
20090203219 | PLASMA ETCHING METHOD, PLASMA ETCHING APPARATUS AND COMPUTER-READABLE STORAGE MEDIUM - A plasma etching method includes etching a silicon layer formed on a substrate to be processed through a patterned mask layer by using a plasma of a processing gas. The processing gas contains at least a CF | 2009-08-13 |
20090203220 | Method for Reducing an Unevenness of a Surface and Method for Making a Semiconductor Device - In order to reduce an unevenness of a surface of a body, a sacrificial layer is applied to the surface, a chemical-mechanical polishing of the sacrificial layer and material of said body is performed to reduce the unevenness of the surface, and a remainder of the sacrificial layer, if any, may be removed. | 2009-08-13 |
20090203221 | APPARATUS AND METHOD FOR INCORPORATING COMPOSITION INTO SUBSTRATE USING NEUTRAL BEAMS - An apparatus and method for incorporating a composition into a substrate using neutral beams are provided to repeatedly process an oxide layer using the neutral beams having low energy to minimize electrical damage to the oxide layer and improve characteristics of the oxide layer. The apparatus is mounted in a plasma generating chamber, and includes: an ion beam generating gas inlet, which injects a gas for generating ion beams; an ion source, which generates the ion beams having a polarity from the gas introduced through the ion beam generating gas inlet; a grid assembly, which is installed on one end of the ion source; a reflector, which is aligned with the grid assembly and converts the ion beams to the neutral beams; and a stage, on which the substrate is placed on a traveling path of the neutral beams. Formation of the oxide layer and application of the neutral beams are repeatedly performed on the substrate so as to improve the characteristics of the oxide layer. | 2009-08-13 |
20090203222 | METHOD OF FORMING DIELECTRIC FILMS, NEW PRECURSORS AND THEIR USE IN SEMICONDUCTOR MANUFACTURING - Method of deposition on a substrate, of a metal containing dielectric film comprising a compound of the formula (I): | 2009-08-13 |
20090203223 | SUBSTRATE MOUNTING TABLE FOR PLASMA PROCESSING APPARATUS, PLASMA PROCESSING APPARATUS AND INSULATING FILM FORMING METHOD - A substrate mounting table includes an electrostatic chuck for attracting and holding a target substrate and a base for holding the electrostatic chuck thereon. The base includes a protruding portion having a large height; and an outer peripheral surface provided around the protruding portion at a position lower than the protruding portion by a preset height. A thermally sprayed film having a thickness equivalent to a height difference between the protruding portion and the outer peripheral surface is deposited on the outer peripheral surface such that the thermally sprayed film becomes continuous with the protruding portion. The electrostatic chuck is formed by installing an electrode between insulating members, and the electrostatic chuck is fixed to the base by using an adhesive to cover a boundary between a top surface of the protruding portion and a surface of the thermally sprayed film. | 2009-08-13 |