33rd week of 2009 patent applcation highlights part 55 |
Patent application number | Title | Published |
20090204730 | MANUAL PROVISION METHOD, PERIPHERAL DEVICE, AND CONTROL PROGRAM - A terminal device used by a user transmits identification information on an application used along with a multi-function peripheral by the terminal device to that multi-function peripheral. The multi-function peripheral then transmits, to the terminal device, for-display manual data on a manual corresponding to the application indicated by the identification information received from the terminal device. | 2009-08-13 |
20090204731 | AUTOMATICALLY DISABLING INPUT/OUTPUT SIGNAL PROCESSING BASED ON THE REQUIRED MULTIMEDIA FORMAT - A system and method operable to automatically disable input/output signal processing based on the required data format is provided. The need for an input/output module, such as an encoder, required to process input signal having a first data format (i.e. multimedia format) and produce an output signal having a second format (i.e. multimedia format) is determined. When the input/output module is not required to produce the output signal in the second format, the input/output module is disabled. | 2009-08-13 |
20090204732 | Single-Chip Multi-Media Card/Secure Digital (MMC/SD) Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage - A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program. | 2009-08-13 |
20090204733 | PATH MAINTENANCE MECHANISM - In the computer system including a host computer and a storage system, the storage system includes a physical disk and a disk controller, and provides a storage area of the physical disk as at least one logical unit. The processor obtains, at a first time point and a second time point different from the first time point, a relation between a logical path and a component through which the logical path passes, stores, as logical path connection information, the relations obtained at the first time point and the second time point, refers to the logical path connection information to compare the logical paths existing at the first time point and the logical paths existing at the second time point with each other, and specifies the logical path which does not exist at the second time point among the logical paths existing at the first time point. | 2009-08-13 |
20090204734 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR ENHANCED SHARED STORE BUFFER MANAGEMENT SCHEME WITH LIMITED RESOURCES FOR OPTIMIZED PERFORMANCE - The exemplary embodiment of the present invention provides a storage buffer management scheme for I/O store buffers. Specifically, the storage buffer management system as described within the exemplary embodiment of the present invention is configured to comprise storage buffers that have the capability to efficiently support 128 byte or 256 byte I/O data transmission lines. The presently implemented storage buffer management scheme enables for a limited number of store buffers to be associated with a fixed number of storage state machines (i.e., queue positions) and thereafter the allowing for the matched pairs to be allocated in order to achieve maximum store throughput for varying combinations of store sizes of 128 and 256 bytes. | 2009-08-13 |
20090204735 | SYSTEMS AND METHODS FOR SELECTIVELY ACTIVATING FUNCTIONS PROVIDED BY A MOBILE PHONE - Methods for selectively activating one of multiple functions provided by a mobile phone are provided. An embodiment of a method for selectively activating one of multiple functions comprises the following steps. That the mobile phone has been coupled to a computer system is detected. A first interface is displayed to facilitate selection of a first function from the functions. That the first function is selected is detected by the first interface. At least one software module is configured to activate the first function, thereby the computer system is directed to employ the mobile phone as a first external electronic device corresponding to the first function. | 2009-08-13 |
20090204736 | COMPUTING DEVICE WITH FLEXIBLY CONFIGURABLE EXPANSION SLOTS, AND METHOD OF OPERATION - A computing device that allows for a flexible allocation of bandwidth among peripheral devices using a peripheral bus is disclosed. The computing device includes a peripheral bus and at least two slots. The computing device may be used with a single peripheral card or multiple peripheral cards. In a multi-card configuration the invention allows the bandwidth on the peripheral bus to be shared by all the cards. In a single-card configuration, the computing device allows available bandwidth on the peripheral bus to be used by a single card. The device is particularly useful with PCI express compliant expansion cards, such as graphics adapters. | 2009-08-13 |
20090204737 | Wireless universal serial bus system and driving method thereof - Disclosed is a wireless universal serial bus system that includes a device; a first host communicating with the device according to a wireless universal serial bus protocol; and a second host communicating with the device according to a wireless universal serial bus protocol, wherein when the first host receives a beacon from the second host, the first host provides new host information read out from the beacon to the device. | 2009-08-13 |
20090204738 | COMMUNICATION BETWEEN AN ACCESSORY AND A MEDIA PLAYER WITH MULTIPLE PROTOCOL VERSIONS - An interface and protocol allow a media player to communicate with external accessories over a transport link. The protocol includes a core protocol functionality and a number of accessory lingoes. Examples of accessory lingoes include a microphone lingo, a simple remote lingo, a display remote lingo, an RF transmitter lingo, and an extended interface lingo. | 2009-08-13 |
20090204739 | Interruptible write block and method for using same - A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input selectably coupled to an output of the primary register and to an output of the secondary register through an interrupt circuit. The interrupt circuit is utilized to interrupt flow of new data from the primary register to the secondary register during an interrupt of a write operation, such that upon resumption of the write operation the secondary register contains valid data. A method of utilizing an interruptible write block during a write operation comprises loading data into a primary register, interrupting the write operation to perform one or more other operations, loading the data into a secondary register while loading new data into the primary register, and resuming the write operation using valid data from the secondary register. | 2009-08-13 |
20090204740 | Method and Device for Performing Switchover Operations in a Computer System Having at Least Two Execution Units - A method and device for performing switchover operations in a computer system having at least two execution units are provided, in which switchover units are included which are configured in such a way that they switch over between at least two operating modes, a first operating mode corresponding to a compare mode, and a second operating mode corresponding to a performance mode. An interrupt controller is provided and, furthermore, at least three memory areas are provided, and the access to the memory areas is implemented in such a way that one first memory area is assigned to at least one first execution unit, and one second memory area is assigned to the at least one second execution unit, and at least one third memory area is assignable to the at least two execution units. | 2009-08-13 |
20090204741 | READER BOARD ASSEMBLY CIRCUIT, SYSTEM, AND METHOD FOR IDENTIFYING A DIGITAL DEVICE AMONG MULTIPLE DIGITAL DEVICES - The present invention provides an electronic circuit for detecting, identifying, and/or activating a digital device, including a touch-and-hold connector configured to hold an object of interest, the digital device coupled to the touch-and-hold connector, for example, wherein the digital device has a unique digital registration number, a microcontroller that reads the unique digital registration number of the digital device, a storage receptacle configured to selectively receive the touch-and-hold connector, a light-emitting source coupled to the storage receptacle and associated with the touch-and-hold connector, and an electrical power source. | 2009-08-13 |
20090204742 | Switching Device and Method of Manufacturing Same - In some embodiments, a switching device is configured to couple a first computer to a first peripheral device and one or more second peripheral devices. The switching device is further configured to couple a second computer to a third peripheral device and the one or more second peripheral devices. The switching device includes: (a) a switch configured to couple to the one or more second peripheral devices; (b) a first hub including: (1) a first upstream port configured to couple to the first computer; (2) a first downstream port configured to couple to the first peripheral device; and (3) at least one second downstream port coupled to the switch; (c) a second hub including: (1) a first upstream port configured to couple to the second computer; (2) a first downstream port configured to couple to the third peripheral device; and (3) at least one second downstream port coupled to the switch. Other embodiments are also disclosed herein. | 2009-08-13 |
20090204743 | STORAGE SUBSYSTEM AND CONTROL METHOD THEREFOF - Provided is a storage subsystem capable of inhibiting the deterioration in system performance to a minimum while improving reliability and availability. This storage subsystem includes a first controller for controlling multiple drive units connected via multiple first switch devices, and a second controller for controlling the multiple drive units connected via multiple second switch devices associated with the multiple first switch devices. This storage subsystem also includes a connection path that mutually connects the multiple first switch devices and the corresponding multiple second switch devices. When the storage [sub]system detects the occurrence of a failure, it identifies the fault site in the connection path, and changes the connection configuration of the switch device so as to circumvent the fault site. | 2009-08-13 |
20090204744 | METHODS AND SYSTEMS FOR RECONFIGURING DATA MEMORY OF EMBEDDED CONTROLLER MANAGED FLASH MEMORY DEVICES - Methods and systems for reconfiguring data memory of an embedded controller managed flash memory device are disclosed. According to one method, using a controller managed flash memory device reconfiguration module configured to execute on a general purpose computing platform separate from a computing platform in which an embedded controller managed flash memory device is located, reconfiguration data to be written to a data memory of the embedded controller managed flash memory device is received from a user and I/O commands for writing the reconfiguration data to an external device are generated. Flash device commands corresponding to the I/O commands are generated. The reconfiguration data is communicated to the data memory of the embedded controller managed flash memory device by sending the flash device commands and the reconfiguration data over a flash device interface of the embedded controller managed flash memory device. | 2009-08-13 |
20090204745 | Programming device for non-volatile memory and programming method thereof - The invention presents a programming method for a non-volatile memory with a bit signal to be programmed unidirectionally. The method includes the steps of a) providing first data each having a first number of sequential bits of first status in a data page in a non-volatile memory, b) decoding the first number of sequential bits of the first status in the first data into a second number of sequential bits of second status, and c) programming second data in a portion of the data page where the first status has been decoded to the second status. | 2009-08-13 |
20090204746 | FLASH MEMORY STORAGE DEVICE FOR ADJUSTING EFFICIENCY IN ACCESSING FLASH MEMORY - A flash memory storage device for boosting efficiency in accessing flash memory is disclosed. The flash memory storage device provides a Multi-level cell (MLC) flash memory for storing data, a single-level cell (SLC) flash memory for storing data, and a control unit for determining whether to store a file into the MLC NAND flash memory or a SLC NAND flash memory based on the file's data characteristics. | 2009-08-13 |
20090204747 | Non binary flash array architecture and method of operation - A Flash memory array comprises a plurality of Erase Sectors (Esecs) arranged in a plurality of Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs), and there is a non-binary number of at least one of the Erase Sector Groups (ESGs), Physical Pages (slices), and Physical Sectors (PSecs). A user address is translated into a physical address using modular arithmetic to determine pointers (ysel, esg, psec) for specifying a given Erase Sector (ESec) within a given Erase Sector Group (ESG); a given Erase Sector Group (ESG) within a given Physical Sector (Psec); and a given Physical Sector (PSec) within the array. | 2009-08-13 |
20090204748 | MULTI-CHANNEL FLASH MEMORY SYSTEM AND ACCESS METHOD - Disclosed is a multi-channel flash memory system formed by flash memories having pages divided into sectors and accessed by corresponding channels. An interface device is configured to access the flash memories via the channels by a unit of at least one sector, wherein the interface device divides an address into a plurality of addresses of sector unit and controls the divided addresses so as to be jumped by a given size. | 2009-08-13 |
20090204749 | Redimdamt purge for flash storage device - A flash storage device includes flash storage units that are purged in response to a condition or command. A flash controller interface receives a command for purging the flash storage device and provides a purge command to flash controllers in the flash storage device. Alternatively, the flash storage device detects a condition in response to which the flash controller interface provides a purge command to the flash controllers. Each flash controller independently erases a flash storage unit in response to receiving the purge command, by writing a pattern of data to the flash storage unit, such that the flash storage units are purged substantially in parallel with each other. | 2009-08-13 |
20090204750 | DIRECT LOGICAL BLOCK ADDRESSING FLASH MEMORY MASS STORAGE ARCHITECTURE - A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address. | 2009-08-13 |
20090204751 | MULTIPROCESSOR SYSTEM AND PORTABLE TERMINAL USING THE SAME - [PROBLEMS] To provide a portable terminal designated for speeding up the startup time of a multiprocessor system which is configured to be started up by a program being transferred from a specific processor to another processor. [MEANS OF SOLVING PROBLEMS] As a storing pattern of a program to a memory (ROM) transferred to another processor, a header is given to each code section. The header stores information as to whether or not the section needs to be transferred in each startup mode and size information of the corresponding code section. The startup time for each mode is shortened by enabling to transfer only the necessary portion from the transfer source processor to the transfer destination processor for each startup mode. | 2009-08-13 |
20090204752 | MEMORY DEVICE AND REFRESH ADJUSTING METHOD - When a single error of data is detected by an ECC circuit, a cycle adjusting unit provided on a memory board shortens a refresh cycle T | 2009-08-13 |
20090204753 | SYSTEM FOR REFRESHING CACHE RESULTS - A system and method for refreshing a cache based on query responses provided by a searching system in response to queries, includes providing a cache entry for each unique query, if space is available in the cache, and assigning a temperature value to each cache entry based on a frequency of occurrence of the corresponding query An age value is assigned to each cache entry based on a time of last refresh or creation of the corresponding query response. The age of the cache entries is periodically updated, and the temperature of a cache entry is updated when a corresponding query reoccurs. If system resources are available, the query response of a cache entry is refreshed based on the temperature and age of the cache entry. If resources are not available, the refreshing is limited. | 2009-08-13 |
20090204754 | MICROPROCESSOR AND METHOD FOR REGISTER ADDRESSING THEREIN - A microprocessor architecture comprising a microprocessor operably coupled to a plurality of registers and arranged to execute at least one instruction. The microprocessor is arranged to determine a class of data operand. The at least one instruction comprises one or more codes in a register specifier that indicates whether relative addressing or absolute addressing is used in accessing a register. In this manner, absolute and relative register addressing is supported within a single instruction word. | 2009-08-13 |
20090204755 | MULTI-READER, MULTI-WRITER LOCK-FREE RING BUFFER - A method for accessing cells of a ring buffer by one or more writers, comprising: storing a current writer cell position value in each of a done writer index and a reserved writer index; storing a current reader cell position value in a done reader index; copying the current writer cell position value to an old writer variable of a writer of the one or more writers; assigning a trial next writer cell position value to a new writer variable of the writer; accepting the trial next writer cell position value if the trial next writer cell position value is not equal to the done reader index value; as a single operation, first, accepting the trial next writer cell position value as a next writer cell position value if the reserved writer index value is equal to the old writer variable value, and second, replacing the reserved writer index value with the new writer variable value; writing data by the writer to a cell of the ring buffer indicated by the next writer cell position value; and, when the done writer index value is equal to the old writer variable value, replacing the done writer index value with the new writer variable value; whereby the one or more writers are prevented from simultaneously accessing the cell of the ring buffer. In addition, a method for accessing cells of a ring buffer by one or more readers, comprising: storing a current reader cell position value in each of a done reader index and a reserved reader index; storing a current writer cell position value in a done writer index; copying the current reader cell position value to an old reader variable of a reader of the one or more readers; assigning a trial next reader cell position value to a new reader variable of the reader; accepting the trial next reader cell position value if the old reader variable value is not equal to the done writer index value; as a single operation, first, accepting the trial next reader cell position value as a next reader cell position value if the reserved reader index value is equal to the old reader variable value, and second, replacing the reserved reader index value with the new reader variable value; reading data by the reader from a cell of the ring buffer indicated by the next reader cell position value; and, when the done reader index value is equal to the old reader variable value, replacing the done reader index value with the new reader variable value; whereby the one or more readers are prevented from simultaneously accessing the cell of the ring buffer. | 2009-08-13 |
20090204756 | METHOD FOR PROTECTING EXPOSED DATA DURING READ/MODIFY/WRITE OPERATIONS ON A SATA DISK DRIVE - A method and system for saving and retrieving data includes saving data in data storage fields of a data storage device in a computer. A back-up data storage field is selected in the data storage device. A data changing operation including new data is initiated on specified data saved in a current data storage field. A copy of all the data stored in boundary data storage fields is copied and stored in the back-up data storage field before changing the current data to provide data retrieval if the data is unrecoverable in the current data storage field, when a loss of power to the data storage device occurs. | 2009-08-13 |
20090204757 | Systems and Methods for Automatically Generating A Mirrored Storage Configuration For a Storage Array - An information handling system includes a plurality of storage enclosures, a plurality of logical storage units located in each storage enclosure, a controller connected to each of the plurality of logical storage units. The controller is configured to receive data regarding the plurality of logical storage units, and automatically execute an algorithm based on the received logical storage unit data to generate a mirrored storage configuration to be implemented, the mirrored storage configuration defining mirrored pairs of the plurality of logical storage units. | 2009-08-13 |
20090204758 | SYSTEMS AND METHODS FOR ASYMMETRIC RAID DEVICES - An information handling system can include an asymmetric RAID device. The information handling system comprises a RAID controller and a RAID volume. The RAID volume includes a first disk and a second disk attached to the RAID controller, wherein the first disk provides faster access than the second disk. In a particular embodiment, the first disk is an SSD and the second disk is a HDD. The RAID controller may be configured to support symmetric or asymmetric write operations. | 2009-08-13 |
20090204759 | ON-LINE VOLUME COALESCE OPERATION TO ENABLE ON-LINE STORAGE SUBSYSTEM VOLUME CONSOLIDATION - A mechanism to permit consolidation of storage subsystem volumes into larger, more easily managed volumes and an operating system device driver which includes a trap mechanism for intercepting calls from a host into logical unit devices that were previously consolidated into a single physical volume. A map converts such calls to a logical unit device into a corresponding offset in the single physical volume. A driver accesses the single physical volume with corresponding offsets to transfer data associated with a particular logical unit device. So, logical unit devices can be consolidated and reconsolidated to single physical volumes and other physical volumes without requiring changes to the operating system or its application software and without requiring application or host downtime. | 2009-08-13 |
20090204760 | STORAGE APPARATUS, RELAY DEVICE, AND METHOD OF CONTROLLING OPERATING STATE - Each time any one of HDDs is accessed, a corresponding relationship between the disk address of the accessed HDD and the time information indicating a time at which the HDD is accessed is added to a first operating-state management table. When a corresponding relationship with the same disk address already exists in the first operating-state management table, the time information is updated. When the first operating-state management table has no space available for new entry, corresponding relationships are deleted from the one having the oldest time information. Only HDDs of which disk address is recorded in the first operating-state management table is turned on. | 2009-08-13 |
20090204761 | PSEUDO-LRU CACHE LINE REPLACEMENT FOR A HIGH-SPEED CACHE - Embodiments of the present invention provide a system that replaces an entry in a least-recently-used way in a skewed-associative cache. The system starts by receiving a cache line address. The system then generates two or more indices using the cache line address. Next, the system generates two or more intermediate indices using the two or more indices. The system then uses at least one of the two or more indices or the two or more intermediate indices to perform a lookup in one or more lookup tables, wherein the lookup returns a value which identifies a least-recently-used way. Next, the system replaces the entry in the least-recently-used way. | 2009-08-13 |
20090204762 | Self Test Apparatus for Identifying Partially Defective Memory - A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold. | 2009-08-13 |
20090204763 | SYSTEM AND METHOD FOR AVOIDING DEADLOCKS WHEN PERFORMING STORAGE UPDATES IN A MULTI-PROCESSOR ENVIRONMENT - A system and method for avoiding deadlocks when performing storage updates in a multi-processor environment. The system includes a processor having a local cache, a store queue having a temporary buffer with capability to reject exclusive cross-interrogates (XI) while an interrogated cache line is owned exclusive and is to be stored, and a mechanism for performing a method. The method includes setting the processor into a slow mode. A current instruction that includes a data store having one or more target lines is received. The current instruction is executed, with the executing including storing results associated with the data store into the temporary buffer. The store queue is prevented from rejecting an exclusive XI corresponding to the target lines of the current instruction. Each target line is acquired with a status of exclusive ownership, and the contents from the temporary buffer are written to each target line after instruction completion. | 2009-08-13 |
20090204764 | Cache Pooling for Computing Systems - In a computing system a method and apparatus for cache pooling is introduced. Threads are assigned priorities based on the criticality of their tasks. The most critical threads are assigned to main memory locations such that they are subject to limited or no cache contention. Less critical threads are assigned to main memory locations such that their cache contention with critical threads is minimized or eliminated. Thus, overall system performance is improved, as critical threads execute in a substantially predictable manner. | 2009-08-13 |
20090204765 | DATA BLOCK FREQUENCY MAP DEPENDENT CACHING - A method for increasing the performance and utilization of cache memory by combining the data block frequency map generated by data de-duplication mechanism and page prefetching and eviction algorithms like Least Recently Used (LRU) policy. The data block frequency map provides weight directly proportional to the frequency count of the block in the dataset. This weight is used to influence the caching algorithms like LRU. Data blocks that have lesser frequency count in the dataset are evicted before those with higher frequencies, even though they may not have been the topmost blocks for page eviction by caching algorithms. The method effectively combines the weight of the block in the frequency map and its eviction status by caching algorithms like LRU to get an improved performance and utilization of the cache memory. | 2009-08-13 |
20090204766 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR HANDLING ERRORS IN A CACHE WITHOUT PROCESSOR CORE RECOVERY - A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache into a low level cache of the processor. Upon determining that the fetched data failed an error check indicating that the fetched data is corrupted, the method includes requesting an execution pipeline to discontinue processing and flush its contents, and initiating a clean up sequence, which includes sending an invalidation request to the low level cache causing the low level cache to remove lines associated with the corrupted data, and requesting the execution pipeline to restart. The execution pipeline accesses a copy of the requested data from a higher-level storage location. | 2009-08-13 |
20090204767 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR GENERALIZED LRU IN CACHE AND MEMORY PERFORMANCE ANALYSIS AND MODELING - The exemplary embodiment of the present invention relates to a generalized LRU algorithm is provided that is associated with a specified cache associativity line set value that is determined by a system user. As configured, the LRU algorithm as presented can comprise n-levels for an LRU tree, each specified tree being individually analyzed within the LRU algorithm. Within each LRU tree level comprises the associativity line value can be further broken down into sub-analysis groups of any desired configuration, however, the total sub-analysis group configuration must equal the specified cache associativity line value. | 2009-08-13 |
20090204768 | ADAPTIVE CACHE SIZING - A runtime code manipulation system is provided that supports code transformations on a program while it executes. The runtime code manipulation system uses code caching technology to provide efficient and comprehensive manipulation of an application running on an operating system and hardware. The code cache includes a system for automatically keeping the code cache at an appropriate size for the current working set of an application running. | 2009-08-13 |
20090204769 | Method to Bypass Cache Levels in a Cache Coherent System - Embodiments of the invention provide methods and apparatus for selectively bypassing cache levels when processing non-reusable transient data in a cache coherent system. To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit “bypass type” field among other attribute bits that index which bits of a Special Purpose Register (SPR) identify the cache levels to be bypassed. | 2009-08-13 |
20090204770 | DEVICE HAVING SHARED MEMORY AND METHOD FOR CONTROLLING SHARED MEMORY - A device having a shared memory and a shared memory controlling method are disclosed. A digital processing device can include a shared memory, having a storage area including at least one common section, coupled to each of the processors through separate buses and outputting access information to whether a processor is accessing a common section. With the present invention, each processor can efficiently use or/and control a shared memory by using access information. | 2009-08-13 |
20090204771 | DEVICE FOR CONTROLLING ACCESS FROM A PLURALITY OF MASTERS TO SHARED MEMORY COMPOSED OF A PLURALITY OF BANKS EACH HAVING A PLURALITY OF PAGES - The memory access device includes: a plurality of command division sections provided for a plurality of masters; a plurality of inter-master arbitration sections provided for a plurality of banks; and a memory control section. Each of the command division sections divides a command issued by the corresponding master into a plurality of micro-commands when the access region of the command is over two or more banks among the plurality of banks, each of the micro-commands being a command accessing only one of the two or more banks, and gives each of the micro-commands to an inter-master arbitration section corresponding to the bank including the access region of the micro-command. Each of the inter-master arbitration sections arbitrates micro-commands given from the command division sections to select one. The memory control section selects one of a plurality of micro-commands selected by the inter-master arbitration sections to perform memory access. | 2009-08-13 |
20090204772 | Memory depth optimization in communications systems with ensemble PHY layer requirements - Memory depth optimization in communications systems with ensemble PHY layer requirements. Memory depth, for one or more modules in a communication device, is managed based on a limited amount of provisioned hardware. For example, each of a number of various modules within a communication device is configurable to operate at various memory depths. Considered together, various sets or profiles of operational parameters (e.g., associated with particular settings for each of the various modules within the communication device), may be employed to configure the communication device to operate in accordance with one of a variety of operational modes. For example, in a first operational mode, latency may be minimized (e.g., using shorted codewords, shorter interleaver depth, etc.), whereas in a second operational mode, a higher latency may be tolerated but with an expectation of much lower error rates (e.g., achieved using more powerful ECC, longer interleaver depth, etc.). | 2009-08-13 |
20090204773 | METHOD OF WRITING DEVICE DATA IN DUAL CONTROLLER NETWORK STORAGE ENVIRONMENT - A method of writing device data in a dual controller network storage environment is described. According to the method, functions of a virtual data router (VD router) and a mirror technology are integrated, so as to efficiently transmit internal network data and write data into disk devices on different controllers in a dual controller network storage environment. Thereby, the internal network data transmission efficiency and actual internal network utilization can be improved. | 2009-08-13 |
20090204774 | Remote Copy System and Method of Deciding Recovery Point Objective in Remote Copy System - A remote copy system comprises a primary storage system having a primary volume, and a secondary storage system having a secondary volume forming a pair relationship with the primary volume. When the primary storage system receives a write command from a primary host computer, it stores the command in the primary volume and creates a journal added with time information. The secondary storage system receives the journal from the primary storage system and updates the secondary volume based on the received journal. The primary host computer determines, based on the operating status of the secondary storage system, either the time added to the latest journal that the secondary storage system received or the time added to the latest journal that updated the secondary volume as the recovery point objective, and provides the determined time this to the user. | 2009-08-13 |
20090204775 | DATA COPYING METHOD - A method for controlling a switch apparatus connectable to a host and a storage device including first and second areas, the method includes: establishing schedule of copying data stored in the first area of the storage device into the second area of the storage device; monitoring a state of access by the host to the storage device; carrying out copying the data stored in the first area into the second area while the monitored state of the access by the host allows copying of the data from the first area into the second area; and enhancing copying, if any portion of the data remains when a time set by the schedule is expired, the remaining portion of the data from the first area into the second area. | 2009-08-13 |
20090204776 | SYSTEM FOR SECURING AN ACCESS TO FLASH MEMORY DEVICE AND METHOD FOR THE SAME - A system for securing an access to a flash memory is provided. The system includes a first flash memory storage device having a plurality of storage elements for storing data, and a host for accessing the first flash memory storage device. The host includes a control unit, a storing unit, and an identification unit. The control unit is used for generating an identification code and assigning the identification code into a random storage element selected from the plurality of storage elements, when the first flash memory storage device is to be accessed by the host at the first time. The storing unit is used for storing the identification code and a set address corresponding to the stored storage element. The identification unit is used for examining whether the set address complies with the storage element address to be stored the identification code of the first flash memory storage device, and whether the identification code stored in the storing unit complies with an identification code of another flash memory storage device, when the first flash memory storage device is not to be accessed by the host at the first time. | 2009-08-13 |
20090204777 | Integated circuits and methods to control access to multiple layers of memory - Circuits and methods to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. | 2009-08-13 |
20090204778 | SIMPLE NON-AUTONOMOUS PEERING ENVIRONMENT, WATERMARKING AND AUTHENTICATION - A Secure Non-autonomous Peering (SNAP) system includes a hierarchical digital watermarking scheme, a central licensing authority, licensed fabricators and assemblers. | 2009-08-13 |
20090204779 | CONTROLLING EMBEDDED MEMORY ACCESS - A microcontroller ( | 2009-08-13 |
20090204780 | DATA STORAGE UNIT, DATA STORAGE CONTROLLING APPARATUS AND METHOD, AND DATA STORAGE CONTROLLING PROGRAM - A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the hardware. It includes a memory controlling means including a data storage controller ( | 2009-08-13 |
20090204781 | System for Limiting the Size of a Local Storage of a Processor - A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage. | 2009-08-13 |
20090204782 | SYSTEM AND METHOD FOR SAFELY AUTOMATING THE GENERATION OF MULTIPLE DATA DEFINITION LANGUAGE STATEMENTS - A system and method includes steps or acts of: organizing table partitions in logical order; presenting the partition table numbers and their current ending values in logical order to a user; receiving an alter command from the user, the alter command specifying at least one logical partition number and its corresponding ending value; internally matching the specified logical partition number to its corresponding physical partition number; altering the physical partitioning of the table by manipulating one or more current ending values of partitions by altering the current ending value of the physical partition to which the specified logical partition is associated, such that new ending values are generated; and automatically generating at least one data definition language statement corresponding to the alter command, using the new ending value. | 2009-08-13 |
20090204783 | Systems And Methods For Handling Addresses Within A Database Application - A system and method store addresses within a database. An address and an address usage type that define an intended use of the address for an entity are captured. Address elements of the address are determined using an address template based upon the address usage type. If the address is not already stored within the database, an address entry having a new unique address identification number is created within an address table, each of the address elements are stored within an address element table of the database in association with the new unique address identification number, and an association entry is created within an address association table to associate the new unique address identification number with the entity, as well as to store the address usage type. If the address is already stored within the database, an existing unique address identification number for the address within the database is determined and an association entry within the address association table is created to associate the existing unique address identification number with the entity and to store the address usage type. | 2009-08-13 |
20090204784 | METHOD AND SYSTEM FOR GEOMETRY-BASED VIRTUAL MEMORY MANAGEMENT - Methods, digital systems, and computer readable media are provided for managing a tiled virtual memory by maintaining a region quadtree representing a current allocation state of tiled virtual memory pages in the tiled virtual memory. | 2009-08-13 |
20090204785 | Computer with two execution modes - A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture. or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction's page. | 2009-08-13 |
20090204786 | Storage system, release method, and secondary storage apparatus - The storage system includes page area association information that associates a page area that partitions a storage area in a real volume into predetermined storage areas with a page area that partitions a storage area in a virtual volume into predetermined storage areas; a pair setting unit for pairing a primary virtual volume that stores data from a host computer and a secondary virtual volume to store a copy of the data stored in the primary virtual volume; and a page release unit for releasing association between a page area in the secondary virtual volume and a page area in the secondary real volume associated in advance with the page area in the secondary virtual volume. | 2009-08-13 |
20090204787 | Butterfly Physical Chip Floorplan to Allow an ILP Core Polymorphism Pairing - Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times. Separate processor cores may be morphed to appear differently for different applications. For example, two processor cores each capable of executing N-wide issue groups of instructions may be morphed to appear as a single processor core capable of executing 2N-wide issue groups. | 2009-08-13 |
20090204788 | Programmable pipeline array - Disclosed is an array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an input cell, an output cell, and a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell. Additional cells are similarly configured. Memory presents configuration instructions to cells in response to a configuration code. Data advances through ranks of the cells. The configuration code advances to memory associated with a rank in tandem with the data. | 2009-08-13 |
20090204789 | DISTRIBUTING PARALLEL ALGORITHMS OF A PARALLEL APPLICATION AMONG COMPUTE NODES OF AN OPERATIONAL GROUP IN A PARALLEL COMPUTER - Methods, apparatus, and products for distributing parallel algorithms of a parallel application among compute nodes of an operational group in a parallel computer are disclosed that include establishing a hardware profile, the hardware profile describing thermal characteristics of each compute node in the operational group; establishing a hardware independent application profile, the application profile describing thermal characteristics of each parallel algorithm of the parallel application; and mapping, in dependence upon the hardware profile and application profile, each parallel algorithm of the parallel application to a compute node in the operational group. | 2009-08-13 |
20090204790 | BUFFER MANAGEMENT FOR REAL-TIME STREAMING - Technologies are described herein for buffer management during real-time streaming. A video frame buffer stores video frames generated by a real-time streaming video capture device. New video frames received from the video capture device are stored in the video frame buffer prior to processing by a video processing pipeline that processes frames stored in the video frame buffer. A buffer manager determines whether a new video frame has been received from the video capture device and stored in the video frame buffer. When the buffer manager determines that a new video frame has arrived at the video frame buffer, it then determines whether the video processing pipeline has an unprocessed video frame. If the video processing pipeline has an unprocessed video frame, the buffer manager discards the new video frame stored in the video frame buffer or performs other processing on the new video frame. | 2009-08-13 |
20090204791 | Compound Instruction Group Formation and Execution - A method and apparatus for forming compound issue groups containing instructions from multiple cache lines of instructions are provided. By pre-fetching instruction lines containing instructions targeted by a conditional branch statement, if it is predicted that the conditional branch will be taken, a compound issue group may be formed with instructions from the I-line containing the branch statement and the I-line containing instructions targeted by the branch. | 2009-08-13 |
20090204792 | Scalar Processor Instruction Level Parallelism (ILP) Coupled Pair Morph Mechanism - Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times. Separate processor cores may be morphed to appear differently for different applications. For example, two processor cores each capable of executing N-wide issue groups of instructions may be morphed to appear as a single processor core capable of executing 2N-wide issue groups. | 2009-08-13 |
20090204793 | RAW Hazard Detection and Resolution for Implicitly Used Registers - The present invention provides a system, apparatus, and method for detecting and resolving read-after-write hazards encountered in processors following the dispatch of instructions requiring one or more implicit reads in a processor. | 2009-08-13 |
20090204794 | METHODS COMPUTER PROGRAM PRODUCTS AND SYSTEMS FOR UNIFYING PROGRAM EVENT RECORDING FOR BRANCHES AND STORES IN THE SAME DATAFLOW - The present invention relates to a method for the unification of PER branch and PER store operations within the same dataflow. The method comprises determining a PER range, the PER range comprising a storage area defined by a designated storage starting area and a designated storage ending area, wherein the storage starting area is designated by a value of the contents of a first control register and the storage ending area is designated by a value of the contents of a second control register. The method also comprises retrieving register field content values that are stored at a plurality of registers, wherein the retrieved content values comprises a length field content value, and setting the length field content value to zero for a PER branch instruction, thereby enabling a PER branch instruction to performed similarly to a PER storage instruction. | 2009-08-13 |
20090204795 | Method and System for Automatically Testing Performance of Applications run in a Distributed Processing Structure and Corresponding Computer Program Product - Performance of applications run on a distributed processing structure including a grid of processing units is automatically tested by: running at least one application on the distributed processing structure; loading the application with processing workload to thereby produce processing workload on the distributed processing structure; sensing the operating status of the processing units in the distributed processing structure under the processing workload and producing information signals indicative of such operating status; collecting these information signals; providing a rule engine and selectively modifying, as a function of the rules in the rule engine and the information signals collected, at least one of: the processing workload on the application, and the operating status of the processing units in the grid. | 2009-08-13 |
20090204796 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR VERIFYING ADDRESS GENERATION, INTERLOCKS AND BYPASSES - Method, system and computer program product for verifying the address generation, address generation, interlocks, and address generation bypassing controls in a CPU. An exemplary embodiment includes a verification method in a processor, the method including propagating a first set general purpose register values fern a first instruction to a second instruction, wherein the simulation monitor is coupled to a first stage of the instruction pipeline, and wherein the first set of general purpose register values are stored in a simulation instruction object, selecting a second set of general purpose register values, updating the first set of general purpose register values with the second set of general purpose register values and placing the second, set of general purpose register values on a bus. | 2009-08-13 |
20090204797 | METHOD AND SYSTEM FOR MITIGATING LOOKAHEAD BRANCH PREDICTION LATENCY WITH BRANCH PRESENCE PREDICTION AT THE TIME OF INSTRUCTION FETCHING - System and method for mitigating lookahead branch prediction latency with branch presence prediction at the time of instruction fetching. An exemplary embodiment includes a method for mitigating lookahead branch prediction latency, the method including receiving an instruction address in an instruction cache for fetching instructions in the microprocessor pipeline, receiving the instruction address in a branch presence predictor coupled to the microprocessor pipeline, and releasing instructions extracted from the instruction cache after determining that a branch prediction is available or unlikely to occur for instructions identified as potential predictable branches by the branch presence prediction. | 2009-08-13 |
20090204798 | Simplified Implementation of Branch Target Preloading - A system for using complex branch execution hardware and a hardware based Multiplex (MUX) to multiplex a fetch address of a future branch and a branch fetch address to one index hash value used to index a branch target prediction table for execution by a processor core, to reduce branch mis-prediction by preloading. | 2009-08-13 |
20090204799 | METHOD AND SYSTEM FOR REDUCING BRANCH PREDICTION LATENCY USING A BRANCH TARGET BUFFER WITH MOST RECENTLY USED COLUMN PREDICTION - System and method for reducing branch prediction latency using a branch target buffer with most recently used column prediction. An exemplary embodiment includes a method for reducing branch prediction latency, the method including reading most-recently-used information from a most-recently-used table associated with the branch target buffer where each most-recently-used entry corresponds to one or more branch target buffer rows and specifies the ordering from least-recently-used to most-recently-used of the associated branch target buffer columns, selecting a row from the branch target buffer and simultaneously selecting the associated entry from the most-recently-used table and speculating that there is a prediction in the most recently used column of the plurality of columns from the selected row from the branch target buffer while determining whether there is a prediction and which column contains the prediction. | 2009-08-13 |
20090204800 | MICROPROCESSOR WITH MICROARCHITECTURE FOR EFFICIENTLY EXECUTING READ/MODIFY/WRITE MEMORY OPERAND INSTRUCTIONS - The microprocessor includes an instruction translator that translates a macroinstruction of a macroinstruction set in its macroarchitecture into exactly three microinstructions to perform a read/modify/write operation on a memory operand. The first microinstruction instructs the microprocessor to load the memory operand into the microprocessor from a memory location and to calculate a destination address of the memory location. The second microinstruction instructs the microprocessor to perform an arithmetic or logical operation on the loaded memory operand to generate a result. The third microinstruction instructs the microprocessor to write the result to the memory location whose destination address is calculated by the first microinstruction. A first execution unit receives the first microinstruction and responsively loads the memory operand into the microprocessor from the memory location, and a second distinct execution unit also receives the first microinstruction and responsively calculates the destination address of the memory location. | 2009-08-13 |
20090204801 | MECHANISM FOR SECURE DOWNLOAD OF CODE TO A LOCKED SYSTEM - Techniques for securely downloading of boot code to a locked system. | 2009-08-13 |
20090204802 | DISTRIBUTED INFORMATION GENERATOR AND RESTORING DEVICE - Check data corresponding to distributed confidential information is generated, and the confidential information and check data are distribution-coded. When the confidential information is restored, the confidential information and check data are restored and it is determined whether or not the restored check data correspond to the restored confidential information. If the data correspond to the information, the information is determined to be correct and is output. If not, the information is judged to be false (i.e., tampered distributed information), and a symbol indicating that falsity has been detected is output. | 2009-08-13 |
20090204803 | HANDLING OF SECURE STORAGE KEY IN ALWAYS ON DOMAIN - Techniques for handling a secure storage key maintain the key in an always on domain and restore the key to the encryption/decryption engine when the engine is turned back on. The secure storage key however is only accessible by the boot loader code, which provides a secure chain of trust. In addition, the techniques allow the secure storage key to be updated. | 2009-08-13 |
20090204804 | Information processing device - An information processing device includes an authenticating part that authenticates user, an authentication canceling part that cancels authentication of the user when the authenticating part authenticated, and removes setting information and screen information input by the user; an operation condition storing part that stores the setting information and the screen information input by the user in an external memory medium when canceling authentication of the user, and a reproducing part that reads the setting information and the screen information stored in the external memory medium from the external memory medium when the authenticating part authenticates the user, and reproduces an operation condition based on the setting information and the screen information that were read. | 2009-08-13 |
20090204805 | Method for secure signal transmission in a telecommunication network, in particular in a local area network - In a telecommunication network, a modular expandable gateway connects a local area network to a wide area network and includes a base module and a plurality of add-on modules arranged in one or more stacks, the base module and the add-modules including respective encryption/decryption engines to exchange secure information with each other, thus frustrating any possible fraudulent interception of the information at the module interconnections. | 2009-08-13 |
20090204806 | CERTIFYING DEVICE, VERIFYING DEVICE, VERIFYING SYSTEM, COMPUTER PROGRAM AND INTEGRATED CIRCUIT - An authentication system that can show having an authentic computer program, can certify the authenticity of itself, and can verify the certification. The authentication system is composed of a terminal (requesting device) and a card (verifying device). The card stores secret information to be used by the terminal, and an update program for the terminal. The card verifies authenticity of the terminal using information obtained from the terminal. When it judges that the terminal is authentic, the card outputs the secret information to the terminal. When it judges that the terminal is not authentic, the card outputs the update program. With this structure, the terminal is forced to update the program when it attempts to use the secret information. | 2009-08-13 |
20090204807 | ABSTRACTION FUNCTION FOR MOBILE HANDSETS - Handset, computer software and method for protecting sensitive network information, available in the handset, from disclosure to an unauthorized server, by using an abstraction function module, the handset being connected to a network. The method includes receiving at the abstraction function module an encoding key from an abstraction server; receiving at the abstraction function module a request from a client or application for providing the sensitive network information from a control plane module of the handset, wherein the client or application resides in a user plane module, which is different from the control plane module, the sensitive network information is stored in the control plane module of the handset, and both the control plane module and the user plane module reside in the handset; retrieving by the abstraction function module the requested sensitive network information from the control plane module; encrypting, by the abstraction function module, the retrieved sensitive network information based on the received encoding key; and providing the encrypted sensitive network information to the client or application in the user plane module. | 2009-08-13 |
20090204808 | Session Key Security Protocol - Exchanging information in a multi-site authentication system. A network server receives, from an authentication server, a request by a client computing device for a service provided by the network server along with an authentication ticket. The authentication ticket includes: a session key encrypted by a public key associated with the network server, message content encrypted by the session key, and a signature for the encrypted session key and the encrypted message content. The signature includes address information of the network server. The network server identifies its own address information in the signature to validate the signature included in the authentication ticket and verifies the authentication ticket content based on the signature included in the authentication ticket. The network server decrypts the encrypted session key via a private key associated with the second network server and decrypts the encrypted message content via the decrypted session key. | 2009-08-13 |
20090204809 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - An information processing device is arranged to acquire a first public key certificate and a first secret key from a server device by acquiring an individual identification information which is uniquely discriminable for the information processing device from the information processing device and transmitting the individual identification information to the server device. The information processing device is arranged to determine whether the information processing device is permitted to transmit device information to the server device through an encryption communication using the first public key certificate and the first secret key, by acquiring the individual identification information from the information processing device and comparing the acquired individual identification information with the individual identification information associated with at least one of the first public key certificate and the first secret key. | 2009-08-13 |
20090204810 | Architecture and Design for Central Authentication and Authorization in an On-Demand Utility Environment - A Centralized Authentication & Authorization (CAA) system that facilitates secure communication between service clients and service providers. CAA comprises a Service Request Filter (SRF), a Service Client Authentication Program (SCAP), a Service Authorization Program (SAP), and an Authorization Database (ADB). The SRF intercepts service requests, extracts the service client's identifier from a digital certificate attached to the request, and stores the identifier in memory accessible to service providers. In the preferred embodiment, the SRF forwards the service request to a web service manager. The web service manager invokes SCAP. SCAP matches the identifier with a record stored in ADB. SAP queries ADB to determine if the service request is valid for the service client. If the service request is valid, SAP authorizes the service request and the appropriate service provider processes the service request. | 2009-08-13 |
20090204811 | Method For The Encrypted Transmission Of Synchronization Messages - There is described a method for transmitting synchronization messages, for example PTP messages of the IEEE 1588 standard, the PTP message being inserted into a data packet in line with the Internet Protocol, the data packet having an IP header, and the data packet having a UDP header. In this case, for the encrypted transmission on the PTP message, the data packet is addressed to a UDP port that is reserved for encrypted PTP messages, the data packet is provided with an additional S-PTP header that is provided for encryption, the PTP message is extended with a pseudo random number, and the PTP message is encrypted together with the pseudo random number. | 2009-08-13 |
20090204812 | MEDIA PROCESSING - In an example embodiment, an apparatus comprising a communication interface configured to be in data communication with another device, and processing logic that is operably coupled to the communication interface. The processing logic is operable to process a packet received via the communication interface, the packet comprising a header and a payload. The processing logic is configured to acquire information about the contents of the payload from the header. For example, the processing logic can determine from the header of the packet whether the payload contains sensitive data; contains analytic, video, and/or audio data; and/or whether the payload is encrypted. | 2009-08-13 |
20090204813 | SYSTEM AND METHOD FOR AUTHENTICATING DATA USING INCOMPATIBLE DIGEST FUNCTIONS - A system for authenticating data of interest includes a digest locator engine capable to locate a first and a second digest result in a data file, including a set of data; a first digest creator capable to create, using a first digest function, a first digest of the set of data, the first digest function being identical to a digest function used to create the first digest result; a second digest creator capable to create, using a second digest function that is incompatible with the first digest function, a second digest of the set of data, the second digest function being identical to a second digest function used to create the second digest result; and a digest comparator engine, communicatively coupled to the digest locator, first digest creator and the second digest creator, capable to compare the first and second created digests with the first and second located digest results respectively. | 2009-08-13 |
20090204814 | Method and apparatus for communicating information between a security panel and a security server - A security panel includes a processor, memory, and a network interface having a unique MAC address, and is configured to communicate over a network with a server. A method for registering the security panel with the server includes contacting the server utilizing a network address stored in the memory. A dealer ID, a line number, and a unique account number is sent to the server. The dealer ID, the line number, and the unique account number are stored in the memory. An encryption key is received for encryption of additional communication between the security panel and the server. The unique MAC address is sent to the server in an encrypted session to verify the security panel to the server. | 2009-08-13 |
20090204815 | System and method for wireless device based user authentication - An automated system and method for authenticating entities or individuals attempting to access a computer application, network, system or device using a wireless device is provided. The system employs one or more short-range wireless interfaces (e.g. BLUETOOTH or Wi-Fi) or long-range wireless interfaces (e.g. cellular or WiMAX) to detect the presence or location of the wireless device and it's proximity to the secure system to be accessed. The wireless device incorporates a unique identifier and secure authentication key information associated with the user of the wireless device. An authentication result is generated and may be used for a variety of applications. The application may process the result and determine the degree of access for which the entity or individual is allowed. | 2009-08-13 |
20090204816 | Method Of Authorizing Network Publishing - A method of authorizing printing of a publication at a printer by a publisher in a network is provided, in which an alias identity of a user is created from both a sensing device identity and an application identity when the user interacts with a printed application tag associated with the publication using the sensing device, the publication is addressed to the user by the alias identity, the publication is signed using a private key of the publisher, the signed publication is sent to the printer, and it is confirmed that the signed publication may be printed at the printer by verifying the private key signature. | 2009-08-13 |
20090204817 | COMMUNICATION SYSTEM - In a method and system for a communications system, identifying at least one of a received message that has been decrypted using a first decryption method and a message to be sent that is to be encrypted using a first encryption method, generating a copy of the at least one of the received message and the message to be sent, encrypting the copy of the at least one of the received message and the message to be sent using a second encryption method to create an encrypted copy of the at least one of the received message and the message to be sent, and transmitting the encrypted copy of the at least one of the received message and the message to be sent from the communications device for decryption and storage. | 2009-08-13 |
20090204818 | METHOD AND APPARATUS FOR GENERATING AND VERIFYING ELECTRONIC SIGNATURE OF SOFTWARE DATA, AND COMPUTER READABLE RECORDING MEDIUM THEREOF - Provided are methods of generating and verifying an electronic signature of software data, wherein software data is split into a plurality of blocks, electronic signatures corresponding to each of the blocks are generated, and some of the electronic signatures are randomly selected for verification. Accordingly, a time required for verifying an electronic signature can be reduced while maintaining the advantages of an electronic signature system. | 2009-08-13 |
20090204819 | ADVERTISEMENT-BASED HUMAN INTERACTIVE PROOF - An arrangement for providing advertisement-based (“ad-based”) HIPs (human interactive proofs) is realized by using an advertisement as the basis of a HIP challenge that is readily solved by a user but is difficult for a computer-based application to solve. Users are accustomed to advertisements and can generally understand the content or message being delivered by them. But the typically complex mixture of graphics, colors, logos, texture, transparency, text, and other elements that may be utilized in a graphical advertisement provides the basis for an ad-based HIP challenge that is difficult to solve by a computer. In another illustrative example, audio comprising a slogan, musical jingle or ditty, spoken words, or other sounds (or combinations thereof) is used to convey an advertising message, while also providing the basis for an audio ad-based HIP. | 2009-08-13 |
20090204820 | Method and apparatus for Account Management - A method and apparatus for on-line account management controls access to a computer such as a web server. The method and apparatus reduces interference from Internet bots while minimizing the impact on a legitimate user's use of a web site. | 2009-08-13 |
20090204821 | DATA PROTECTION MECHANISM - A control system in a device allows for installation of application packages to impart different position data processing abilities to the device. The position data may be generated by an electronic pen, and the control system may be arranged in such a pen. Each application package comprises a license specification and an application program. The application program is configured to access the position data and device functions via the control system. The license specification provides for digital rights management and data protection. For example, the license specification may be used by the control system to verify an application program for installation in the device. Further, the license specification may cause the control system to selectively allow the application program to access a specific device function only if it is listed in the license specification. | 2009-08-13 |
20090204822 | REDUCING THE BOOT TIME OF A TCPA BASED COMPUTING SYSTEM WHEN THE CORE ROOT OF TRUST MEASUREMENT IS EMBEDDED IN THE BOOT BLOCK CODE - A method, computer program product and system for reducing the boot time of a TCPA based computing system. A flash memory in the TCPA based computing system may include a register comprising bits configured to indicate whether the segments of the flash memory have been updated. The flash memory may further include a table configured to store measurements of the segments of the flash memory. The flash memory may further include a boot block code that includes a Core Root of Trust for Measurement (CRTM). The CRTM may read the bits in the register to determine if any of the segments of the flash memory have been updated. The CRTM may further obtain the measurement values in the table for those segments that store the POST BIOS code that have not been updated thereby saving time from measuring the POST BIOS code and consequently reducing the boot time. | 2009-08-13 |
20090204823 | METHOD AND APPARATUS FOR CONTROLLING SYSTEM ACCESS DURING PROTECTED MODES OF OPERATION - A microprocessor to provide software development debugging capabilities while providing security for confidential and/or sensitive information. The processor may operate in one of an open, a secure entry, and a secure mode. In open mode, security measures may prevent access to certain registry bits and access to a private memory area. Secure entry mode may be entered upon receipt of a request to run secure code and/or access the private memory area. The secure code may be authenticated in secure entry mode. Authentication may be performed using digital signatures. Secure mode may be entered if authentication is successful. Authenticate code may be executed in the secure mode environment. The private memory area may be accessible in secure mode. | 2009-08-13 |
20090204824 | SYSTEM, METHOD AND MEMORY DEVICE PROVIDING DATA SCRAMBLING COMPATIBLE WITH ON-CHIP COPY OPERATION - Data scrambling techniques implemented externally to a flash memory device are disclosed which can be used in concert with flash memory on-chip copy functionality operating internally to the flash device, thus supporting high performance copying operations. All the data stored in the flash may be scrambled, including headers and control structures. Robust file system operation may be achieved, including the capability to tolerate a power loss at any time, and yet be able to relocate data internally within the flash without having to de-scramble and then re-scramble the data. An exemplary hardware based solution has little or no impact on overall system performance, and may be implemented at very low incremental cost to increase overall system reliability. The data scrambling technique preferably uses a logical address, such as logical block address or logical page address, rather than a physical address, to determine a seed scrambling key. | 2009-08-13 |
20090204825 | INFORMATION PROCESSING APPARATUS AND METHOD, INFORMATION RECORDING MEDIUM, AND COMPUTER PROGRAM - An information processing apparatus includes a data processor configured to obtain first content stored in a first information recording medium and second content which is stored in a second information recording medium and which is usable together with the first content, and to perform content playback processing by using the first content and the second content. The data processor calculates a hash value of a certificate stored in the first information recording medium, and verifies the calculated hash value against a hash value stored in a content certificate corresponding to the first content, and on the condition that the calculated hash value and the hash value stored in the content certificate coincide with each other, the data processor performs the content playback processing by using the first content and the second content. | 2009-08-13 |
20090204826 | Method for Power Conservation in Virtualized Environments - A system and method for enabling power conservation when making placement and relocation decisions. More specifically, a virtualized environment power conservation module enables power conservation when making placement and relocation decisions within a virtual environment. The virtualized environment power conservation module assigns virtual machines among a group of physical hosts in order to minimize the net power consumption. The virtualized environment power conservation module makes use of server power profile or real time power consumption data to make power consumption aware Virtual Machine assignment decisions. In certain embodiments, a server system exposes real power consumption (e.g. System Watts, Cumulative kWh. etc.) via system management interfaces. Additionally, in certain embodiments, the server systems may expose real power consumption via standard power profiles. These systems leverage PMBus-enabled power supplies to read the power metric information. | 2009-08-13 |
20090204827 | SYSTEM AND METHOD FOR ENERGY SAVINGS ON A PHY/MAC INTERFACE FOR ENERGY EFFICIENT ETHERNET - A system and method for energy savings on a PHY/MAC interface for energy efficient Ethernet. Power savings for a PHY due to low-link utilization can also be realized in the higher layer elements that interface with the PHY. In one embodiment, subrating is implemented on a MAC/PHY interface to match a subrating of the PHY with a remote link partner. This subrating is less than the full capacity rate and can be zero. | 2009-08-13 |
20090204828 | HYBRID TECHNIQUE IN ENERGY EFFICIENT ETHERNET PHYSICAL LAYER DEVICES - A hybrid technique in energy efficient Ethernet (EEE) physical layer devices (PHYs). A hybrid approach is defined that combines multiple low power modes. In one embodiment, the hybrid approach uses low power idle (LPI) and subset PHY techniques that can be selectively activated. | 2009-08-13 |
20090204829 | CONTROL DEVICE AND INFORMATION PROCESSING APPARATUS - A control device includes a main control unit that serves as a main component for device control and to which power is supplied from a first power unit; a power control unit that controls the first power unit and to which power is supplied from a second power unit; a memory control unit that accesses a memory that stores therein a computer program and data and to which power is supplied from the second power unit; and a network control unit that receives packets through a network and transfers the packets to the memory through the memory control unit and to which power is supplied from the second power unit. | 2009-08-13 |