33rd week of 2015 patent applcation highlights part 53 |
Patent application number | Title | Published |
20150228592 | MILLIMETER WAVE BANDS SEMICONDUCTOR PACKAGE AND MILLIMETER WAVE BANDS SEMICONDUCTOR DEVICE - Certain embodiments provide a millimeter wave bands semiconductor package including a first metal block, a second metal block, and a circuit board. The first metal block includes a first penetration hole and a second penetration hole, each of which has a flattening film on an inner surface thereof. The second metal block includes a first non-penetration hole and a second non-penetration hole, each of which has a flattening film on an inner surface thereof. The circuit board is disposed between the first metal block and the second metal block and has an input signal line and an output signal line on a front side surface thereof. The first metal block and the second metal block are disposed such that the first non-penetration hole and the first penetration hole constitute a first waveguide and the second non-penetration hole and the second penetration hole constitute a second waveguide. | 2015-08-13 |
20150228593 | Under Bump Metallization - A structure of an under bump metallization and a method of forming the same are provided. The under bump metallization has a redistribution via hole, viewed from the top, in a round shape or a polygon shape having an angle between adjacent edges greater than 90°. Therefore, the step coverage of the later formed metal layer can be improved. | 2015-08-13 |
20150228594 | VIA UNDER THE INTERCONNECT STRUCTURES FOR SEMICONDUCTOR DEVICES - A semiconductor device is provided that has a redistribution layer with reduced resistance. The semiconductor device comprises a plurality of bonding pads on a substrate, a redistribution layer coupled to the bonding pads through a plurality of vias, a dielectric layer over the redistribution layer, that includes an opening that exposes a portion of the redistribution layer. The bonding pads are at least partially under the opening. | 2015-08-13 |
20150228595 | METHODS FOR ETCHING COPPER DURING THE FABRICATION OF INTEGRATED CIRCUITS - Methods for etching copper in the fabrication of integrated circuits are disclosed. In one exemplary embodiment, a method for fabricating an integrated circuit includes providing an integrated circuit structure including a copper bump structure and a copper seed layer underlying and adjacent to the copper bump structure and etching the seed layer selective to the copper bump structure using a wet etching chemistry consisting of H | 2015-08-13 |
20150228596 | SEMICONDUCTOR PACKAGING STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor packaging structure and a manufacturing method for the same are disclosed. The semiconductor packaging structure includes a chip, a dielectric layer and a plurality of redistribution circuit layers. The chip has a plurality of connection pads. The dielectric layer is disposed on the chip and defined with a plurality of containers therein. The connection pads are exposed from the containers, respectively. The redistribution circuit layers are disposed within the containers and electrically connected with the connection pads, respectively. Via these arrangements, the bonding surfaces between the redistribution circuit layers and the dielectric layer can be increased. | 2015-08-13 |
20150228597 | COPPER POST STRUCTURE FOR WAFER LEVEL CHIP SCALE PACKAGE - In a method for forming a packaging structure, a metal pad is formed on a semiconductor substrate, and a first polymer insulating layer is formed over the semiconductor substrate. An opening passing through the first polymer insulating layer is formed to expose a portion of the metal pad. A copper-containing material is deposited in the opening and over the first polymer insulating layer, thereby forming a copper-containing layer having a first thickness and a first width over the first polymer insulating layer. A conductive bump having a second width is formed over the copper-containing layer, in which the second width is smaller than the first width. An exposed portion of the copper-containing layer is etched using the conductive bump as a mask until the exposed portion is reduced to a second thickness, thereby forming a monolithic copper-containing structure. | 2015-08-13 |
20150228598 | Semiconductor Device with Post-Passivation Interconnect Structure and Method of Forming the Same - A semiconductor device, including a protective layer overlying a contact pad and a dummy pad on a semiconductor substrate, an interconnect structure overlying the protective layer and contacting part of the dummy pad through a contact via passing through the protective layer, a bump overlying the interconnect structure positioned over the dummy pad. | 2015-08-13 |
20150228599 | SELF-ALIGNMENT STRUCTURE FOR WAFER LEVEL CHIP SCALE PACKAGE - A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure. | 2015-08-13 |
20150228600 | PACKAGES WITH STRESS-REDUCING STRUCTURES AND METHODS OF FORMING SAME - A chip includes a semiconductor substrate, an electrical connector over the semiconductor substrate, and a molding compound molding a lower part of the electrical connector therein. A top surface of the molding compound is lower than a top end of the electrical connector. A recess extends from the top surface of the molding compound into the molding compound. | 2015-08-13 |
20150228601 | SUBSTRATE WITH CORNER CUT-OUTS AND SEMICONDUCTOR DEVICE ASSEMBLED THEREWITH - A semiconductor device is assembled from a rectangular substrate sheet. The substrate sheet has die mounting pads accessible from a first side and package mounting pads accessible from an opposite side. Corner regions of the substrate sheet have receding edges. A semiconductor die is attached to the substrate sheet such that electrodes or bonding pads of the die are mounted to respective die mounting pads of the substrate sheet. An encapsulating material covers the semiconductor die and the first side of the substrate sheet. Corner covering sections of the encapsulating material further cover the receding edges of the corner regions. | 2015-08-13 |
20150228602 | SEMICONDCUTOR CHIP AND SEMIONDUCOT MODULE - A semiconductor chip includes a signal terminal disposed on a chip substrate; a ground terminal disposed on the chip substrate; a signal cell disposed on the chip substrate; a ground cell disposed on the chip substrate; a signal line connecting the signal cell and the signal terminal; and a ground line wired along the signal line to connect the ground cell and the ground terminal. A semiconductor module includes the semiconductor chip; and a semiconductor package having a ground pad connected to the ground terminal, and a power source pad connected to the power source terminal. | 2015-08-13 |
20150228603 | Semiconductor Constructions and Methods of Planarizing Across a Plurality of Electrically Conductive Posts - Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts. | 2015-08-13 |
20150228604 | SELF-ALIGNING CONDUCTIVE BUMP STRUCTURE AND METHOD OF FABRICATION - A semiconductor device includes a substrate having a major surface and conductive bumps distributed over the major surface of the substrate. Each conductive bump of a first subset of the conductive bumps comprises a regular body and a second subset of the conductive bumps comprises a group of separate conductive bumps uniformly distributed around a periphery of a central opening. | 2015-08-13 |
20150228605 | Interconnect Structure and Method of Forming the Same - An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature. | 2015-08-13 |
20150228606 | SEMICONDUCTOR DEVICE INCLUDING AN EMBEDDED SURFACE MOUNT DEVICE AND METHOD OF FORMING THE SAME - Embodiments of the present disclosure include devices and methods of forming the same. An embodiment is a device including a solder resist coating over a first side of a substrate, an active surface of a die bonded to the first side of the substrate by a first connector, and a surface mount device mounted to the die by a second set of connectors, the surface mount device being between the die and the first side of the substrate, the surface mount device being spaced from the solder resist coating. | 2015-08-13 |
20150228607 | LAYER STACKS AND INTEGRATED CIRCUIT ARRANGEMENTS - In various embodiments, a layer stack is provided. The layer stack may include a carrier; a first metal disposed over the carrier; a second metal disposed over the first metal; and a solder material disposed above the second metal or a material that provides contact to a solder that is supplied by an external source. The second metal may have a melting temperature of at least 1800° C. and is not or substantially not dissolved in the solder material at least one of during a soldering process and after the soldering process. | 2015-08-13 |
20150228608 | Semiconductor Device With An Interlocking Wire Bond - In one embodiment, a semiconductor device having a die attach pad, an interlocking wire bond, a semiconductor die and an adhesive material is disclosed. The adhesive material may be configured to adjoin the semiconductor die and the die attach pad. A portion of the interlocking wire bond may be submerged within the adhesive material. In another embodiment, a device having a semiconductor die, a die attach glue and a die attach pad is disclosed. The device may comprise an interlock bonding structure submerged within the adhesive material. In yet another embodiment, a light-emitting device comprising an interlock structure is disclosed. | 2015-08-13 |
20150228609 | SEMICONDUCTOR DEVICE - Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads. | 2015-08-13 |
20150228610 | Semiconductor Package Including a Power Stage and Integrated Output Inductor - In one implementation, a power semiconductor package includes a conductive carrier including a switch node segment and a power output segment. The power semiconductor package also includes an integrated output inductor stacked over the conductive carrier and configured to couple the switch node segment to the power output segment. The power semiconductor package further includes a power stage stacked over the integrated output inductor, the power stage including a pulse-width modulation (PWM) control and driver coupled to a control transistor and a sync transistor. | 2015-08-13 |
20150228611 | SEMICONDUCTOR DEVICE WITH AN INTERLOCKING STRUCTURE - In one embodiment, a semiconductor device having a die attach pad, a semiconductor die and an adhesive material is disclosed. The adhesive material may be configured to adjoin the semiconductor die and the die attach pad. The die attach pad may be sandwiched between the semiconductor die and the die attach pad. In another embodiment, a device having a semiconductor die, a die attach glue and a die attach pad is disclosed. The device may comprise an interlock structure formed integrally with the die attach pad. In yet another embodiment, a light-emitting device comprising an interlock structure is disclosed. | 2015-08-13 |
20150228612 | DIE BONDING APPARATUS - The die bonding apparatus including a transferring unit, a loading member loading a substrate to the transferring unit, an unloading member unloading the substrate from the transferring unit, a wafer holder supporting a wafer providing dies, and a bonding member picking up one of the dies from the wafer and bonding the picked-up die to the substrate loaded on the transferring unit by pressuring the picked-up die against the substrate using a gas may be provided. | 2015-08-13 |
20150228613 | Apparatus and Method for Placing and Mounting Solder Balls on an Integrated Circuit Substrate - An apparatus for placing and mounting solder balls on an integrated circuit substrate contains: a fixture, a vacuuming device, a guiding plate, and a storage tank. The fixture includes a plurality of first grooves defined therein, the vacuuming device is disposed over the fixture and includes a vacuum chamber which has an air pore so that when air is drawn out of the vacuum chamber via the air pore, a plurality of solder balls are attached, and when the air is fed into the vacuum chamber from the air pore, the plurality of solder balls are released. The guiding plate is secured below the fixture, and the storage tank is arranged below the guiding plate and is applied to accommodate the plurality of solder balls. Thereby, a production yield of placing and mounting the plurality of solder balls on an integrated circuit substrate is enhanced. | 2015-08-13 |
20150228614 | 3D BOND AND ASSEMBLY PROCESS FOR SEVERELY BOWED INTERPOSER DIE - An interposer structure containing a first set of solder balls is placed in proximity to a vacuum distribution plate which has a planar contact surface and a plurality of openings located therein. A vacuum is then applied through the openings within the vacuum distribution plate such that the first set of solder balls are suspended within the plurality of openings and the interposer structure conforms to the planar contact surface of the vacuum distribution plate. A semiconductor chip containing a second set of solder balls is tacked to a surface of the interposer structure. A substrate is then brought into contact with a surface of the interposer structure containing the first set of solder balls, and then a solder reflow and underfill processes can be performed. Warping of the interposer structure is substantially eliminated using the vacuum distribution plate mentioned above. | 2015-08-13 |
20150228615 | METHOD FOR FORMING INTERPOSERS AND STACKED MEMORY DEVICES - Methods for forming a stacking interposer are provided that create a more compact and/or reliable interposer cavity. According to one method, a segmentation process that partially cuts a multi-cell, multi-layer PCB panel to a controlled depth along the internal walls/edges of a cavity region with each of the interposer cell sites defined within the PCB panel is used. The material within the cavity region is then removed (by routing) to a controlled depth to form the internal cavity for each interposer cell site. Pillars may then be removed from the PCB panel. As a result of the initial partial cuts of the internal walls of the cavity region, the corners of the cavities may have a square configuration for fitting over the top of a BGA/memory device (which has very square corners). | 2015-08-13 |
20150228616 | Semiconductor Modules with Semiconductor Dies Bonded to a Metal Foil - A method of manufacturing semiconductor modules includes providing a metal composite substrate including a metal foil attached to a metal layer, the metal foil being thinner than and comprising a different material than the metal layer, attaching a first surface of a plurality of semiconductor dies to the metal foil prior to structuring the metal foil, and encasing the semiconductor dies attached to the metal foil in an electrically insulating material. The metal layer and the metal foil are structured after the semiconductor dies are encased with the electrically insulating material so that surface regions of the electrically insulating material are devoid of the metal foil and the metal layer. The electrically insulating material is divided along the surface regions devoid of the metal foil and the metal layer to form individual modules. | 2015-08-13 |
20150228617 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device and a method of manufacturing the same. In the method of manufacturing a semiconductor device, a substrate is prepared which is transparent and has a plurality of first electrodes thereon, and a semiconductor chip having a plurality of second electrodes thereon is disposed on the substrate to allow the first and second electrodes to respectively face each other. A polymer layer including solder particles and an oxidizing agent is formed between the substrate and the semiconductor chip, and the solder particles is locally fused between the first and second electrodes by using a laser beam and a fused solder layer is formed which electrically connects between the first and second electrodes. | 2015-08-13 |
20150228618 | Method of Manufacturing Semiconductor Device - A method of manufacturing a semiconductor device which improves the reliability of a semiconductor device. The method of manufacturing the semiconductor device includes the step of connecting a ball portion formed at the tip of a wire with a pad (electrode pad) of a semiconductor chip. The pad is comprised of an aluminum-based material and has a trench in its portion to be connected with the ball portion. The ball portion is comprised of a harder material than gold. The step of connecting the ball portion includes the step of applying ultrasonic waves to the ball portion. | 2015-08-13 |
20150228619 | ELECTRONIC COMPONENT PACKAGE AND METHOD FOR MANUFACTURING SAME - There is provided a method for manufacturing an electronic component package, wherein a first electronic component and a second electronic component are placed on a carrier, and a sealing resin layer is formed on the carrier, followed by the carrier being peeled away to be removed, and thereby providing a package precursor in which the first and second electronic components are embedded such that an electrode of at least one of the first and second electronic components is exposed at a surface of the sealing resin layer. Upon the placing of the first and second electronic components, the first and second electronic components are positioned such that their height levels differ from each other. After the removal of the carrier, a metal plating layer is formed such that the metal plating layer is in contact with the exposed surface of the electrode of the at least one of the first and second electronic components. | 2015-08-13 |
20150228620 | BUNDLED MEMORY AND MANUFACTURE METHOD FOR A BUNDLED MEMORY WITH AN EXTERNAL INPUT/OUTPUT BUS - A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus. | 2015-08-13 |
20150228621 | SEMICONDUCTOR DEVICE INCLUDING ALTERNATING STEPPED SEMICONDUCTOR DIE STACKS - A semiconductor device including alternating stepped semiconductor die stacks to allow for large numbers of semiconductor die to be provided within a semiconductor device using short wire bonds. | 2015-08-13 |
20150228622 | CHIP SUPPORT SUBSTRATE, CHIP SUPPORT METHOD, THREE-DIMENSIONAL INTEGRATED CIRCUIT, ASSEMBLY DEVICE, AND FABRICATION METHOD OF THREE-DIMENSIONAL INTEGRATED CIRCUIT - The present invention relates to a chip support substrate including a lyophilic region | 2015-08-13 |
20150228623 | STAIRCASE-SHAPED CONNECTION STRUCTURES OF THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions. | 2015-08-13 |
20150228624 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a wiring substrate, a first semiconductor chip flip-chip connected to the wiring substrate, a first underfill resin filled between the wiring substrate and the first semiconductor chip, the first underfill resin including a pedestal portion arranged in a periphery of the first semiconductor chip, a second semiconductor chip flip-chip connected to the first semiconductor chip, and being larger in area than the first semiconductor chip, and a second underfill resin filled between the first semiconductor chip and the second semiconductor chip, the second underfill resin covering an upper face of the pedestal portion of the first underfill resin and a side face of the second semiconductor chip. | 2015-08-13 |
20150228625 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - There are provided a semiconductor package and a method of manufacturing the same. According to an exemplary embodiment of the present disclosure, a semiconductor package includes: a semiconductor device formed in a multilayer; a plurality of wires electrically connected to both sides of a plurality of semiconductor devices; a first mold via electrically connected to the plurality of wires which are formed at one side of the plurality of semiconductor devices; a second mold via electrically connected to the plurality of wires which are formed at the other side of the plurality of semiconductor device; and a first molding part enclosing the plurality of semiconductor device and formed to expose upper surface parts of the first mold via and the second mold via. | 2015-08-13 |
20150228626 | ACCESSING OR INTERCONNECTING INTEGRATED CIRCUITS - Multiple integrated circuits (ICs) die, from different wafers, can be picked-and-placed, front-side planarized using a vacuum applied to a planarizing disk, and attached to each other or a substrate. The streets between the IC die can be filled, and certain techniques or fixtures allow application of monolithic semiconductor wafer processing for interconnecting different die. High density I/O connections between different IC die can be obtained using structures and techniques for aligning vias to I/O structures, and programmably routing IC I/O lines to appropriate vias. Existing IC die can be retrofitted for such interconnection to other IC die, such as by using similar techniques or tools. | 2015-08-13 |
20150228627 | STACKED SEMICONDUCTOR PACKAGES, METHODS FOR FABRICATING THE SAME, AND /OR SYSTEMS EMPLOYING THE SAME - An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound. | 2015-08-13 |
20150228628 | Semiconductor Device and Method of Embedding Thermally Conductive Layer in Interconnect Structure for Heat Dissipation - A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer. | 2015-08-13 |
20150228629 | DIMMABLE LIGHT-EMITTED DIODE (LED) PACKAGING STRUCTURE - A dimmable light-emitted diode (LED) packaging structure is described. The dimmable LED packaging structure employs a plurality of first fluorescent layers respectively positioned on some of a plurality of first types of LED chips to solve the problems of color temperature and light mixing uniformity. Further, a second fluorescent layer overlays the first fluorescent layers and a potion of the first types of LED chips to simplify the manufacturing step of dimmable LED packaging structure. | 2015-08-13 |
20150228630 | LIGHT-EMITTING DIODE MODULE AND MOTOR VEHICLE HEADLIGHT - A light-emitting diode module includes a carrier and a plurality of optoelectronic semiconductor chips mounted on a carrier top and configured to generate primary radiation. The semiconductor chips are arranged in part at a first distance and in part at a second, greater distance from one another. Between the adjacent semiconductor chips arranged at the first distance from one another there is located a radiation-transmissive first filling for optical coupling. Between the adjacent semiconductor chips arranged at the second distance from one another there is located a radiation-opaque second filling for optical isolation. | 2015-08-13 |
20150228631 | PROCESS FOR FORMING ULTRA-MICRO LEDS - A flexible light sheet includes a bottom conductor layer overlying a flexible substrate. An array of vertical light emitting diodes (VLEDs) is printed as an ink over the bottom conductor layer so that bottom electrodes of the VLEDs electrically contact the bottom conductor layer. A top electrode of the VLEDs is formed of a first transparent conductor layer, and a temporary hydrophobic layer is formed over the first transparent conductor layer. A dielectric material is deposited between the VLEDs but is automatically de-wetted off the hydrophobic layer. The hydrophobic layer is then removed, and a second transparent conductor layer is deposited to electrically contact the top electrode of the VLEDs. The VLEDs can be made less than 10 microns in diameter since no top metal bump electrode is used. The VLEDs are illuminated by a voltage differential between the bottom conductor layer and the second transparent conductor layer. | 2015-08-13 |
20150228632 | Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices - Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die. | 2015-08-13 |
20150228633 | FRONT FACING PIGGYBACK WAFER ASSEMBLY - Front facing piggyback wafer assembly. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The plurality of piggyback substrates are dissimilar in composition to the carrier wafer. The plurality of piggyback substrates are processed, while attached to the carrier wafer, to produce a plurality of integrated circuit devices. The plurality of integrated circuit devices are singulated to form individual integrated circuit devices. The carrier wafer may be processed to form integrated circuit structures prior to the attaching. | 2015-08-13 |
20150228634 | LED CIRCUIT - An LED circuit ( | 2015-08-13 |
20150228635 | INTEGRATED CIRCUIT DEVICE HAVING SUPPORTS FOR USE IN A MULTI-DIMENSIONAL DIE STACK - Provided is an integrated circuit (IC) device having a support structure for use in a multi-dimensional (e.g., 3-D) die stack. The IC device includes a first chip (e.g., a memory die) positioned over a second chip (e.g., a logic layer), and a set of support structures between the memory die and the logic layer, wherein the set of support structures is arranged so as to radiate from a center of the memory die. In one approach, the set of support structures comprises two linear arrays each including a plurality of support members coupled to the memory die, the two linear arrays arranged in a standardized diagonal crossing configuration to provide increased stability between the memory die and the logic layer. In an exemplary embodiment, the set of support structures is connected to a power grid to help deliver power to circuitry of the memory die. | 2015-08-13 |
20150228636 | LAYOUT OF COMPOSITE CIRCUIT ELEMENTS - Physical layouts of ratioed circuit elements, such as transistors, are disclosed. Such layouts can maintain electrical characteristics of the ratioed circuit elements relative to one another in the presence of mechanical stresses applied to an integrated circuit, such as an integrated circuit encapsulated in plastic. The ratioed circuit elements can include first and second composite circuit elements formed of first and second groups of circuit elements, respectively, arranged around a center point. The first group of circuit elements can be arranged on a grid and the second group of circuit elements can include four circuit elements spaced approximately the same distance from the center point. Each of the circuit elements in the second group can be off the grid in at least one dimension. The first and second groups of circuit elements can be arranged around a perimeter of dummy circuit elements in some embodiments. | 2015-08-13 |
20150228637 | PATTERN ARRANGEMENT METHOD, SILICON WAFER AND SEMICONDUCTOR DEVICE USING A SILICON WAFER WITH A PATTERN ARRANGEMENT - A silicon wafer includes a plurality of chip patterns arranged parallel to a first direction and a second direction intersecting the first direction, wherein the plurality of chip patterns include one or more patterns arranged in the first direction and the second direction in a straight line, the plurality of chip patterns include a first chip pattern and a second chip pattern adjacent to the first chip pattern, and the second chip pattern is arranged by rotating the first chip pattern at 90 degrees, the plurality of chip patterns are arranged so that an axis in which a cleavage plane of the silicon wafer and a surface arranged with the pattern on the silicon wafer intersect, and the first direction are different, and an angle between the axis and the first direction of the second chip pattern is 90 degrees. | 2015-08-13 |
20150228638 | Diode Circuit Layout Topology With Reduced Lateral Parasitic Bipolar Action - Diode circuit layout topologies and methods are disclosed that exhibit reduced lateral parasitic bipolar characteristics at lateral parasitic bipolar circuit emitter edges during ESD or other voltage events as compared to conventional circuit layout topologies. The disclosed diode circuit layout topologies may be implemented to recess parasitic emitter ends relative to surrounding well ties, for example, to reduce or substantially eliminate parasitic bipolar action at lateral emitter edges of the circuitry during ESD events so as to provide higher current threshold for device failure, allowing for smaller device area and/or improved ESD robustness for a given circuit device. | 2015-08-13 |
20150228639 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device having a P-type substrate, a common N-well formed in the P-type substrate, a common N-doped region formed in the first common N-well, wherein the common N-doped region is electrically connected to a reference voltage node. The device further has a common P-doped region formed in the common N-well, wherein the common P-doped region surrounds the common N-doped region, the common P-doped region and the common N-well form a common diode, a plurality of peripheral N-wells formed in the P-type substrate and surrounding the common N-well, each of the peripheral N-wells comprising a P-type doped region and a N-type doped region, wherein the P-type doped region is electrically connected to one of a plurality of I/O terminals, and a circular P-doped region formed in the P-type substrate and disposed between the common N-well and the peripheral N-wells, and the circular P-doped region surrounding the common N-well. | 2015-08-13 |
20150228640 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor device. The semiconductor device includes: a first semiconductor layer having a first region with a first device and a second region with a second device; a device isolation pattern provided in the first semiconductor layer and electrically separating the first device and the second device from each other; a drain provided on a lower surface of the first region of the first semiconductor layer; and a second semiconductor layer provided on a lower surface of the second region of the first semiconductor layer. | 2015-08-13 |
20150228641 | SEMICONDUCTOR DEVICE, CONTROL IC FOR SWITCHING POWER SUPPLY, AND SWITCHING POWER SUPPLY UNIT - Aspects of the invention can include a semiconductor device, control IC for switching power supply and switching power supply unit, which allow input voltage detecting function to be realized without resistor-voltage dividing circuit. An npn-type element consisting of p-type region, collector region and emitter region is included inside of drain region of starting element. On a first interlayer insulating film, aspects of the invention can provide collector electrode wiring of npn-type element, emitter-drain electrode wiring serving as both emitter electrode wiring of npn-type electrode and drain electrode wiring of starting element, source electrode wiring of starting element, and gate electrode wiring of starting element. A first metal wiring can serve both as input terminal of starting element and input terminal of npn-type element is connected to collector electrode wiring. The npn-type element can function as input voltage detecting means for detecting input voltage drop applied to the first wiring. | 2015-08-13 |
20150228642 | SEMICONDUCTOR ELEMENT, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor element includes a first transistor section, a second transistor section, a contact region, and a capacitive element section. The first transistor section includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, the third semiconductor region, and the third semiconductor region being connected to the second electrode, and a third electrode. The second transistor section includes a fourth electrode, a fifth electrode, a fourth semiconductor region, a fifth semiconductor region, a sixth semiconductor region, and the sixth semiconductor region being connected to the fifth electrode, and a sixth electrode, the second transistor section being arranged adjacent to the first transistor section. The contact region includes a seventh electrode, electrically connecting the fifth electrode and the first electrode. The capacitive element section is connected between the second electrode and the fourth electrode. | 2015-08-13 |
20150228643 | DIODE-CONNECTED BIPOLAR JUNCTION TRANSISTORS AND ELECTRONIC CIRCUITS INCLUDING THE SAME - A diode-connected bipolar junction transistor includes a common collector region of a first conductivity, a common base region of a second conductivity disposed over the common collector region, and a plurality of emitter regions of the first conductivity disposed over the common base region, arranged to be spaced apart from each other, and arranged to have island shapes. | 2015-08-13 |
20150228644 | CAPACITOR ARRAY HAVING CAPACITOR CELL STRUCTURES - A capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures of the plurality of cell structures each includes a first capacitor electrode, a second capacitor electrode over the first capacitor electrode, a third capacitor electrode adjacent to first sidewalls of the first and second capacitor electrodes, a fourth capacitor electrode adjacent to second sidewalls of the first and second capacitor electrodes, and a fifth capacitor electrode adjacent to the fourth capacitor electrode. | 2015-08-13 |
20150228645 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device includes a semiconductor substrate, and first and second transistors over the semiconductor substrate. Both the first and second transistors are p-type transistors or both the first and second transistors are n-type transistors. The first and second transistors have the same nominal operating voltage. The first transistor has a higher threshold voltage than the second transistor. The second transistor has at least one of a source region or a drain region with higher charge carrier mobility than at least one of a source region or a drain region of the first transistor. | 2015-08-13 |
20150228646 | GATE STRUCTURES WITH VARIOUS WIDTHS AND METHOD FOR FORMING THE SAME - Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure. | 2015-08-13 |
20150228647 | INDENTED GATE END OF NON-PLANAR TRANSISTOR - In some embodiments, a semiconductor structure includes a substrate, a dielectric region, a non-planar structure and a gate stack. The dielectric region is formed on the substrate, and has a top surface. The non-planar structure protrudes from the top surface, and includes a channel region, and source and drain regions formed on opposite sides of the channel region. The gate stack is formed on the top surface, wraps around the channel region, and includes a gate top surface, and a gate side wall that does not intersect the non-planar structure. The gate side wall has a first distance from a vertical plane at a level of the top surface, and a second distance from the vertical plane at a level of the gate top surface. The vertical plane is vertical with respect to the top surface, and intersects the non-planar structure. The first distance is shorter than the second distance. | 2015-08-13 |
20150228648 | FINFET WITH MULTILAYER FINS FOR MULTI-VALUE LOGIC (MVL) APPLICATIONS AND METHOD OF FORMING - A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers. | 2015-08-13 |
20150228649 | TRANSISTOR WITH WELL TAP IMPLANT - A fin of a FinFET, being p or n-type, includes a well encompassing the active region, the well being of the opposite type than the fin. An implant of the same type as the well is provided for the well tap at an edge of the active region. A dummy gate material on the fin between the source/drain and the well tap implant reduces an inherent resistance of a well tap contact. | 2015-08-13 |
20150228650 | STANDARD CELL GLOBAL ROUTING CHANNELS OVER ACTIVE REGIONS - An integrated circuit chip includes CMOS integrated circuit cells arranged in a semiconductor layer, each including first and second active regions, having first and second polarities, respectively. A first power rail is routed along boundaries of the CMOS integrated circuit cells proximate to the first active regions. A second power rail is routed over second active regions. Global routing channels are routed over the second active regions such that the second power rail is disposed between the global routing channels and the first power rail. The global routing channels are coupled between the CMOS integrated circuit cells to couple the CMOS integrated circuit cells together globally in the integrated circuit chip. | 2015-08-13 |
20150228651 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of formation are provided. A semiconductor arrangement includes a first semiconductor device adjacent a second semiconductor device. The first semiconductor device includes a first gate over a first shallow well in a substrate. A first active area is in the first shallow well on a first side of the first gate. The second semiconductor device includes a second gate over a second shallow well. A third active area is in the second shallow well on a first side of the second gate. The second shallow well abuts the first shallow well in the substrate to form a P-N junction. The P-N junction increases capacitance of the semiconductor arrangement, as compared to a device without such a P-N junction. | 2015-08-13 |
20150228652 | SEMICONDUCTOR DEVICE INCLUDING NANOWIRE TRANSISTORS WITH HYBRID CHANNELS - A semiconductor device is provided that includes an n-type field effect transistor including a plurality of vertically stacked silicon-containing nanowires located in one region of a semiconductor substrate, and a p-type field effect transistor including a plurality of vertically stacked silicon germanium alloy nanowires located in another region of a semiconductor substrate. Each vertically stacked silicon-containing nanowire of the n-type field effect transistor has a different shape than the shape of each vertically stacked silicon germanium alloy nanowire of the p-type field effect transistor. | 2015-08-13 |
20150228653 | SiGe and Si FinFET Structures and Methods for Making the Same - FinFET structures and methods for making the same. A method includes: creating a plurality of Silicon fins on a first region of a substrate, creating a plurality of Silicon-Germanium fins on a second region of the substrate, adjusting a Silicon fin pitch of the plurality of Silicon fins to a predetermined value, and adjusting a Silicon-Germanium fin pitch of the plurality of Silicon-Germanium fins to a predetermined value, where the creating steps are performed in a manner that Silicon material and Silicon-Germanium material used in making the plurality of fins will be on the semiconductor structure at a same time. | 2015-08-13 |
20150228654 | METHOD AND STRUCTURE FOR FINFET CMOS - According to an embodiment, the invention provides an nFET/pFET pair of finFETs formed on a gate stack. At least one fin extends into a source drain region of each of the FET pair and a carbon doped silicon (Si:C) layer is formed on each such fin. Another aspect of the invention is a process flow to enable dual in-situ doped epitaxy to fill the nFET and pFET source drain with different epi materials while avoiding a ridge in the hard cap on the gate between the pair of finFETS. The gate spacer in both of the pair can be the same thickness. The extension region of both of the pair of finFETs can be activated by a single anneal. | 2015-08-13 |
20150228655 | SEMICONDUCTOR DEVICE - Provided is a semiconductor resistor circuit with high accuracy. An insulating film is formed to cover a plurality of resistor groups having upper portions covered with a plurality of metal wirings. The insulating film has a membrane stress that is higher than that of the metal wirings, and is formed between the metal wirings and the resistor groups. | 2015-08-13 |
20150228656 | REPLACEMENT GATE COMPATIBLE eDRAM TRANSISTOR WITH RECESSED CHANNEL - An eDRAM is fabricated including high performance logic transistor technology and ultra low leakage DRAM transistor technology. Embodiments include forming a recessed channel in a substrate, forming a first gate oxide to a first thickness lining the channel and a second gate oxide to a second thickness over a portion of an upper surface of the substrate, forming a first polysilicon gate in the recessed channel and overlying the recessed channel, forming a second polysilicon gate on the second gate oxide, forming spacers on opposite sides of each of the first and second polysilicon gates, removing the first and second polysilicon gates forming first and second cavities, forming a high-k dielectric layer on the first and second gate oxides, and forming first and second metal gates in the first and second cavities, respectively. | 2015-08-13 |
20150228657 | SEMICONDUCTOR DEVICE, MODULE AND SYSTEM EACH INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A barrier for preventing a bridge between adjacent storage node contacts is formed below a bit line located between the bit line contacts, so that a contact region between each storage node contact and an active region is increased in size. The semiconductor device includes a device isolation film defining an active region, a bit line contact coupling the active region to a bit line, and a barrier formed below the bit line located between the bit line contacts. | 2015-08-13 |
20150228658 | Semiconductor Device - Provided is a semiconductor device wherein chip size is reduced, while potential on the dummy word lines is fixed. The semiconductor device is provided with: a memory cell array including a plurality of memory cells, a plurality of word lines for controlling memory operations of the plurality of memory cells, and a plurality of dummy word lines that do not participate in memory operations of the plurality of memory cells; and a guard ring surrounding the memory cell array. The plurality of dummy word lines are electrically fixed to the guard ring. | 2015-08-13 |
20150228659 | DATA LINE ARRANGEMENT AND PILLAR ARRANGEMENT IN APPARATUSES - Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD). | 2015-08-13 |
20150228660 | SEMICONDUCTOR DEVICES HAVING AIRGAPS AND METHODS OF MANUFACTURING THE SAME - Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction. | 2015-08-13 |
20150228661 | SELF-ALIGNED LINER METHOD OF AVOIDING PL GATE DAMAGE - A self-align method of preparing semiconductor gates for formation of a silicide, such as a cobalt silicide (CoSi) layer, is disclosed. Deposition of silicon nitride (SiN) and low-temperature oxide (LTO) liner types, the SiN liner having an overhang structure, prevent damage to the gates while forming a self-aligned source. The undamaged gates are suitable for CoSi deposition. | 2015-08-13 |
20150228662 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH CHARGE STORAGE LAYER IN MEMORY CELL - A nonvolatile semiconductor memory device includes a semiconductor portion, a first oxygen-containing portion provided on the semiconductor portion, a silicon-containing portion provided on the first oxygen-containing portion, a first film provided on the silicon-containing portion and including a lamination of a first portion containing silicon and oxygen and a second portion containing silicon and nitrogen, a first high dielectric insulating portion provided on the first film and having an oxide-containing yttrium, hafnium or aluminum, a second oxygen-containing portion provided on the first high dielectric insulating portion, a second high dielectric insulating portion provided on the second oxygen-containing insulating portion and having an oxide-containing yttrium, hafnium or aluminum, a third oxygen-containing portion provided on the second high dielectric insulating portion, and a second film provided on the third oxygen-containing portion. | 2015-08-13 |
20150228663 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING NICKEL-CONTAINING FILM - A method of manufacturing a semiconductor device is provided. A substrate including a structure in which a hole is formed is prepared. Precursors including a nickel alkoxide compound are vaporized. A nickel-containing layer is formed in the hole by providing the vaporized precursors including the nickel alkoxide compound onto the substrate. | 2015-08-13 |
20150228664 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes a first switching element, an organic layer disposed on the first switching element, a capping layer disposed on the organic layer and a cover electrode covering the first emission hole. The first switching element is electrically connected to a gate line extending in a first direction, a data line extending in a second direction crossing the first direction and the pixel electrode disposed adjacent to the data line. The capping layer includes a first emission hole. The cover electrode overlaps the gate line as a first width. The cover electrode overlaps the first switching element as a second width. The second width is smaller than the first width. | 2015-08-13 |
20150228665 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes a substrate, a gate line and a data line on the substrate, a thin film transistor on the substrate, being connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and an insulating layer on the substrate, wherein the insulating layer has a contact hole extending therethrough and the contact hole has a relatively steep sidewall including a sidewall portion with a sidewall taper angle of about 60° to about 90°. | 2015-08-13 |
20150228666 | ELECTRO-OPTIC DISPLAY BACKPLANE STRUCTURES WITH DRIVE COMPONENTS AND PIXEL ELECTRODES ON OPPOSED SURFACES - This invention relates to an electro-optic display having a backplane with a front surface and a reverse surface on opposed sides of the backplane, a front surface having a plurality of pixel electrodes arranged in a matrix of columns and rows with column and row lines, a reverse surface having at least one driver chip, and conductive vias electrically connecting the column and row lines on the front surface to the driver chip on the reverse surface, such that the entire front surface area may be optically active. | 2015-08-13 |
20150228667 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THE SAME - An object is to manufacture and provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region serves as an oxide semiconductor film, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed after an oxide insulating film serving as a protective film is formed in contact with an oxide semiconductor layer. Then, the impurities such as moisture, which exist not only in a source electrode layer, in a drain electrode layer, in a gate insulating layer, and in the oxide semiconductor layer but also at interfaces between the oxide semiconductor film and upper and lower films which are in contact with the oxide semiconductor layer, are reduced. | 2015-08-13 |
20150228668 | ENABLING BULK FINFET-BASED DEVICES FOR FINFET TECHNOLOGY WITH DIELECTRIC ISOLATION - A method for forming a dielectric-isolated bulk fin field-effect transistor (finFET) device includes forming a second isolation layer over a first structure including multiple partially exposed fins and horizontal areas including a first isolation layer. The second isolation layer is removed from horizontal areas of a first portion of the first structure. An oxide layer is formed under the fins of the first portion of the first structure. The second isolation layer is removed in order to expose the partially exposed fins and horizontal areas of the first structure to form a second structure, on which gate regions are formed. | 2015-08-13 |
20150228669 | METHOD TO FORM GROUP III-V AND Si/Ge FINFET ON INSULATOR - A method includes providing a structure having a substrate, a first electrically insulating layer overlying the substrate, a first semiconductor layer comprised of a first semiconductor material overlying the first electrically insulating layer, a second electrically insulating layer overlying the first semiconductor layer in a first portion of the structure and a second semiconductor layer comprised of a second, different semiconductor material overlying the second electrically insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure to form a regrown semiconductor layer; forming fins; forming gate structures orthogonal to the fins and removing at least a portion of the first semiconductor layer in the first portion of the structure to form a void and filling the void with insulating material. Structures formed by the method are also disclosed. | 2015-08-13 |
20150228670 | METHOD TO FORM DUAL CHANNEL GROUP III-V AND Si/Ge FINFET CMOS - A method includes providing a structure having a substrate, a first insulating layer on the substrate, a first semiconductor material layer on the first insulating layer, a second insulating layer on the first semiconductor layer in a first portion of the structure and a second semiconductor layer of a second, different semiconductor material on the second insulating layer in the first portion. The method further includes growing additional first semiconductor material on the first semiconductor layer in a second portion of the structure forming a regrown semiconductor layer; forming first fins in the regrown semiconductor layer and second fins in the second semiconductor layer; and forming gate structures upon the first and second fins. A height difference, relative to a surface of the first insulating layer, of the gate structures formed upon the first fins and the gate structures formed upon the second fins is less than a predetermined value. | 2015-08-13 |
20150228671 | METHOD OF MANUFACTURING A FinFET DEVICE USING A SACRIFICIAL EPITAXY REGION FOR IMPROVED FIN MERGE AND FinFET DEVICE FORMED BY SAME - A method for manufacturing a fin field-effect transistor (FinFET) device comprises forming a plurality of fins on a substrate, epitaxially growing a sacrificial epitaxy region between the fins, stopping growth of the sacrificial epitaxy region at a beginning of merging of epitaxial shapes between neighboring fins, and forming a dielectric layer on the substrate including the fins and the sacrificial epitaxy region, wherein a portion of the dielectric layer is positioned between the sacrificial epitaxy region extending from fins of adjacent transistors. | 2015-08-13 |
20150228672 | FINFET DEVICE - A method for fabricating a field effect transistor device includes removing a portion of a first semiconductor layer and a first insulator layer to expose a portion of a second semiconductor layer, wherein the second semiconductor layer is disposed on a second insulator layer, the first insulator layer is disposed on the second semiconductor layer, and the first semiconductor layer is disposed on the first insulator layer, removing portions of the first semiconductor layer to form a first fin disposed on the first insulator layer and removing portions of the second semiconductor layer to form a second fin disposed on the second insulator layer, and forming a first gate stack over a portion of the first fin and forming a second gate stack over a portion of the second fin. | 2015-08-13 |
20150228673 | DISPLAY PANEL AND ACTIVE DEVICE THEREOF - A display panel and an active device thereof are provided. The active device includes a gate, a semiconductor layer, a first source and a plurality of first drains. The first source includes a first side and a second side opposite to each other, the first side has a plurality of first recesses, and the second side has a plurality of second recesses. Each of the first recesses and a corresponding second recess are disposed opposite to each other to constitute a recess-pair. A minimum distance between the first recess and the second recess of each recess-pair is A, a minimum distance between two neighboring recess-pairs is B, wherein A is greater than B. The first drains are electrically connected to each other, and each of the first drains is respectively disposed in one of the recesses of the first source. | 2015-08-13 |
20150228674 | THIN FILM TRANSISTOR AND DISPLAY DEVICE - Provided is a thin film transistor which is provided with an oxide semiconductor thin film layer and has a threshold voltage that does not change much due to light, a bias stress or the like, thereby exhibiting excellent stress stability. A thin film transistor of the present invention is provided with a gate electrode, an oxide semiconductor layer composed of a single layer which is used as a channel layer, an etch stopper layer to protect a surface of the oxide semiconductor layer, a source-drain electrode, and a gate insulator layer arranged between the gate electrode and the channel layer. The metal elements constituting the oxide semiconductor layer comprise In, Zn and Sn. The hydrogen concentration in the gate insulator layer in direct contact with the oxide semiconductor layer is controlled to 4 atomic % or lower. | 2015-08-13 |
20150228675 | LIQUID CRYSTAL DISPLAY - The present invention provides a liquid crystal display capable of enhancing moisture resistance and resist applicability while suppressing alignment disorder of liquid crystal molecules. The present invention relates to a liquid crystal display including: an organic insulating film; a transparent electrode arranged on the organic insulating film; and an interlayer insulating film arranged on the transparent electrode, the transparent electrode including a plasma-treated surface, the organic insulating film being shaved vertically from an end portion of the transparent electrode, and thereby including a step portion under the end portion, the transparent electrode not laterally protruding from the step portion, the step portion having a height of 20 nm or lower. | 2015-08-13 |
20150228676 | DISPLAY DEVICE AND ELECTRONIC APPLIANCE - A display device with low manufacturing cost, a display device with low power consumption, a display device capable of being formed over a large substrate, a display device with a high aperture ratio of a pixel, and a display device with high reliability are provided. The display device includes a transistor electrically connected to a light-transmitting pixel electrode and a capacitor. The transistor includes a gate electrode, a gate insulating film, and a first multilayer film including an oxide semiconductor layer. The capacitor includes the pixel electrode and a second multilayer film overlapping with the pixel electrode, positioned at a predetermined distance from the pixel electrode, and having the same layer structure as the first multilayer film. A channel formation region of the transistor is at least one layer, which is not in contact with the gate insulating film, of the first multilayer film. | 2015-08-13 |
20150228677 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced. | 2015-08-13 |
20150228678 | IMAGE PICKUP APPARATUS, ENDOSCOPE, SEMICONDUCTOR APPARATUS, AND MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS - An image pickup apparatus includes: an image pickup device chip that has junction terminals, which is connected with an image pickup unit, on a reverse surface; a cable having lead wires connected with the image pickup unit; and a wiring board that includes junction electrodes joined to the junction terminals, terminal electrodes connected with the lead wires, wirings that connect the junction electrodes formed at a central portion and the terminal electrodes formed at extending portions, and a heat transmission pattern formed in a region where the junction electrodes, the terminal electrodes and the wirings are not formed, the extending portions being bent and thereby the wiring board being arranged within a projected plane of the image pickup device chip. | 2015-08-13 |
20150228679 | UNIT PIXEL OF IMAGE SENSOR AND IMAGE SENSOR INCLUDING THE SAME - A unit pixel of an image sensor includes a photoelectric conversion region, an isolation region, a floating diffusion region and a transfer gate. The photoelectric conversion region is formed in a semiconductor substrate. The isolation region surrounds the photoelectric conversion region, extends substantially vertically with respect to a first surface of the semiconductor substrate, and crosses the incident side of the photoelectric conversion region so as to block leakage light and diffusion carriers. The floating diffusion region is disposed in the semiconductor substrate above the photoelectric conversion region. The transfer gate is disposed adjacent to the photoelectric conversion region and the floating diffusion region, extends substantially vertically with respect to the first surface of the semiconductor substrate, and transmits the photo-charges from the photoelectric conversion region to the floating diffusion region. | 2015-08-13 |
20150228680 | Infrared Reflection/Absorption Layer For Reducing Ghost Image of Infrared Reflection Noise And Image Sensor Using the Same - An image sensor includes a photosensing element for receiving infrared (IR) radiation and detecting the IR radiation and generating an electrical signal indicative of the IR radiation. A redistribution layer (RDL) is disposed under the photosensing element, the RDL comprising pattern of conductors for receiving the electrical signal. An IR reflection layer, an IR absorption layer or an isolation layer is disposed between the photosensing element and the RDL. The IR reflection layer, IR absorption layer or isolation layer provides a barrier to IR radiation such that the IR radiation does not impinge upon the RDL. As a result, a ghost image of the RDL is not generated, resulting in reduced noise and improved sensitivity and performance of the image sensor. | 2015-08-13 |
20150228681 | Method for producing optoelectronic components, and products produced thereby - The production of optoelectronic components, optical components being mounted in the composite wafer. Provided to this end is a method for producing optoelectronic components, in particular image signal acquiring or image signal outputting components, in the case of which optical components are respectively provided, picked up and mounted on a wafer, the optical components preferably respectively being positioned individually or in groups relative to the position of assigned optoelectronic or optical components of the wafer or of a wafer to be connected thereto. | 2015-08-13 |
20150228682 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided which can suppress corrosion by chemicals in processes, while preventing generation of thermal stress on a mark. A semiconductor device includes a semiconductor layer with a front-side main surface and a back-side main surface opposed to the front-side main surface, a plurality of light receiving elements formed in the semiconductor layer for performing photoelectric conversion, a light receiving lens disposed above the back-side main surface for supplying light to the light receiving element, and a mark formed inside the semiconductor layer. The mark extends from the front-side main surface to the back-side main surface. The mark has a deeply located surface recessed toward the front-side main surface rather than the back-side main surface. The deeply located surface is formed of silicon. | 2015-08-13 |
20150228683 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND PHOTOELECTRIC CONVERSION DEVICE - A semiconductor device manufacturing method includes a step of forming a hole reaching a first insulating layer over a first conductive member; a step of forming a trench reaching a second insulating layer and in communication with the hole; a step of forming an opening exposing the first conductive member in the hole; and a step of forming a second conductive member connected to the first conductive member by embedding a conductive material in the opening, the hole, and the trench. The trench is formed under an etching condition such that the etching rate with respect to the second insulating layer is lower than the etching rate with respect to the third insulating layer. | 2015-08-13 |
20150228684 | SOLID-STATE IMAGING DEVICE - According to one embodiment, in a solid-state imaging device, a signal storage portion in each of a plurality of pixels includes a first semiconductor region and a second semiconductor region. The first semiconductor region is of a first conductive type. The first semiconductor region coveres a side wall of an element isolation portion on a side of the signal storage portion. The second semiconductor region is of a second conductive type. The second conductive type is an opposite conductive type to the first conductive type. The second semiconductor region is arranged vertically in a depth direction from a deeper position than a front surface in a semiconductor substrate and extending in a plate shape along the first semiconductor region. | 2015-08-13 |
20150228685 | LIGHT RECEIVING ELEMENT, IMAGE CAPTURING ELEMENT INCLUDING THE LIGHT RECEIVING ELEMENT AND IMAGE CAPTURING APPARATUS INCLUDING THE IMAGE CAPTURING ELEMENT - A light receiving element includes a surface recombination prevention layer composed of a first compound semiconductor on which light is incident; a photoelectric conversion layer composed of a second compound semiconductor; and a compound semiconductor layer composed of a third compound semiconductor, the surface recombination prevention layer having a thickness of 30 nm or less. Also, there are provided an image capturing element including the light receiving element, and an image capturing apparatus including the image capturing element. | 2015-08-13 |
20150228686 | PHOTOELECTRIC CONVERSION APPARATUS AND PHOTOELECTRIC CONVERSION SYSTEM - A photoelectric conversion apparatus includes a first unit pixel including a first transfer transistor configured to transfer electric charges from a photoelectric conversion unit to an impurity diffusion region and a second unit pixel including a second transfer transistor configured to transfer electric charges from a photoelectric conversion unit to an impurity diffusion region, and a potential at a channel of the first transfer transistor when the first transfer transistor is on-state is higher than a potential at a channel of the second transfer transistor when the second transfer transistor is on-state. | 2015-08-13 |
20150228687 | SOLID-STATE IMAGE SENSOR AND IMAGING DEVICE - A ranging pixel located in a peripheral region of a solid-state image sensor includes a microlens having a center axis that is shifted relative to a center axis of the ranging pixel, a first photoelectric conversion unit, and a second photoelectric conversion unit. The first photoelectric conversion unit is disposed on a side of the center axis of the ranging pixel that is in a direction opposite to a direction (projection shift direction) obtained by projecting a shift direction of the microlens onto a straight line connecting a center of the first photoelectric conversion unit and a center of the second photoelectric conversion unit, and the second photoelectric conversion unit is disposed on another side of the center axis of the ranging pixel that is in a direction identical to the projection shift direction of the microlens. In addition, the area of the first photoelectric conversion unit is greater than the area of the second photoelectric conversion unit. | 2015-08-13 |
20150228688 | IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - According to one embodiment, an image sensor includes an image-sensing element region formed by arranging a plurality of image-sensing elements on a semiconductor substrate, and a logic circuit region formed in a region different from the image-sensing element region on the substrate and including a plurality of gate patterns. Further, dummy gate patterns are formed with a constant pitch on the image-sensing element region. | 2015-08-13 |
20150228689 | IMAGING SYSTEMS WITH INFRARED PIXELS HAVING INCREASED QUANTUM EFFICIENCY - An imaging device may include an image sensor having an array of image pixels. The array of image pixels may include one or more infrared pixels that are configured to detect infrared light. The infrared pixels may include reflective structures for increasing quantum efficiency in the infrared spectral range. The reflective structures may include first and second parallel structures formed on opposing sides of a photodiode in an infrared pixel. The reflective structures may be partially transparent to infrared light and non-transparent to visible light. The reflective structures may form an optical cavity so that infrared light that enters an infrared pixel is reflected back and forth between the reflective structures until it is absorbed by the photodiode in the infrared pixel. Reflective structures may also be formed between infrared filters and color filters to suppress optical crosstalk between infrared pixels and color pixels. | 2015-08-13 |
20150228690 | Pad Structure Including Glue Layer and Non-Low-K Dielectric Layer in BSI Image Sensor Chips - An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed. | 2015-08-13 |
20150228691 | FLAT PANEL DETECTOR AND MANUFACTURING METHOD THEREOF, CAMERA DEVICE - A flat panel detector comprises a photoelectric conversion layer and a pixel detecting element disposed under the photoelectric conversion layer. The pixel detecting element comprises: a pixel electrode for receiving charges, a storage capacitor for storing the received charges, and a thin film transistor for controlling outputting of the stored charges. The storage capacitor comprises a first electrode and a second electrode. The first electrode comprises an upper electrode and a bottom electrode that are disposed opposite to each other and electrically connected. A second electrode is sandwiched between the upper electrode and the bottom electrode. It is insulated between the upper electrode and the second electrode and between the second electrode and the bottom electrode. | 2015-08-13 |