33rd week of 2018 patent applcation highlights part 54 |
Patent application number | Title | Published |
20180233386 | Platen For Reducing Particle Contamination On A Substrate and a Method Thereof | 2018-08-16 |
20180233387 | Wafer Transport Assembly With Integrated Buffers | 2018-08-16 |
20180233388 | METHOD AND SYSTEM FOR DETECTING A COOLANT LEAK IN A DRY PROCESS CHAMBER WAFER CHUCK | 2018-08-16 |
20180233389 | ALIGNMENT METHOD, PATTERN FORMATION SYSTEM, AND EXPOSURE DEVICE | 2018-08-16 |
20180233390 | WAFER SUPPORT COLUMN WITH INTERLOCKING FEATURES | 2018-08-16 |
20180233391 | RETRIEVING DEVICE AND STORING DEVICE | 2018-08-16 |
20180233392 | SUBSTRATE PROCESSING SYSTEM AND SUBSTRATE TRANSFER METHOD | 2018-08-16 |
20180233393 | Methods for Controlling Clamping of Insulator-Type Substrate on Electrostatic-Type Substrate Support Structure | 2018-08-16 |
20180233394 | METHOD FOR THE BONDING AND DEBONDING OF SUBSTRATES | 2018-08-16 |
20180233395 | METHOD OF MANUFACTURING ELEMENT CHIP | 2018-08-16 |
20180233396 | SUBSTRATE POSITION CALIBRATION FOR SUBSTRATE SUPPORTS IN SUBSTRATE PROCESSING SYSTEMS | 2018-08-16 |
20180233397 | Material-Handling Robot With Multiple End-Effectors | 2018-08-16 |
20180233398 | METHOD TO CREATE AIR GAPS | 2018-08-16 |
20180233399 | Devices with Backside Metal Structures and Methods of Formation Thereof | 2018-08-16 |
20180233400 | METHOD OF DEPOSITING CHARGE TRAPPING POLYCRYSTALLINE SILICON FILMS ON SILICON SUBSTRATES WITH CONTROLLABLE FILM STRESS | 2018-08-16 |
20180233401 | LOCAL TRAP-RICH ISOLATION | 2018-08-16 |
20180233402 | SEMICONDUCTOR DEVICE | 2018-08-16 |
20180233403 | SELF-ALIGNED QUADRUPLE PATTERNING (SAQP) FOR ROUTING LAYOUTS INCLUDING MULTI-TRACK JOGS | 2018-08-16 |
20180233404 | VARIABLE SPACE MANDREL CUT FOR SELF ALIGNED DOUBLE PATTERNING | 2018-08-16 |
20180233405 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE | 2018-08-16 |
20180233406 | Method of Semiconductor Integrated Circuit Fabrication | 2018-08-16 |
20180233407 | METHOD OF FORMING A SELF-ALIGNED CONTACT USING SELECTIVE SiO2 DEPOSITION | 2018-08-16 |
20180233408 | SELF ALIGNED CONDUCTIVE LINES WITH RELAXED OVERLAY | 2018-08-16 |
20180233409 | TECHNIQUES FOR REVEALING A BACKSIDE OF AN INTEGRATED CIRCUIT DEVICE, AND ASSOCIATED CONFIGURATIONS | 2018-08-16 |
20180233410 | WAFER DICING METHODS | 2018-08-16 |
20180233411 | SEMICONDUCTOR DIE SINGULATION METHODS | 2018-08-16 |
20180233412 | FORMING TS CUT FOR ZERO OR NEGATIVE TS EXTENSION AND RESULTING DEVICE | 2018-08-16 |
20180233413 | GRAPHENE CONTACTS ON SOURCE/DRAIN REGIONS OF FINFET DEVICES | 2018-08-16 |
20180233414 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH WIDER SIDEWALL SPACER FOR A HIGH VOLTAGE MISFET | 2018-08-16 |
20180233415 | FINFET DEVICE AND METHOD OF MANUFACTURING | 2018-08-16 |
20180233416 | METHOD FOR PREVENTING DISHING DURING THE MANUFACTURE OF SEMICONDUCTOR DEVICES | 2018-08-16 |
20180233417 | DUAL LINER SILICIDE | 2018-08-16 |
20180233418 | STRUCTURE AND METHOD FOR TENSILE AND COMPRESSIVE STRAINED SILICON GERMANIUM WITH SAME GERMANIUM CONCENTRATION BY SINGLE EPITAXY STEP | 2018-08-16 |
20180233419 | OVERLAY MARK AND METHOD FOR EVALUATING STABILITY OF SEMICONDUCTOR MANUFACTURING PROCESS | 2018-08-16 |
20180233420 | METHODS FOR ASSESSING SEMICONDUCTOR STRUCTURES | 2018-08-16 |
20180233421 | Semiconductor Package, Assembly and Module Arrangements for Measuring Gate-to-Emitter/Source Voltage | 2018-08-16 |
20180233422 | SEMICONDUCTOR PACKAGE WITH A WIRE BOND MESH | 2018-08-16 |
20180233423 | FLIP-CHIP MOUNTING OF SILICON-ON-INSULATOR DIE | 2018-08-16 |
20180233424 | SEMICONDUCTOR PACKAGE DEVICE | 2018-08-16 |
20180233425 | SEMICONDUCTOR PACKAGE WITH EMBEDDED SUPPORTER AND METHOD FOR FABRICATING THE SAME | 2018-08-16 |
20180233426 | Chip scale package | 2018-08-16 |
20180233427 | GRAPHITE HEAT SINK | 2018-08-16 |
20180233428 | HEAT DISSIPATION ASSEMBLY | 2018-08-16 |
20180233429 | MULTILAYER BOARD AND ELECTRONIC DEVICE | 2018-08-16 |
20180233430 | PROCESSING DEVICE AND PROCESSING SYSTEM | 2018-08-16 |
20180233431 | LITHOGRAPHACALLY DEFINED VIAS FOR ORGANIC PACKAGE SUBSTRATE SCALING | 2018-08-16 |
20180233432 | ELECTRONIC COMPONENT PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME | 2018-08-16 |
20180233433 | FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME | 2018-08-16 |
20180233434 | SEMICONDUCTOR DEVICE | 2018-08-16 |
20180233435 | SEMICONDUCTOR DEVICE | 2018-08-16 |
20180233436 | CHIP-ON-FILM PACKAGE, DISPLAY PANEL, AND DISPLAY DEVICE | 2018-08-16 |
20180233437 | SEMICONDUCTOR DEVICE | 2018-08-16 |
20180233438 | LEADFRAME, SEMICONDUCTOR PACKAGE INCLUDING A LEADFRAME AND METHOD FOR FORMING A SEMICONDUCTOR PACKAGE | 2018-08-16 |
20180233439 | SEMICONDUCTOR CHIP PACKAGE HAVING HEAT DISSIPATING STRUCTURE | 2018-08-16 |
20180233440 | RECONSTITUTED INTERPOSER SEMICONDUCTOR PACKAGE | 2018-08-16 |
20180233441 | PoP Device | 2018-08-16 |
20180233442 | FABRICATION METHOD OF LAYER STRUCTURE FOR MOUNTING SEMICONDUCTOR DEVICE | 2018-08-16 |
20180233443 | SEMICONDUCTOR PACKAGES | 2018-08-16 |
20180233444 | LOW RESISTANCE SEED ENHANCEMENT SPACERS FOR VOIDLESS INTERCONNECT STRUCTURES | 2018-08-16 |
20180233445 | LOW RESISTANCE SEED ENHANCEMENT SPACERS FOR VOIDLESS INTERCONNECT STRUCTURES | 2018-08-16 |
20180233446 | INTEGRATING METAL-INSULATOR-METAL CAPACITORS WITH AIR GAP PROCESS FLOW | 2018-08-16 |
20180233447 | MICROELECTRONIC COMPONENTS WITH FEATURES WRAPPING AROUND PROTRUSIONS OF CONDUCTIVE VIAS PROTRUDING FROM THROUGH-HOLES PASSING THROUGH SUBSTRATES | 2018-08-16 |
20180233448 | Substrate-Less Stackable Package With Wire-Bond Interconnect | 2018-08-16 |
20180233449 | METHOD FOR FABRICATING CONTACT ELECTRICAL FUSE | 2018-08-16 |
20180233450 | Methods of Manufacturing Semiconductor Devices | 2018-08-16 |
20180233451 | PAD STRUCTURE AND METHOD FOR FABRICATING THE SAME | 2018-08-16 |
20180233452 | SEMICONDUCTOR PACKAGE ASSEMBLY | 2018-08-16 |
20180233453 | INPUT/OUTPUT PINS FOR CHIP-EMBEDDED SUBSTRATE | 2018-08-16 |
20180233454 | FAN-OUT SEMICONDUCTOR PACKAGE | 2018-08-16 |
20180233455 | SEMICONDUCTOR PROCESSING METHOD | 2018-08-16 |
20180233456 | METHOD FOR DETERMINING MISALIGNMENT BETWEEN A FIRST AND A SECOND ETCHING ZONES | 2018-08-16 |
20180233457 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME | 2018-08-16 |
20180233458 | INTEGRATED CIRCUIT PACKAGE | 2018-08-16 |
20180233459 | MODULE, MODULE MANUFACTURING METHOD, AND PACKAGE | 2018-08-16 |
20180233460 | DECOUPLING CAPACITOR | 2018-08-16 |
20180233461 | SEMICONDUCTOR DEVICE AND AUTHENTICATION SYSTEM | 2018-08-16 |
20180233462 | SEAL RING FOR WAFER LEVEL PACKAGE | 2018-08-16 |
20180233463 | GROUNDING TECHNIQUES FOR BACKSIDE-BIASED SEMICONDUCTOR DICE AND RELATED DEVICES, SYSTEMS AND METHODS | 2018-08-16 |
20180233464 | SEMICONDUCTOR MODULE | 2018-08-16 |
20180233465 | INTEGRATED CIRCUIT PACKAGE | 2018-08-16 |
20180233466 | SEMICONDUCTOR DEVICE WITH CONTACT PAD AND FABRICATION METHOD THEREFORE | 2018-08-16 |
20180233467 | Method for Building up a Fan-Out RDL Structure with Fine Pitch Line-Width and Line-Spacing | 2018-08-16 |
20180233468 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | 2018-08-16 |
20180233469 | DEVICE INCLUDING SEMICONDUCTOR CHIPS AND METHOD FOR PRODUCING SUCH DEVICE | 2018-08-16 |
20180233470 | HANDLING THIN WAFER DURING CHIP MANUFACTURE | 2018-08-16 |
20180233471 | Filter and Capacitor Using Redistribution Layer and Micro Bump Layer | 2018-08-16 |
20180233472 | MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE | 2018-08-16 |
20180233473 | PASTE THERMOSETTING RESIN COMPOSITION, SEMICONDUCTOR COMPONENT, SEMICONDUCTOR MOUNTED ARTICLE, METHOD FOR MANUFACTURING SEMICONDUCTOR COMPONENT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR MOUNTED ARTICLE | 2018-08-16 |
20180233474 | SEMICONDUCTOR PACKAGE WITH RIGID UNDER BUMP METALLURGY (UBM) STACK | 2018-08-16 |
20180233475 | SEMICONDUCTOR DEVICE | 2018-08-16 |
20180233476 | SEMICONDUCTOR PACKAGE | 2018-08-16 |
20180233477 | ELECTRONIC PACKAGING STRUCTURE | 2018-08-16 |
20180233478 | METHOD OF FABRICATING PACKAGING STRUCTURE | 2018-08-16 |
20180233479 | SEMICONDUCTOR APPARATUS AND METHOD FOR PREPARING THE SAME | 2018-08-16 |
20180233480 | SEMICONDUCTOR APPARATUS AND METHOD FOR PREPARING THE SAME | 2018-08-16 |
20180233481 | HIGH VOLTAGE DEVICE WITH MULTI-ELECTRODE CONTROL | 2018-08-16 |
20180233482 | GALLIUM LIQUID METAL EMBRITTLEMENT FOR DEVICE REWORK | 2018-08-16 |
20180233483 | GALLIUM LIQUID METAL EMBRITTLEMENT FOR DEVICE REWORK | 2018-08-16 |
20180233484 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | 2018-08-16 |
20180233485 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | 2018-08-16 |