33rd week of 2022 patent applcation highlights part 57 |
Patent application number | Title | Published |
20220262372 | Method for Controlling Electrical Appliance, and Non-Transitory Computer-Readable Storage Medium - A method for controlling an electrical appliance, and a non-transitory computer-readable storage medium. The control method comprises: receiving a voice control instruction (S | 2022-08-18 |
20220262373 | LAYERED CODING OF AUDIO WITH DISCRETE OBJECTS - A first layer of data having a first set of Ambisonic audio components can be decoded where the first set of Ambisonic audio components is generated based on ambience and one or more object-based audio signals. A second layer of data is decoded having at least one of the one or more object-based audio signals. One of the object-based audio signals is subtracted from the first set of Ambisonic audio components. The resulting Ambisonic audio components are rendered to generate a first set of audio channels. The one or more object-based audio signals are spatially rendered to generate a second set of audio channels. Other aspects are described and claimed. | 2022-08-18 |
20220262374 | SIGNAL PROCESSING DEVICE AND SIGNAL PROCESSING METHOD, AND PROGRAM - The present technology relates to a signal processing device, a signal processing method, and a program for enabling reproduction of high-quality sounds with a low process load. The signal processing device includes a demultiplexing section that extracts encoded audio signals and overamplitude flags, which have been generated for a plurality of respective panel loudspeakers and each indicate whether overamplitude will occur in the corresponding panel loudspeaker, by demultiplexing encoded data, a decoding section that decodes the encoded audio signals, and an adjustment section that adjusts audio signals to be supplied to the plurality of panel loudspeakers on the basis of the overamplitude flags and audio signals resulting from the decoding. The present technology is applicable to an encoding device and a decoding device. | 2022-08-18 |
20220262375 | DEEP LEARNING SEGMENTATION OF AUDIO USING MAGNITUDE SPECTROGRAM - A method, system, and computer readable medium for decomposing an audio signal into different isolated sources. The techniques and mechanisms convert an audio signal into K input spectrogram fragments. The fragments are sent into a deep neural network to isolate for different sources. The isolated fragments are then combined to form full isolated source audio signals. | 2022-08-18 |
20220262376 | SIGNAL PROCESSING DEVICE, METHOD, AND PROGRAM - The present technology relates to a signal processing device, a method, and a program that can obtain a signal with higher sound quality. | 2022-08-18 |
20220262377 | ELECTRONIC DEVICE AND CONTROL METHOD THEREOF - The disclosure relates to an electronic device and a control method thereof. The electronic device includes a memory, and a processor configured to: obtain first feature data for estimating a waveform by inputting acoustic data of a first quality to a first encoder model; and obtain waveform data of a second quality that is a higher quality than the first quality by inputting the first feature data to a decoder model to. | 2022-08-18 |
20220262378 | AUDIO SIGNAL ENCODING AND DECODING METHOD USING LEARNING MODEL, TRAINING METHOD OF LEARNING MODEL, AND ENCODER AND DECODER THAT PERFORM THE METHODS - An audio signal encoding and decoding method using a learning model, a training method of the learning model, and an encoder and decoder that perform the method, are disclosed. The audio signal decoding method may include extracting a first residual signal and a first linear prediction coefficient by decoding a bitstream received from an encoder, generating a first audio signal from the first residual signal using the first linear prediction coefficient, generating a second linear prediction coefficients and a second residual signal from the first audio signal, obtaining a third linear prediction coefficient by inputting the second linear prediction coefficient into a trained learning model, and generating a second audio signal from the second residual signal using the third linear prediction coefficient. | 2022-08-18 |
20220262379 | AUDIO DECODER, AUDIO ENCODER, METHOD FOR PROVIDING A DECODED AUDIO SIGNAL, METHOD FOR PROVIDING AN ENCODED AUDIO SIGNAL, AUDIO STREAM, AUDIO STREAM PROVIDER AND COMPUTER PROGRAM USING A STREAM IDENTIFIER - An audio decoder for providing a decoded audio signal representation on the basis of an encoded audio signal representation is configured to adjust decoding parameters in dependence on a configuration information, to decode one or more audio frames using a current configuration information, to compare a configuration information in a configuration structure associated with one or more frames to be decoded by the current configuration information, and to make a transition to perform decoding using the configuration information in the configuration structure associated with the one or more frames to be decoded as a new configuration information if the configuration information in the configuration structure associated with the one or more frames to be decoded, or a relevant portion thereof, is different from the current configuration information, and to consider a stream identifier information included in the configuration structure when comparing the configuration information. | 2022-08-18 |
20220262380 | RESAMPLING OUTPUT SIGNALS OF QMF BASED AUDIO CODEC - An apparatus for processing an audio signal includes a configurable first audio signal processor for processing the audio signal in accordance with different configuration settings to obtain a processed audio signal, wherein the apparatus is adapted so that different configuration settings result in different sampling rates of the processed audio signal. The apparatus furthermore includes n analysis filter bank having a first number of analysis filter bank channels, a synthesis filter bank having a second number of synthesis filter bank channels, a second audio processor being adapted to receive and process an audio signal having a predetermined sampling rate, and a controller for controlling the first number of analysis filter bank channels or the second number of synthesis filter bank channels in accordance with a configuration setting. | 2022-08-18 |
20220262381 | RESAMPLING OUTPUT SIGNALS OF QMF BASED AUDIO CODEC - An apparatus for processing an audio signal includes a configurable first audio signal processor for processing the audio signal in accordance with different configuration settings to obtain a processed audio signal, wherein the apparatus is adapted so that different configuration settings result in different sampling rates of the processed audio signal. The apparatus furthermore includes n analysis filter bank having a first number of analysis filter bank channels, a synthesis filter bank having a second number of synthesis filter bank channels, a second audio processor being adapted to receive and process an audio signal having a predetermined sampling rate, and a controller for controlling the first number of analysis filter bank channels or the second number of synthesis filter bank channels in accordance with a configuration setting. | 2022-08-18 |
20220262382 | RESAMPLING OUTPUT SIGNALS OF QMF BASED AUDIO CODEC - An apparatus for processing an audio signal includes a configurable first audio signal processor for processing the audio signal in accordance with different configuration settings to obtain a processed audio signal, wherein the apparatus is adapted so that different configuration settings result in different sampling rates of the processed audio signal. The apparatus furthermore includes n analysis filter bank having a first number of analysis filter bank channels, a synthesis filter bank having a second number of synthesis filter bank channels, a second audio processor being adapted to receive and process an audio signal having a predetermined sampling rate, and a controller for controlling the first number of analysis filter bank channels or the second number of synthesis filter bank channels in accordance with a configuration setting. | 2022-08-18 |
20220262383 | RESAMPLING OUTPUT SIGNALS OF QMF BASED AUDIO CODEC - An apparatus for processing an audio signal includes a configurable first audio signal processor for processing the audio signal in accordance with different configuration settings to obtain a processed audio signal, wherein the apparatus is adapted so that different configuration settings result in different sampling rates of the processed audio signal. The apparatus furthermore includes n analysis filter bank having a first number of analysis filter bank channels, a synthesis filter bank having a second number of synthesis filter bank channels, a second audio processor being adapted to receive and process an audio signal having a predetermined sampling rate, and a controller for controlling the first number of analysis filter bank channels or the second number of synthesis filter bank channels in accordance with a configuration setting. | 2022-08-18 |
20220262384 | PERSONAL AUDIO ASSISTANT DEVICE AND METHOD - A system includes a first microphone that captures audio, a communication module communicatively coupled to the first microphone, a logic circuit communicatively coupled to the first microphone and communication module, a speaker operatively coupled to the logic circuit, and an interaction element. The interaction element and logic circuit are configured to initiate control of audio content for output from the speaker in response to at least one voice command detected in captured audio. Other embodiments are disclosed. | 2022-08-18 |
20220262385 | VOICE CONTROL DEVICE AND VOICE CONTROL SYSTEM - The voice control device includes a sound source signal input unit, a frequency determination unit, a band controller, a sound image controller, and a voice output unit. The sound source signal input unit inputs a sound source signal of content from a sound source. The frequency determination unit determines a cutoff frequency. The band controller acquires a high frequency signal in a frequency band equal to or higher than the cutoff frequency and a low frequency signal in a frequency band equal to or lower than the cutoff frequency, from the sound source signal of the content. The sound image controller generates a plurality of sound image control signals for controlling sound images of the plurality of speakers, by controlling at least one of a phase and a sound pressure level of the high frequency signal. The voice output unit outputs the low frequency signal to a first speaker, and outputs the plurality of sound image control signals to a second speaker composed of a plurality of speakers. | 2022-08-18 |
20220262386 | SPEECH ENHANCEMENT METHOD AND APPARATUS, ELECTRONIC DEVICE, AND COMPUTER- READABLE STORAGE MEDIUM - Embodiments of this disclosure provide a speech enhancement method and apparatus, an electronic device, and a computer-readable storage medium. The method includes: obtaining a clean speech sample; decomposing the clean speech sample to obtain a first sparse matrix and m base matrices, values in the first sparse matrix being all positive numbers, and m being a positive integer greater than 1; obtaining, according to the first sparse matrix and a weight matrix of a target neural network, state vectors of neurons in a visible layer of the target neural network; and updating the weight matrix according to the state vectors of the neurons in the visible layer and the clean speech sample, to obtain a deep dictionary used for speech enhancement. | 2022-08-18 |
20220262387 | AUDIO DE-ESSER INDEPENDENT OF ABSOLUTE SIGNAL LEVEL - Methods, systems, and computer program products of automatic de-essing are disclosed. An automatic de-esser can be used without manually setting parameters and can perform reliable sibilance detection and reduction regardless of absolute signal level, singer gender and other extraneous factors. An audio processing device divides input audio signals into buffers each containing a number of samples, the buffers overlapping one another. The audio processing device transforms each buffer from the time domain into the frequency domain and implements de-essing as a multi-band compressor that only acts on a designated sibilance band. The audio processing device determines an amount of attenuation in the sibilance band based on comparison of energy level in sibilance band of a buffer to broadband energy level in a previous buffer. The amount of attenuation is also determined based on a zero-crossing rate, as well as a slope and onset of a compression curve. | 2022-08-18 |
20220262388 | METHOD AND APPARATUS FOR POST-PROCESSING AUDIO SIGNAL, STORAGE MEDIUM, AND ELECTRONIC DEVICE - This application discloses a method and an apparatus for processing an audio signal. The method includes obtaining a first speech signal acquired by a first device; performing frame blocking on the first speech signal, to obtain multiple speech signal frames; converting the multiple speech signal frames into multiple first frequency domain signal frames; performing aliasing processing on a first sub-frequency domain signal frame among the multiple first frequency domain signal frames with a frequency lower than or equal to a target frequency threshold, and retaining a second sub-frequency domain signal frame among the multiple first frequency domain signal frames with a frequency higher than the target frequency threshold, to obtain multiple second frequency domain signal frames, the target frequency threshold being related to a sampling frequency of a second device; and performing frame fusion on the multiple second frequency domain signal frames, to obtain a second speech signal. | 2022-08-18 |
20220262389 | METHOD AND APPARATUS FOR IMPROVING SPEECH INTELLIGIBILITY IN A ROOM - A method for improving speech intelligibility in a room includes detecting an active speaker, or speech, identifying the active speaker, and influencing at least one apparatus for producing sound for the room in such a way that the level of sound emitted into the room by this apparatus is reduced at frequencies or in frequency ranges that tally with or are adjacent to the frequencies, or frequency ranges, of the speaker that are relevant to speech intelligibility, and/or influencing at least one apparatus for producing sound for the room in such a way that the level of sound transmitted into the room is reduced by at least one apparatus for reducing sound by destructive interference at the frequencies or in the frequency ranges that are relevant to the speech intelligibility of the speaker or at frequencies or in frequency ranges that are adjacent to the frequencies or frequency ranges. | 2022-08-18 |
20220262390 | NETWORK OPERATION BASED ON DOMAIN SPECIFIC LANGUAGE - A network validation system is described which may perform operations such as generating, analyzing, verifying, correcting, recommending, and deploying language, symbols, etc., such as domain specific language, configured to allow users to express their intent on the configuration and operation of a network, such as a cloud-based network. The network validation system may provide domain specific language that includes rules, statements, symbols, data, etc., configured to convey the intent of users on the configuration and operation of networks for purposes such as configuring and/or validating communication paths, testing or setting associated network object configurations, and may be employed to report violations in such configurations relative to user intent of the one or more users. The network validation system may also be employed to monitor such domain specific language and generate telemetry signaling, for example, that a rule has or has not been violated, actions a user may take, etc. | 2022-08-18 |
20220262391 | ELECTRONIC DEVICE AND METHOD FOR SPEECH RECOGNITION PROCESSING OF ELECTRONIC DEVICE - An electronic device and method are disclosed. The device includes a memory and speech recognition circuitry and/or a processor, which implements the method, including: receiving a first utterance, and processing the first utterance to initiate a session and generate a first response result, after the session related to the first utterance is terminated, receiving a second utterance, processing the second utterance to generate a second response result, based on the second response result, determining whether to execute follow-up utterance processing on the second utterance as if the session were active, based on determining to execute the follow-up utterance processing, reprocessing the second utterance based at least in part on the first response result related to the first utterance to generate a third response result, and outputting the third response result. | 2022-08-18 |
20220262392 | INFORMATION PROCESSING DEVICE - An information processing device includes an acquisition unit that acquires a sound signal and a control unit that segments the sound signal into a plurality of sections, calculates a variation value as a variation amount per section time in regard to each of the plurality of sections based on the sound signal, identifies sections where the variation value is less than or equal to a predetermined threshold value among the plurality of sections, calculates power of the sound signal in each of the identified sections based on the sound signal, determines a maximum value among values of the power of the sound signal in each of the identified sections, sets a value based on the maximum value as a detection threshold value, and detects sections where the power of the sound signal with elapse of time is higher than or equal to the detection threshold value as detection target sections. | 2022-08-18 |
20220262393 | SUSPENSION ASSEMBLY AND DISK DEVICE - According to one embodiment, a suspension assembly includes a support plate, a wiring member disposed on the support plate, and a head supported on the support plate through the wiring member. The wiring member includes a distal end portion electrically connected to the head, a connection end portion extending outside the support plate, and a plurality of wirings extending between the distal end portion and the connection end portion. The connection end portion includes an opening with predetermined length and width and thirteen or more connection terminals disposed in the opening and arranged at intervals in a direction of the length. A percentage of an area of the opening occupied by areas of the thirteen or more connection terminals is 40% to 65% inclusive. | 2022-08-18 |
20220262394 | DISK DEVICE - A disk device includes a plurality of magnetic disks, a plurality of magnetic heads, a first actuator assembly having a plurality of arms and a plurality of suspension assemblies for the magnetic heads and supported to be rotatable about a support shaft, a second actuator assembly having a plurality of arms and a plurality of suspension assemblies for the magnetic heads and supported to be rotatable about the support shaft, and a protective member formed from a material different from a material for the arms. The protective member is provided on a tip end portion of at least one of a first arm closest to the second actuator assembly among the of arms in the first actuator assembly and a second arm closest to the first actuator assembly among the arms in the second actuator assembly. | 2022-08-18 |
20220262395 | Hard Disk Drive Gimbal Design with High Yaw Mode - A trace gimbal is described herein. In some embodiments, the trace gimbal includes outer struts including a front outrigger at a distal end of the trace gimbal and a rear outrigger at a proximal end of the trace gimbal. The front outrigger includes a distal front outrigger and a proximal front outrigger, and the rear outrigger includes a distal rear outrigger and a proximal rear outrigger. The trace gimbal further includes a middle strut extending in a width direction of the trace gimbal and adjoining the proximal front outrigger to the rear outrigger, and an inner strut connecting the middle strut to a slider tongue. The inner strut includes a slot, and the inner strut and the middle strut adjoin the outer gimbal struts to the slider tongue. | 2022-08-18 |
20220262396 | DATA STORAGE DEVICE INDEPENDENTLY DRIVING OUTER AND INNER FINE ACTUATORS - A data storage device is disclosed comprising a plurality of disks each comprising a top disk surface and a bottom disk surface. A plurality of inner actuator arms each comprise a first inner fine actuator configured to actuate a top head over one of the top disk surfaces and a second inner fine actuator configured to actuate a bottom head over one of the bottom disk surfaces. A first outer actuator arm comprises a first outer fine actuator configure to actuate a top head over a top disk surface of a top disk, and a second outer actuator arm comprises a second outer fine actuator configured to actuate a bottom head over a bottom disk surface of a bottom disk, wherein the inner fine actuators are controlled independent from the outer fine actuators. | 2022-08-18 |
20220262397 | DISK DEVICE - According to one embodiment, a disk device includes a base, a drive motor, disk-shaped magnetic recording media, a carriage supporting a magnetic head to be movable with respect to the magnetic recording medium, and a plurality of fixing members. The base includes a bottom wall and a side wall having a first corner and a second corner. The fixing member includes a support post erected on the bottom wall, and extending parts each extending from the support post between the magnetic recording media. The fixing members include a first fixing member provided between the magnetic recording medium and the first corner, a second fixing member provided between the magnetic recording medium and the second corner, and a third fixing member provided on a side facing the first fixing member. | 2022-08-18 |
20220262398 | Detection Apparatus, Optical Drive, and Detection Method - A detection apparatus determines whether a recording layer of an optical disc is at a focal point of an objective lens. The detection apparatus includes an objective lens, a beam splitter, a reflector, a detector, and a servo controller. The reflector and the detector are disposed opposite to each other on two sides of an optical axis of the objective lens, and a normal line of the reflector is perpendicular to the optical axis. The beam splitter is disposed between the reflector and the detector and is located on the optical axis. The servo controller is connected to the detector. | 2022-08-18 |
20220262399 | BASE PLATE, SPINDLE MOTOR AND DISK DRIVE - A base plate includes a base body including a bottom plate and a pivot post, and an electrodeposition coating film. The bottom plate extends perpendicular to a first axis, a rotation axis of the disk, and a second axis, a swing axis of a head; and, when viewed from an axial direction, has a rectangular shape with a first direction as a short side direction and a second direction as a long side direction. The pivot post protrudes upward from an upper surface of the bottom plate at a position overlapping the second axis. The bottom plate has a thin bottom arranged in a radially outward direction orthogonal to the second axis of the pivot post and including at least one of a lower recess recessed upward from a lower surface of the bottom plate and an upper recess recessed downward from the upper surface of the bottom plate. | 2022-08-18 |
20220262400 | MAGNETIC DISK DEVICE AND WRITE PROCESSING METHOD - According to one embodiment, a magnetic disk device includes a disk including a normal recording region written in a normal recording and a shingled recording region written in a shingled recording, a head including a write head and a plurality of read heads, the head moving on the disk by rotation about, a rotation axis, and a controller which selects and executes the normal recording and the shingled recording, wherein a first minimum value of a cross track interval in the radial direction of the disk between two read heads in the plurality of read heads in the normal recording region is smaller than a first maximum value of the cross track interval in the shingled recording region. | 2022-08-18 |
20220262401 | DATA STORAGE DEVICE DETECTING WRITE POLE DEGRADATION FOR MAGNETIC WRITE HEAD - A data storage device is disclosed comprising a head actuated over a magnetic media, wherein the head comprises a write coil and a write pole. A test pattern is written to the magnetic media by applying a first current to the write coil. A second current is applied to the write coil while the head passes over the test pattern, wherein the second current has a polarity opposite the first current. After applying the second current to the write coil while the head passes over the test pattern, the test pattern is read from the magnetic media using the head to generate a first read signal, and a first noise power of the first read signal is measured. A degradation of the write pole is detected based on the first noise power measurement. | 2022-08-18 |
20220262402 | DATA STORAGE DEVICE INDEPENDENTLY DRIVING OUTER AND INNER FINE ACTUATORS - Control circuitry is disclosed configured to control inner fine actuators of a first plurality of inner actuator arms and independently control a first outer fine actuator of a first outer actuator arm. Inner fine actuators of a second plurality of inner actuator arms are controlled while independently controlling a second outer fine actuator of a second outer actuator arm. Each actuator arm comprises at least one head configured to access a disk surface of a disk. | 2022-08-18 |
20220262403 | BASE PLATE, SPINDLE MOTOR, DISK DRIVE APPARATUS AND MANUFACTURING METHOD OF BASE PLATE - A base plate is a portion of a housing of a disk drive apparatus, including a base body being a casting product, and an electrodeposition coating film covering at least a portion of a surface of the base body. The base body includes a bottom plate rectangular as viewed from an axial direction, a pivot post, and a protrusion. The bottom plate extends perpendicular to a rotation axis of a disk that extends vertically and a swing axis of a head that is disposed in a different position from the rotation axis and that extends vertically. The head reads or writes information from or to the disk. The pivot post protrudes upward from an upper surface of the bottom plate along the swing axis. The protrusion is provided protruding radially outward from a peripheral surface of the pivot post and protruding to the upper surface of the bottom plate. | 2022-08-18 |
20220262404 | AUDIOVISUAL CAPTURE AND SHARING FRAMEWORK WITH COORDINATED, USER-SELECTABLE AUDIO AND VIDEO EFFECTS FILTERS - Coordinated audio and video filter pairs are applied to enhance artistic and emotional content of audiovisual performances. Such filter pairs, when applied in audio and video processing pipelines of an audiovisual application hosted on a portable computing device (such as a mobile phone or media player, a computing pad or tablet, a game controller or a personal digital assistant or book reader) can allow user selection of effects that enhance both audio and video coordinated therewith. Coordinated audio and video are captured, filtered and rendered at the portable computing device using camera and microphone interfaces, using digital signal processing software executable on a processor and using storage, speaker and display devices of, or interoperable with, the device. By providing audiovisual capture and personalization on an intimate handheld device, social interactions and postings of a type made popular by modern social networking platforms can now be extended to audiovisual content. | 2022-08-18 |
20220262405 | COLLABORATIVE MEDIA OBJECT GENERATION AND PRESENTATION IN IMPROVED COLLABORATIVE WORKSPACE - In the present disclosure, a collaborative workspace fosters content creation between users in a synchronous and/or asynchronous manner by enabling automatic generation and management of collaborative media objects that automatically combine content from a plurality of users into a single media object. This is extremely beneficial in technical scenarios where users are creating projects, assignments, presentations, etc., by removing the need for users to manually stitch together and combine content to create a final product. For example, the collaborative workspace is adapted for a video discussion application/service, where users create one or more video clips (e.g., video feeds, live video feeds) in response to a posted topic. In at least one instance, a collaborative workspace for a video discussion application/service may be integrated to display within another type of application/service. However, the present disclosure is extensible to work with any type of application/service and any content type. | 2022-08-18 |
20220262406 | SYSTEM AND METHODS FOR AUTONOMOUS SYNCHRONOUS RENDERING OF MEDIA OBJECTS OBTAINED FROM A PLURALITY OF MEDIA SOURCES - Systems and methods for autonomous rendering of synchronous media objects are disclosed. The system may obtain unsynchronized media objects from user devices and initialize a media object analysis procedure for each media object by collecting metadata associated with each media object and determine a plurality of labels for each media object based on the collected metadata. Further, the system may execute audio analysis for at least one audio track associated with each media object to determine an audio score. The system may then select a best audio track corresponding to each media object based on the audio scores and create a narrative sequence comprising of media object slots filled with media objects and corresponding best audio tracks for each media object. Furthermore, based on approval of the narrative sequence by a user device, the system may generate a synchronized media object preview for display on the user device. | 2022-08-18 |
20220262407 | Audio/video outroduction by reusing content from introduction and other parts - A multimedia production method includes: reusing the content in the introduction before the main content or other part in the multimedia file for an outroduction after the main content and playing the audio and/or video content in the reverse direction. A producer can make the multimedia file by attaching such an outtrocution. A multimedia editing program can provide a user interface with menu options for such a production technique. The media production program could be associated with the multimedia sharing and distributing network. Such a production method could be applied to multiple multimedia files in the same media sharing and distributing network by the same producer. The same content can be reused in a cluster of media files. | 2022-08-18 |
20220262408 | BASE PLATE, SPINDLE MOTOR, DISK DRIVE APPARATUS AND MANUFACTURING METHOD OF BASE PLATE - A base plate is a portion of a housing of a disk drive apparatus, including a base body defined by a metal die cast member, and an electrodeposition coating film covering at least a portion of a surface of the base body. The base body includes a bottom plate rectangular as viewed from an axial direction, and a pivot post. The bottom plate extends perpendicular to a rotation axis of a disk and a swing axis of a head. The rotation axis extends vertically. The swing axis is disposed in a different position from the rotation axis and extends vertically. The head reads or writes information from or to the disk. The pivot post protrudes upward from an upper surface of the bottom plate along the swing axis, and a portion of the die cast member is segregated. | 2022-08-18 |
20220262409 | CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER - Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel. | 2022-08-18 |
20220262410 | AREA-EFFICIENT, WIDTH-ADJUSTABLE SIGNALING INTERFACE - A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure. | 2022-08-18 |
20220262411 | MEMORY DEVICE - The present technology includes a memory device. The memory device includes memory cells, page buffers configured to store sensed data obtained from the memory cells, a current sensing circuit configured to compare a sensed voltage generated according to the sensed data and a reference voltage generated according to an allowable fail bit code, and output a pass signal or a fail signal according to a comparison result, and a fail bit manager configured to increase an allowable number of fail bits included in the allowable fail bit code until the pass signal is output from the current sensing circuit, change the allowable fail bit code according to the allowable number of fail bits, and provide the allowable fail bit code to the current sensing circuit. | 2022-08-18 |
20220262412 | MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION - Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated. | 2022-08-18 |
20220262413 | RESET SPEED MODULATION CIRCUITRY FOR A DECISION FEEDBACK EQUALIZER OF A MEMORY DEVICE - Systems and methods described herein provide decision feedback equalizer (DFE) circuitry that includes one or more phases. The one or more phases receive bit feedback at respective inputs of the phases. The DFE circuitry also may include variable reset circuitry. The variable reset circuitry may reset voltages of the bit feedback at inputs of each of the phases. The variable reset circuitry is configured to change its reset frequency between resets. | 2022-08-18 |
20220262414 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - A data storage device includes a nonvolatile memory device and a controller including a command parser configured to match a clock corresponding to each of a plurality of memory access types to generate a clock index matched with each of the memory access types and configured to determine, when a command is received, a memory access type of the command and the clock index matched with the determined memory access type by analyzing the command, and a memory interface configured to determine a locking value and the clock index corresponding to each of a plurality of clocks having different frequencies and change the locking value for processing of a command according to the clock index determined by the command parser. | 2022-08-18 |
20220262415 | MEMORY INTERFACE MAPPING - System connections map interface connections between the memory device and the memory controller. The memory controller is configured with information about these ‘mapped’ connections. The memory controller uses the mapping information to: correctly present commands and addresses to the memory device, perform CA training on mapped connections, generate read training data that accounts for mapped connections, correctly address mapped memory device pins for write training per pin adjustments, correctly calculate error detection coding, and correctly read vendor identification information. | 2022-08-18 |
20220262416 | ENABLE SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates an operation code and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on the operation code and the strobe pulse and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys based on a plurality of operation codes and the strobe pulse and prevents the generation of the enable signal for a predetermined time when the plurality of guard keys are not sequentially enabled. | 2022-08-18 |
20220262417 | CRYOGENIC MAGNETIC DEVICE MORE PARTICULARLY FOR LOGIC COMPONENT OR MEMORY - A cryogenic magnetic device includes a free layer having a free magnetisation and a magnetic anisotropy favouring the orientation of the free magnetisation according to a first orientation or a second orientation, the magnetic anisotropy being defined by an energy barrier separating the first orientation and the second orientation, the amplitude of the energy barrier being less than 6300 k | 2022-08-18 |
20220262418 | MEMORY DEVICE HAVING BITLINE SEGMENTED INTO BITLINE SEGMENTS AND RELATED METHOD FOR OPERATING MEMORY DEVICE - A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed. | 2022-08-18 |
20220262419 | MAGNETIC MEMORY DEVICES HAVING MULTIPLE MAGNETIC LAYERS THEREIN - A magnetic memory device includes a first magnetic layer extending in a first direction, a second magnetic layer that extends on and parallel to the first magnetic layer, and a conductive layer extending between the first magnetic layer and the second magnetic layer. The first magnetic layer includes a first region having magnetic moments oriented in a first rotational direction along the first direction. The second magnetic layer includes a second region having magnetic moments oriented in a second rotational direction along the first direction. The second rotational direction is different from the first rotational direction. | 2022-08-18 |
20220262420 | NONVOLATILE MEMORY CELL, NONVOLATILE MEMORY CELL ARRAY, AND INFORMATION WRITING METHOD OF NONVOLATILE MEMORY CELL ARRAY - A nonvolatile memory cell includes a resistance-change nonvolatile memory element | 2022-08-18 |
20220262421 | POWER SUPPLY GENERATOR ASSIST - The disclosed system and method reduce on-chip power IR drop caused by large write current, to increase the write IO number or improve write throughput and to suppress write voltage ripple at the start and end of a write operation. The disclosed systems and methods are described in relation to stabilizing the bit line voltage for MRAMs, however, the disclosed systems and methods can be used to stabilize the bit line voltage of any memory configuration that draws large currents during short write pulses or, more generally, to selectively assist a power supply generator in supplying adequate power to a load at times of large power consumption. | 2022-08-18 |
20220262422 | MEMORY DEVICE AND MEMORY METHOD - A memory device according to an embodiment includes first and second interconnects, memory cells, and a control circuit. In a first process, the control circuit applies a write voltage of a first direction to a memory cell coupled to selected first and second interconnects, and applies a write voltage of a second direction to a memory cell coupled to the selected first interconnect and a non-selected second interconnect. In second processes of first to m-th trial processes, the control circuit applies the write voltage of the second direction to the memory cell coupled to the selected first and second interconnects, and omits a write operation in which the memory cell coupled to the selected first interconnect and the non-selected second interconnect is targeted. | 2022-08-18 |
20220262423 | Write Driver Boost Circuit for Memory Cells - Circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. In one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. The boost circuit also includes a transistor and a capacitor. The transistor is coupled to an output of the first inverter. The transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. The capacitor is coupled to an output of the second inverter. The capacitor is configured to generate and provide a delta voltage to the write driver. | 2022-08-18 |
20220262424 | COMPUTE IN MEMORY SYSTEM - A computing device in some examples includes an array of memory cells, such as 8-transisor SRAM cells, in which the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, in which the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. The computing device can be used to compute, for example, sum of input weighted by multi-bit weights. | 2022-08-18 |
20220262425 | VERTICAL MEMORY DEVICE - A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines. | 2022-08-18 |
20220262426 | Memory System Capable of Performing a Bit Partitioning Process and an Internal Computation Process - A memory system includes a plurality of first memory units, a plurality of read word lines, and a plurality of read bit lines. Each first memory unit of the plurality of first memory units includes a second memory unit, a first transistor coupled to the second memory unit, and a second transistor coupled to the second memory unit and the first transistor. Each read word line of the plurality of read word lines is coupled to a plurality of first transistors disposed along a corresponding row. Each read bit line of the plurality of read bit lines is coupled to a plurality of second transistors disposed along a corresponding column. | 2022-08-18 |
20220262427 | MEMORY POWER MANAGEMENT METHOD AND APPARATUS - A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS. | 2022-08-18 |
20220262428 | METHOD OF POLLING ROW HAMMER (RH) INDICATOR INSIDE MEMORY - Methods and apparatus for row hammer (RH) mitigation and recovery. A host comprising a memory controller is configured to interface with one or more DRAM devices, such as DRAM DIMMs. The memory controller includes host-side RH mitigation logic and the DRAM devices include DRAM-side RH mitigation logic that cooperates with the host-side RH mitigation logic to perform RH mitigation and/or recovery operations in response to detection of RH attacks. The memory controller and DRAM device are configured to support an RH polling mode under which the memory controller periodically polls for RH attack detection indicia on the DRAM device that is toggled when the DRAM device detects an RH attack. The memory controller and DRAM device may also be configured to support an RH ALERT_n mode under which the use of an ALERT_n signal and pin is used to provide an alert to the memory controller to initiate RH mitigation and/or recovery. | 2022-08-18 |
20220262429 | MEMORY AND OPERATION METHOD OF THE MEMORY - A memory core including a memory core including memory cells that are arranged in a plurality of rows and a plurality of columns; and a refresh target selection circuit suitable for storing an address and a risk score of each of activated rows among the rows, wherein the refresh target selection circuit is further suitable for increasing the risk score of a corresponding row whenever the corresponding row is activated, whenever a row at a ‘+2’ position of the corresponding row is activated, and whenever a row at a ‘−2’ position of the corresponding row is activated. | 2022-08-18 |
20220262430 | Systems and Methods for Reducing Standby Power in Floating Body Memory Devices - Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set. | 2022-08-18 |
20220262431 | DETECTED THRESHOLD VOLTAGE STATE DISTRIBUTION OF FIRST AND SECOND PASS PROGRAMED MEMORY PAGES - Systems, apparatuses, and methods provide for technology for distinguishing an erased state, a first pass programmed state, and a second pass programmed state of a memory page. A threshold voltage state verify sense is performed. A memory page status is determined based on the threshold voltage state verify sense. The memory page status is one of erased, programmed with first pass data, and programmed with second pass data based on the threshold voltage state verify sense. A program continuation is performed after a program interruption based on the memory page status. | 2022-08-18 |
20220262432 | SYSTEM AND METHOD APPLIED WITH COMPUTING-IN-MEMORY - A system includes a global generator and local generators. The global generator is coupled to a memory array, and is configured to generate global signals, according to a number of a computational output of the memory array. The local generators are coupled to the global generator and the memory array, and are configured to generate local signals, according to the global signals. Each one of the local generators includes a first reference circuit and a local current mirror. The first reference circuit is coupled to the global generator, and is configured to generate a first reference signal at a node, in response to a first global signal of the global signals. The local current mirror is coupled to the first reference circuit at the node, and is configured to generate the local signals, by mirroring a summation of at least one signal at the node. | 2022-08-18 |
20220262433 | PROGRAMMABLE INTERPOSERS FOR ELECTRICALLY CONNECTING INTEGRATED CIRCUITS - Programmable interposers for connecting integrated circuits, methods for programming programmable interposers, and integrated circuit packaging are provided. The programmable interposers are electrically reconfigurable to allow custom system-in-package (SiP) operation and configuration, field configurability, and functional obfuscation for secure integrated circuits fabricated in non-trusted environments. The programmable interposer includes, in one implementation, an interposer substrate and a programmable metallization cell (PMC) switch. The PMC switch is formed on the interposer substrate and is coupled between a signal input and a signal output. The PMC switch is electrically configurable between a high resistance state and a low resistance state. | 2022-08-18 |
20220262434 | ReRAM Memory Array - A ReRAM memory array includes ReRAM memory cells and a select circuit having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on. | 2022-08-18 |
20220262435 | Storage and Computing Unit and Chip - This application provides a unit, including a first transistor, a memristor, and a resistance modulation unit, where a first port of the resistance modulation unit and a first port of the memristor are connected to a first electrode of the first transistor, and the first electrode of the first transistor is configured to control the first transistor to be connected and disconnected; the resistance modulation unit is configured to adjust, based on a resistance of the memristor, a voltage applied to the first electrode of the first transistor; where the resistance of the memristor is used to indicate the first data stored by the memristor; and when a voltage used to indicate second data is input to a second electrode of the first transistor which is configured to output a computation result of the first data and the second data from a third electrode of the first transistor. | 2022-08-18 |
20220262436 | VARIABLE RESISTANCE MEMORY DEVICE - A variable resistance memory device includes: a memory cell including a first and second sub memory cell; and a first, second and third conductor. The first sub memory cell is above the first conductor, and includes a first variable resistance element and a first bidirectional switching element. The second sub memory cell is above the second conductor, and includes a second variable resistance element and a second bidirectional switching element. The second conductor is above the first sub memory cell. The third conductor is above the second sub memory cell. The variable resistance memory device is configured to receive first data and to write the first data to the memory cell when the first data does not match second data read from the memory cell. | 2022-08-18 |
20220262437 | TECHNIQUES FOR PROGRAMMING MULTI-LEVEL SELF-SELECTING MEMORY CELL - Techniques are provided for programming a multi-level self-selecting memory cell that includes a chalcogenide material. To program one or more intermediate memory states to the self-selecting memory cell, a programming pulse sequence that includes two pulses may be used. A first pulse of the programming pulse sequence may have a first polarity and a first magnitude and the second pulse of the programming pulse sequence may have a second polarity different than the first polarity and a second magnitude different than the first magnitude. After applying both pulses in the programming pulse sequence, the self-selecting memory cell may store an intermediate state that represents two bits of data (e.g., a logic ‘01’ or a logic ‘10’). | 2022-08-18 |
20220262438 | MEMORY DEVICE - A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. The first conductor is provided with a first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor. | 2022-08-18 |
20220262439 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line. | 2022-08-18 |
20220262440 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - According to a certain embodiment, the nonvolatile semiconductor memory device includes: a memory cell array including a plurality of selected blocks and a plurality of non-selected blocks; and a row decoder including a block decoder configured to switch between the selected block and the non-selected block. The row decoder switches a block determined to be a defective block to a non-selected block and switches a block determined not to be a defective block to a selected block, on the basis of the multi-level data. The block decoder includes a defective block flag circuit including a plurality of latch circuits configured to store multi-level data. | 2022-08-18 |
20220262441 | MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY - According to one embodiment, a controller permits a host to write data to a host memory. The controller acquires from the host memory first write data having a first size, and instructs the nonvolatile memory to perform a first-step write operation for writing the first write data to a plurality of memory cells connected to a first word line. The first write data is written to the host memory by the host after the host is permitted to write data to the host memory. When the second-step write operation for the first word line becomes executable, the controller acquires the first write data again from the host memory and instructs the nonvolatile memory to perform a second-step write operation. | 2022-08-18 |
20220262442 | SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, AND OPERATING METHOD THEREOF - Disclosed is an operating method of a controller for controlling an operation of a semiconductor memory device including a plurality of memory cells. In the operating method of the controller, program data to be stored in a selected page of the semiconductor memory device is generated, and the semiconductor memory device is controlled to program the program data in the selected page. Bit data at a predetermined position in the program data is data for allowing a threshold voltage of a corresponding memory cell to maintain an erase state. | 2022-08-18 |
20220262443 | SEMICONDUCTOR MEMORY WITH DIFFERENT THRESHOLD VOLTAGES OF MEMORY CELLS - According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell. | 2022-08-18 |
20220262444 | SEMICONDUCTOR STORAGE DEVICE - A non-volatile memory of an embodiment includes: a memory cell array including a plurality of memory cell transistors; a plurality of word lines connected to a plurality of gates of the plurality of respective memory cell transistors; a VPGM monitor connected to at least one of the plurality of word lines; and a sequencer. When writing voltage is applied to a selected word line selected from among the plurality of word lines at data writing to the memory cell array, the sequencer detects voltage of the selected word line through the VPGM monitor and determines whether detected voltage obtained through the detection has reached a predetermined value. | 2022-08-18 |
20220262445 | NON-VOLATILE MEMORY CIRCUIT AND METHOD - A memory circuit includes a first bank of non-volatile memory (NVM) devices, a first plurality of decoders, a first plurality of high-voltage (HV) drivers corresponding to the first plurality of decoders, and a first plurality of HV power switches. A first HV power switch is coupled to each HV driver of the first plurality of HV drivers, and each decoder is configured to generate an enable signal corresponding to a column of the first bank of NVM devices. Each HV driver is configured to output a HV activation signal to the corresponding column of the first bank of NVM devices responsive to a power signal of the first HV power switch and to the enable signal of the corresponding decoder. | 2022-08-18 |
20220262446 | MEMORY CIRCUIT AND METHOD OF OPERATING SAME - A memory circuit includes a non-volatile memory cell, a sense amplifier coupled to the non-volatile memory cell, and configured to generate a first output signal, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier. | 2022-08-18 |
20220262447 | ERROR DETECTION PIN ENCODING SCHEME TO AVOID MAXIMUM TRANSITIONS AND FURTHER IMPROVE SIGNAL INTEGRITY ON HIGH SPEED GRAPHIC MEMORY INTERFACES - First symbols are generated on a plurality of data channels by applying PAM-N encoding on a first subset of bits of a data burst, the first symbols generated without maximum transitions; second symbols are generated on at least one optionally-activated additional data channel, the second symbols generated by applying the PAM-N encoding on a second subset of bits of the data burst, the second symbols generated without maximum transitions; and third symbols are generated on a channel for communicating error correction bits for the first bits and second bits, the third symbols generated by applying hybrid PAM-N encoding on the error correction bits and a third subset of bits of the data burst, the hybrid PAM-N encoding comprising an interleaving of symbols with N voltage levels and symbols with less than N voltage levels. | 2022-08-18 |
20220262448 | MEMORY DEVICE AND MEMORY SYSTEM FOR EXECUTING A TEST - A memory device includes a data storage circuit configured to store, when a write operation is performed, a first internal write data and a second internal write data in a memory cell array which is accessed by an internal address, and output, when a read operation is performed, data stored in a memory cell array which is accessed by the internal address, as internal read data; and a flag generation circuit configured to generate a flag for controlling generation of a data strobe signal, based on the internal read data. | 2022-08-18 |
20220262449 | ELECTRONIC DEVICE FOR PERFORMING DATA MASKING OPERATION - An electronic device includes a core circuit configured to store write data and a write parity after outputting read data and a read parity in a data masking operation. The electronic device also includes an error correction circuit configured to correct an error included in the read data, based on the read parity; generate the write parity from the error-corrected read data, input data, and masking data; and generate the write data from the error-uncorrected read data, the input data, and the masking data. | 2022-08-18 |
20220262450 | SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - The present technology includes a method of operating a controller that controls a semiconductor memory device including a plurality of memory blocks. The method includes receiving a read request for data included in any one memory block among the plurality of memory blocks from a host, and controlling the semiconductor memory device to read data corresponding to the read request using a read-history table. The read-history table includes read voltages used for a plurality of read pass operations for the any one memory block, respectively. | 2022-08-18 |
20220262451 | SEMICONDUCTOR DEVICE PERFORMING LOOP-BACK TEST OPERATION - Disclosed herein is an apparatus that includes a memory cell array; a data input/output terminal; a read data path and a write data path coupled in parallel between the memory cell array and the data input/output terminal, wherein the read data path includes a pre-driver and an output driver coupled in series, and wherein the write data path includes an input receiver and a latch circuit coupled in series; and a test path configured to provide a shortcut between the pre-driver in the read data path and the latch circuit in the write data path. | 2022-08-18 |
20220262452 | MEMORY DEVICE AND MEMORY SYSTEM - A memory system includes a memory device and a memory controller. The memory device includes a memory cell array including normal memory cells and redundancy memory cells suitable for replacing failed memory cell among the normal memory cells, and a device controller for activating reserved memory cells which are included in the redundancy memory cells and not used to replace the failed memory cell. The memory controller controls the memory device, when a first memory cells are accessed more than a threshold access number, to move data stored in the first memory cells to the reserved memory cells and replace the first memory cells with the reserved memory cells. | 2022-08-18 |
20220262453 | MEMORY DEVICE AND MEMORY SYSTEM - A memory device includes: a memory cell array; a sense amplifier for amplifying data stored in the memory cell array; a first memory cell sub-array included in the memory cell array directly coupled to the sense amplifier; a switch coupled to the first memory cell sub-array; and a second memory cell array included in the memory cell array coupled to the sense amplifier through the first memory cell sub-array and the switch. When the switch is enabled, the first memory cell sub-array has a first operation speed, and the second memory cell sub-array has a second operation speed slower than the first operation speed. When the switch is disabled, a bit line loading associated with the second memory cell sub-array is decreased, and the first memory cell sub-array has a third operation speed faster than the first operation speed. | 2022-08-18 |
20220262454 | MEMORY DEVICE AND MEMORY SYSTEM - A memory system includes a plurality of memory devices and a controller. Each of the memory devices includes a memory cell array, a sense amplifier for amplifying data stored in the memory cell array, a first memory cell sub-array included in the memory cell array directly coupled to the sense amplifier, a switch coupled to the first memory cell sub-array, and a second memory cell array included in the memory cell array coupled to the sense amplifier through the first memory cell sub-array and the switch. When the switch is enabled, the memory device operates as a normal mode, and when the switch is disabled, the memory device operates as a fast mode faster than the normal mode. The controller dynamically sets a mode of each of the memory devices based on requests externally provided, by controlling the switch of each of the memory devices. | 2022-08-18 |
20220262455 | DETERMINING THE GOODNESS OF A BIOLOGICAL VECTOR SPACE - A system for determining a goodness of a deep learning model comprises a memory coupled with a processor. The processor accesses a first set of vectors representative of images of a biological assay. The vectors of the first set of vectors are outputs of a first deep learning model. The processor creates a first distribution of a first plurality of pairwise comparisons of vectors, of the first set of vectors, which were generated from image pairs with similar cell perturbations. The processor creates a second distribution of a second plurality of pairwise comparisons of vectors, of the first set of vectors, which were generated from image pairs with dissimilar cell perturbations. The processor determines a difference between the first distribution and the second distribution and uses the difference to make a determination of goodness of the deep learning model as applied to the biological assay. | 2022-08-18 |
20220262456 | HLA CLUSTERS, GLOBAL FREQUENCIES, AND BINDING ACROSS SARS-CoV-2 VARIATION - Techniques are provided for determining pan-HLA binding of viral proteins. A trained classifier model is operable to determine, independently per HLA, at least one of (a) an average binding prediction of overlapping peptides at each position of a viral protein, (b) a maximum value of a binding prediction of overlapping peptides at each position of the viral protein, (c) standard deviation of a binding prediction of overlapping peptides at each position of the viral protein, and (d) a combination of one or more of (a)-(c). A classification engine uses the classifier model to determine average binding predictions of overlapping peptides at each position of the viral protein independently for test HLA-I and HLA-II functional groupings, where a peptide is classified as a binder when an average binding prediction corresponding to the peptide satisfies a binding value threshold. | 2022-08-18 |
20220262457 | A DEEP LEARNING APPROACH TO CORRELATE CELLULAR MORPHOLOGY AND GENETICS - Provided is a data-driven deep-learning based algorithm for synthetic biology applications that makes no assumptions and/or hypotheses on genotype-phenotype interactions. deep-learning based algorithm trains a neural network with morphological features from single genetic modifications and tests the neural network with morphological features from multiple genetic modifications. The trained and tested neural network uses a link between the morphological features caused by the single and multiple gene modifications as input and outputs a genotype-phenotype mapping highlighting perturbation subspaces. The genotype-phenotype mapping is used to select one or more genetic insults as a starting point to engineer cells in synthetic biology applications. | 2022-08-18 |
20220262458 | DETECTING NEURALLY PROGRAMMED TUMORS USING EXPRESSION DATA - Embodiments disclosed herein generally relate to classifying a tumor, based on gene expression data, as being neurally related or non-neurally related. The tumor may be classified using a machine-learning model, which may have been trained to differentiate gene-expression data associated with neuronal or neuroendocrine tumors from gene-expression data associated with non-neuronal and non-neuroendocrine tumors. Differential treatment and/or treatment recommendations may be provided based on the classification. First-line checkpoint blockade therapy may be used or recommended when a tumor is identified as being non-neurally related, and a combination therapy (e.g., initial chemotherapy and subsequent checkpoint blockade therapy) may be used or recommended when a tumor is identified as being neurally related. | 2022-08-18 |
20220262459 | METHODS AND SYSTEMS FOR IDENTIFYING TARGET GENES - The present disclosure provides methods and systems for identification of genomic regions for therapeutic targeting. A method for identifying one or more genomic regions for therapeutic targeting, which may facilitate re-programming of a cell from one phenotypic state to another, may comprise: providing single-cell RNA-seq data for a plurality of diseased cells and a plurality of normal cells of a cell type; mapping the single-cell RNA-seq data for the plurality of diseased cells and the plurality of normal cells into a latent space corresponding to a plurality of phenotypic states of the cell type; identifying, based at least in part on a topology of the latent space, the one or more genomic regions for therapeutic targeting; and electronically outputting the one or more genomic regions for therapeutic targeting. | 2022-08-18 |
20220262460 | METHODS FOR ACCURATE COMPUTATIONAL DECOMPOSITION OF DNA MIXTURES FROM CONTRIBUTORS OF UNKNOWN GENOTYPES - Computer methods and systems for quantifying a nucleic acid sample comprising nucleic acid of one or more contributors to: receive nucleic acid sequence reads obtained from the nucleic acid sample and mapped to alleles at polymorphism loci; determine, using the nucleic acid sequence reads, allele counts for each of the alleles at the polymorphism loci; use a probabilistic mixture model that applies a probabilistic mixture model to the allele counts, and that uses probability distributions to model the allele counts at the polymorphism loci; quantify, using the probabilistic mixture model, one or more fractions of nucleic acid of the one or more contributors in the nucleic acid sample; determine a probability that a specific contributor among the one or more contributors has a specific genotype; and call, based on the posterior probability, that the nucleic acid sample includes nucleic acid from the specific contributor. | 2022-08-18 |
20220262461 | SYSTEM AND METHOD FOR COPY NUMBER VARIANT ERROR CORRECTION - A system for managing a CNV reference panel is disclosed, wherein the system includes a database arrangement configured to store a plurality of sample genomic DNA sequences and metadata associated with each of plurality of sample genomic DNA sequences. The system further includes a computing arrangement communicatively coupled to the database arrangement. The computing arrangement is configured to render a user interface to receive a target genomic DNA sequence along with interpretation request for calling CNVs in target genomic DNA sequence. The computing arrangement compares the plurality of characteristic attributes in the interpretation request with the metadata associated with each of plurality of sample genomic DNA sequences. Furthermore, the computing arrangement identifies a set of sample genomic DNA sequences as a reference panel, based on the comparison. Moreover, the computing arrangement utilise the reference panel for calling CNVs in the target genomic DNA sequence. | 2022-08-18 |
20220262462 | COMPUTATIONAL FILTERING OF METHYLATED SEQUENCE DATA FOR PREDICTIVE MODELING - Computational techniques are disclosed for using methylation profiles to classify the medication condition of a person. Initial sequence data is obtained containing sequences of an initial set of nucleic acids from a biological sample of a person. The initial sequence data is filtered to generate filtered sequence data that describes sequences of a filtered subset of nucleic acids from the biological sample. A methylation profile is determined for the filtered subset of nucleic acids from the biological sample. The methylation profile can be processed to determine a likelihood that the person has the specified medical condition. The system outputs an indication of the likelihood that the person has the specified medical condition. | 2022-08-18 |
20220262463 | METHOD FOR SIMULATING OLIGOMER OR POLYMER GROWTH - A method for simulating oligomer or polymer growth includes: receiving a reaction recipe including a plurality of reactive molecules; for each reactive molecule of the plurality of reactive molecules, determining at least one functional group associated with the reactive molecule; assigning a functional group type to each of the functional groups associated with the plurality of reactive molecules; determining at least one reaction rule associated with each functional group type; simulating a plurality of oligomer or polymer forming reactions from the plurality of reactive molecules based on the at least one reaction rule to form a plurality of simulated oligomers or polymers; and determining at least one oligomer or polymer structure associated with a first oligomer or polymer of the plurality of simulated oligomers or polymers. | 2022-08-18 |
20220262464 | DEVICE AND METHOD FOR DETERMINING A PROPERTY OF A SUBSTANCE OR A MATERIAL - A device and method for determining a property of a substance or a material, in particular, the viscosity of an adhesive agent. A model is provided which includes a plurality of modules, which are configured to process data as a function of input variables. A module of the plurality of modules is configured to determine output variables, which characterize the properties of substances or materials. In one selection, at least one of the output variables, which is determined, being selectable. The selection is identified, and at least one of the input variables, whose data are processed by the model, being determined as a function of the selection. At least one of the modules is selected to process data for the at least one of the input variables. | 2022-08-18 |
20220262465 | RADIOLOGY-BASED RISK ASSESSMENT FOR BIOPSY-BASED SCORES - A computer-implemented method for determining tumor heterogeneity is provided. Embodiments of the method involve analyzing a radiological image of a tumor to calculate a value indicative of tumor activity at each of a plurality of locations in the tumor; determining whether each calculated value is above a predetermined threshold; and calculating a heterogeneity score for the tumor; wherein the heterogeneity score is calculated based on a volume fraction of the tumor having a value indicative of tumor activity above the predetermined threshold. Also provided are associated systems and computer program products. | 2022-08-18 |
20220262466 | STORING DATA FROM A PROCESS TO PRODUCE A CHEMICAL, PHARMACEUTICAL, BIOPHARMACEUTICAL AND/OR BIOLOGICAL PRODUCT - Aspects relate to a computer-implemented method, a computer program and a system for storing a heterogeneous sequence of discrete-time data determined from a process to produce a chemical, pharmaceutical, biopharmaceutical and/or biological product. The method comprises receiving the discrete-time data, the discrete-time data comprising data from one or more first scientific instruments and including data comprising one or more timestamps corresponding to one or more digital signals. | 2022-08-18 |
20220262467 | HEALTH DATA PROCESSING SYSTEM AND HEALTH DATA PROCESSING METHOD - A health data processing system in which an arithmetic unit can gain access to a database storing basic data of residents, health data of residents, and social capital index measurement data is provided. The health data processing system includes: an individual health condition analysis part which analyzes an individual health condition being each resident's health condition with use of the health data; a regional health condition analysis part which analyzes a regional health condition being a health condition of residents who belong to a region with use of the health data; an SCI derivation part which derives a regional SCI being a social capital index for every region with use of the social capital index measurement data; and an individually providing information generation part which generates information contributing to residents' health with use of the individual health condition, the regional health condition, and the regional SCI. | 2022-08-18 |
20220262468 | System and method for managing electronic medical records - A system and method for managing electronic medical/dental records are provided. The system is designed to improve communication and increase medical accessibility in a convenient way for both medical/dental practitioners and patients, empower patients and provide secure communication, increase access to medical care and decrease time and cost associated with medical consultations. | 2022-08-18 |
20220262469 | DATA ABSTRACTION SYSTEM ARCHITECTURE NOT REQUIRING INTEROPERABILITY BETWEEN DATA PROVIDERS - Described are data abstraction systems, methods, and media for aggregating and abstracting data records from data providers, which are not substantially interoperable with each other. Features include data provider connector modules dynamically loaded, based on definitions stored on disk, that facilitate data mapping and individual matching. | 2022-08-18 |
20220262470 | System and Method for Patient Care Improvement - Described is a system comprising an input module receiving a first data set indicative of at least one patient condition for each of a plurality of patients obtained during a predetermined time period, a comparison module comparing each of the at least one patient condition to at least one filter criteria, a filter module selecting a patient to include in a second data set if the at least one patient condition of the patient satisfies the at least one filter criteria, a report module generating a report based on the second data set, wherein the report includes at least one patient identifier for each patient in the second data set and at least one descriptor of the at least one patient condition for each patient in the second data set, and a classification module storing at least one classification value for the at least one patient condition. | 2022-08-18 |
20220262471 | DOCUMENT CREATION SUPPORT APPARATUS, METHOD, AND PROGRAM - Provided is at least one processor, and the processor is configured to analyze an image to derive property information indicating a property of a structure of interest included in the image, generate a sentence related to the image based on the property information, analyze the sentence to specify a term representing the property related to the structure of interest included in the sentence, and collate the property information with the term. | 2022-08-18 |