33rd week of 2021 patent applcation highlights part 62 |
Patent application number | Title | Published |
20210257239 | STORAGE SHELF - A storage shelf includes a body frame and a shelf plate attached to the body frame with an elastic body therebetween, the storage shelf storing thereon a FOUP including a contained object. The storage shelf includes a feed nozzle on the shelf plate to feed gas to the FOUP, and a feed tube with one end communicating with the feed nozzle and the other end communicating with a main tube connected to a feed source of the gas to be fed to the FOUP, the main tube being supported by the body frame. The feed tube has a flexible portion having flexibility at least partially between the one end and the other end. | 2021-08-19 |
20210257240 | CONTAINER FOR STORING WAFER - The present invention relates to a container for storing a wafer, particularly to a container for storing a wafer in which a plurality of purging areas is vertically partitioned in the interior of a storage chamber, and a purge gas is sprayed into the plurality of purging areas, thereby allowing not only uniform purging of the wafer to be assured but also efficient purging of the wafer without waste of the purge gas to be achieved. | 2021-08-19 |
20210257241 | SUBSTRATE PROCESSING APPARATUS - A substrate transport apparatus comprising a support frame an articulated arm connected to the support frame, having at least one movable arm link and an end effector connected to the movable arm link, with a substrate holding station located thereon. Wherein the movable arm link is a reconfigurable arm link having a modular composite arm link casing, formed of link case modules rigidly coupled to each other, and a pulley system cased in and extending through the rigidly coupled link case modules substantially end to end of the modular composite arm link casing, wherein the rigidly coupled link case modules include link case end modules connected by at least one interchangeable link case extension module having a predetermined characteristic determining a length of the movable arm link, wherein at least one interchangeable link case extension module is selectable for connection to link case end modules forming the reconfigurable arm link. | 2021-08-19 |
20210257242 | SUBSTRATE TRANSFER APPARATUS AND METHOD OF MEASURING POSITIONAL DEVIATION OF SUBSTRATE - A substrate transfer apparatus of the present invention includes: a robot including a hand configured to hold a substrate, and an arm configured to move the hand; a robot control device configured to set a moving path for the hand and control the arm such that the hand moves on the moving path toward a target position; and a camera disposed so as to be able to capture an image of the substrate held by the hand located at a predetermined confirmation position. The robot control device sets the moving path so as to pass through the confirmation position, obtains an image captured by the camera when the hand is located at the confirmation position, calculates a distance between a predetermined environment and the substrate which are taken in the image, and calculates a positional deviation amount from a reference position of the substrate on the basis of the distance. | 2021-08-19 |
20210257243 | ELECTROSTATIC CHUCK AND METHOD FOR MANUFACTURING ELECTROSTATIC CHUCK - An electrostatic chuck of the disclosure includes a ceramic base in plate form, and an electrostatic attraction electrode. The ceramic base includes a plurality of particles containing aluminum oxide as a main component. The plurality of particles contain magnesium atoms and zirconium atoms. | 2021-08-19 |
20210257244 | 3D SEMICONDUCTOR DEVICE AND STRUCTURE - A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; a second level including a second single crystal layer, the second level including second transistors; and a third level including a third single crystal layer, the third level including third transistors, where the second level overlays the first level, where the second level is bonded to the first level, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonds, where the bonded includes metal to metal bonds, where the second level includes a first array of first memory cells, and where the third level includes a second array of second memory cells. | 2021-08-19 |
20210257245 | METHODS FOR PRODUCING A 3D SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE - A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming first alignment marks and control circuits including first single crystal transistors; forming at least one second level above the first level; performing a first etch step including etching first holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching second holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where the etching first holes includes performing a lithography step aligned to the first alignment marks. | 2021-08-19 |
20210257246 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device package includes a substrate, a partition structure and a polymer film. The partition structure is disposed on the substrate and defines a space for accommodating a semiconductor device. The polymer film is adjacent to a side of the partition structure distal to the substrate. A first side surface of the polymer film substantially aligns with a first side surface of the partition structure. | 2021-08-19 |
20210257247 | SYSTEM AND METHOD FOR RING FRAME CLEANING AND INSPECTION - A system and method for cleaning and inspecting ring frames is disclosed here. In one embodiment, a ring frame processing system includes: a cleaning station configured to remove a first tape on a first surface of a ring frame using a first blade, clean first adhesive residues from the first tape on the first surface of the ring frame using a first wheel brush, and remove second adhesive residues from a second tape on a second surface of the ring frame using a second blade; and an inspection station, wherein the inspection station comprises an automated optical inspection system configured to determine the cleanness of the first and second surfaces of the ring frame after cleaning. | 2021-08-19 |
20210257248 | POLISHING INTERCONNECT STRUCTURES IN SEMICONDUCTOR DEVICES - A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature. | 2021-08-19 |
20210257249 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device, including a high-voltage device region and a low-voltage device region, includes the steps of: providing a substrate, wherein a bottom mask layer and a top mask layer are sequentially disposed thereon; forming a doped region in the substrate based on a first layout pattern; patterning the substrate based on a second layout pattern to form at least two trenches in the substrate respectively in the high-voltage device region and the low-voltage device region; and patterning the top mask layer in the high-voltage device region based on a third layout pattern to form a patterned top mask layer and expose the bottom mask layer from the patterned top mask layer, wherein the third layout pattern is generated by comparing the first layout pattern and the second layout pattern and executing a Boolean operation. | 2021-08-19 |
20210257250 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate having first fin and a second fin spaced apart and extending lengthwise in parallel. A fin remnant is disposed between the first fin and the second fin, extends lengthwise in parallel with the first and second fins, and has a height lower than a height of each of the first fin and the second fin. A first field insulation layer is disposed between a sidewall of the first fin and a first sidewall of the fin remnant and a second field insulating layer is disposed on a sidewall of the second fin. A blocking liner conforms to a sidewall and a bottom surface of a trench bounded by a second sidewall of the fin remnant and a sidewall of the second field insulating layer. A trench insulation layer is disposed on the blocking liner in the trench. | 2021-08-19 |
20210257251 | METHOD FOR FABRICATING ELECTRODE AND SEMICONDUCTOR DEVICE - A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening. | 2021-08-19 |
20210257252 | MULTI-STEP PROCESS FOR FLOWABLE GAP-FILL FILM - Generally, examples described herein relate to methods and processing systems for performing multiple processes in a same processing chamber on a flowable gap-fill film deposited on a substrate. In an example, a semiconductor processing system includes a processing chamber and a system controller. The system controller includes a processor and memory. The memory stores instructions, that when executed by the processor cause the system controller to: control a first process within the processing chamber performed on a substrate having thereon a film deposited by a flowable process, and control a second process within the process chamber performed on the substrate having thereon the film. The first process includes stabilizing bonds in the film to form a stabilized film. The second process includes densifying the stabilized film. | 2021-08-19 |
20210257253 | DIFFUSION BARRIER COLLAR FOR INTERCONNECTS - Representative implementations of techniques and devices are used to reduce or prevent conductive material diffusion into insulating or dielectric material of bonded substrates. Misaligned conductive structures can come into direct contact with a dielectric portion of the substrates due to overlap, especially while employing direct bonding techniques. A barrier interface that can inhibit the diffusion is disposed generally between the conductive material and the dielectric at the overlap. | 2021-08-19 |
20210257254 | Methods for Forming Contact Plugs with Reduced Corrosion - A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug. | 2021-08-19 |
20210257255 | Melting Laser Anneal of Epitaxy Regions - A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten. | 2021-08-19 |
20210257256 | WAFER PROCESSING METHOD - There is provided a wafer processing method including a protective member disposing step of disposing a protective member on a top surface of a wafer; a modified layer forming step of forming an annular modified layer by irradiating the wafer with a laser beam so as to position, within a peripheral surplus region, a condensing point of the laser beam having a wavelength transmissible through the wafer; a separating step of separating a part or a whole of the peripheral surplus region from the wafer by dividing the wafer with the annular modified layer as a starting point; and a grinding step of thinning the wafer by grinding an undersurface of the wafer. In the modified layer forming step, the modified layer is formed in a shape of a circular truncated cone whose diameter is decreased from the top surface to the undersurface of the wafer. | 2021-08-19 |
20210257257 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor structure includes: providing a substrate; forming a stacked structure on the substrate; forming a barrier layer on a sidewall of the stacked structure; forming a first dielectric layer covering the barrier layer and the stacked structure; removing a portion of the first dielectric layer to expose an upper portion of the stacked structure; forming a metal layer covering the stacked structure and the first dielectric layer; performing an annealing process to react the metal layer with the stacked structure to form a metal silicide layer at the upper portion of the stacked structure; removing an unreacted portion of the metal layer; removing a portion of the barrier layer to form a recess above the barrier layer; and forming a second dielectric layer covering the metal silicide layer and the first dielectric layer to form air gaps on both sides of the stacked structure. | 2021-08-19 |
20210257258 | Multiple Threshold Voltage Implementation Through Lanthanum Incorporation - A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon. | 2021-08-19 |
20210257259 | ETCH PROFILE CONTROL OF POLYSILICON STRUCTURES OF SEMICONDUCTOR DEVICES - A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions. The method also includes forming first and second source/drain regions on first and second recessed portions of the first and second fin structures, respectively and replacing the first and second polysilicon structures with first and second gate structures, respectively. | 2021-08-19 |
20210257260 | Semiconductor Device and Method - Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride (HF) and ammonia (NH | 2021-08-19 |
20210257261 | Semiconductor Devices and Methods of Forming the Same - A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features. | 2021-08-19 |
20210257262 | Selective Dual Silicide Formation Using A Maskless Fabrication Process Flow - A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor. | 2021-08-19 |
20210257263 | NMOS and PMOS Transistor Gates with Hafnium Oxide Layers and Lanthanum Oxide Layers - A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack. | 2021-08-19 |
20210257264 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern. | 2021-08-19 |
20210257265 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming a first stack structure; forming first holes penetrating the first stack structure; forming a second stack structure on the first stack structure; forming second holes penetrating the second stack structure; measuring first direction distances between edges of the first holes and edges of the second holes; and correcting a first direction position at which the second holes are to be formed. The second holes may include one of a first shift hole shifted in a positive first direction from a first hole and a second shift hole shifted in a negative first direction from a first hole. | 2021-08-19 |
20210257266 | MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHODS OF OPERATION - A memory device includes a first wafer including a first bonding pad disposed on a first surface; a second wafer, including a second bonding pad disposed on a second surface of the second wafer, the second surface of the second wafer bonded on the first surface of the first wafer; and a first test pattern. The first test pattern includes a pair of first test pads disposed on the first surface and electrically coupled to each other; a pair of second test pads disposed on the second surface of the second wafer and respectively coupled to the pair of first test pads, when no misalignment failure between the first bonding pad and the second bonding pad occurs; and a pair of third test pads disposed on a third surface of the second wafer, which is opposite to the second surface, and respectively coupled to the pair of second test pads. | 2021-08-19 |
20210257267 | DISPLAY PANEL AND METHOD FOR MANUFACTURING SAME - The present disclosure provides a display panel and a method for manufacturing the same. The method includes providing a substrate including a display area and a non-display area. A chip on film (COF) and a testing structure are disposed in the non-display area. A testing circuit includes a signal trace including a non-metal trace and a metal trace connecting to each other. A cutting line is disposed on the signal trace. The method further includes testing the display area of the substrate by the testing structure, and removing a test pad. | 2021-08-19 |
20210257268 | SEMICONDUCTOR MODULE - A semiconductor module, including a ceramic board, a circuit pattern metal plate formed on a principal surface of the ceramic board, an external connection terminal bonded, via a solder, to the circuit pattern metal plate, and a low linear expansion coefficient metal plate located between the circuit pattern metal plate and the external connection terminal. The circuit pattern metal plate has a first edge portion and a second edge portion, which are opposite to each other and are respectively at a first side and a second side of the circuit pattern metal plate. The low linear expansion coefficient metal plate has a linear expansion coefficient lower than a linear expansion coefficient of the circuit pattern metal plate. | 2021-08-19 |
20210257269 | SEMICONDUCTOR DEVICE - A semiconductor device having a base circuit board, a case surrounding the base circuit board to demarcate, in a plan view, an opening area in which the base circuit board is disposed, and a sealing member that seals the base circuit board disposed in the case. The base circuit board includes a metal base substrate, a resin layer formed on the metal base substrate, and a circuit pattern formed on the resin layer. The case has an inner wall surface that faces an outer peripheral side surface of the base circuit board, and that includes a first inner wall portion which is in surface contact with an outer peripheral side surface of the metal base substrate, and a second inner wall portion that is separate from the outer peripheral side surface of the base circuit board, to thereby have a first gap therebetween filled with the sealing member. | 2021-08-19 |
20210257270 | COVER LID WITH SELECTIVE AND EDGE METALLIZATION - A cover lid for use with a semiconductor package is disclosed. First, a polyamide mask is applied to one surface of the lid plate. Next, the exposed areas of the surface, as well as the sides of the lid plate, are metallized. The polyamide mask can then be removed. This reduces pullback and shrinkage of the metallized layer, while lowering the manufacturing cost and process times. | 2021-08-19 |
20210257271 | SELF-CLEANING HEATSINK FOR ELECTRONIC COMPONENTS - Systems for cooling semiconductor devices that can comprise a heatsink and a cleaning element for the heatsink. The heatsink can have fins spaced apart from each other by channels. The cleaning element can have a base and one or more arms extending from the base. The cleaning element can be positioned with respect to the heatsink such that each arm is aligned with a corresponding channel between the fins, and the arms are moveable between a flow configuration in which the arms are in the channels and a cleaning configuration in which the arms are outside of the channels. | 2021-08-19 |
20210257272 | CUSTOMIZED INTEGRATED HEAT SPREADER DESIGN WITH TARGETED DOPING FOR MULTI-CHIP PACKAGES - Embodiments include semiconductor packages. A semiconductor package includes a first die and a second die on a package substrate, and an integrated heat spreader (IHS) over the first die, the second die, and the package substrate, wherein the IHS has a lid and a plurality of sidewalls. The semiconductor package also includes a plurality of conductive slugs in the lid of the IHS. The lid of the IHS has a bottom surface that is coplanar to bottom surfaces of the conductive slugs. The conductive slugs are comprised of high-k thermal conductive materials, including cubic boron nitride, hexagonal boron nitride, graphite, carbon-based materials, diamonds, or diamond-based materials. The bottom surfaces of the conductive slugs are on a top surface of the first die and a top surface of the second die. The IHS is comprised of thermal conductive materials, including aluminum, copper, copper-based metals, or alloys. | 2021-08-19 |
20210257273 | SEMICONDUCTOR MODULE - A semiconductor module includes a power element, a signal wiring, and a heat sink. The signal wiring is connected to a signal pad of the power element. The heat sink cools the power element. The power element has an active area provided by a portion where the signal pad is formed. The signal pad is thermally connected to the heat sink via the signal wiring. | 2021-08-19 |
20210257274 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - A semiconductor element includes a main body and an obverse face electrode. The main body includes an obverse face that faces in a thickness direction. The obverse face electrode is electrically connected to the main body. The obverse face electrode includes a first section and a plurality of second sections. The first section is provided on the obverse face. The plurality of second sections are in contact with the first section, and spaced apart from each other in a direction perpendicular to the thickness direction. A total area of the plurality of second sections is smaller than an area of the first section including portions overlapping with the plurality of second sections, in a view along the thickness direction. | 2021-08-19 |
20210257275 | SEMICONDUCTOR PACKAGE - A semiconductor package provided. The semiconductor package includes an interposer layer including a first surface and a second surface opposing each other, a first semiconductor chip and a second semiconductor chip on the first surface of the interposer layer, and a block copolymer film on the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chip are different from each other. The block copolymer film includes a first pattern and a second pattern, which are different from each other, and one of the first pattern and the second pattern contains graphite. | 2021-08-19 |
20210257276 | POWER CONVERSION APPARATUS - To improve cooling capability, power conversion apparatus | 2021-08-19 |
20210257277 | ENHANCED BASE DIE HEAT PATH USING THROUGH-SILICON VIAS - Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy. | 2021-08-19 |
20210257278 | MAGNETOFLUID PUMP DEVICE FOR IGBT HEAT DISSIPATION AND TEST METHOD THEREFOR - A magnetofluid pump device for IGBT heat dissipation and a test method therefor are provided. The magnetofluid pump device uses a liquid metal as a coolant, which can absorb more heat than an ordinary water-cooling device and better dissipate heat for IGBT chips. Temperature and pressure changes in an inlet pipe and an outlet pipe of a magnetofluid pump can be monitored in real time through temperature sensors and pressure sensors, and temperature changes of the IGBT chips can be observed in real time through a thermal imager. The test method for the magnetofluid pump device for IGBT heat dissipation proposed by the present invention is simple and easy to implement. A magnetic fluid can be driven to flow by energizing positive and negative electrodes in the magnetofluid pump under the action of magnetic fields, and water-cooling equipment can dissipate heat for the magnetic fluid in the magnetofluid pump. | 2021-08-19 |
20210257279 | ELECTRONIC DEVICE HAVING SUBSTRATE - An electronic device having a substrate includes a substrate and at least one outer layer. The substrate has a plurality of first vias. The outer layer has a plurality of second vias. The outer layer is disposed on a side of the substrate. The first vias have a larger distribution density or quantity than the second vias so that a portion of the first vias are electrically connected to the second vias, and a portion of the first vias are electrically floating. | 2021-08-19 |
20210257280 | POWER MODULE - A power module is disclosed. A power module according to an embodiment of the present disclosure may include a first substrate and a second substrate spaced apart from each other, an electronic device unit provided on at least either one of the first and second substrates, and a lead frame unit provided between the first and second substrates. One side of the lead frame unit may be connected to an external circuit, and the other side thereof may be configured to electrically connect the first and second substrates. Accordingly, the lead frame unit may perform a function of electrically connecting the first and second substrates instead of a via spacer in the related art. | 2021-08-19 |
20210257281 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device, including: a semiconductor element which includes an element main surface and an element rear surface that face opposite sides in a thickness direction and in which a first electrode and a second electrode are formed on the element main surface; a first conductive member electrically connected to the first electrode; a second conductive member electrically connected to the second electrode; and a sealing resin configured to cover part of the first conductive member, part of the second conductive member, and the semiconductor element. | 2021-08-19 |
20210257282 | MULTI-CHIP MODULE LEADLESS PACKAGE - A multi-chip module (MCM) package includes a leadframe including half-etched lead terminals including a full-thickness and half-etched portion, and second lead terminals including a thermal pad(s). A first die is attached by a dielectric die attach material to the half-etched lead terminals. The first die includes first bond pads coupled to first circuitry configured for receiving a control signal and for outputting a coded signal and a transmitter. The second die includes second bond pads coupled to second circuitry configured for a receiver with a gate driver. The second die is attached by a conductive die attach material to the thermal pad. Bond wires include die-to-die bond wires between a portion of the first and second bond pads. A high-voltage isolation device is between the transmitter and receiver. A mold compound encapsulates the first and the second die. | 2021-08-19 |
20210257283 | NOTEBOOK BATTERY PROTECTION CIRCUIT PACKAGE AND METHOD OF FABRICATING THE SAME - Provided is a notebook battery protection circuit package including a package substrate, a fuel gauge integrated circuit (FGIC) module mounted on the package substrate, a protection integrated circuit (IC) module mounted on the package substrate, a charge/discharge transistor module mounted on the package substrate, and a mold provided on the package substrate to encapsulate the FGIC module, the protection IC module, and the charge/discharge transistor module into one. | 2021-08-19 |
20210257284 | SEMICONDUCTOR MODULE - A semiconductor module includes a ceramic board, a circuit pattern metal plate on a principal surface of the ceramic board, and an external connection terminal including a bonding portion and a conductive portion. The metal plate includes a bonding area at a first surface thereof, and a stress relaxation portion disposed within the bonding area. The bonding portion has a bonding surface, and an edge that is located at a position overlapping an area in which the stress relaxation portion is disposed in a plan view. A solder is disposed between the bonding surface and the bonding area, to bond the external connection terminal to the circuit pattern metal plate. | 2021-08-19 |
20210257285 | Semiconductor Device and Method of Manufacture - A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%. | 2021-08-19 |
20210257286 | SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure includes a substrate. The substrate includes a first ground layer. The first ground layer has a body and a first tooth protruding from a side of the body. The first tooth has a first lateral side. The first lateral side of the first tooth is inclined relative to the side of the body in a top view of the first ground layer. | 2021-08-19 |
20210257287 | CHIP PACKAGE AND CIRCUIT BOARD THEREOF - A chip package includes a circuit board, a chip and an underfill. The circuit board includes a substrate, first circuit lines and second circuit lines. Each of the first circuit lines includes an inner lead and a first line fragment that are disposed on a chip mounting area and an underfill covering area of the substrate, respectively. The second circuit lines are disposed on the chip mounting area and not located between the adjacent inner leads so as to form a wider space between the adjacent first line fragments. The wider space enables the underfill to flow to between the circuit board and the chip and prevents air bubbles from being embedded in the underfill filled between the circuit board and the chip. | 2021-08-19 |
20210257288 | Chip-Last Wafer-Level Fan-Out with Optical Fiber Alignment Structure - A redistribution layer is formed on a carrier wafer. A cavity is formed within the redistribution layer. An electro-optical die is flip-chip connected to the redistribution layer. A plurality of optical fiber alignment structures within the electro-optical die is positioned over and exposed to the cavity. Mold compound material is disposed over the redistribution layer and the electro-optical die. A residual kerf region of the electro-optical die interfaces with the redistribution layer to prevent mold compound material from entering into the optical fiber alignment structures and the cavity. The carrier wafer is removed from the redistribution layer. The redistribution layer and the mold compound material are cut to obtain an electro-optical chip package that includes the electro-optical die. The cutting removes the residual kerf region from the electro-optical die to expose the plurality of optical fiber alignment structures and the cavity at an edge of the electro-optical chip package. | 2021-08-19 |
20210257289 | PACKAGE CORE ASSEMBLY AND FABRICATION METHODS - The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like. | 2021-08-19 |
20210257290 | SEMICONDUCTOR DEVICE WITH CONNECTING STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, and a first connecting structure including a first connecting insulating layer positioned on the first semiconductor structure, a plurality of first connecting contacts positioned in the first connecting insulating layer, and a plurality of first supporting contacts positioned in the first connecting insulating layer. A top surface of the first connecting insulating layer, top surfaces of the plurality of first connecting contacts, and top surfaces of the plurality of first supporting contacts are substantially coplanar. Bottom surfaces of the plurality of first connecting contacts contact a top surface of the first semiconductor structure. | 2021-08-19 |
20210257291 | APPARATUSES AND METHODS FOR PROTECTING TRANSISTOR IN A MEMORY CIRCUIT - A semiconductor device may include a multi-level wiring structure comprising a first-level wiring layer, a second-level wiring layer and an insulating layer between the first-level wiring layer and the second-level wiring layer. The device may also include a bond pad, a first wiring extending from the bond pad, and a second wiring overlapping at least in part with the first wiring through the insulating layer to be capacitively coupled to the first wiring. The first wiring and the second wiring may each be formed respectively as the first-level wiring layer and the second-level wiring layer. The device may also include a protection circuit configured to be DC coupled to the second wiring. The first-level wiring layer may include a redistribution layer (RDL). | 2021-08-19 |
20210257292 | SEMICONDUCTOR DEVICE WITH COMPOSITE PASSIVATION STRUCTURE AND METHOD FOR PREPARING THE SAME - A semiconductor device includes a conductive pattern formed over a semiconductor substrate, and an interconnect structure formed over the conductive pattern. The semiconductor device also includes a first passivation layer over the conductive pattern; a second passivation layer over the first passivation layer; an interconnect structure disposed over the conductive pattern and in the first passivation layer and the second passivation layer; and an interconnect liner disposed between the interconnect structure and the conductive pattern and surrounding the interconnect structure, wherein inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern. | 2021-08-19 |
20210257293 | Nitrogen Plasma Treatment For Improving Interface Between Etch Stop Layer And Copper Interconnect - Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect. The nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration, the first nitrogen concentration to a second nitrogen concentration, and/or the first number of nitrogen-nitrogen bonds to a second number of nitrogen-nitrogen bonds, each of which minimizes accumulation of copper vacancies at the interface. | 2021-08-19 |
20210257294 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a semiconductor substrate, a conductive pad disposed on the semiconductor substrate, and a pillar pattern disposed on the conductive pad. The semiconductor device further includes a solder seed pattern disposed on the pillar pattern, and a solder portion disposed on the pillar pattern and the solder seed pattern. A first width of the solder seed pattern is less than a second width of a top surface of the pillar pattern. | 2021-08-19 |
20210257295 | SEMICONDUCTOR DEVICE AND METHOD - A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a low-k dielectric layer over the second dielectric layer, a second dielectric layer on the high resistance layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer. | 2021-08-19 |
20210257296 | STRUCTURE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE WITH RESISTIVE ELEMENTS - A method of forming a semiconductor device includes forming a conductive feature and a first punch stop layer, where the conductive feature has a first top surface, and where the first punch stop layer has a second top surface that is substantially level with the first top surface. The method further includes forming a resistive element over the first punch stop layer. The method further includes etching through a first portion of the resistive element to form a first trench that exposes both the second top surface of the first punch stop layer and a first sidewall surface of the resistive element. The method further includes forming a first conductive via within the first trench, where the first conductive via contacts the first sidewall surface of the resistive element. | 2021-08-19 |
20210257297 | SEMICONDUCTOR DEVICE WITH PROGRAMMABLE ANTI-FUSE FEATURE AND METHOD FOR FABRICATING THE SAME - The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a peak portion positioned on the substrate, a gate insulating layer positioned on the peak portion and the substrate, a gate bottom conductive layer positioned on the gate insulating layer, and a first doped region positioned in the substrate and adjacent to one end of the gate insulating layer. | 2021-08-19 |
20210257298 | MICROELECTRONIC DEVICES WITH SYMMETRICALLY DISTRIBUTED STAIRCASE STADIUMS AND RELATED SYSTEMS AND METHODS - Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed. | 2021-08-19 |
20210257299 | HYBRID INTERCONNECT WITH A RELIABILITY LINER IN WIDE FEATURES - A back-end-of-the-line (BEOL) interconnect structure is provided that includes a hybrid metal-containing electrically conductive structure and a copper-containing electrically conductive structure embedded in an interconnect dielectric material layer. The hybrid metal-containing electrically conductive structure has a first critical dimension and includes an optional diffusion barrier liner and a hybrid metal-containing region. The copper-containing electrically conductive structure has a second critical dimension that is greater than the first critical dimension and includes an optional first diffusion barrier liner, a hybrid metal-containing liner, a second diffusion barrier liner and a copper-containing region. The hybrid metal-containing region and the hybrid metal-containing liner are compositionally the same and include a metal or metal alloy that has a higher bulk resistivity than copper. | 2021-08-19 |
20210257300 | THIN FILM CONDUCTIVE MATERIAL WITH CONDUCTIVE ETCH STOP LAYER - A structure comprises a substrate and a conductive pad disposed over the substrate. A conductive layer overlies the conductive pad. A via is disposed over the conductive pad. The via penetrates through the conductive layer and touches a surface of the conductive pad. | 2021-08-19 |
20210257301 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a plurality of conductive layers, a plurality of contacts, a plurality of dielectric members, a channel body, and a memory film. The plurality of conductive layers is stacked to be separated from each other and formed in a plate shape extending in a direction intersecting a stacking direction so as to extend over first and second regions. Each of the plurality of contacts penetrates a different number of conductive layers among the plurality of conductive layers and is connected to a different conductive layer of the plurality of conductive layers at a different one of positions of the plurality of conductive layers stacked in the first region. Each of the plurality of dielectric members is arranged from substantially same height position to a different one of height positions and connected to a different one of the plurality of contacts. | 2021-08-19 |
20210257302 | Partial Barrier Free Vias for Cobalt-Based Interconnects and Methods of Fabrication Thereof - Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium. | 2021-08-19 |
20210257303 | EMBEDDED MULTI-DIE INTERCONNECT BRIDGE PACKAGES WITH LITHOTGRAPHICALLY FORMED BUMPS AND METHODS OF ASSEMBLING SAME - An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly. | 2021-08-19 |
20210257304 | SEMICONDUCTOR DEVICE HAVING THROUGH SILICON VIAS AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes a substrate, a conductive feature, a redistribution layer, at least one through silicon via and at least one bump. The conductive feature is disposed over a front surface of the substrate, and the redistribution layer is disposed over a back surface opposite to the front surface. The through silicon via penetrates through the substrate and contacts the conductive feature embedded in an insulative layer. The bump contacts the redistribution layer and the through silicon via and serves as an electrical connection therebetween. | 2021-08-19 |
20210257305 | SEMICONDUCTOR PACKAGE, AND PACKAGE ON PACKAGE HAVING THE SAME - A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer. | 2021-08-19 |
20210257306 | PACKAGE STRUCTURE AND FABRICATION METHODS - The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein. | 2021-08-19 |
20210257307 | RECONSTITUTED SUBSTRATE STRUCTURE AND FABRICATION METHODS FOR HETEROGENEOUS PACKAGING INTEGRATION - The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device. | 2021-08-19 |
20210257308 | BARRIER REMOVAL FOR CONDUCTOR IN TOP VIA INTEGRATION SCHEME - A multi-layer device comprising a barrier or adhesion layer located on a portion of a first top surface of a first layer, a conductive metal layer located on barrier or adhesion layer; and a dielectric layer located on top of the first layer, wherein the dielectric layer is in direct contact with the sidewall of the conductive metal layer. | 2021-08-19 |
20210257309 | MULTI-LAYERED ADHESION PROMOTION FILMS - Structures are described that include multi-layered adhesion promotion films over a conductive structure in a microelectronic package. The multi-layered aspect provides adhesion to surrounding dielectric material without a roughened surface of the conductive structure. Furthermore, the multi-layered aspect allows for materials with different dielectric constants to be used, the average of which can provide a closer match to the dielectric constant of the surrounding dielectric material. According to an embodiment, a first dielectric layer that includes at least one nitride material can provide good adhesion with the underlying conductive structure, while one or more subsequent dielectric layers that include at least one oxide material can provide different dielectric constant values (e.g., typically lower) compared to the first dielectric layer to bring the overall dielectric constant closer to that of a surrounding dielectric material. The first and second layers may be discrete layers or a single continuous layer with grading. | 2021-08-19 |
20210257310 | Alignment Structure for Semiconductor Device and Method of Forming Same - An alignment structure for a semiconductor device and a method of forming same are provided. A method includes forming an isolation region over a substrate and forming an alignment structure over the isolation region. Forming the alignment structure includes forming a sacrificial gate electrode layer over the substrate and the isolation region. The sacrificial gate electrode layer is patterned to form a plurality of first sacrificial gates over the isolation region. At least one of the plurality of first sacrificial gates is reshaped. The at least one of the plurality of first sacrificial gates is disposed at an edge of the alignment structure in a plan view. A sidewall of the at least one of the plurality of first sacrificial gates comprises a notch at an interface between the at least one of the plurality of first sacrificial gates and the isolation region. | 2021-08-19 |
20210257311 | SEMICONDUCTOR DEVICE PACKAGE - A semiconductor device package includes a first substrate, a second substrate, a first electronic component, a second electronic component and a shielding layer. The second substrate is disposed over the first substrate. The first electronic component is disposed between the first substrate and the second substrate. The second electronic component is disposed between the first substrate and the second substrate and adjacent to the second substrate than the first electronic component. The shielding element electrically connects the second electronic component to the second substrate. The second electronic component and the shielding element define a space accommodating the first electronic component. | 2021-08-19 |
20210257312 | STRAPPED COPPER INTERCONNECT FOR IMPROVED ELECTROMIGRATION RELIABILITY - A semiconductor device a strapped interconnect line, which in turn includes a first interconnect line at a first level above a semiconductor substrate, and a second interconnect line at a second level above the interconnect substrate. A dielectric capping layer is located directly on the first interconnect line. A plurality of strapping vias are connected between the first interconnect line and the second interconnect line. Each of the strapping vias extends from a first side of the first interconnect line to a second side of the second interconnect line. | 2021-08-19 |
20210257313 | REGULATOR CIRCUIT PACKAGE TECHNIQUES - Techniques are provided for containing magnetic fields generated by an integrated switching package and for reducing electromagnetic interference generated from an integrated switching package. | 2021-08-19 |
20210257314 | WARPAGE CONTROL IN MICROELECTRONIC PACKAGES, AND RELATED ASSEMBLIES AND METHODS - A microelectronic device and/or microelectronic device package having a warpage control structure. The warpage control structure may be positioned over an encapsulating material, wherein the encapsulating material is positioned between the warpage control structure and a die positioned over a substrate. The warpage control structure may have a first thickness over a first portion of the encapsulating material and a second thickness over a second portion of the encapsulating material. Methods of forming the microelectronic device are also disclosed herein. | 2021-08-19 |
20210257315 | LEADFRAME WITH PAD ANCHORING MEMBERS AND METHOD OF FORMING THE SAME - A leadframe having extensions around an outer edge of a die pad are disclosed. More specifically, leadframes are created with a flange formed at the outer edge of the die pad and extending away from the die pad. The flange is bent, such that it is positioned at an angle with respect to the die pad. Leadframes are also created with anchoring posts formed adjacent the outer edge of the die pad and extending away from the die pad. The anchoring posts have a central thickness that is less than a thickness of first and second portions opposite the central portion. When the leadframe is incorporated into a package, molding compound completely surrounds each flange or anchoring post, which increases the bond strength between the leadframe and the molding compound due to increased contact area. The net result is a reduced possibility of delamination at edges of the die pad. | 2021-08-19 |
20210257316 | SEMICONDUCTOR DEVICE INCLUDING DUMMY CONDUCTIVE CELLS - A method includes forming signal lines in a pair of neighboring metal layers of a semiconductor device, and forming first dummy conductive cells in an empty area without metal lines passing therethrough, between the pair of neighboring metal layers. At least two dummy conductive cells of the first dummy conductive cells that are separated from each other, and the at least two dummy conductive cells fully overlap one of the signal lines in plan view. | 2021-08-19 |
20210257317 | DISTRIBUTING ON CHIP INDUCTORS FOR MONOLITHIC VOLTAGE REGULATION - Distributions of on-chip inductors for monolithic voltage regulation are described. On-chip voltage regulation may be provided by integrated voltage regulators (IVRs), such as a buck converter with integrated inductors. On-chip inductors may be placed to ensure optimal voltage regulation for high power density applications. With this technology, integrated circuits may have many independent voltage domains for fine-grained dynamic voltage and frequency scaling that allows for higher overall power efficiency for the system. | 2021-08-19 |
20210257318 | RADIO FREQUENCY MODULE - A radio frequency module includes a radio frequency integrated circuit (RFIC) to input or output a base signal and a radio frequency (RF) signal having a higher frequency than the base signal, a wiring via extending upward from the RFIC and a feed line electrically connected to the wiring via to provide a transmission path of the RF signal, a second ground layer surrounding the feed line, a first ground layer spaced above the second ground layer, a third ground layer between the second ground layer and the RFIC, a feed-line insulating layer disposed between the first and third ground layers, an IC wiring layer between the third ground layer and the RFIC, electrically connected to the RFIC, and providing a transmission path of the base signal, and an IC insulating layer between the third ground layer and the RFIC, having a higher dielectric constant than the feed-line insulating layer. | 2021-08-19 |
20210257319 | Gallium Arsenide Radio Frequency Circuit and Millimeter Wave Front-End Module - A gallium arsenide (GaAs) radio frequency (RF) circuit is disclosed. The GaAs RF circuit includes a power amplifier and a low noise amplifier; a first transmit/receive (TR) switch, coupled to the power amplifier and the low noise amplifier, wherein the first TR switch is fabricated by a pHEMT (Pseudomorphic High Electron Mobility Transistor) process; and a first active phase shifter, coupled to the power amplifier or the low noise amplifier, wherein the first active phase shifter is fabricated by an HBT (Heterojunction Bipolar Transistor) process; wherein the GaAs RF circuit is formed within a GaAs die. | 2021-08-19 |
20210257320 | Semiconductor Having a Backside Wafer Cavity for Radio Frequency (RF) Passive Device Integration and/or Improved Cooling and Process of Implementing the Same - A semiconductor device configured for a radio frequency (RF) application and further configured for passive device integration and/or improved cooling includes a substrate; an active region portion arranged on the substrate, the active region portion includes at least one radio frequency (RF) transistor amplifier; a cavity arranged within the substrate; and one or more radio frequency (RF) devices arranged in the cavity. | 2021-08-19 |
20210257321 | INTEGRATED CIRCUIT PACKAGE WITH A MAGNETIC CORE - Aspects of the present disclosure provide an integrated circuit package having an inductive element with a magnetic core. An example integrated circuit package generally includes a semiconductor die, a redistribution layer, and a magnetic core. The semiconductor die includes a metal layer having first conductive traces and conductive pillars coupled to and extending from the metal layer. The redistribution layer is disposed below the semiconductor die and includes second conductive traces. A portion of the first conductive traces, a portion of the conductive pillars, and a portion of the second conductive traces are arranged to form an inductive element disposed below a portion of the semiconductor die. The magnetic core is disposed in the inductive element. | 2021-08-19 |
20210257322 | SEMI-FINISHED PRODUCT OF POWER DEVICE, MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF POWER DEVICE - A semi-finished product of a power device including a semiconductor chip and a first solder pad is provided. The semiconductor chip has an active surface and a rear surface opposite to the active surface. The first solder pad is positioned and fixed on a center of the semiconductor chip. The first solder pad is sheet-shaped. The semiconductor chip is connected to the first solder pad with the active surface. A size of the first solder pad is smaller than a size of the semiconductor chip to expose a portion of the semiconductor chip. A manufacturing method of the semi-finished product of the power device and a manufacturing method of the power device are also provided. | 2021-08-19 |
20210257323 | SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP HAVING POINT SYMMETRIC CHIP PADS - A semiconductor package according to an aspect of the present disclosure includes a package substrate and a plurality of semiconductor chips stacked on the package substrate. Each of the semiconductor chips includes a chip body, at least one first side power pad and at least one first side ground pad that are disposed on a first side portion on one surface of the chip body, and at least one second side power pad and at least one second side ground pad that are disposed on a second side portion opposite to the first side portion on one surface of the chip body. One of the second side power pads is disposed point-symmetrically to corresponding one of the first side power pads with respect to a reference point on the one surface, and one of the second side ground pads is disposed point-symmetrically to corresponding one of the first side ground pads with respect to a reference point on the one surface. | 2021-08-19 |
20210257324 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a redistribution layer and a semiconductor chip provided on the redistribution layer having a first surface and a second surface opposite to the first surface. The semiconductor chip includes a first chip pad and a second chip pad which are exposed at the first surface. The semiconductor package further includes a capacitor chip disposed between the first surface and the redistribution layer and including a capacitor chip pad connected to the first chip pad, an insulating layer covering the first surface and the capacitor chip, and a conductive post being in contact with the second chip pad and penetrating the insulating layer so as to be connected to the redistribution layer. The conductive post may be spaced apart from the capacitor chip. | 2021-08-19 |
20210257325 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a chip including a pad; a first insulation pattern on the chip and exposing the pad; a redistribution layer (RDL) on an upper surface of the first insulation pattern and connected to the pad; a second insulation pattern on the upper surface of the first insulation pattern and including an opening exposing a ball land of the RDL and a patterned portion in the opening; an under bump metal (UBM) on upper surfaces of the second insulation pattern and patterned portion and filling the opening, the UBM including a first locking hole exposing an edge of an upper surface of the ball land; and a conductive ball on an upper surface of the UBM and including a first locking portion in the first locking hole. The first locking hole may be about 10% to about 50% of the area of the UBM upper surface. | 2021-08-19 |
20210257326 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a plurality of conductive bumps on the plurality of pads correspondingly; disposing a solder bracing material surrounding the plurality of conductive bumps and over the surface of the substrate after the disposing of the plurality of conductive bumps, wherein the solder bracing material is in contact with a sidewall of each of the plurality of pads and the plurality of conductive bumps; disposing a release film on the solder bracing material and the plurality of conductive bumps; and removing the release film to form a rough surface of the solder bracing material. The rough surface of the solder bracing material includes a plurality of protruded portions and a plurality of recessed portions. | 2021-08-19 |
20210257327 | ELECTRICAL CONNECTION MEMBER, ELECTRICAL CONNECTION STRUCTURE, AND METHOD FOR MANUFACTURING ELECTRICAL CONNECTION MEMBER - An electrical connection member ( | 2021-08-19 |
20210257328 | SEMICONDUCTOR DEVICE, RECEIVER AND TRANSMITTER - A semiconductor device includes a semiconductor chip and a package. The semiconductor chip includes a signal processing circuit, a plurality of pads, and a first resistor which arc formed on a semiconductor substrate. On the semiconductor chip, there is no shot-circuiting between a first pad and a second pad of the plurality of pads. A signal input terminal of the signal processing circuit is connected to the second pad. The first resistor is provided between a reference potential supply terminal for supplying a power supply potential and the first pad. A specific terminal of the plurality of terminals of the package is connected to the first pad by a first bonding wire, and is connected to the second pad by a second bonding wire. | 2021-08-19 |
20210257329 | SEMICONDUCTOR CHIP MOUNTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a mounting device in which two or more semiconductor chips are laminated and mounted at a plurality of locations on a substrate, said mounting device including: a stage that supports the substrate; a bonding part that laminates and mounts the plurality of semiconductor chips on the substrate while heating the plurality of semiconductor chips and the substrate; and a heat insulating member that is interposed between the stage and the substrate, said heat insulating member including a first layer which is in contact with the substrate and to which heat is applied from the bonding part via the semiconductor chips and the substrate, and a second layer which is disposed closer to the stage side than the first layer, wherein the first layer has a larger heat resistance than the second layer. | 2021-08-19 |
20210257330 | ULTRASONIC TRANSDUCER SYSTEMS INCLUDING TUNED RESONATORS, EQUIPMENT INCLUDING SUCH SYSTEMS, AND METHODS OF PROVIDING THE SAME - An ultrasonic transducer system is provided. The ultrasonic transducer system includes: a transducer mounting structure; a transducer, including at least one mounting flange for coupling the transducer to the transducer mounting structure; and a tuned resonator having a desired resonant frequency, the tuned resonator being integrated with at least one of the transducer mounting structure and the at least one mounting flange. | 2021-08-19 |
20210257331 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Present disclosure provides a semiconductor package, including a first substrate having a first active surface and a first trench recessed from the first active surface, a second substrate having a second trench facing the first trench, and a pathway cavity defined by the first trench and the second trench. The first trench comprises a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed. | 2021-08-19 |
20210257332 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate having a plurality of pads on a surface of the substrate, a semiconductor chip that includes a plurality of metal bumps connected to corresponding pads on the substrate, a first resin layer between the surface of the substrate and the semiconductor chip, a second resin layer between the substrate and the semiconductor chip and between the first resin layer and at least one of the metal bumps, and a third resin layer on the substrate and above the semiconductor chip. | 2021-08-19 |
20210257333 | HYBRID WAFER BONDING METHOD AND STRUCTURE THEREOF - A hybrid wafer bonding method includes providing a first semiconductor structure and providing a second semiconductor structure. The first semiconductor structure includes a first substrate, a first dielectric, and a first via structure. The first via structure includes a first contact via and first metal impurities doped in the first contact via. The second semiconductor structure includes a second substrate, a second dielectric layer, and a second via structure. The second via structure includes a second contact via and second metal impurities doped in the second contact via. The method further includes bonding the first semiconductor structure with the second semiconductor and forming a self-barrier layer by an alloying process. The self-barrier layer is formed by a multi-component oxide corresponding to the first and second metal impurities. | 2021-08-19 |
20210257334 | SEMICONDUCTOR PACKAGING METHOD AND SEMICONDUCTOR PACKAGE DEVICE - The present disclosure provides a semiconductor packaging method and a semiconductor package device. The semiconductor packaging method includes providing a chip, where the chip includes a chip substrate having a front surface and a back surface, where the front surface includes a photosensitive region; soldering pads disposed at the front surface of the chip substrate surrounding the photosensitive region; a metal part formed on a side of each soldering pad facing away from the chip substrate; and a transparent protective layer formed on the front surface of the chip substrate, where a first end of the metal part is exposed by protruding over a surface of the transparent protective layer. The method further includes electrically connecting the first end of the metal part to a circuit board using a conductive connection part, such that the chip is electrically connected to the circuit board. | 2021-08-19 |
20210257335 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a semiconductor package. The semiconductor package includes a first die, a second die, a plurality of conductive plugs and a redistribution layer. The redistribution layer includes a first segment and a second segment electrically isolated from the first segment. The first segment of the redistribution layer electrically connects the first die to the second die, and the second segment of the redistribution layer electrically connects the first die to the conductive plugs. | 2021-08-19 |
20210257336 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the at least one side surface. The first adhesive layer and the first resin layer contact each other. | 2021-08-19 |
20210257337 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure. | 2021-08-19 |
20210257338 | CHANNEL ROUTING FOR MEMORY DEVICES - Systems and devices for routing signals between a memory device and an interface of a host device are described. Some memory technologies may have a defined, preconfigured interface (e.g., bumpout), where each interface terminal may have a specific location and a specific function. Using preconfigured interfaces may allow device maker and memory makers to make parts that are able to connect with one another without special designs. In some cases, a memory device may include a redistribution layer that includes a plurality of interconnects that may be configured couple channel terminals of the memory device with an interface associated with the host device. | 2021-08-19 |