33rd week of 2021 patent applcation highlights part 64 |
Patent application number | Title | Published |
20210257439 | METAL LAYER ON DISPLAY PANEL, AND DISPLAY PANEL - A metal layer and a display panel are provided. The metal layer includes a first frame strip, a second frame strip, and a wiring portion between the first and second frame strips. An input portion is disposed on the first frame strip. The wiring portion includes a first wiring group, a second wiring group, and a third wiring group. The second frame strip includes a first, a second and a third connecting portion. The first wiring group is connected between the first frame strip and the first connecting portion, the second wiring group is connected between the first frame strip and the second connecting portion, and the third wiring group is connected between the first frame strip and the third connecting portion. The first connecting portion is connected to the third connecting portion, and the second connecting portion is spaced apart from the first and third connecting portions. | 2021-08-19 |
20210257440 | ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE - The disclosure discloses an array substrate, a display panel, and a display device. A first power signal line is configured to be formed by electrically connecting a first signal line located in a first source-drain metal layer and a second signal line located in a second source-drain metal layer through a via hole, which is equivalent to that the first power signal line is composed of the first signal line and the second signal line connected in parallel, and the equivalent resistance of the parallel-connected first signal line and second signal line included in the first power signal line is smaller than the resistance of any of the signal lines. Thus, the resistance of the first power signal line may be effectively reduced, so that an IR drop of a display panel with an array substrate may be reduced, and the display uniformity of the display panel is improved. | 2021-08-19 |
20210257441 | DISPLAY APPARATUS - A display apparatus including a substrate, a first power source line disposed in a peripheral area adjacent to a display area, the first power source line including a first layer and a second layer electrically connected to each other, a first gate pattern disposed between the first layer of the substrate and including a first gate fan-out line in the peripheral area and a first gate connecting line connected to the first gate fan-out line and extending between the first gate fan-out line and the display area, a first insulation layer disposed between the first layer and the second layer of the first power source line, a second insulation layer disposed between the first insulation layer and the second layer, and a first insulating dam disposed on and contacting the second layer, the first insulating dam disposed in the peripheral area and surrounding the display area. | 2021-08-19 |
20210257442 | Defining Solution, Display Panel, Display Apparatus, and Method of Preparing Pixel Defining Layer - The present disclosure provides a defining solution for preparing a pixel defining layer configured to define individual pixels on a substrate, comprising: a lyophilic material, a lyophobic material and an initiator, wherein the lyophobic material comprises: a first lyophobic material and a second lyophobic material, and wherein a mass average molecular weight of the first lyophobic material is greater than a mass average molecular weight of the second lyophobic material, and a mass average molecular weight of the lyophilic material is greater than the mass average molecular weight of the first lyophobic material. The present disclosure further provides a display panel, a display apparatus and a method of preparing a pixel defining layer. | 2021-08-19 |
20210257443 | SEMICONDUCTOR DEVICE - A resistance element includes a conductor, the conductor having a repeating pattern of: a first conductive layer formed on a first interlayer insulating layer on a semiconductor substrate; a second conductive layer formed on a second interlayer insulating layer different from the first interlayer insulating layer; and an interlayer conductive layer connecting the first conductive layer and the second conductive layer, and the second conductive layer has a resistance-value fluctuation characteristic opposite to a resistance-value fluctuation characteristic of the first conductive layer after a heat treatment. | 2021-08-19 |
20210257444 | CAPACITOR STRUCTURE WITH LOW CAPACITANCE - Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger. | 2021-08-19 |
20210257445 | CAPACITIVE DEVICE - A capacitive device including a metallic layer; a network of nanotube or nanowire bundles that extend from a face of the metallic layer; a capacitive stack covering the metallic layer and the nanotube bundles in a conforming manner, the stack including an upper conducting layer and an insulating layer, the device including a capacitive zone and a lower contact zone, the capacitive zone being a zone wherein the upper conducting layer encapsulates the nanotube bundles and the insulating layer, while the lower contact zone is a zone wherein the capacitive stack leaves the free ends exposed, and the insulating layer encapsulates the upper conducting layer. | 2021-08-19 |
20210257446 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - According to a certain embodiment, the semiconductor device includes: a semiconductor region having a first conductivity type including a first surface; an insulating portion formed on the semiconductor region, and having a second surface moved backward in the depth direction of the semiconductor region more than the first surface; a first region disposed on the semiconductor region between a first portion and second portions of the insulating portion; a second region disposed on the semiconductor region between the first and second portions to be separated from the first region; a control electrode disposed above the first surface to be located between the first and second regions; a first electrode disposed on the first region so as to be contacted with the first region; and a first insulating film containing hafnium disposed on a side wall of the semiconductor region at a stepped portion between the first and second surfaces. | 2021-08-19 |
20210257447 | DESIGN AND MANUFACTURE OF ROBUST, HIGH-PERFORMANCE DEVICES - An embodiment relates to a device comprising SiC, the device having a p-shield region that is outside a junction gate field-effect transistor region, wherein a doping concentration in a p-well region within a MOSFET channel is non-uniform. Another embodiment relates to a device comprising SiC, the device having a p-shield region, wherein a doping concentration in a p-well region within a MOSFET channel is non-uniform, wherein at least a portion of the p-shield region is located within the p-well region. | 2021-08-19 |
20210257448 | PARTIAL DISCHARGE SUPPRESSION IN HIGH VOLTAGE SOLID-STATE DEVICES - Devices, methods and techniques are disclosed to suppress electrical discharge and breakdown in insulating or encapsulation material(s) applied to solid-state devices. In one example aspect, a multi-layer encapsulation film includes a first layer of a first dielectric material and a second layer of a second dielectric material. An interface between the first layer and the second layer is configured to include molecular bonds to prevent charge carriers from crossing between the first layer and the second layer. The multi-layer encapsulation configuration is structured to allow an electrical contact and a substrate of the solid-state device to be at least partially surrounded by the multi-layer encapsulation configuration. | 2021-08-19 |
20210257449 | SEMICONDUCTOR DEVICE INCLUDING GUARD RINGS - A semiconductor device includes a substrate; a guard ring disposed on the substrate and adjacent to an edge of the substrate; an integrated circuit structure surrounded by the guard ring and disposed on the substrate; and an insulating material structure disposed on a side surface of the guard ring, and wherein the guard ring includes a plurality of guard active structures on the substrate, a plurality of guard contact structures disposed on each of the plurality of guard active structures, and a guard interconnection structure disposed on a pair of guard contact structures adjacent to each other, among the plurality of guard contact structures, wherein each of the plurality of guard active structures includes a plurality of guard active fins spaced apart from each other. | 2021-08-19 |
20210257450 | CREATION OF STRESS IN THE CHANNEL OF A NANOSHEET TRANSISTOR - Provided are embodiments for a semiconductor device. The semiconductor device includes a nanosheet stack comprising one or more layers, wherein the one or more layers are induced with strain from a modified sacrificial gate. The semiconductor device also includes one or more merged S/D regions formed on exposed portions of the nanosheet stack, wherein the one or more merged S/D regions fix the strain of the one or more layers, and a conductive gate formed over the nanosheet stack, wherein the conductive gate replaces a modified sacrificial gate without impacting the strain induced in the one or more layers. Also provided are embodiments for a method for creating stress in the channel of a nanosheet transistor. | 2021-08-19 |
20210257451 | VERTICAL 2D STRUCTURES FOR ADVANCED ELECTRONIC AND OPTOELECTRONIC SYSTEMS - The present invention relates to methods for fabricating vertical homogenous and heterogeneous two-dimensional structures, the fabricated vertical two-dimensional structures, and methods of using the same. The methods demonstrated herein produce structures that are free standing and electrically isolated. | 2021-08-19 |
20210257452 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES - Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons. | 2021-08-19 |
20210257453 | GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES - Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons. | 2021-08-19 |
20210257454 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH ONE OR MORE SEALED AIRGAP - The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having one or more sealed airgap and methods of manufacture. The structure includes: a subcollector region in a substrate; a collector region above the substrate; a sealed airgap formed at least partly in the collector region; a base region adjacent to the collector region; and an emitter region adjacent to the base region. | 2021-08-19 |
20210257455 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer. | 2021-08-19 |
20210257456 | Reduced Local Threshold Voltage Variation MOSFET Using Multiple Layers of Epi for Improved Device Operation - A device structure with multiple layers of low temperature epitaxy is disclosed that eliminates source and drain and extension implants, providing a planar interface with abrupt junctions between epitaxial extensions and substrate, mitigating electrostatic coupling between transistor drain and transistor channel and reducing short channel effects. The reduction of channel doping results in improved device performance from reduced impurity scattering and reduction of random dopant induced threshold voltage variations (sigma-Vt). Avoiding implants further reduces device sigma-Vt due to random dopants' diffusion from source and drain extensions, which creates device channel length variations during thermal activation anneal of implanted dopants. The defined transistor structure employs at least two levels of low-temperature epitaxy, and creates a planar interface with various types of transistor substrates resulting in performance improvement. Mixed epitaxial layer growth materials inducing tensile or compressive gate stresses can be advantageously used with the invention to further improve device characteristics. | 2021-08-19 |
20210257457 | NANOWIRE TRANSISTOR FABRICATION WITH HARDMASK LAYERS - A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor. | 2021-08-19 |
20210257458 | SWITCH BODY CONNECTIONS TO ACHIEVE SOFT BREAKDOWN - Devices and methods for switch body connections to achieve soft breakdown. In some embodiments, a field-effect transistor (FET) can include an assembly of source, gate, and drain implemented on an active region, a first body contact implemented at a first end of the assembly, and a second body contact implemented at a second end of the assembly. The second end can be distal from the first end along a width of the field-effect transistor. | 2021-08-19 |
20210257459 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. | 2021-08-19 |
20210257460 | TRENCH PLANAR MOS CELL FOR TRANSISTORS - A power transistor layout structure is described that includes a planar cell with a planar gate electrode forming an horizontal MOS channel, and a plurality of trench recesses with gate electrodes, which are arranged at various angles to the longitudinal direction of the planar cells. This cell concept can adopt both planar MOS channels, and Trench MOS channels in a single MOS cell structure. As an alternative, the planar cell gate electrode may be grounded. The device is easy to manufacture based on a self-aligned process with minimum number of masks, with the potential of applying additional layers. | 2021-08-19 |
20210257461 | METHOD FOR FORMING SUPER-JUNCTION CORNER AND TERMINATION STRUCTURE WITH GRADED SIDEWALLS - A method for forming a superjunction power semiconductor device includes forming multiple epitaxial layers of a first conductivity type on a semiconductor substrate and implanting dopants of a second conductivity type into each epitaxial layer to form a first group of implanted regions in a first region and a second group of implanted regions in a second region in each epitaxial layer. The multiple epitaxial layers are annealed to form multiple columns of the second conductivity type having slanted sidewalls across the first to last epitaxial layers. The columns include a first group of columns formed by the implanted regions of the first group and having a first grading and a second group of columns formed by the implanted regions of the second group and having a second grading, where the second grading is less than the first grading. | 2021-08-19 |
20210257462 | Silicon-Germanium Fins and Methods of Processing the Same in Field-Effect Transistors - A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance. | 2021-08-19 |
20210257463 | FIELD ASSISTED INTERFACIAL DIFFUSION DOPING THROUGH HETEROSTRUCTURE DESIGN - An apparatus includes a heterostructure including a substrate of Group-III-nitride material, a source layer including a dopant positioned on a surface of the substrate, and a conductive cap layer positioned on the source layer. A method of electric field-enhanced impurity diffusion includes obtaining a heterostructure including a substrate of Group-III-nitride semiconductor material, a source layer including a dopant positioned directly on the substrate, and a conductive cap layer positioned above the source layer, and applying a thermal annealing treatment to the heterostructure. An electric field gradient is established within the source layer and the cap layer for causing diffusion of an element from the substrate to the cap layer, and for causing diffusion of the dopant from the source layer to a former location of the element in the substrate thereby changing a conductivity and/or magnetic characteristic of the substrate. | 2021-08-19 |
20210257464 | GALLIUM-NITRIDE-BASED MODULE WITH ENHANCED ELECTRICAL PERFORMANCE AND PROCESS FOR MAKING THE SAME - The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening. | 2021-08-19 |
20210257465 | OXIDE SEMICONDUCTOR THIN FILM, THIN FILM TRANSISTOR, METHOD PRODUCING THE SAME, AND SPUTTERING TARGET - [Solving Means] An oxide semiconductor thin film according to an embodiment of the present invention includes: an oxide semiconductor that mainly contains In, Sn, and Ge. An atom ratio of Ge/(In+Sn+Ge) is 0.07 or more and 0.40 or less. As a result, it is possible to achieve transistor characteristics with a mobility of 10 cm | 2021-08-19 |
20210257466 | SEMICONDUCTOR DEVICE - A semiconductor device includes a compound semiconductor layer disposed on a substrate, a protection layer disposed on the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode penetrating the protection layer and on the compound semiconductor layer, wherein the gate electrode is disposed between the source electrode and the drain electrode. The semiconductor device also includes a plurality of field plates disposed over the protection layer and between the gate electrode and the drain electrode, wherein the plurality of field plates are separated from each other. | 2021-08-19 |
20210257467 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure is provided. The semiconductor structure includes a substrate, a buffer layer, a barrier layer, a dielectric layer, a source structure, and a drain structure. The buffer layer is disposed on the substrate. The barrier layer is disposed on the buffer layer. The dielectric layer is disposed on the barrier layer. The passivation layer is disposed on the dielectric layer. The source structure and the drain structure are disposed on the passivation layer. | 2021-08-19 |
20210257468 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first nitride semiconductor layer; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a bandgap larger than a bandgap of the first nitride semiconductor layer; a nitride insulating layer provided between the first nitride semiconductor layer and the second nitride semiconductor layer; a plurality of first drain electrodes each having a part provided on the nitride insulating layer and a part provided beneath the nitride insulating layer; a plurality of second drain electrodes each having a part provided on the nitride insulating layer and a part provided beneath the nitride insulating layer; a plurality of third drain electrodes each having a part provided on the nitride insulating layer and a part provided beneath the nitride insulating layer; a plurality of fourth drain electrodes each having a part provided on the nitride insulating layer and a part provided beneath the nitride insulating layer; a plurality of first source electrodes provided between the first drain electrodes and the third drain electrodes, the first source electrodes each having a part provided on the nitride insulating layer and a part provided beneath the nitride insulating layer; and a plurality of second source electrodes provided between the first drain electrodes and the third drain electrodes, the second source electrodes each having a part provided on the nitride insulating layer and a part provided beneath the nitride insulating layer. The first drain electrodes are separated from each other by a first distance in a first direction parallel to an interface between the first nitride semiconductor layer and the nitride insulating layer. The second drain electrodes are separated from each other by a second distance in the first direction and positioned from the first drain electrodes by a third distance in the first direction and positioned from the first drain electrodes by a fourth distance in a second direction intersecting with the first direction and parallel to the interface and electrically connected to the first drain electrodes. The third drain electrodes are separated from each other by a fifth distance in the first direction and separated from the first drain electrodes and the second drain electrodes in the second direction. The fourth drain electrodes are separated from each other by a sixth distance in the first direction and positioned from the third drain electrodes by a seventh distance in the first direction and positioned from the third drain electrodes by an eighth distance in the second direction and separated from the first drain electrodes and the second drain electrodes and electrically connected to the third drain electrodes. The first source electrodes are separated from each other by a ninth distance in the first direction. The second source electrodes are separated from each other by a tenth distance in the first direction and positioned from the first source electrodes by an eleventh distance in the first direction and positioned from the first source electrodes by a twelfth distance in the second direction and electrically connected to the first source electrodes. | 2021-08-19 |
20210257469 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes first, second and third conductive parts, a first semiconductor region, and a first insulating part. A direction from the first conductive part toward the second conductive part is along a first direction. The first semiconductor region includes first, second, and third partial regions. A second direction from the first partial region toward the second partial region crosses the first direction. The third partial region is between the first partial region and the second conductive part in the first direction. The third partial region includes an opposing surface facing the second conductive part. A direction from the opposing surface toward the third conductive part is along the second direction. The first insulating part includes a first insulating region. At least a portion of the first insulating region is between the opposing surface and the third conductive part. | 2021-08-19 |
20210257470 | SEMICONDUCTOR DEVICE - A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer. | 2021-08-19 |
20210257471 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE - A first gate and a second gate are formed on a substrate with a gap between the first and second gates. The first gate has a first sidewall. The second gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap. | 2021-08-19 |
20210257472 | SEMICONDUCTOR DEVICE AND ELECTRONIC CIRCUIT - The wiring length of MOS transistors is shortened. A source region has both ends made smaller in width than a central part. A first channel region and a second channel region are adjacent to corresponding outer peripheral parts. A first drain region and a second drain region are adjacent to the first channel region and the second channel region, respectively. Gate electrodes are on respective surfaces of the first channel region and the second channel region through an insulating film, joined to each other, and connected to a gate wire. Drain electrodes are placed on the respective surfaces of the first drain region and the second drain region and joined to each other near a second end and connected to a drain wire. At least one of the gate wire or the drain wire is smaller in width than the central part of the source region. | 2021-08-19 |
20210257473 | SEMICONDUCTOR DEVICE - Plural gate trenches are formed on an upper surface side of a semiconductor substrate of a first conductivity type. Gate electrodes are embedded in the plural gate trenches. Plural dummy gate trenches are formed at equivalent intervals between the neighboring gate trenches on the upper surface side of the semiconductor substrate. Dummy gate electrodes are embedded in the plural dummy gate trenches and connected with an emitter electrode. An interval between the gate trench and the dummy gate trench that neighbor each other is shorter than an interval between the neighboring dummy gate trenches. | 2021-08-19 |
20210257474 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate, a gate structure on the substrate, and a gate contact in the gate structure. The gate structure includes a gate electrode extending in a first direction and a gate capping pattern on the gate electrode. The gate contact is connected to the gate electrode. The gate electrode includes a protrusion extending along a boundary between the gate contact and the gate capping pattern. | 2021-08-19 |
20210257475 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a barrier layer disposed above the substrate, and a dielectric layer disposed on the barrier layer and defining a first recess. The semiconductor device further includes a spacer disposed within the first recess and a gate disposed between a first portion of the spacer and a second portion of the spacer, wherein the gate defining a first recess. | 2021-08-19 |
20210257476 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a substrate, a gate structure on the substrate, and a source structure and a drain structure on opposite sides of the gate structure. The gate structure includes a gate electrode on the substrate and a gate metal layer on the gate electrode. The gate metal layer has at least one notch, which exposes the gate electrode below. The electric potential of the source structure is different from that of the gate structure. | 2021-08-19 |
20210257477 | HIGH VOLTAGE SEMICONDUCTOR DEVICE INCLUDING A DOPED GATE ELECTRODE - A high voltage semiconductor device includes a semiconductor region of a first conductivity type having a first region and a second region, a first insulation pattern disposed over the first region of the semiconductor region to have a first thickness, a second insulation pattern disposed over the second region of the semiconductor region to have a second thickness greater than the first thickness, and a gate electrode disposed over the first and second insulation patterns to have a step structure over a boundary region between the first and second regions. The gate electrode has a doping profile that a position of a maximum projection range of impurity ions distributed in the gate electrode over the first region is located at substantially the same level as a position of a maximum projection range of impurity ions distributed in the gate electrode over the second region. | 2021-08-19 |
20210257478 | Reducing Pattern Loading in the Etch-Back of Metal Gate - A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode. | 2021-08-19 |
20210257479 | FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD - A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess. | 2021-08-19 |
20210257480 | Multi-Gate Device and Method of Fabrication Thereof - A method includes forming a semiconductor fin extruding from a substrate; forming a sacrificial capping layer on sidewalls of the semiconductor fin; forming first and second dielectric fins sandwiching the semiconductor fin; forming a sacrificial gate stack over the semiconductor fin, the sacrificial capping layer, and the first and second dielectric fins; forming gate spacers on sidewalls of the sacrificial gate stack; removing the sacrificial gate stack to form a gate trench, wherein the gate trench exposes the semiconductor fin, the sacrificial capping layer, and the first and second dielectric fins; removing the sacrificial capping layer from the gate trench, thereby exposing the sidewalls of the semiconductor fin; and forming a metal gate stack in the gate trench engaging the semiconductor fin. | 2021-08-19 |
20210257481 | Metal Gate Structures And Methods Of Fabricating The Same In Field-Effect Transistors - A method includes forming a dummy gate stack over a fin protruding from a semiconductor substrate, forming gate spacers on sidewalls of the dummy gate stack, forming source/features over portions of the fin, forming a gate trench between the gate spacers, which includes trimming top portions of the gate spacers to form a funnel-like opening in the gate trench, and forming a metal gate structure in the gate trench. A semiconductor structure includes a fin protruding from a substrate, a metal gate structure disposed over the fin, gate spacers disposed on sidewalls of the metal gate structure, where a top surface of each gate spacer is angled toward the semiconductor fin, a dielectric layer disposed over the top surface of each gate spacer, and a conductive feature disposed between the gate spacers to contact the metal gate structure, where sidewalls of the conductive feature contact the dielectric layer. | 2021-08-19 |
20210257482 | EPITAXIAL FEATURES OF SEMICONDUCTOR DEVICES AND RELATED METHODS - A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure. | 2021-08-19 |
20210257483 | Parasitic Capacitance Reduction - The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottommost surface of the gate structure is closer to the substrate than a bottommost surface of the source/drain contact. | 2021-08-19 |
20210257484 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion. | 2021-08-19 |
20210257485 | Gate-turn-off thyristor and manufacturing method thereof - A gate-turn-off thyristor is provided. The gate-turn-off thyristor includes a plurality of strips formed by repeatedly arranging a plurality of N-type emitter regions with high doping concentration of an upper transistor on an upper surface of an N-type silicon substrate with high resistivity, wherein a periphery of each strip of the plurality of strips is surrounded with a P-type dense base region bus bar of the upper transistor, a cathode metal layer is disposed on an N-type emitter region of the plurality of N-type emitter regions of the upper transistor, and a P-type base region of the upper transistor is disposed below the N-type emitter region of the upper transistor; a side of the P-type base region of the upper transistor is connected to a P-type dense base region of the upper transistor or a P-type dense base region bus bar of the upper transistor. | 2021-08-19 |
20210257486 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a channel layer disposed on the substrate, and a barrier layer disposed on the channel layer. The semiconductor device further includes a dielectric layer disposed on the barrier layer and defining a first recess exposing a portion of the barrier layer. The semiconductor device further includes a first spacer disposed within the first recess, wherein the first spacer comprises a surface laterally connecting the dielectric layer to the barrier layer. | 2021-08-19 |
20210257487 | Epi Block Structure In Semiconductor Product Providing High Breakdown Voltage - The present disclosure is generally directed to semiconductor structures and methods that improve breakdown characteristics in finFET device designs, while retaining cost effectiveness for integration into the process flow. The semiconductor structure includes an extended lightly-doped-drain (LDD) region formed on a source/drain structure. The extended LDD regions provide extra separation between source and drain regions, which in turn provides for an increased source to drain resistance. The increased source to drain resistance improves the breakdown voltage of the semiconductor device, and significantly reduces its susceptibility to latch-up. The source to drain resistance may be tuned by adjusting the length of epi block regions, and may also be tuned by selecting desired doping profiles for the LDD and source/drain regions. The length of epi block regions may also be adjusted to maintain high uniformity of epitaxial growth in the S/D regions. | 2021-08-19 |
20210257488 | EEPROM DEVICE WITH BOTTOM GATE STRUCTURE - Certain aspects of the present disclosure generally relate to electrically erasable programmable read-only memory (EEPROM) device comprising at least one EEPROM cell structure. The EEPROM device generally includes a first active region, a second active region, a channel region disposed between the first active region and the second active region, a floating gate structure disposed above the channel region and separated from the channel region by a first dielectric layer, a control gate structure disposed above the floating gate structure and separated from the floating gate structure by a second dielectric layer, and a bottom gate structure disposed below the channel region. | 2021-08-19 |
20210257489 | Semiconductor Component with Edge Termination Region - A semiconductor component includes a semiconductor body having opposing first surface and second surfaces, and a side surface surrounding the semiconductor body. The semiconductor component also includes an active region including a first semiconductor region of a first conductivity type, which is electrically contacted via the first surface, and a second semiconductor region of a second conductivity type, which is electrically contacted via the second surface. The semiconductor component further includes an edge termination region arranged in a lateral direction between the first semiconductor region of the active region and the side surface, and includes a first edge termination structure and a second edge termination structure. The second edge termination structure is arranged in the lateral direction between the first edge termination structure and the side surface and extends from the first surface in a vertical direction more deeply into the semiconductor body than the first edge termination structure. | 2021-08-19 |
20210257490 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device can include: a substrate having a first doping type; a first well region located in the substrate and having a second doping type, where the first well region is located at opposite sides of a first region of the substrate; a source region and a drain region located in the first region, where the source region has the second doping type, and the drain region has the second doping type; and a buried layer having the second doping type located in the substrate and below the first region, where the buried layer is incontact with the first well region, where the first region is surrounded by the buried layer and the first well region, and the first doping type is opposite to the second doping type. | 2021-08-19 |
20210257491 | MULTI-GATE SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A multi-gate semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate having an active area and an isolation structure adjacent to the active area. The semiconductor structure includes a gate structure formed on the substrate and a gate dielectric layer between the gate structure and the substrate. The gate structure includes a first part above the top surface of the substrate and a second part connected to the first part. The second part of the gate structure is formed in the isolation structure, wherein the isolation structure is in direct contact with the bottom surface and sidewalls of the second part of the gate structure. A method of manufacturing the semiconductor structure includes partially etching the isolation structure to form a trench exposing the top portion of sidewalls of the substrate. The gate dielectric layer and the gate structure extend into the trench. | 2021-08-19 |
20210257492 | MULTIPLE STRAIN STATES IN EPITAXIAL TRANSISTOR CHANNEL THROUGH THE INCORPORATION OF STRESS-RELIEF DEFECTS WITHIN AN UNDERLYING SEED MATERIAL - Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired. | 2021-08-19 |
20210257493 | SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURES AND MANUFACTURING METHOD THEREOF - A semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first to a third stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode. | 2021-08-19 |
20210257494 | Structure and Manufacturing Method of Field-Effect Transistor with Low Gate Resistance - A field-effect transistor structure includes a semiconductor substrate, a metal gate, a metal trench for source, a metal trench for drain, an etching-stop layer, and a gate contact, the etching-stop layer is overlaid on the metal trench for source and the metal trench for drain. The gate contact is above an active region. | 2021-08-19 |
20210257495 | NON-VOLATILE MEMORY DEVICE WITH REDUCED AREA - A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, and a first gate electrode and a second gate electrode over the substrate and extending in a second direction. The semiconductor fin extends through the second gate electrode and terminates on the first gate electrode at one end. The memory device further includes a first conductive via over and electrically coupled to the first gate electrode. The one end of the semiconductor fin is surrounded by the first gate electrode. | 2021-08-19 |
20210257496 | Semiconductor Device and Methods of Forming Same - A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus. | 2021-08-19 |
20210257497 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, at least one semiconductor fin and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The semiconductor fin includes a first portion, a second portion and a first neck portion between the first portion and the second portion. A width of the first portion decreases as the first portion becomes closer to the first neck portion, and a width of the second portion increases as the second portion becomes closer to a bottom surface of the semiconductor substrate. The gate stack partially covers the semiconductor fin. | 2021-08-19 |
20210257498 | SEMICONDUCTOR DEVICE - A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion. | 2021-08-19 |
20210257499 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are stacked in a vertical direction. Each channel extends in a first direction. The gate structure extends in a second direction. The gate structure covers the channels. The source/drain layer is connected to each of opposite sidewalls in the first direction of the channels on the substrate, and includes a doped semiconductor material. The source/drain layer includes first and second epitaxial layers having first and second impurity concentrations, respectively. The first epitaxial layer covers a lower surface and opposite sidewalls in the first direction of the second epitaxial layer. A portion of each of opposite sidewalls in the first direction of the gate structure protrudes in the first direction from opposite sidewalls in the first direction of the channels to partially penetrate through the first epitaxial layer but not to contact the second epitaxial layer. | 2021-08-19 |
20210257500 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a stacked film including electrode layers and insulating layers that are alternately stacked in a first direction. The device further includes a first insulator, a charge storage layer, a second insulator and a semiconductor layer that are provided in the stacked film. The device further includes a third insulator provided between an electrode layer and an insulating layer and between the electrode layer and the first insulator, and including aluminum oxide having an α crystal phase. | 2021-08-19 |
20210257501 | THIN-FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A body layer formed of a semiconductor layer, the body layer comprising, a first region, a second region, and a channel region positioned therebetween; a channel stopper formed on the channel region; source and drain electrodes electrically connected to the first and second regions via first and second contact layers respectively are provided. Each of the first and second contact layers comprises an impurities-containing first amorphous silicon layer; a thickness of each of the first and second regions is less than a thickness of the channel region; and the first and second regions comprise a second amorphous silicon layer containing impurities in a concentration being less than a concentration of impurities contained in the first amorphous silicon layer. This makes it possible to suppress a photoexcited current and improve the aperture ratio in a case that a display apparatus is configured. | 2021-08-19 |
20210257502 | INTEGRATED CAPACITOR AND METHOD OF PRODUCING AN INTEGRATED CAPACITOR - Integrated capacitor including a first electrode structure, a second electrode structure, and an interposed dielectric layer structure. The dielectric layer structure includes a layer combination having an SiO | 2021-08-19 |
20210257503 | GRAPHIC APPEARANCE FOR SOLAR MODULES - Methods of producing a graphic mesh for a solar module are described in which mesh parameters such as warp fiber thickness, weft fiber thickness, and open area size are determined to meet a target energetic efficiency and a chromatic effectiveness. In some embodiments, chromatic effectiveness is based on mesh count, where the mesh count is set according to a distance at which the mesh will be viewed when assembled into the solar module. The mesh has a plurality of warp fibers having the warp fiber thickness and a plurality of weft fibers having the weft fiber thickness, that are interlaced to form a plurality of mesh unit cells. A graphic appearance is printed into the mesh using a coloring substance, where the coloring substance is absorbed by the fiber material to form the graphic mesh. | 2021-08-19 |
20210257504 | ANTI-REFLECTIVE ARTICLES WITH NANOSILICA-BASED COATINGS - Article comprising a transparent substrate having an anti-reflective, structured surface and a coating comprising a porous network of silica nanoparticles thereon, wherein the silica nanoparticles are bonded to adjacent silica nanoparticles. | 2021-08-19 |
20210257505 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A solar cell, comprising: a silicon substrate, wherein the silicon substrate has a front side and a rear side; a finger electrode formed on the front side of the silicon substrate, wherein the finger electrode is in electric contact with the silicon substrate, wherein the finger electrode comprises a silver component and a glass binder, and wherein the finger electrode is substantively free of other conductive metals than the silver component; and a busbar electrode formed on the front side of the silicon substrate, wherein the busbar electrode is in electric contact with the finger electrode and wherein the busbar electrode comprises a silver component, a second metal selected from the group consisting of nickel, copper, alloy thereof and mixture thereof and a glass binder. | 2021-08-19 |
20210257506 | SOLAR CELL STRING, STRING GROUP, MODULE, AND MANUFACTURING METHOD THEREOF - Disclosed is a solar cell string, a string group, a module, and a manufacturing method thereof. The solar cell string is formed by connecting a plurality of first type of solar cells and at least one second type of solar cell, wherein front electrodes of the plurality of first type of solar cells ( | 2021-08-19 |
20210257507 | VERTICAL PHOTODIODE - A vertical photodiode includes an active area. The contacting pads for the diode terminals are laterally shifted away from the active area so as to not be located above or below the active area. The active area is formed in a layer of semiconductor material by a lower portion of a germanium area that is intrinsic and an upper portion of the germanium area that is doped with a first conductivity type. The vertical photodiode is optically coupled to a waveguide formed in the layer of semiconductor material. | 2021-08-19 |
20210257508 | Photon Avalanche Diode and Methods of Producing Thereof - A photon avalanche diode includes a semiconductor body having a first side and a second side opposite the first side, a primary doped region of a first conductivity type at the first side of the semiconductor body, a primary doped region of a second conductivity type opposite the first conductivity type at the second side of the semiconductor body, an enhancement region of the second conductivity type below and adjoining the primary doped region of the first conductivity type, the enhancement region forming an active pn-junction with the primary doped region of the first conductivity type, and a collection region of the first conductivity type interposed between the enhancement region and the primary doped region of the second conductivity type and configured to transport a photocarrier generated in the collection region or the primary doped region of the second conductivity type towards the enhancement region. | 2021-08-19 |
20210257509 | SUBSTRATE PROCESSING APPARATUS INCLUDING LIGHT RECEIVING DEVICE AND CALIBRATION METHOD OF LIGHT RECEIVING DEVICE - Examples of a substrate processing apparatus includes a chamber configured to contain a stage, a light receiving device configured to receive light inside the chamber, and a substrate transfer apparatus that includes a shaft and a rotation arm configured to rotate with rotation of the shaft and is configured to supply a plurality of light beams having different amounts of light to the light receiving device. | 2021-08-19 |
20210257510 | LIGHT EMITTING DIODE CONTAINING PINHOLE MASKING LAYER AND METHOD OF MAKING THEREOF - A structure includes a first material layer, a second material layer, and a dielectric masking layer having a thickness of 20 nm or less and containing pinholes having a width of 200 nm or less filled with the second material of second material layer located between the first material layer and the second material layer. A method of forming a LED includes forming a buffer layer over a support substrate, forming a dielectric masking layer having a thickness of 20 nm or less and containing pinholes having a width of 200 nm or less on the semiconductor buffer layer, forming a n-doped semiconductor material layer on the dielectric masking layer such that the n-doped semiconductor material of the n-doped semiconductor layer fills the pinholes and contacts the buffer layer, forming an active region over the n-doped semiconductor material layer, and forming a p-doped semiconductor material layer over the active region. | 2021-08-19 |
20210257511 | HIGH EFFICIENCY VISIBLE AND ULTRAVIOLET NANOWIRE EMITTERS - GaN-based nanowire heterostructures have been intensively studied for applications in light emitting diodes (LEDs), lasers, solar cells and solar fuel devices. Surface charge properties play a dominant role on the device performance and have been addressed within the prior art by use of a relatively thick large bandgap AlGaN shell covering the surfaces of axial InGaN nanowire LED heterostructures has been explored and shown substantial promise in reducing surface recombination leading to improved carrier injection efficiency and output power. However, these lead to increased complexity in device design, growth and fabrication processes thereby reducing yield/performance and increasing costs for devices. Accordingly, there are taught self-organising InGaN/AlGaN core-shell quaternary nanowire heterostructures wherein the In-rich core and Al-rich shell spontaneously form during the growth process. | 2021-08-19 |
20210257512 | METHOD FOR MANUFACTURING AN OPTOELECTRONIC DEVICE WITH SELF-ALIGNING LIGHT CONFINEMENT WALLS - The manufacture of an optoelectronic device includes the formation of light-emitting diodes where each one has a wire form, the formation of spacing walls made of a first dielectric material transparent to the light radiation originating from the diodes. The lateral sidewalls of each diode are surrounded by spacing walls. Light confinement walls are made of a second material adapted to block the light radiation originating from the diodes. The light confinement walls directly cover the lateral sidewalls of the spacing walls by being in contact with the wherein. A thin layer of the second material is deposited so as to directly cover the lateral sidewalls of the spacing walls by being in contact with the wherein and cover the upper border of the light-emitting diodes. The empty spaces delimited between the spacing walls at the level of the areas between the light-emitting diodes are also filled by the thin layer. | 2021-08-19 |
20210257513 | LIGHT-EMITTING DEVICE - A light-emitting device includes a light-emitting element which emits ultraviolet light, and a fluorescent layer provided on the light-emitting element. The fluorescent layer includes fluorescent particles. The fluorescent particles are excited by the ultraviolet light emitted by the light-emitting element and the excited fluorescent particles emit ultraviolet light of a wavelength longer than the ultraviolet light emitted by the light-emitting element. | 2021-08-19 |
20210257514 | OPTOELECTRONIC DEVICE COMPRISING LIGHT-EMITTING DIODES - An optoelectronic device including a substrate having opposite first and second surfaces; insulation trenches extending through the substrate, surrounding portions of the substrate and electrically insulating the portions from each other, each insulation trench being filled with at least one electrically insulating block and a gaseous volume or being filled with an electrically conductive element electrically isolated from the substrate; at least one light-emitting diode resting on the first surface for each portion of the substrate, the light-emitting diodes comprising wired, conical, or frustoconical semiconductor elements; an electrode layer covering at least one of the light-emitting diodes and a conductive layer overlying the electrode layer around the light-emitting diodes; and a layer encapsulating the light-emitting diodes and covering the entire first surface. | 2021-08-19 |
20210257515 | SEMICONDUCTOR GROWTH SUBSTRATE, SEMICONDUCTOR ELEMENT, SEMICONDUCTOR LIGHT EMITTING ELEMENT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT - A semiconductor growth substrate includes: an r-plane of a sapphire as a main plane; and a plurality of convex shapes formed on the main plane, in which the convex shapes have a length of 2000 nm or less in a predetermined first direction among in-plane directions of the main plane, and heights of the convex shapes adjacent to each other are different. | 2021-08-19 |
20210257516 | DISPLAY PANEL AND METHOD FOR MANUFACTURING SAME - Disclosed is a display panel. The display panel comprises: a light-emitting device; a first protection layer disposed on the light-emitting device and having an anti-glare-treated surface; a second protection layer disposed on the first protection layer and having a surface having been subjected to at least one of an anti-glare treating and an anti-reflection treating; and a transparent layer containing a transparent material that allows visible lights to penetrate there through and absorbs or reflects ultraviolet rays and infrared rays. | 2021-08-19 |
20210257517 | DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - A display apparatus is provided. The display apparatus includes a substrate, a transistor, a metal layer, and a light-emitting diode. The transistor is disposed on the substrate. The metal layer is disposed on the transistor and electrically connected to the transistor, wherein a first distance is between the upper surface of the metal layer and the substrate in a direction perpendicular to the substrate. The light-emitting diode is disposed on the metal layer, wherein the light-emitting diode includes a light-emitting diode body and an electrode, the light-emitting diode body is electrically connected to the metal layer via the electrode, the light-emitting diode body has a first surface and a second surface opposite to the first surface, the first surface and the second surface are parallel to the substrate, and in the direction above, a second distance is between the first surface and the second surface, wherein the ratio of the second distance to the first distance is greater than or equal to 0.25 and less than or equal to 6. | 2021-08-19 |
20210257518 | DISPLAY DEVICE - A display device includes: a display module; a driving chip assembly electrically connected to the display module and including a driving chip and a heat dissipator at least partially surrounding the driving chip; and a main circuit board electrically connected to the driving chip assembly and contacting the heat dissipator. | 2021-08-19 |
20210257519 | SEMICONDUCTOR PACKAGE SUBSTRATE, SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor package substrate includes a semiconductor housing space including a mounting surface being provided on a bottom side and configured to mount a semiconductor light-emitting element, and a reflective wall being provided around the mounting surface and configured to reflect light emitted from the semiconductor light-emitting element to be mounted on the mounting surface; a mounting region being provided at a rim portion and configured to mount a lid member for covering the semiconductor light-emitting element; and a flow-suppressing portion separating the mounting region and the reflective wall spatially in such a manner that a joining member joining the lid member to the rim portion is suppressed from flowing from the mounting region into the semiconductor housing space. | 2021-08-19 |
20210257520 | DISPLAY DEVICE - A display device includes a carrier, a substrate unit, a plurality of light emitting elements and a circuit unit. The carrier has a top surface and a bottom surface opposite to each other, and a peripheral surface interconnecting the top and bottom surfaces. The substrate unit is disposed on one side of the peripheral surface of the carrier. The light emitting elements are spacedly disposed on the top surface of the carrier. The circuit unit includes a plurality of circuit modules that are disposed on the substrate unit and that are electrically connected to the light emitting elements. Each of the circuit modules includes a switch control circuit and a driving circuit that are configured to control the light emitting elements. | 2021-08-19 |
20210257521 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode (LED) package includes a substrate, at least one micro LED chip, a black material layer, and a transparent material layer. The substrate has a width ranging from 100 micrometers to 1000 micrometers. The at least one micro LED chip is electrically mounted on a top surface of the substrate and has a width ranging from 1 micrometer to 100 micrometers. The black material layer covers the top surface of the substrate to expose the at least one micro LED chip. The transparent material layer covers the at least one micro LED chip and the black material layer. | 2021-08-19 |
20210257522 | Conversion Element, Optoelectronic Component and Method for Producing a Conversion Element - A conversion element, an optoelectronic component, an arrangement and a method for producing a conversion element are disclosed. In an embodiment an arrangement includes a conversion element having a wavelength converting conversion material, a matrix material in which the conversion material is embedded and a substrate on which the matrix material with the embedded conversion material is directly arranged, wherein at least one condensed sol-gel material, and a laser source configured to emit primary radiation during operation, wherein the conversion element is arranged in a beam path of the laser source, wherein the conversion element is mechanically immovably mounted with respect to the laser source, and wherein the primary radiation of the laser source is dynamically arranged to the conversion element. | 2021-08-19 |
20210257523 | EMITTING DEVICES, ASSOCIATED DISPLAY SCREEN AND METHODS FOR FABRICATING AN EMITTING DEVICE - An emitting device comprising a first light emitter adapted to emit a first radiation, and a second light emitter adapted to emit a second radiation different from the first radiation, the first light emitter comprising a first semiconducting structure and a first radiation converter, the second light emitter comprising a second semiconducting structure and a second radiation converter, each semiconducting structure comprising a semiconducting layer adapted to emit a third radiation, each radiation converter comprising a set of particles able to convert the third radiation into the first or second radiation, the particles of the first radiation converter being attached to a surface by a bulk of photosensitive resin and the particles of the second radiation converter being attached to a surface by grafting. | 2021-08-19 |
20210257524 | METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT - A method of manufacturing a light emitting element includes: providing a first light emitting part and a second light emitting part, the first light emitting part comprising a first base member and a first semiconductor layered body, the second light emitting part comprising a second base member and a second semiconductor layered body; bonding the first and second light emitting parts to each other such that the first base member and the second base member are disposed between the first semiconductor layered body and the second semiconductor layered body; disposing a light reflecting member to cover the bonded first and second light emitting parts; removing a portion of the light reflecting member to expose surfaces of the first and second base members; and disposing a wavelength conversion member on the exposed surface of the first base member and the exposed surface of the second base member. | 2021-08-19 |
20210257525 | DISPLAY DEVICE - A display device includes a first pixel and a second pixel adjacent to each other in a first direction, first voltage wires disposed in the first pixel and the second pixel in a second direction, a second wire disposed along a boundary between the first pixel and the second pixel in the second direction, first electrodes disposed between the first voltage wires and the second wire in the first pixel an the second pixel, a second electrode disposed between and spaced apart from the first electrodes in the first pixel and the second pixel, and light-emitting elements disposed at each of the first pixel and the second pixel and disposed on the first electrodes and the second electrode, wherein the first voltage wires, the first electrodes, and the light-emitting elements are symmetric with respect to the second wire. | 2021-08-19 |
20210257526 | OHMIC CONTACTS FOR SEMICONDUCTOR STRUCTURES - A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAl | 2021-08-19 |
20210257527 | LIGHT-EMITTING STRUCTURE ALIGNMENT PRESERVATION IN DISPLAY FABRICATION - Techniques are disclosed for forming a frame on the backplane comprising structures at least partially circumscribing or enclosing metal contacts on the backplane. In some embodiments, the frame may comprise a photoresist. The dimensions and structural integrity of the frame can help prevent misalignment and/or damage of physical obtrusions of light-emitting structures during a bonding process of the light-emitting structures to the backplane. | 2021-08-19 |
20210257528 | LIGHT EMITTING DIODE - A light emitting diode includes a first conductivity type semiconductor layer, a mesa with an active layer and a second conductivity type semiconductor layer disposed thereon, a first contact layer comprising an outer contact portion contacting the first conductivity type semiconductor layer near an edge thereof and an inner contact portion contacting the first conductivity type semiconductor layer in a region surrounded by the outer contact portion; a second contact layer disposed on the mesa and contacting the second conductivity type semiconductor layer; a first insulation layer covering the mesa, insulating the first contact layer, and exposing the first conductivity type semiconductor layer for the outer contact portion and the inner contact portion to contact the first conductivity type semiconductor layer, wherein the outer contact portion and the first insulation layer alternately contact the first conductivity type semiconductor layer along a side surface of the mesa. | 2021-08-19 |
20210257529 | LIGHT-EMITTING ELEMENT PACKAGE AND LIGHT SOURCE MODULE - A light-emitting element package according to an embodiment comprises: a body comprising a cavity; the cavity; a first frame and a second frame arranged on the bottom surface of the cavity; a first metal layer disposed on the first frame; an ultraviolet light-emitting element disposed on the first metal layer; and a second metal layer disposed on the second frame and electrically connected to the second frame, wherein the body comprises a separation portion between the first frame and the second frame, the second metal layer extends over the sloping surface of the cavity and the separation portion of the body, and the second metal layer is spaced apart from the first metal layer in the cavity and surrounds the first metal layer. | 2021-08-19 |
20210257530 | THERMOELECTRIC CONVERSION MATERIAL, THERMOELECTRIC CONVERSION MODULE USING SAME, AND METHOD OF MANUFACTURING THERMOELECTRIC CONVERSION MATERIAL - A thermoelectric conversion material includes a sintered body including a main phase including a plurality of crystal grains including Ce, Mn, Fe, and Sb and forming a skuttterudite structure, and a grain boundary between crystal grains adjacent to each other. The grain boundary includes a sintering aid phase including at least Mn, Sb, and O. Thus, with respect to a skutterudite-type thermoelectric conversion material including Sb, which is a sintering-resistant material, it is possible to improve sinterability while maintaining a practical dimensionless figure-of-merit ZT, and to reduce processing cost. | 2021-08-19 |
20210257531 | THERMOELECTRIC CONVERSION MATERIAL CHIP MANUFACTURING METHOD, AND METHOD FOR MANUFACTURING THERMOELECTRIC CONVERSION MODULE USING CHIP OBTAINED BY SAID MANUFACTURING METHOD - A method for producing a chip of a thermoelectric conversion material formed of a thermoelectric semiconductor composition, including a step of forming a sacrificial layer on a substrate, (B) a step of forming a thermoelectric conversion material layer of a thermoelectric semiconductor composition on the sacrificial layer, (C) a step of annealing the thermoelectric conversion material layer, (D) a step of transferring the annealed thermoelectric conversion material layer to a pressure-sensitive adhesive layer, (E) a step of individualizing the thermoelectric conversion material layer into individual chips of a thermoelectric conversion material, and (F) a step of peeling the individualized chips of a thermoelectric conversion material; and a method for producing a thermoelectric conversion module using the chip produced according to the production method. | 2021-08-19 |
20210257532 | SUPERCONDUCTING BUMP BOND ELECTRICAL CHARACTERIZATION - Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment. | 2021-08-19 |
20210257533 | COOLER DEVICE WITH ALUMINUM OXIDE INSULATORS - A solid state cooler device is disclosed that comprises a first normal metal pad, a first aluminum layer and a second aluminum layer disposed on the first normal metal pad and separated from one another by a gap, a first aluminum oxide layer formed on the first aluminum layer, and a second aluminum oxide layer formed on the second aluminum layer, and a first superconductor pad disposed on the first aluminum oxide layer and a second superconductor pad disposed on the second aluminum oxide layer. The device further comprises a first conductive pad coupled to the first superconductor pad, and a second conductive pad coupled to the second superconductor pad, wherein hot electrons are removed from the first normal metal pad when a bias voltage is applied between the first conductive pad and the second conductive pad. | 2021-08-19 |
20210257534 | Switch Cell Device - Various implementations described herein are related to a device having multiple conductive terminals formed with a superconductive material. The device may include at least one switching layer formed with correlated-electron material (CEM) that is disposed between the multiple conductive terminals. The CEM may comprise carbon or a carbon based compound. The device may refer to a switch structure or similar. | 2021-08-19 |
20210257535 | TREATMENT DURING FABRICATION OF A QUANTUM COMPUTING DEVICE TO INCREASE CHANNEL MOBILITY - Methods related to the treatment of a quantum computing device to increase channel mobility are described. An example method includes forming a superconducting metal layer on a surface of a wafer. The method further includes selectively removing a portion of the superconducting metal layer to allow a subsequent formation of a gate dielectric associated with the device, where the selectively removing causes a decrease in channel mobility associated with the quantum computing device. The method further includes prior to forming the gate dielectric, subjecting the wafer to a plasma treatment, where a set of parameters associated with the plasma treatment is selected to increase the channel mobility. | 2021-08-19 |
20210257536 | FABRICATION OF MAGNETIC NANOWIRE FOR MAJORANA QUBITS - According to an embodiment of the present invention, a method for fabricating a Majorana fermion structure includes providing a substrate, and depositing a superconducting material on the substrate. The method includes depositing a magnetic material on the superconducting material using angled deposition through a mask. The method includes annealing the magnetic material and the superconducting material to form a magnetic nanowire partially embedded in the superconducting material such that the magnetic nanowire and the superconducting material form a Majorana fermion structure. | 2021-08-19 |
20210257537 | FABRICATION OF A DEVICE - A method of fabricating a device, wherein the device comprises a plurality of lengths of material and at least one junction joining two or more of the lengths of material. In a masking phase, a mask is formed on an underlying layer of the device. The mask comprises a plurality of trenches exposing the underlying layer, each trench corresponding to one of the lengths of material. A respective section of two or more of the trenches either (a) narrow down, or (b) are separated by a discontinuity, at a position corresponding to the at least one junction. In a selective area growth phase, material is grown in the set of trenches to form the lengths of material on the underlying layer. The two or more lengths of material are joined at the at least one junction. | 2021-08-19 |
20210257538 | DEVICE CONSISTING OF AN ELASTOMER MATRIX, COMPRISING PIEZOELECTRIC CHARGES AND ELECTRODES - A piezoelectric device comprises at least one piezoelectric composite layer P inserted between two conductive composite layers E, each layer E forming an electrode, characterized in that: the layer P is a rubber composition containing more than 50 parts by weight per hundred parts by weight rubber, phr, of diene elastomer, a cross-linking system and at least 5 vol. %, in relation to the total volume of the rubber composition, of piezoelectric inorganic charges; and each layer E is a rubber composition containing at least 50 phr of diene elastomer, a cross-linking system, and conductive charges. A method for producing the device and a tire comprising the device are also disclosed. | 2021-08-19 |