34th week of 2009 patent applcation highlights part 19 |
Patent application number | Title | Published |
20090206897 | SKEW ADJUSTMENT CIRCUIT AND A METHOD THEREOF - Provided are a skew adjustment circuit and a method thereof. The skew adjustment circuit inputs an input clock signal and an input start pulse signal to output an output clock signal and an output start pulse signal which are delayed according to a skew value of a skew control signal. The skew adjustment circuit includes a delay circuit, a selection circuit, and an output circuit. The delay circuit delays an input clock signal by a skew value in response to a skew control signal to generate an output clock signal. The selection circuit compares the skew control signal and an offset control signal to select one of the input start pulse signal and a delayed start pulse signal to output the selected signal as a start pulse signal. The output circuit responds to the output clock signal to output the start pulse signal as an output start pulse signal. | 2009-08-20 |
20090206898 | Control of a Variable Delay Line Using Line Entry Point to Modify Line Power Supply Voltage - Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point. | 2009-08-20 |
20090206899 | SYSTEM FOR CONTROLLING A SIGNAL SLEW RATE IN A DIGITAL DEVICE - A system for controlling a slew rate of a signal, such as used in an imaging device, comprises a counter for measuring a duration that the signal drops from a maximum voltage to a predetermined reference voltage; a register for retaining a desired duration that the signal drops from the maximum voltage to the predetermined reference voltage; and a comparator for comparing the measured duration to the desired duration, the comparator being operative of a current source for the signal. An anti-oscillation circuit prevents the system from oscillating between two discrete durations. | 2009-08-20 |
20090206900 | DUTY CYCLE CORRECTION CIRCUIT AND METHOD FOR CORRECTING DUTY CYCLE - A duty cycle correction circuit capable of reducing current consumption and that includes a back-bias voltage supply circuit for supplying back-bias voltages, wherein a duty cycle of an input clock is reflected on the back-bias voltages; and a buffer for adjusting the duty cycle of the input clock and configured to receive the back-bias voltages. | 2009-08-20 |
20090206901 | DUTY CYCLE CORRECTION CIRCUIT WITH REDUCED CURRENT CONSUMPTION - A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit. | 2009-08-20 |
20090206902 | METHOD FOR PROVIDING POWER FACTOR CORRECTION INCLUDING SYNCHRONIZED CURRENT SENSING AND PWM GENERATION - A method for providing power factor correction for a boost converter in accordance with an embodiment of the present application includes providing a current sense signal indicative of a current flowing through an inductor of the boost converter, sampling the current sense signal to provide a digital current sense signal, generating a pulse width modulated output signal to control an on time of a PFC switch of the boost converter based on the digital current sense signal, generating a first synchronous signal based on a carrier frequency of a triangular carrier wave used to generate the pulse width modulated output signal, wherein the first synchronous signal triggers generation of the pulse width modulated output signal and generating a second synchronous signal based on the first synchronous signal, wherein the second synchronous signal indicates a sampling rate to be used in sampling the current sense signal to provide the digital current sense signal, such that sampling takes place substantially in a middle of a cycle of the pulse width modulated output signal. | 2009-08-20 |
20090206903 | RADIO FREQUENCY AND MICROWAVE SIGNALS - A device for generating high powered Radio Frequency (RF) or microwave signals comprising a fast rise-time video pulse generator, a modulator to modify the generated UWB pulses by gyromagnetic action to transfer a portion of the UWB pulse energy from lower frequencies to frequencies in the RF or microwave range thereby producing a resultant RF or microwave waveform that can be radiated. | 2009-08-20 |
20090206904 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: a first flip-flop, a combined circuit and a second flip-flop that form a critical path; a first delay circuit and a third flip-flop that are provided in the post-stage of the combined circuit; a second delay circuit and a fourth flip-flop that are provided in the post-stage of the combined circuit; a first comparison circuit that compares the output of the second flip-flop with the output of the third flip-flop; a second comparison circuit that compares the output of the second flip-flop with the output of the fourth flip-flop: and a control circuit that controls a source voltage supplied to the combined circuit in accordance with the outputs of the comparison circuits. A delay time by the first delay circuit is different from a delay time by the second delay circuit. | 2009-08-20 |
20090206905 | SELF CLOCK GENERATION - A clock signal may be generated for a receiving circuit without requiring an external oscillator. A first digital circuit may convert a first signal edge at an input into a first clock signal at an output, and a second digital circuit, in feedback connection with the first digital circuit, may generate a second signal edge at the input based on the first clock signal at the output. Then, the first circuit may convert the second signal edge at the input to a second clock signal at the output. Thus, the first circuit and the second circuit, in combination, may generate a continuous stream of signal edges at the input and clock signals at the output. The second circuit may communicate with the controller circuit that may indicate that a subsequent clock signal is needed. The controller circuit may send commands and receive status from the receiving circuit. | 2009-08-20 |
20090206906 | SIGNAL SPLITTER - A controllable-gain circuit (TI, Rt, TS | 2009-08-20 |
20090206907 | Thermaltronic Analog Device - A method is provided for the electronic processing of analog signals in thermaltronic device. The method accepts an analog input signal, e.g., an AC signal, at a thermaltronic device input and generates a thermal electric (TE) temperature having a first transfer function responsive to the input signal. As opposed to having a digital response, the transfer function is either linear or logarithmic. An analog output signal, e.g., an AC signal, is generated having a second transfer function responsive to the TE, which is likewise either linear or logarithmic. | 2009-08-20 |
20090206908 | Radio Frequency Switch - An RF switch includes first, second and third transmission lines for forming ports, respectively, and first, second and third slot line pattern portions connected to one another, for transferring signals to the first, second and third transmission lines, respectively. The first slot line pattern portion has a slot line pattern for transferring a signal received from the first transmission line to a connection point with the other slot line pattern portions, and a switching circuit for shorting the gap of a corresponding slot line and thus blocking the signal transfer. The second slot line pattern portion includes a loop slot line formed by a first and a second half loop slot line, a second sub-slot line for transferring a signal received from the connection point to the second transmission line through the loop slot line, and a switching circuit for shorting the gap of a corresponding slot line. | 2009-08-20 |
20090206909 | BIDIRECTIONAL CONTROLLING DEVICE FOR INCREASING RESISTANCE OF ELEMENTS ON VOLTAGE STRESS - A bidirectional controlling device is utilized for receiving two input signals, which are respectively provided from a first input terminal and a second input terminal, and for respectively providing two output signals to a first output terminal and a second output terminal, by controlling a plurality of switch sets. | 2009-08-20 |
20090206910 | HIGH-FREQUENCY SWITCH CIRCUIT - A high frequency switch circuit is provided with a switch section composed of a field effect transistor having a plurality of bias circuits; and a potential generating circuit for generating a bias voltage from a control signal and supplying a bias circuit with the bias voltage. The field effect transistor serves as a path for a high frequency signal by turning on and off corresponding to the control signal. The bias circuit is provided for generating a potential difference between the drain terminal and the source terminal of the field effect transistor and for applying a bias voltage lower than the voltage of the control signal to the drain terminal and the source terminal. | 2009-08-20 |
20090206911 | Solid State Thermal Electric Logic - A method is provided for thermal electric binary logic control. The method accepts an input voltage representing an input logic state. A heat reference is controlled in response to the input voltage. The method supplies an output voltage representing an output logic state, responsive to the heat reference. More explicitly, the heat reference controls the output voltage of a temperature-sensitive voltage divider. For example, the temperature-sensitive voltage divider may be a thermistor voltage divider. | 2009-08-20 |
20090206912 | Temperature detection circuit - Provided is a temperature detection circuit which can, even when a set range of detected temperature is enlarged, suppress a rise in a lowest operating voltage. The temperature sensor circuit has a function of adjusting a voltage level of an output voltage, thereby suppressing the output voltage of the temperature sensor circuit and a reference voltage from a reference voltage circuit at a predetermined temperature. | 2009-08-20 |
20090206913 | Edge Termination with Improved Breakdown Voltage - A MOSFET switch which has a low surface electric field at an edge termination area, and also has increased breakdown voltage. The MOSFET switch has a new edge termination structure employing an N-P-N sandwich structure. The MOSFET switch also has a polysilicon field plate configuration operative to enhance any spreading of any depletion layer located at an edge of a main PN junction of the N-P-N sandwich structure. | 2009-08-20 |
20090206914 | SEMICONDUCTOR DEVICE GENERATING VARIED INTERNAL VOLTAGES - The present invention describes a semiconductor device that generates internal voltages having different levels using an external voltage. The semiconductor device includes a plurality of asynchronous internal voltage generating circuits that share an external voltage source and generate internal voltages having different levels from one another. The plurality of asynchronous internal voltage generating circuits maintain the levels of the internal voltages at target levels by using the external voltage at different time points, respectively. The semiconductor device minimizes noise in the external voltage according to the use of the internal voltages. | 2009-08-20 |
20090206915 | Two Stage Voltage Boost Circuit, IC and Design Structure - A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage; a first passgate coupled to the first stage; a first gate control circuit for generating an on-state gate voltage level for the first passgate adjusted to reduce gate oxide voltage stress on the passgate; a second stage for boosting the first boosted voltage to a second boosted voltage; a second passgate coupled to the second stage, and a gate control circuit for generating an on-state gate voltage level for the second passgate adjusted to reduce gate oxide voltage stress on the second pass-gate. | 2009-08-20 |
20090206916 | Voltage Boost System, IC and Design Structure - A voltage boost system, IC and design structure are disclosed for boosting a supply voltage while preventing forward biasing of n-well structures. The voltage boost system may include a first voltage boost circuit producing a first boosted voltage using at least one voltage boost sub-circuit, each of the at least one voltage boost sub-circuit having an output passgate in an n-well; a second voltage boost circuit producing a second boosted voltage, the n-well of each output passgate being biased using the second boosted voltage, wherein the second boosted voltage is greater than the first boosted voltage. Voltage boost sub-circuits may use gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. | 2009-08-20 |
20090206917 | Two Stage Voltage Boost Circuit With Precharge Circuit Preventing Leakage, IC and Design Structure - A two stage voltage boost circuit, IC and design structure are disclosed for boosting a supply voltage using gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used. The voltage boost circuit may include a first stage for boosting the supply voltage to a first boosted voltage and a second stage for boosting the first boosted voltage to a second boosted voltage. Each stage may include a passgate and a gate control circuit for generating an on-state gate voltage level for the respective passgate adjusted to reduce gate oxide voltage stress on the passgate. The circuit may also include a precharge circuit for coupling a voltage on a high node of the second stage to a gate node of a precharge transistor thereof for disabling the precharge transistor and preventing leakage back to a power supply voltage. | 2009-08-20 |
20090206918 | SEMICONDUCTOR DEVICE AND CELL PLATE VOLTAGE GENERATING APPARATUS THEREOF - A semiconductor device includes a monitor voltage transfer unit and a voltage generating unit. The monitor voltage transfer unit selects one of a plurality of internal voltages including a cell plate voltage in accordance with a test mode to output it to a voltage monitor pad or outputs an external voltage supplied from the voltage monitor pad as a first pre cell plate voltage. The voltage generating unit generates the cell plate voltage using any one of the first pre cell plate voltage and a second pre cell plate voltage generated within itself in accordance with the test mode. The semiconductor device can generate a pre cell plate voltage at the desired level. | 2009-08-20 |
20090206919 | NO-TRIM LOW-DROPOUT (LDO) AND SWITCH-MODE VOLTAGE REGULATOR CIRCUIT AND TECHNIQUE - An optimized output voltage circuit and technique obtainable without trimming is set forth. A voltage reference circuit and method devoid of trim resistors comprising a high gain amplifier, a plurality of bandgap resistors, and at least a plurality of bipolar devices interconnected across circuitry in a predetermined configuration having emitter areas greater than traditional emitter areas of traditional bipolar devices is set forth. | 2009-08-20 |
20090206920 | SOFT-START DEVICE - A soft-start device including a current source, a first transistor, and a second transistor is described. The first transistor is coupled to the current source, and an amount of current conducted by the first transistor is determined according to a voltage. The second transistor is also coupled to the current source, and an amount of current conducted by the second transistor is determined according to a fixed bias. An initial voltage value of the voltage is smaller than a voltage value of the fixed bias. However, after a soft start, the voltage value of the first voltage is increased gradually to be larger than the voltage value of the fixed bias, such that the soft start may be implemented smoothly. | 2009-08-20 |
20090206921 | Single-chip common-drain JFET device and its applications - A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation. | 2009-08-20 |
20090206922 | Single-chip common-drain JFET device and its applications - A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation. | 2009-08-20 |
20090206923 | FILTER SWITCHING DEVICE AND FILTER SWITCHING METHOD - A filter switching device includes a first buffer amplifier, a first characteristic resistor with one terminal connected to the output of the first buffer amplifier, first and second filter circuits connected in parallel to the other terminal, the first filter circuit including a first relay and a first low-pass filter, the second filter circuit including a second relay and a second low-pass filter, a third filter circuit connected to the output of the first buffer amplifier, having a second buffer amplifier and a second characteristic resistor connected between the output of the second buffer amplifier and a third low-pass filter, and a multiplexer connected between the first, second, and third filter circuits and a third characteristic resistor selectively connecting the first, second, or third filter circuit to the third characteristic resistor. | 2009-08-20 |
20090206924 | Semiconductor Device Structures and Related Processes - Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery. | 2009-08-20 |
20090206925 | RECEIVING CIRCUIT AND METHOD FOR RECEIVING AN AMPLITUDE SHIFT KEYING SIGNAL - A receiving circuit and method for receiving an amplitude shift keying signal is provided. At least one exponent signal, an exponent-removed in-phase signal, and an exponent-removed quadrature-phase signal are generated from an in-phase input signal and a quadrature-phase input signal. An amplitude is determined as a sum of several summands, whereby the summands are determined from the exponent signal and/or from the exponent-removed in-phase signal and/or from the exponent-removed quadrature-phase signal (Q′), and wherein the amplitude (A) is demodulated. | 2009-08-20 |
20090206926 | High Efficiency Amplifier - When an input signal level is small, the electrical length of a phase line | 2009-08-20 |
20090206927 | Amplifier - There is provided an amplifier for combining outputs of a plurality of amplifying circuits to generate an amplifier output. The amplifier includes a first amplifying circuit for operating a first amplifying device in class-AB, wherein the first amplifying circuit is one among the plurality of the amplifying circuits; a second amplifying circuit for operating a second amplifying device in class-B or class-C, wherein the second amplifying circuit is one among the plurality of the amplifying circuits; and a summing node at which an output of the first amplifying circuit is combined with an output of the second amplifying circuit via a first impedance transformer containing a transmission line of an electrical length other than λ/4. The second amplifying device is connected to the summing node via an output matching circuit and a second impedance transformer containing a transmission line. | 2009-08-20 |
20090206928 | Enhanced doherty amplifier with asymmetrical semiconductors - The present disclosures an amplification unit which comprises a first amplifier and a second amplifier connected in parallel, the first amplifier and the second amplifier comprising semiconductor devices that are not the same amplifier design. The present application also discloses a signal input line connected to the first amplifier and the second amplifier. A signal output line is also disclosed which is connected to the first amplifier and the second amplifier. | 2009-08-20 |
20090206929 | OPERATION AMPLIFIER FOR IMPROVING SLEW RATE - An OP amplifier including an input stage and an output stage for improving a slew rate is provided. The input stage receives one of input voltages, and generates an internal voltage according to the received input voltage. The output stage receives and gains the internal voltage, and outputs an output voltage. The output stage includes a first transistor, a plurality of first capacitors and a first switching unit. The first transistor includes a first source/drain terminal coupled to a first voltage, a gate terminal controlled by the internal voltage. The output stage outputs the output voltage according to a voltage at a second source/drain terminal of the first transistor. First terminals of the first capacitors are coupled to the second source/drain terminal of the first transistor. The first switching unit selectively transmits the internal voltage to the second terminal of a corresponding one of the first capacitors. | 2009-08-20 |
20090206930 | AMPLIFIER CIRCUIT WITH VOLTAGE INTERPOLATION FUNCTION - An amplifier circuit with a voltage interpolation function includes an N-type differential pair and a P-type differential pair. The N-type differential pair includes a first transconductance value, and has a first differential input terminal coupled to a first voltage and a second differential input terminal coupled to a voltage output terminal. The P-type differential pair includes a second transconductance value, and has a first differential input terminal coupled to a second voltage and a second differential input terminal coupled to the voltage output terminal. The N-type differential pair and the P-type differential pair are further coupled to the voltage output terminal through an output stage, and voltages outputted by the voltage output terminal are interpolation results of the first voltage and the second voltage weighted by the first transconductance value and the second transconductance value. | 2009-08-20 |
20090206931 | Differential Amplifier and Applications Thereof - A differential amplifier includes a first pair of differential amplifiers and a second pair of differential amplifiers. These first and second pairs of differential amplifiers are connected between first power rails and are arranged to receive a differential input signal. Third and fourth pairs of differential amplifiers are connected between second rails and also connected to the differential input signal. A current summer sums a first output current of the first pair of differential amplifiers, a second output current of the second pair of differential amplifiers, a third output current of the third pair of differential amplifiers and a fourth output current of a fourth pair of differential amplifiers to produce an output signal. | 2009-08-20 |
20090206932 | LOW NOISE AMPLIFIER GAIN CONTROLLED SCHEME - An amplifier includes an amplifier module coupled to an input node, and an attenuating module. The attenuating module includes an attenuation resistor coupled to the input node, and an impedance compensation module coupled to the input node. The impedance compensation module compensates an input impedance when an input RF signal is attenuated by the attenuating module. | 2009-08-20 |
20090206933 | DUAL BIAS CONTROL CIRCUIT - The present invention relates to a bias control circuit and method for supplying a bias signal to at least one stage of an amplifier circuit, wherein a dual bias control is provided by generating a bias current and additionally using this bias current to derive a control signal for limiting a supply voltage of the at least one amplifier stage in response to the control signal. Thereby, a compression of the output signal of the amplifier stage, which results from the voltage limitation, can be realized in addition to the base current steering. This leads to a decrease in small signal gain and thus reduced output noise. | 2009-08-20 |
20090206934 | AMPLIFIER AUTO BIASING - This disclosure relates to monitoring signal overshoot of an amplifier generated signal and automatically adjusting a quiescent current of the amplifier as a function of the monitored signal overshoot. | 2009-08-20 |
20090206935 | Reconfigurable Circuit to Compensate for a Low Noise Amplification Input Matching Variation and a Method for Its Configuration - A method for changing an effective capacitance of an amplifier circuit having a match transistor and a coupled cascode transistor includes changing an on-state of at least one of a plurality of sub-transistors of the match transistor. The method further includes changing a transconductance of the match transistor as a function of the change of the on-state. The method further includes changing an equivalent resistance, as measured between a source and a drain of the cascode transistor, as a function of the change of the transconductance of the match transistor. | 2009-08-20 |
20090206936 | VOLTAGE-CONTROLLED OSCILLATOR TOPOLOGY - A voltage-controlled oscillator is implemented with a succession of delay cells coupled in series to form an oscillator loop. The oscillator loop is supplied with reference voltages produced by a voltage generator. The reference voltages produce stable operation of the voltage-controlled oscillator. Cascode reference current generators are incorporated within the voltage generator to supply a cross-coupled arrangement of pull-up devices within each delay cell. The cross-coupled pull-up devices are instrumental in producing complementary output signaling from each delay cell. A pair of cascode current generators is configured in parallel to produce a magnitude of current according to an applied voltage and be selectable for dual or single operation with a corresponding frequency determination. | 2009-08-20 |
20090206937 | INVERTING CELL - An inverting cell including a first inverter having first and second inputs; a second inverter having first and second inputs, wherein the second input of the second inverter is connected to the first input of the first inverter and the output of the first and second inverters is connected to the second input of the first inverter; and a third inverter connected between the output of the first and second inverters and the first input of the second inverter. | 2009-08-20 |
20090206938 | SURFACE-MOUNT TYPE CRYSTAL OSCILLATOR - A surface-mount type crystal oscillator includes: a container body with a first recess and a second recess; a crystal blank including excitation electrodes on respective principal surfaces thereof and hermetically encapsulated in the first recess; and an IC chip which is accommodated in the second recess and into which at least an oscillation circuit using the crystal blank is integrated. The container body includes a bottom wall and a frame wall provided on the bottom wall. Two openings which make up the first and second recesses, respectively, are formed in juxtaposition in the frame wall. A pair of inspection terminals are provided in an area of a top surface of the frame wall which surrounds the second recess. The inspection terminals are electrically connected to the excitation electrodes of the crystal blank. | 2009-08-20 |
20090206939 | VCO Pre-Compensation - A VCO device is described that has pre-compensation. Digitally switchable compensation capacitors are selectively activated to adjust operation of the VCO to mitigate undesirable operational effects. In some example embodiments, the digitally switchable compensation capacitors of the VCO are adjusted to compensate for the effects of activating (from a quiescent state) an output buffer driven by the VCO. | 2009-08-20 |
20090206940 | POLAR SIGNAL GENERATOR - The present invention relates to a polar signal generator and method of deriving phase and amplitude components from in-phase (I) and quadrature-phase (Q) components of an input signal, wherein the I and Q components are generated at a first sampling frequency based on the input signal, and are then up-sampled in accordance with a predetermined first interpolation factor (N), to generate up-sampled I and Q components at a second sampling frequency higher than the first sampling frequency. The up-sampled I and Q components are converted into the phase and amplitude components, wherein the converting step is operated at the second sampling frequency. Moreover, the phase and amplitude components can be further up-sampled, optionally by different sampling frequencies, to a third and a fourth sampling frequency. Thereby, I-Q generation and cartesian-to-polar transformation can be performed at lower frequencies, which reduces power consumption. | 2009-08-20 |
20090206941 | CHARGE PUMP-BASED FREQUENCY MODULATOR - A charge pump-based frequency modulator is provided. The charge pump-based frequency modulator comprises an analog phase correction path comprising a varactor and a charge pump. The varactor is coupled to an output of the charge pump-based frequency modulator. The charge pump is coupled to a node between the varactor and the output and receives a signal containing the modulated data. | 2009-08-20 |
20090206942 | NON-RECIPROCAL CIRCUIT DEVICE - A non-reciprocal circuit device comprising a magnetic plate F | 2009-08-20 |
20090206943 | NONRECIPROCAL CIRCUIT DEVICE - A nonreciprocal circuit device includes a permanent magnet, a ferrite to which the permanent magnet applies a direct-current magnetic field, first and second central electrodes arranged on the ferrite, and a circuit board. The first central electrode includes electrode layers provided on main surfaces of the ferrite connected by an electrode provided on a top surface of the ferrite. A second central electrode includes electrode layers provided on the main surfaces of the ferrite connected by electrodes arranged on top and bottom surfaces of the ferrite. The second electrode is wound at least about three turns around the ferrite. A width dimension of the outermost electrode layers of the second central electrode is greater than a width dimension of the inner electrode layers of the second central electrode. | 2009-08-20 |
20090206944 | METHOD AND SYSTEM FOR FREQUENCY SELECTION USING MICROSTRIP TRANSCEIVERS FOR HIGH-SPEED APPLICATIONS - Aspects of a method and system for frequency selection using microstrip transceivers for high-speed applications may include determining an operating frequency for operating one or both of a transmitter and a receiver. A frequency response and/or impedance of one or more transmission lines that may be utilized by the transmitter and/or the receiver may be controlled by adjusting one or more capacitances, communicatively coupled to the transmission lines based on the determined operating frequency. The capacitances may be coupled to the one or more transmission line at arbitrary physical spots, and may comprise capacitors and/or varactors. The capacitors and/or the varactors may be adjusted with a digital signal or an analog signal. The capacitances may comprise a matrix arrangement of capacitors and/or varactors. The one or more transmission lines may comprise a microstrip. | 2009-08-20 |
20090206945 | RECONFIGURABLE DUPLEXING COUPLERS - A multi-port reconfigurable coupler includes a coupler and a switching system configured to selectively reconfigure multiple ports of the coupler for increased application flexibility and for efficiently transmitting and receiving radio-frequency signals. The multi-port reconfigurable coupler includes a transmit signal port, a termination port, a receive signal port, an antenna port, and a switching system configured to selectively couple the termination port to a predetermined termination potential based on information indicating one of a transmit only mode, and a receive only mode, and to decouple based on information indicating a transmit-receive mode. | 2009-08-20 |
20090206946 | Apparatus and method for reducing propagation delay in a conductor - An apparatus and method is provided that reduces the propagation delay in a conductor carrying an electrical signal from a first area of a circuit to a second area of the circuit. The conductor is fabricated to include a first conductor extending from the first area to the second area. The conductor also includes a second conductor extending substantially parallel and along the first conductor and electrically connected to the first conductor. A third and additional conductors may also be used which extend substantially parallel and along the first conductor and are electrically connected to the first conductor. The additional second conductor (and any additional conductors) reduces the capacitance of the conductor thereby reducing the propagation delay in the conductor (increasing the speed of the signal). The additional conductor(s) effectively “shield” the first conductor from some capacitance that the first conductor would normally “see” without the use of such additional conductors. | 2009-08-20 |
20090206947 | Directional Coupler - In a directional coupler with two coupled lines arranged in a flat chamber of an enclosed metal housing within the coupling region side-by-side in the longitudinal direction and at a spacing distance from one another, of which the ends are connected to connecting ports attached at the sides of the metal housing, these coupled lines include flat, sheet-metal strip conductors, which are arranged within the coupling region with their broad sides facing towards one another side-by-side at a spacing distance and held by several support elements made of insulating material in a cantilever manner at a spacing distance from the opposing internal walls of the flat metal-housing chamber within the latter. In this context, at least one strip conductor is curved relative to the opposing strip conductor in such a manner that the spacing distance of the strip conductors in coupling region increases starting from the beginning of the coupling region approximately exponentially up to the end of the coupling region. The width of the two strip conductors increases within the coupling region. | 2009-08-20 |
20090206948 | MULTI-BAND HIGH-FREQUENCY CIRCUIT, MULTI-BAND HIGH FREQUENCY CIRCUIT COMPONENT AND MULTI-BAND COMMUNICATION APPARATUS USING SAME - A multi-band high-frequency circuit for performing wireless communications among pluralities of communication systems having different communication frequencies, comprising a high-frequency switch circuit comprising switching elements for switching the connection of pluralities of multi-band antennas to transmitting circuits and receiving circuits; a first diplexer circuit disposed between the high-frequency switch circuit and transmitting circuits for branching a high-frequency signal into frequency bands of the communication systems; a second diplexer circuit disposed between the high-frequency switch circuit and receiving circuits for branching a high-frequency signal into frequency bands of the communication systems; the first and second diplexer circuits each comprising a lower-frequency filter circuit and a higher-frequency filter circuit, a bandpass filter circuit being used as the lower-frequency filter circuit in the second diplexer circuit, or disposed between the lower-frequency filter circuit in the second diplexer circuit and the receiving circuit, the high-frequency switch circuit comprising first to fourth ports, the first port being connected to a first multi-band antenna, the second port being connected to a second multi-band antenna, the third port being connected to the first diplexer circuit, and the fourth port being connected to the second diplexer circuit; and the switching elements being controlled in an ON or OFF state to select a multi-band antenna for performing wireless communications and to switch the connection of the selected multi-band antenna to the transmitting circuit or the receiving circuit. | 2009-08-20 |
20090206949 | Electrical waveform adjuster - An object of the present invention is to provide an electrical waveform adjuster capable of adjusting various voltage waveforms supplied to an electric apparatus to improve an operation capability of the electric apparatus, and also, to provide an electrical waveform adjuster capable of mitigating physical harmful effects on a user of the electric apparatus. | 2009-08-20 |
20090206950 | DYNAMIC HARMONIC FILTER FOR AN AC POWER SYSTEM - A dynamic harmonic filter for an AC power system comprising at least one voltage source (V) and at least one load. The harmonic filter comprises a current sensing or voltage injection transformer (T | 2009-08-20 |
20090206951 | ELECTRONIC DEVICE - An electronic device comprising: a wiring substrate having a first power-supply wiring to which a first power-supply potential is applied and a second power-supply wiring to which a second power-supply potential lower than the first power-supply potential is applied; a microcomputer having first and second power-supply terminals in which the first power-supply terminal is connected to the first power-supply wiring and the second power-supply terminal is connected to the second power-supply wiring; and a connector connected to the first and second power-supply wirings, wherein an inductor element for correcting an impedance error of the first and second wirings is connected in series to either one of the first and second power-supply wirings. According to such configuration, unnecessary electromagnetic radiation posed by a common current can be suppressed. | 2009-08-20 |
20090206952 | DELAY LINE REGULATION USING HIGH-FREQUENCY MICRO-REGULATORS - A regulated delay line device includes main regulator coupled to a node, and a plurality of delay branches coupled to the node to receive a voltage output to the node by the main regulator. Each of the plurality of delay branches includes a micro-regulator and a delay line. The delay line is coupled to the micro-regulator such that unfiltered noise is removed locally at each delay branch by a corresponding micro-regulator. | 2009-08-20 |
20090206953 | RESONANT MEMS DEVICE THAT DETECTS PHOTONS, PARTICLES AND SMALL FORCES - A resonant MEMS device that detects photons, particles and small forces including atomic forces is disclosed. The device comprises a planar substrate | 2009-08-20 |
20090206954 | ELASTIC SURFACE WAVE DEVICE - A surface acoustic wave device includes a pair of reflectors and an interdigital transducer having a cross electrode having a interdigitated portion and a dummy portion and a dummy electrode. The dummy electrode has a length different from the length of the dummy portion of the cross electrode arranged adjacent to the dummy electrode. | 2009-08-20 |
20090206955 | SURFACE ACOUSTIC WAVE DEVICE AND SURFACE ACOUSTIC WAVE OSCILLATOR - A surface acoustic wave device, includes: an interdigital transducer serving as an electrode pattern to excite a Rayleigh surface acoustic wave, the interdigital transducer including a comb-tooth-shaped electrode having a plurality of electrode fingers; a piezoelectric substrate on which the interdigital transducer is formed, the piezoelectric substrate being made of a quartz substrate that is cut out at a cut angle represented by an Euler angle representation (φ, θ, Ψ) of (0°, 95°≦θ≦155°, 33°≦|Ψ|≦46°); electrode finger grooves formed between the electrode fingers of the comb-tooth-shaped electrode; and electrode finger bases being quartz portions sandwiched between the electrode finger grooves and having upper surfaces on which the electrode fingers are positioned The surface acoustic wave device provides an excitation in an upper limit mode of a stop band of the surface acoustic wave. | 2009-08-20 |
20090206956 | SUBSTRATE, COMMUNICATION MODULE, AND COMMUNICATION APPARATUS - A substrate for mounting a filter has a connection line layer having a transmission line for connecting a filter, a ground layer placed below the connection line layer and having a ground, and an insulation layer placed between the transmission line and the ground layer and having a thickness which satisfies a characteristic impedance of the transmission line in a range 0.1 to 50 ohms, the characteristic impedance determined by the thickness and a dielectric constant of the insulation layer and a width of the transmission line. | 2009-08-20 |
20090206957 | RESONANT ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A resonant element is manufactured through a process including a setting step and a forming step. A substrate of the resonant element is made of a dielectric material. A ground electrode is formed on a rear principal surface side of the substrate. Principal-surface electrodes that define resonators together with the ground electrode and the dielectric material are formed on a front principal surface side of the substrate. An electrode protecting layer is formed on substantially entire surfaces on a front principal surface side of the principal-surface electrodes and the substrate. A coupling adjusting electrode with both ends facing a plurality of the principal-surface electrodes is formed on a front principal surface side of the electrode protecting layer. In the setting step, the shape of the coupling adjusting electrode is set in each manufactured lot. In the forming step, the coupling adjusting electrode having the shape set in the setting step in each manufactured lot is formed on the front principal surface side of the substrate and the electrode protecting layer that are sintered in advance, and the coupling adjusting electrode is baked to the electrode protecting layer. | 2009-08-20 |
20090206958 | High Voltage Isolation Semiconductor Capacitor Digital Communication Device and Corresponding Package - According to one embodiment, there is provided a semiconductor digital communication device comprising communication drive and sense electrodes formed in a single plane, where the electrodes have relatively high sidewalls. The relatively high sidewalls permit low electrical field densities to be obtained in the sense and drive electrodes during operation, and further permit very high breakdown voltages to be obtained between the electrodes, and between the drive electrode and an underlying ground plane substrate. The device effects communications between drive and receive circuits through the drive and sense electrodes by capacitive means, and in a preferred embodiment is capable of effecting relatively high-speed digital communications. The device may be formed in a small package using, by way of example, CMOS or other semiconductor fabrication and packaging processes. | 2009-08-20 |
20090206959 | RF MODULE - In a radio-frequency wave module including a transmission path based on a distributed parameter element, the transmission path being part of an input/output terminal, a plurality of cavity-structured concave portions for containing semiconductor-including mounted components therein, grounding-use metallic electrodes, dielectric substrates of at least two or more layers, and semiconductors, electrical separation is established between the grounding-use metallic electrodes which form the transmission paths based on the distributed parameter element and at least one of the grounding-use metallic electrodes which are formed on bottom surfaces of the plurality of cavity-structured concave portions for containing the semiconductor-including mounted components therein. | 2009-08-20 |
20090206960 | High Voltage Isolation Dual Capacitor Communication System - According to one embodiment, there is provided a high voltage isolation dual capacitor communication system comprising communication drive and sense electrodes and corresponding first and second capacitors that are formed in two separate devices. The two devices are electrically connected in series to provide a single galvanicly-isolated communication system that exhibits high breakdown voltage performance in combination with good signal coupling. The system effects communications between drive and receive circuits through the first and second capacitors, and in a preferred embodiment is capable of effecting relatively high-speed digital communications. The system may be formed in a small package using, by way of example, CMOS or other semiconductor fabrication and packaging processes. | 2009-08-20 |
20090206961 | HIGH-FREQUENCY MEMBER ASSEMBLY WITH WAVEGUIDE - A high-frequency member assembly has two high-frequency members of which surfaces are attached to each other. Each member has a rectangular waveguide hole penetrating through the member and two choke grooves opened on the attaching surface. The waveguide holes communicate with each other to form a rectangular waveguide. An electromagnetic wave is transmitted through the waveguide. Each choke groove extends straight along a side of an end of the waveguide hole opened on the attaching surface to be away from the end of the waveguide hole by one quarter of the wavelength of the wave. The depth of each choke groove is equal to one quarter of the wavelength. The choke grooves of one member communicate with the choke grooves of the other member to substantially surround the waveguide with the choke grooves in an attaching area between the member. | 2009-08-20 |
20090206962 | INTEGRATED FRONT-END PASSIVE EQUALIZER AND METHOD THEREOF - A passive equalizer circuit incorporated at a front-end of an integrated receiver circuit uses passive components that are distributed between inside and outside of an integrated circuit package. The passive equalizer circuit has off-chip components that are placed on a printed circuit board and on-chip components that are fabricated on a common integrated circuit die as a receiver chip. The on-chip components include one or more variable resistors for adjusting a degree of equalization. The off-chip components include one or more resistors for fine tuning input impedance matching of the integrated receiver circuit. | 2009-08-20 |
20090206963 | TUNABLE METAMATERIALS USING MICROELECTROMECHANICAL STRUCTURES - A metamaterial comprises a support medium, such as a planar dielectric substrate and a plurality of resonant circuits supported thereby. At least one resonant circuit is a tunable resonant circuit including a conducting pattern and a voltage-tunable capacitor, so that an electromagnetic parameter (such as resonance frequency) may be adjusted using an electrical control signal. In some examples of the present invention, the voltage-tunable capacitor includes a MEMS structure. | 2009-08-20 |
20090206964 | MECHANICAL INTERLOCK FOR CIRCUIT BREAKER TO PREVENT RELATCHING OF THE BREAKER - An apparatus and method for restricting auxiliary latch movement within a tripped circuit breaker. An auxiliary latch is held in a closed state and is biased into an open state. When the trip bar is activated in response to an overload condition, it releases the auxiliary latch which pivots to the open state. The cradle is released and pivots to disengage the breaker contact. Tabs on the cradle and auxiliary latch cooperatively interlock to limit auxiliary latch movement until the latch is properly reset. | 2009-08-20 |
20090206965 | Starter solenoid switch with improved arrangement of resistor - In a solenoid switch according to the invention, a magnetic plate is disposed on one side of a solenoid coil in an axial direction of the solenoid coil. A contact cover is arranged with the magnetic plate interposed between the contact cover and the solenoid coil in the axial direction. First and second fixed contacts are received in the contact cover and respectively electrically connected to first and second terminals that are to be electrically connected to an electric circuit. A resistor is electrically connected between the first and second terminals to limit current flowing through the electric circuit when the first and second fixed contacts are electrically disconnected by a movable contact. The resistor is received in the contact cover and interposed between the magnetic plate and the first and second fixed contacts in the axial direction. | 2009-08-20 |
20090206966 | Structure of electromagnetic switch for starter - An electromagnetic switch for use in actuating a starter for automotive vehicles is provided. The switch includes fixed contacts, a moving contact, and a plunger shaft. The moving contact is joined to a plunger shaft through an insulator. The plunger shaft is to be moved magnetically to bring the moving contact into abutment with the fixed contact to establish electric communication between the fixed contact. The switch also includes a rotation holder working to hold the moving contact and the insulator from rotating relative to each other. Use of the rotation holder results in a decrease in wear of the insulator. This eliminates the need for the insulator to have an additional thickness which would be worn down, thus permitting the insulator to be reduced in thickness to shorten the overall length of the switch. | 2009-08-20 |
20090206967 | High-Field Synchrocyclotron - The magnetic field in an acceleration chamber defined by a magnet structure is shaped by shaping the poles of a magnetic yoke and/or by providing additional magnetic coils to produce a magnetic field in the median acceleration plane that decreases with increasing radial distance from a central axis. The magnet structure is thereby rendered suitable for the acceleration of charged particles in a synchrocyclotron. The magnetic field in the median acceleration plane is “coil-dominated,” meaning that a strong majority of the magnetic field in the median acceleration plane is directly generated by a pair of primary magnetic coils (e.g., superconducting coils) positioned about the acceleration chamber, and the magnet structure is structured to provide both weak focusing and phase stability in the acceleration chamber. The magnet structure can be very compact and can produce particularly high magnetic fields. | 2009-08-20 |
20090206968 | ARMORED SUPERCONDUCTING WINDING AND METHOD FOR ITS PRODUCTION - The superconducting winding ( | 2009-08-20 |
20090206969 | TRIP ACTUATOR INCLUDING A THERMOPLASTIC BUSHING, AND TRIP UNIT AND ELECTRICAL SWITCHING APPARATUS INCLUDING THE SAME - A circuit breaker includes separable contacts, an operating mechanism structured to open and close the contacts, and a trip unit cooperating with the operating mechanism to trip open the contacts. The trip unit includes a sensor structured to sense current flowing through the contacts, a processor structured to output a trip signal responsive to the sensed current, and a trip actuator. The trip actuator includes a housing including a recess, a coil within the recess, the coil having an opening therethrough, a magnet within the recess, a thermoplastic bushing including a conduit therethrough, the thermoplastic bushing being coupled to the housing, and an armature disposable within the opening of the coil and slidably disposed within the conduit of the thermoplastic bushing. The magnet attracts the armature toward the housing. A spring biases the armature away from the housing, in order to cause the operating mechanism to trip open the contacts. | 2009-08-20 |
20090206970 | DEVICE FOR COUPLING AN ATTACHMENT - A coupling ring ( | 2009-08-20 |
20090206971 | CORE FOR REACTOR - A core for a reactor includes: a plurality of core members, each of which has a convexly curved side face that serves as a bonding face; and a gap plate that is interposed between the curved side faces of the core members and that is bonded to the curved side faces. The gap plate includes a flat plate and a plurality of projections which project from each face of the plate and each of which has a tip end that contacts the curved side face. The projections are formed at positions near the outer edges of the plate, which are distant from the center of the plate at which no projection is formed, and which are at equal distances from the center of the plate. | 2009-08-20 |
20090206972 | METHOD AND APPARATUS FOR DYNAMIC MAGNETIC FIELD CONTROL USING MULTIPLE MAGNETS - A method and apparatus for dynamic magnetic field control using multiple magnets. Control methods and system means are described that allow dynamically changing the magnetic field generated at a point in space by a multiplicity of magnets. | 2009-08-20 |
20090206973 | BOND MAGNET FOR DIRECT CURRENT REACTOR AND DIRECT CURRENT REACTOR - The present invention provides a bond magnet for direct current reactor which is to be disposed in a gap formed in a magnetic core of a direct current rector, the bond magnet containing a magnet powder containing a rapidly quenched powder of a rare earth magnet alloy. The present invention also provides a direct current reactor including a magnetic core having a gap and a winding area wound around the magnetic core, in which the bond magnet is disposed in the gap of the magnetic core. | 2009-08-20 |
20090206974 | Helical Coil Design and Process For Direct Fabrication From A Conductive Layer - A conductor assembly of the type which, when conducting current, generates a magnetic field or in which, in the presence of a changing magnetic field, a voltage is induced. According to an exemplary embodiment a conductor is positioned along a path of variable direction relative to a reference axis. The conductor has a width measurable along an outer surface thereof and along a series of different planes transverse to the path direction. The measured conductor width varies among the different planes. In one example, the conductor path is helical, positioned about the axis between turns of helical spaces, and the conductor width varies as a function of the azimuth angle. | 2009-08-20 |
20090206975 | Magnet Core and Method for Its Production - Magnet cores pressed using a powder of nanocrystalline or amorphous particles and a pressing additive should be characterised by minimal iron losses. These particles have first surfaces represented by the original strip surfaces and second surfaces represented by surfaces produced in a pulverisation process, the overwhelming majority of these second particle surfaces being smooth cut or fracture surfaces without any plastic deformation, the proportion T of areas of plastic deformation of the second particle surfaces being 0≦T≦0.5. | 2009-08-20 |
20090206976 | REACTOR SHIELD - A reactor shield including a plurality of closed loops of electrically conductive wires arranged around a reactor. | 2009-08-20 |
20090206977 | Thermal overload relay - A thermal overload relay is provided with an external case, and an adjustment dial with a cam inserted into an adjustment dial insertion hole provided in the external case for adjusting a settling current. A press-fitting section is provided at one of the adjustment dial and the adjustment dial insertion hole, and a locking section is provided at the other of the adjustment dial and the adjustment dial insertion hole. The press-fitting section is press-fit and retained in the locking section. | 2009-08-20 |
20090206978 | Electrical fuse device including a fuse link - Example embodiments relate to an electrical device, for example, to an electrical fuse device that includes a fuse link for linking a cathode and anode. An electrical device may include a cathode, an anode, and a fuse link. The fuse link may link the cathode and the anode. The fuse link may include a multi-metal layer structure. The fuse link may include a first metal layer including a first resistance, and a second metal layer stacked on the first metal layer and including a second resistance. The first resistance may be different from the second resistance. The fuse link may include a weak point as a region at which electrical blowing is performed easier than other regions of the fuse link. | 2009-08-20 |
20090206979 | LAYERED ELECTRICALLY CONDUCTIVE MATERIAL - An electrical resistor has an electrically conductive stack, which includes a plurality of metal first layers and second layers. The stack allows to produce a highly anisotropic resistor, in which the resistance in the direction perpendicular to the layers is much higher than in the plane of the layers. The anisotropy allows the current flowing through the stack to be made homogenous, e.g., to be distributed over the entire stack surface, even if the current is input into the stack in an inhomogenous manner. | 2009-08-20 |
20090206980 | THERMISTOR AND MANUFACTURING METHOD THEREOF - Provided is a thermistor that exhibits small changes in resistance before and after tripping. In a preferred embodiment, the thermistor comprises a pair of electrodes, and a thermistor layer disposed between the pair of electrodes. The thermistor layer is a cured layer of a thermistor composition that comprises a resin, conductive particles, and a cross-linking agent comprising an isocyanurate having allyl groups and glycidyl groups. | 2009-08-20 |
20090206981 | MATCHED RF RESISTOR HAVING A PLANAR LAYER STRUCTURE - The invention relates to an RF resistor, and in particular an RF terminating resistor, having a planar layer structure which has, on a substrate ( | 2009-08-20 |
20090206982 | THIN-FILM RESISTOR WITH A LAYER STRUCTURE AND METHOD FOR MANUFACTURING A THIN-FILM RESISTOR WITH A LAYER STRUCTURE - A thin-film resistor with a layer structure with a Ti layer and a TiN layer is described, wherein a layer thickness of the Ti layer and a layer thickness of the TiN layer are selected such that a resulting temperature coefficient of resistance (TCR) is smaller than 1000 ppm/° C. | 2009-08-20 |
20090206983 | Communication System for a Radio-Frequency Load Control System - A radio-frequency (RF) load control system allows for the expedient transmission of subsequent digital messages to one or more recipients via an RF communication link. The control system comprises at least one load control device for controlling the amount of power delivered to an electrical load in response to a received digital message. Each control device of the load control system is operable to interrupt the propagation of a first digital message to transmit a second digital message in response to determining that the second digital message has a high priority than the first digital message. For example, an originating control device may transmit first and second digital messages in response to a press and a release of an actuator, respectively, and may interrupt the propagation of the first digital message to transmit the second digital message if the first digital message is irrelevant in view of the second digital message. | 2009-08-20 |
20090206984 | APPLICATION CONTROL METHOD IN AN NFC CHIPSET COMPRISING SEVERAL HOST PROCESSORS - A method for controlling the execution of an application in a system having a contactless data sending/receiving interface (CLINT) of NFC type, and host processors (HP | 2009-08-20 |
20090206985 | CONTROL METHOD AND SYSTEM FOR CONTROLLING ACCESS THROUGH AN AUTOMATED DOOR - A control method for controlling access through an automated door is performed by a control system that includes a first communications unit, a processor and a storage space. The control method includes the steps of: a) through the first communications unit, receiving a communications signal transmitted from a second communications unit that has a second identification code and that transmits the communications signal upon dialing of the first identification code, and obtaining the second identification code of the second communications unit from the communications signal; and b) through the processor, comparing the second identification code obtained in step a) with at least one authorized identification code stored in the storage space, and controlling the automated door to permit access therethrough when a match is found. | 2009-08-20 |
20090206986 | METHOD OF PRESENTING IMS PUBLIC USER IDENTIFY TO RFID APPLICATIONS - An IMS node communicating with a user node and an information node is provided. The information node is adapted to conduct access control based on IMS Public User Identity. The IMS node comprises: request mediation means for mediating an access request from the user node to the information node by converting a first protocol conforming to IMS into a second protocol interpretable to the information node; and response mediation means for mediating an access response from the information node to the user node by converting the second protocol into the first protocol. The access request includes the IMS Public User Identity and information identity specifying information which the information node is requested to retrieve. | 2009-08-20 |
20090206987 | METHODS AND SYSTEMS FOR OBJECT IDENTIFICATION AND FOR AUTHENTICATION - Methods and systems for object identification and/or authentication. | 2009-08-20 |
20090206988 | Method and Server of Electronic Safes With Information Sharing - A method of managing electronic safes implemented by a server on behalf of at least one user possessing at least a first electronic safe, said method comprising a step of implementing access means designed to provide said user with access, via a second safe belonging to said user, to a set of data forming part of a content accessible via the first electronic safe, said implementation step being intended to be carried out in the event of authentication of said user as the user owning the first electronic safe. | 2009-08-20 |
20090206989 | ELECTRONIC COMMUNICATION SYSTEM, IN PARTICULAR ACCESS CONTROL SYSTEM FOR P(ASSIVE)K(EYLESS)E(NTRY), AS WELL AS METHOD FOR DETECTING A RELAY ATTACK THEREON - In order to provide an electronic communication system ( | 2009-08-20 |
20090206990 | AFTERMARKET CONVENIENCE ENTRY AND START SYSTEM - A user detection system for a vehicle has a security system including a portable transponder, a touch sensor, a control system in communication with the touch sensor and the security system. A method installs the user detection system in the vehicle. The touch sensor includes a sensor strip installed on the exterior surface proximate the handle and a coating for covering the sensor strip, the coating visibly matching the exterior surface. The control system is operable to transmit the identification signal in response to receiving the sensor contact signal. The control system is operable to transmit the disable command to the security system upon authentication of the reply. An aftermarket push-to-start system includes a steering lock disabling device. | 2009-08-20 |
20090206991 | INCREMENTING COUNTER WITH EXTENDED WRITE ENDURANCE - A method and device for writing a binary count of a length n to a memory having a limited number of write cycles, a physical storage location of bits (R-bits) of the count in the memory are periodically changed, fixed bits of the count are stored at fixed physical storage locations, and a bit value pattern of the fixed bits is used as an indicator for the physical storage locations of the changing bits (R-bits). | 2009-08-20 |
20090206992 | Proximity-Based Healthcare Management System With Automatic Access To Private Information - A healthcare management system and method provide efficient and secure access to private information. A portable physical device, referred to herein as a Personal Digital Key or “PDK”, stores one or more profiles in memory. The biometric profile is acquired in a secure trusted process and is uniquely associated with an individual that is authorized to use and is associated with the PDK. The PDK can wirelessly transmit the identification information including a unique PDK identification number and the biometric profile over a secure wireless channel for use in an authentication process. The PDK is configured to wirelessly communicate with a reader. A provider interface coupled to the reader, and the reader is further configured to receive profile information from the PDK. The healthcare management system also includes an auto login server configured to communicate with the provider interface to allow access to information in a patient database. | 2009-08-20 |
20090206993 | METHOD AND SYSTEM FOR BIO-METRIC VOICE PRINT AUTHENTICATION | 2009-08-20 |
20090206994 | CARD HAVING RFID TAG - A card having radio frequency identification (RFID) tag receives a first electrical signal having a first message sent by a RFID reader and returns a second electrical signal having a second message to the RFID reader in response to the first electrical signal. The card having RFID tag includes a coil, a microprocessor chip, a switch, and a display. The microprocessor chip is disposed in the card and electrically connected to the coil. The switch is disposed between the coil and the microprocessor chip. The display is controlled by the microprocessor chip to display the first message or the second message. The switch is used to control whether to start the RFID tag or not, and then the display displays the transmitted or received message, so as to protect data from being stolen and efficiently control the transmitted and received messages. | 2009-08-20 |
20090206995 | RFID Tag with a Releasable Coupler - A radio-frequency identification (RFID) tag is provided that comprises an RFID transceiver configured to transmit and receive radio frequency (RF) signals, the RFID transceiver comprising an integrated circuit chip (IC) coupled to an antenna having an impedance, gain and directionality that in conjunction with the characteristics of the IC defines a first read range of the RFID tag. The RFID tag also comprises a releasable coupler configured to be releasably engagable with the RFID transceiver comprising a coupling material, the releasable coupler being configured such that when the releasable coupler is releasably engaged with the RFID transceiver, the coupling material altering at least one of the impedance, the gain and the directionality of the antenna to define a second read range of the RFID tag, wherein the second read range is greater than the first read range. | 2009-08-20 |
20090206996 | Phone number identifiers for ISO 11784/85 compatible transponders and associated systems and methods - Systems and methods are disclosed for identifying animals with radio frequency identification transponders using phone number identifiers stored within ISO 11784 code structures in ISO 11784/85 compatible implantable transponders. These phone identification (ID) transponders feature unique telephone numbers, allowing pets to be returned to their owners through direct phone contact, for which ISO 11784 standard does not provide. The phone number information can be stored prior to implantation or after implantation depending upon the type of transponders being utilized. More particularly, within the ISO 11784 code structure, phone number related country codes are stored in bits 17-26, and phone numbers are stored in bits 27-64. Un-used digits can be filled by adding leading zeros or trailing zeros or both, as desired. In addition, variations can be provided to account for particular country conditions, such as 12-digit phone numbers in Germany. | 2009-08-20 |