34th week of 2014 patent applcation highlights part 18 |
Patent application number | Title | Published |
20140231817 | III-N MATERIAL GROWN ON ALO/ALN BUFFER ON SI SUBSTRATE - III-N material grown on a silicon substrate includes a single crystal buffer positioned on a silicon substrate. The buffer is substantially crystal lattice matched to the surface of the silicon substrate and includes aluminum oxynitride adjacent the substrate and aluminum nitride adjacent the upper surface. A first layer of III-N material is positioned on the upper surface of the buffer. An inter-layer of aluminum nitride (AlN) is positioned on the first III-N layer and an additional layer of III-N material is positioned on the inter-layer. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. | 2014-08-21 |
20140231818 | AlN CAP GROWN ON GaN/REO/SILICON SUBSTRATE STRUCTURE - III-N material grown on a silicon substrate includes a single crystal rare earth oxide layer positioned on a silicon substrate. The rare earth oxide is substantially crystal lattice matched to the surface of the silicon substrate. A first layer of III-N material is positioned on the surface of the rare earth oxide layer. An inter-layer of aluminum nitride (AlN) is positioned on the surface of the first layer of III-N material and an additional layer of III-N material is positioned on the surface of the inter-layer of aluminum nitride. The inter-layer of aluminum nitride and the additional layer of III-N material are repeated n-times to reduce or engineer strain in a final III-N layer. A cap layer of AlN is grown on the final III-N layer and a III-N layer of material with one of an LED structure and an HEMT structure is grown on the AlN cap layer. | 2014-08-21 |
20140231819 | LED DEVICE - An LED device is disclosed in which an LED chip is encapsulated in a encapsulant. The LED device includes an LED chip mounted on a support and electrically connected and an encapsulant encapsulating the LED chip, wherein the encapsulant is a transparent amorphous solid made of a metal oxide, and the solid contains as a major component at least one metal oxide selected from the group consisting of Al | 2014-08-21 |
20140231820 | MEMORY DEVICE USING GRAPHENE AS CHARGE-TRAP LAYER AND METHOD OF OPERATING THE SAME - A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges. | 2014-08-21 |
20140231821 | LIGHT-EMITTING DEVICE - A light-emitting device includes a plurality of LED chips arranged in series and each including a chip substrate and a crystal layer including a light-emitting layer. One of the plurality of LED chips is configured such that the chip substrate thereof includes a side surface facing another adjacent LED chip of the plurality of LED chips. The side surface has a highest cleavability among all side surfaces of the chip substrate of the one of the plurality of LED chips. | 2014-08-21 |
20140231822 | VERTICAL TOPOLOGY LIGHT-EMITTING DEVICE - A vertical topology light emitting device comprises a metal support structure; an adhesion structure on the metal support structure, wherein the adhesion structure comprises a first adhesion layer and a second adhesion layer on the first adhesion layer; a metal layer on the adhesion structure, wherein the adhesion structure is thicker than the metal layer; a GaN-based semiconductor structure on the metal layer, wherein the GaN-based semiconductor structure has a thickness less than 5 micrometers; a multi-layered electrode structure on the GaN-based semiconductor structure; and a protective layer on a side surface and a top surface of the GaN-based semiconductor structure, wherein the protective layer is further disposed on the multi-layered electrode structure. | 2014-08-21 |
20140231823 | ELECTRODES FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A III-N semiconductor HEMT device includes an electrode-defining layer on a III-N material structure. The electrode-defining layer has a recess with a first sidewall proximal to the drain and a second sidewall proximal to the source, each sidewall comprising a plurality of steps. A portion of the recess distal from the III-N material structure has a larger width than a portion of the recess proximal to the III-N material structure. An electrode is in the recess, the electrode including an extending portion over the first sidewall. A portion of the electrode-defining layer is between the extending portion and the III-N material structure. The first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle. | 2014-08-21 |
20140231824 | NITRIDE SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR LAYER - According to one embodiment, a nitride semiconductor device includes a foundation layer and a functional layer. The foundation layer is formed on an Al-containing nitride semiconductor layer formed on a silicon substrate. The foundation layer has a thickness not less than 1 micrometer and including GaN. The functional layer is provided on the foundation layer. The functional layer includes a first semiconductor layer. The first semiconductor layer has an impurity concentration higher than an impurity concentration in the foundation layer and includes GaN of a first conductivity type. | 2014-08-21 |
20140231825 | DIAMOND GaN DEVICES AND ASSOCIATED METHODS - Semiconductor devices and methods of making thereof are provided. In one aspect, for example, a method for making a semiconductor device can include polishing a working surface of a diamond layer to a substantially flat surface, depositing a buffer layer on the working surface of the diamond layer, and depositing a semiconductor layer on the buffer layer. In one specific aspect, the c-axis of the buffer layer is oriented perpendicular to the working surface of the diamond layer. | 2014-08-21 |
20140231826 | Methods of Growing a Silicon Carbide Epitaxial Layer on a Substrate to Increase and Control Carrier Lifetime - A method of growing an epitaxial layer on a substrate is generally provided. According to the method, the substrate is heated in a chemical vapor deposition chamber to a growth temperature in the presence of a carbon source gas, then the epitaxial layer is grown on the substrate at the growth temperature, and finally the substrate is cooled in a chemical vapor deposition chamber to at least about 80% of the growth temperature in the presence of a carbon source gas. Substrates formed from this method can have a carrier lifetime between about 0.25 μs and about 9.9 μs. | 2014-08-21 |
20140231827 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed. | 2014-08-21 |
20140231828 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first cell and a second cell. Each of the first cell and the second cell includes a first silicon carbide semiconductor layer including a first region and a second region provided in the first region, a second silicon carbide semiconductor layer provided on and in contact with the first silicon carbide semiconductor layer, a first ohmic electrode in ohmic contact with the second region, and an insulating film provided on the second silicon carbide semiconductor layer. The first cell includes a gate electrode, and the second cell includes no electrode configured to control the electric potential of the second silicon carbide semiconductor layer independently of the electric potential of the first ohmic electrode. | 2014-08-21 |
20140231829 | SEMICONDUCTOR DEVICE - Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP | 2014-08-21 |
20140231830 | CRYSTAL LAYERED STRUCTURE AND METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR ELEMENT - Provided is a crystal layered structure having a low dislocation density on the upper surface of a nitride semiconductor layer on a Ga | 2014-08-21 |
20140231831 | LED CHIP AND METHOD FOR MANUFACTURING THE SAME - The invention provides a substrate structure used for manufacturing a light-emitting diode and a method for manufacturing the light-emitting diode. The substrate structure includes a substrate having a first surface and a second surface opposite to the first surface and a plurality of grooving structure formed on the first surface of the substrate. The light-emitting diode is formed on the first surface of the substrate. | 2014-08-21 |
20140231832 | THREE-TERMINAL LIGHT EMITTING DEVICE (LED) WITH BUILT-IN ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE - A three-terminal light emitting device (LED) chip, associated fabrication method, and LED array are provided. The method forms an n-doped semiconductor layer overlying a substrate, an active semiconductor layer overlying the n-doped semiconductor layer, and a p-doped semiconductor layer overlying the active semiconductor layer. A trench is formed through the p-doped and active semiconductor layers, exposing the n-doped semiconductor layer. In one aspect, the trench is formed at least part way, but not completely, through the n-doped semiconductor layer. Then, an LED P electrode is formed overlying a first region of the p-doped semiconductor layer, a diode P electrode is formed overlying a second region of the p-doped semiconductor layer that is separated from the first region of the p-doped semiconductor layer by the trench, and an N electrode is formed overlying a top surface of the exposed n-doped semiconductor layer in the trench, shared by the LED and diode. | 2014-08-21 |
20140231833 | LIGHT EMITTING DEVICE - A first light emitting structure includes a first semiconductor layer, an active layer, and a second semiconductor layer. A second light emitting structure includes a third semiconductor layer, an active layer, and a fourth semiconductor layer. A first electrode and a second electrode connect to the first semiconductor layer, and the second semiconductor layer, respectively. A third electrode and a fourth electrode connect to the third semiconductor layer, and the fourth semiconductor layer, respectively. A first contact portion includes a first region connected to the first electrode and a second region making contact with a top surface of the first semiconductor layer, and a second contact portion connects to the second and third electrodes. A third contact portion includes a first region connected to the third electrode and a second region making contact with a top surface of the third semiconductor layer. | 2014-08-21 |
20140231834 | TRANSPARENT LED LAYER BETWEEN PHOSPHOR LAYER AND LIGHT EXIT SURFACE OF LAMP - A flexible light sheet lamp includes a thin substrate and an array of printed microscopic vertical LEDs (VLEDs) sandwiched between a transparent first conductor layer and a transparent second conductor layer. The light sheet has a light exit surface. The VLEDs have one surface, facing the light exit surface of the light sheet, covered with a reflective metal. A phosphor layer is provided such that the semi-transparent VLED layer is between the phosphor layer and the light exit surface. A reflector layer is provided such that the phosphor layer is between the reflector layer and the VLED layer. The substrate may form the light exit surface or the light exit surface may be the opposite side of the light sheet. Some VLED light passing through the phosphor layer is reflected by the reflector layer and re-enters the phosphor layer. Therefore, less phosphor is needed to achieve the desired conversion ratio. | 2014-08-21 |
20140231835 | STACKED ASSEMBLY OF LIGHT EMITTING DEVICES - A stacked assembly of light emitting devices includes a first light emitting device, a second light emitting device and a sealing member. The first light emitting device includes a first substrate member extending in a longitudinal direction and defining a plurality of through-holes, and a plurality of first light emitting elements arranged on the first substrate member. The second light emitting device is arranged to overlap with the first light emitting device. The second light emitting device includes a second substrate member extending in the longitudinal direction, and a plurality of second light emitting elements arranged on the second substrate and exposed respectively through the through-holes. The sealing member seals the first light emitting elements and the second light emitting elements. | 2014-08-21 |
20140231836 | STRUCTURE AND METHOD FOR LED WITH PHOSPHOR COATING - The present disclosure provides a light emitting diode (LED) apparatus. The LED apparatus includes an LED emitter having a top surface; and a phosphor feature disposed on the LED emitter. The phosphor feature includes a first phosphor film disposed on the top surface of the LED emitter and having a first dimension defined in a direction parallel to the top surface of the LED emitter; a second phosphor film disposed on the first phosphor film and having a second dimension defined in the direction; and the second dimension is substantially less than the first dimension. | 2014-08-21 |
20140231837 | LED Module - An LED module has an electrically insulating main body, a base surface and a mounting surface located opposite the base surface. A number of electrical connection contacts are arranged at the mounting surface. The connection contacts do not adjoin the base surface. A heat sink is arranged in the main body. The heat sink extends from the mounting surface as far as the base surface. Furthermore, the LED module has a number of LED chips, each having an electrically insulating carrier substrate at a chip underside and two chip contacts at a chip top side. The LED chips are arranged with the electrically insulating carrier substrate on the heat sink. | 2014-08-21 |
20140231838 | SEMICONDUCTOR LIGHT-EMISSION DEVICE AND MANUFACTURING METHOD - A semiconductor light-emission device includes: a p-type conductive layer that is one or more layers each made of a III-V compound semiconductor; an active layer made of a III-V compound semiconductor; and an electron barrier layer inserted between the p-type conductive layer and the active layer, and made of a III-V compound semiconductor. The electron barrier layer includes first and second regions. The first region is provided closer to the active layer than the second region, has a first interface and a second interface located farther from the active layer than the first interface, and has a band gap of a fixed magnitude. The second region is provided in contact with the second interface, and has a band gap smaller than the band gap of the first region and becomes smaller from an interface with the first region towards an interface with the p-type conductive layer of the second region. | 2014-08-21 |
20140231839 | Semiconductor Light Emitting Device - The present disclosure relates to a semiconductor light emitting device, comprising: a plurality of semiconductor layers, including a first semiconductor layer having a first conductivity, a second semiconductor layer having a second conductivity different from the first conductivity, and an active layer interposed between the first semiconductor layer and the second semiconductor layer, generating light via electron-hole recombination; a first electrode, supplying either electrons or holes to the plurality of semiconductor layers; a second electrode, supplying, to the plurality of semiconductor layers, electrons if the holes are supplied by the first electrode, or holes if the electrons are supplied by the first electrode; a non-conductive distributed bragg reflector coupled to the plurality of semiconductor layers, reflecting the light from the active layer; and a first light-transmitting film coupled to the distributed bragg reflector from a side opposite to the plurality of semiconductor layers with respect to the non-conductive distributed bragg reflector, with the first light-transmitting film having a refractive index lower than an effective refractive index of the distributed bragg reflector. | 2014-08-21 |
20140231840 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD FOR PRODUCING SAME - Disclosed is a nitride semiconductor light-emitting element comprising a p-type nitride semiconductor layer | 2014-08-21 |
20140231841 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device is disclosed including a light emitting structure comprising a lower layer of the first conductivity type, an active layer, an upper layer of the second conductivity type; a first electrode connected to the lower layer of the first conductivity type; a second electrode connected to the upper layer of the second conductivity type. The light emitting structure is formed using a shell member, which comprises a planar portion and a shell portion. The extent of growth defects such as misfit dislocations is reduced and the extraction of light and heat is improved in the present device. The beam profile of the device may be altered by patterning the light emitting structure instead of shaping the entire chip. The device may be manufactured in a way more compatible with the established, cost-effective processing and packaging methods for large size wafers from the IC industry. | 2014-08-21 |
20140231842 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, a first insulating film, a first interconnection layer, a second interconnection layer, a first metal pillar, a second metal pillar, a second insulating film and a fluorescent material layer. The first electrode is provided in an emitting region of the semiconductor layer. The first electrode, the first insulating film, the first interconnection layer, the second interconnection layer, and the second insulating layer are configured to transmit radiated light of the light emitting layer. | 2014-08-21 |
20140231843 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode and a fluorescent material layer. The semiconductor layer has a first surface and a second surface on an opposite side to the first surface and includes a light emitting layer. The fluorescent material layer includes a plurality of fluorescent materials and a bonding material integrating the fluorescent materials. The fluorescent material layer includes a lower layer portion provided to spread over the entire first surface and having a larger thickness than a size of the fluorescent materials and an upper layer portion partially provided on the lower layer portion and having a larger thickness and a larger width than a size of the fluorescent materials. The fluorescent materials do not exist on a portion of the lower layer portion not provided with the upper layer portion. | 2014-08-21 |
20140231844 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a fluorescent material layer and a scattering layer. The semiconductor layer has a first surface and a second surface on an opposite side to the first surface and includes a light emitting layer. The p-side electrode and the n-side electrode are provided on the semiconductor layer on a side of the second surface. The fluorescent material layer is provided on a side of the first surface and includes a plurality of fluorescent materials and a first bonding material. The first bonding material integrates the fluorescent materials. The scattering layer is provided on the fluorescent material layer and includes scattering materials and a second bonding material. The scattering materials are configured to scatter radiated light of the light emitting layer. The second bonding material integrates the scattering materials. | 2014-08-21 |
20140231845 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, a fluorescent material layer and a reflection film. The semiconductor layer has a first surface and a second surface on an opposite side to the first surface and includes a light emitting layer. The p-side electrode and the n-side electrode are provided on the semiconductor layer on a side of the second surface. The fluorescent material layer is provided on a side of the first surface and includes a plurality of fluorescent materials and a bonding material. The bonding material integrates the fluorescent materials. The reflection film is partially provided on the fluorescent material layer and has a higher reflectance to the radiated light of the light emitting layer than to the radiated light of the fluorescent materials. | 2014-08-21 |
20140231846 | LIGHT EMITTING MODULE - A light emitting module includes a light-emitting unit, a wavelength converting element and an optical convergent element for partially or totally converting the wavelength of incident light. The light-emitting unit includes a light-emitting element which emits a first light, the wavelength converting element and an optical convergent element disposed in a light path of the first light from the light-emitting element, such that the first light is converted into a particular light at a specific area with a reduced beam diameter after passing through the optical convergent element and before entering the wavelength converting element. | 2014-08-21 |
20140231847 | Light Emitting Module and Lighting Device - A light emitting module according to one embodiment includes a substrate; a light emitting body disposed on the substrate; a first phosphor which is excited by emitted light of the light emitting body; and a second phosphor which is arranged between the first phosphor and the light emitting body. The first phosphor has a light emitting peak whose half-value width is 20 nm or less in a wavelength range from 610 nm to less than 650 nm. The second phosphor is excited by the emitted light of the light emitting body, and has the light emitting peak in the wavelength range between a peak wavelength of a light emitting spectrum of the light emitting body and the peak wavelength of the light emitting spectrum of the first phosphor. | 2014-08-21 |
20140231848 | ENGINEERED-PHOSPHOR LED PACKAGES AND RELATED METHODS - In accordance with certain embodiments, regions of spatially varying wavelength-conversion particle concentration are formed over light-emitting dies. | 2014-08-21 |
20140231849 | SEMICONDUCTOR LIGHT-EMITTING DEVICES - Semiconductor light-emitting devices including a semiconductor region that includes a light-emitting structure; and an electrode layer including a first reflection metal layer that contacts a first portion of the semiconductor region and being configured to reflect light from the light-emitting structure and a second reflection metal layer that contacts a second portion of the semiconductor region and being configured to reflect light from the light-emitting structure, wherein the second reflection metal layer is spaced apart from the first reflection metal layer and at least partially covers the first reflection metal layer. | 2014-08-21 |
20140231850 | ENGINEERED-PHOSPHOR LED PACKAGES AND RELATED METHODS - In accordance with certain embodiments, regions of spatially varying wavelength-conversion particle concentration are formed over light-emitting dies. | 2014-08-21 |
20140231851 | LIGHT EMITTING DIODE - A light emitting diode includes a semiconductor stacked structure, a substrate, a first electrode, a second electrode and a third electrode. The semiconductor stacked structure includes a first semiconductor layer, a second semiconductor layer and a light emitting layer. The first semiconductor layer has a first surface and a second surface opposite to each other and has a first region and a second region. The second semiconductor layer is disposed on the second surface. The light emitting layer is disposed between the first semiconductor layer and the second semiconductor layer. The substrate has a first conductive layer and a second conductive layer thereon. The first electrode is disposed between the second semiconductor layer and the first conductive layer. The second electrode is disposed on the first surface. The third electrode is disposed between the second region and the second conductive layer, and electrically connected to the second electrode. | 2014-08-21 |
20140231852 | LED CHIP RESISTANT TO ELECTROSTATIC DISCHARGE AND LED PACKAGE INCLUDING THE SAME - A light emitting diode chip and a light emitting diode package including the same. The light emitting diode chip includes a substrate, a light emitting diode section disposed on the substrate, an inverse parallel diode section disposed on the substrate and connected inversely parallel to the light emitting diode section. In the light emitting diode chip, the light emitting diode section is disposed together with the inverse parallel diode section. | 2014-08-21 |
20140231853 | GROUP-III NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND MANUFACTURING METHOD THEREFOR - A group-III nitride semiconductor light emitting element includes a semiconductor layer that includes a light emitting layer, a p-type semiconductor layer and an n-type semiconductor layer, a p-contact electrode that is in contact with the p-type semiconductor layer, an n-contact electrode that is in contact with the n-type semiconductor layer, and a support substrate that supports the semiconductor layer. The p-contact electrode and the n-contact electrode are disposed at a position between the semiconductor layer and the support substrate. In a case where the p-contact electrode and the n-contact electrode are orthogonally projected on a plate surface of the support substrate, the p-contact electrode and the n-contact electrode are formed in a shape in which the orthogonally projected p-contact electrode and the orthogonally projected n-contact electrode are not overlapped with each other. | 2014-08-21 |
20140231854 | ENGINEERED-PHOSPHOR LED PACKAGES AND RELATED METHODS - In accordance with certain embodiments, regions of spatially varying wavelength-conversion particle concentration are formed over light-emitting dies. | 2014-08-21 |
20140231855 | METHOD FOR PRODUCING A LIGHT-EMITTING DIODE AND LIGHT-EMITTING DIODE - A method of producing a light-emitting diode includes providing at least one light-emitting diode chip, providing a suspension comprising a solvent and particles of at least one luminescent material, arranging the at least one light-emitting diode chip in the suspension, electrophoretically depositing the particles on an outer face of the at least one light-emitting diode chip, and completing the light-emitting diode. | 2014-08-21 |
20140231856 | Method for Producing at Least One Radiation-Emitting and/or -Receiving Semiconductor Component, and Semiconductor Component - A method for producing a radiation-emitting or radiation-receiving semiconductor component is specified. In a method step, a carrier body having a mounting surface is provided. In a further method step, a barrier frame is formed on the mounting surface, in such a way that the barrier frame laterally encloses a mounting region of the mounting surface. In a further method step, a radiation-emitting or radiation-receiving semiconductor chip is mounted within the mounting region on the mounting surface. The semiconductor chip is potted with a liquid lens material, wherein the lens material is applied to the mounting surface within the mounting region. The lens material is cured. The mounting surface, the barrier frame and the lens material are adapted to one another. | 2014-08-21 |
20140231857 | PHOSPHOR MATERIALS AND RELATED DEVICES - A phosphor material is presented that includes a blend of a first phosphor, a second phosphor and a third phosphor. The first phosphor includes a composition having a general formula of RE | 2014-08-21 |
20140231858 | LED Sub-Mount and Method for Manufacturing Light Emitting Device Using the Sub-Mount - A LED sub-mount includes a substrate body and a plurality of first electrical-conductive layers. The substrate body has a first surface. The first electrical-conductive layers are positioned on the first surface of the substrate body, wherein the first surface between every adjacent two of the first electrical-conductive layers has an adhesive-filling groove. | 2014-08-21 |
20140231859 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT - A semiconductor light emitting device may include: a light emitting structure including an n-type semiconductor layer, a p-type semiconductor layer, and an active layer interposed therebetween; a first electrode connected to one of the n-type semiconductor layer and the p-type semiconductor layer; and a second electrode connected to the other of the n-type semiconductor layer and the p-type semiconductor layer. The first electrode may include a first electrode pad disposed in a central portion of one side of the light emitting structure and first to third branch electrodes connected to the first electrode pad, having a fork shape. The second electrode may include second and third electrode pads disposed separately in both corners of the other side opposing the one side and fourth to seventh branch electrodes connected thereto. The fourth and seventh branch electrodes may extend in an interdigitated manner between the first to third branch electrodes. | 2014-08-21 |
20140231860 | LIGHT EMITTING ELEMENT - A heat radiation structure of a light emitting element has leads, each lead having a plurality of leg sections, and a light emitting chip mounted on any one of the leads. The present invention can provide a high-efficiency light emitting element, in which a thermal load is reduced by widening a connecting section through which a lead and a chip seating section of the light emitting element are connected, and the heat generated from a heat source can be more rapidly radiated to the outside. Further, the present invention can also provide a high-efficiency light emitting element, in which heat radiation fins are formed between a stopper and a molding portion of a lead of the light emitting element so that natural convection can occur between the heat radiation fins, and an area in which heat radiation can occur is widened to maximize a heat radiation effect. | 2014-08-21 |
20140231861 | CURABLE COMPOSITION AND METHOD FOR MANUFACTURING THE SAME - A curable composition comprises the following: (A) a branched polymer having an average unit formula (I′): | 2014-08-21 |
20140231862 | CURABLE COMPOSITION AND METHOD FOR MANUFACTURING THE SAME - A curable composition comprises the following: (A) a polymer having at least two silicon-bonded alkenyl groups and having an average unit formula (I′): | 2014-08-21 |
20140231863 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND FABRICATION METHOD THEREOF - A method of fabricating a nitride semiconductor light emitting device is provided. The method includes growing a first group-III-nitride semiconductor layer on a substrate, the first group-III-nitride semiconductor layer having a top surface formed as a group-III-rich surface exhibiting a group-III-polarity and a bottom surface formed as a N-rich surface exhibiting a N-polarity. The method further includes selectively etching a N-polarity region in the top surface of the first group III nitride semiconductor layer, forming a second group III nitride semiconductor layer on the first group III nitride semiconductor layer to fill the etched N-polarity region and forming a light emitting structure including first and second conductivity type nitride semiconductor layers and an active layer on the second group III nitride semiconductor layer. | 2014-08-21 |
20140231864 | HIGH VOLTAGE ELECTROSTATIC DISCHARGE PROTECTION DEVICE - An electrostatic discharge protection device is provided. The electrostatic discharge protection device can include a semiconductor substrate having a first well and a second well, a silicon controller rectifier (SCR) device, and first and second impurity areas disposed on the first and second wells to form a PN junction. The SCR can have a PNPN structure or an NPNP structure, and the PN junction structure and the SCR device can be alternately disposed when the substrate is viewed from above. | 2014-08-21 |
20140231865 | INSULATED GATE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An insulated gate semiconductor device includes a region that is provided between trenches in which a gate electrode is filled through a gate insulating film in a surface layer of a substrate, includes a p base region and an n+ emitter region, and comes into conductive contact with an emitter electrode and a p-type floating region that is electrically insulated by an insulating film which is interposed between the p-type floating region and the emitter electrode. The p-type floating region is deeper than the trench and has a lower impurity concentration than the p base region. | 2014-08-21 |
20140231866 | IGBT AND METHOD OF MANUFACTURING THE SAME - An IGBT has an emitter region, a top body region that is formed below the emitter region, a floating region that is formed below the top body region, a bottom body region that is formed below the floating region, a trench, a gate insulating film that covers an inner face of the trench, and a gate electrode that is arranged inside the trench. When a distribution of a concentration of p-type impurities in the top body region and the floating region, which are located below the emitter region, is viewed along a thickness direction of a semiconductor substrate, the concentration of the p-type impurities decreases as a downward distance increases from an upper end of the top body region that is located below the emitter region, and assumes a local minimum value at a predetermined depth in the floating region. | 2014-08-21 |
20140231867 | DIODE AND SEMICONDUCTOR DEVICE INCLUDING BUILT-IN DIODE - A diode is provided with a pillar region formed so as to extend between a barrier region and an anode electrode, contact the barrier region, and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region; and a barrier height adjusting region formed so as to be located between the pillar region and the anode electrode, and contact the pillar region and the anode electrode. The barrier height adjusting region includes at least one component selected from the group consisting of a second conductivity type semiconductor having a concentration lower than that of an anode region, the first conductivity type semiconductor having a concentration lower than that of the pillar region, and an i-type semiconductor. The barrier height adjusting region and the anode electrode are connected through a Schottky junction. | 2014-08-21 |
20140231868 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate and a first electrode. An element region, and a non-element region that surrounds this element region, are formed on the semiconductor substrate. The first electrode is arranged on the semiconductor substrate and is electrically connected to the element region formed on the semiconductor substrate. The first electrode is made of at least two materials having different moduli of elasticity. A modulus of elasticity per unit area of an outer peripheral portion of the first electrode when the semiconductor substrate is viewed from above is smaller than a modulus of elasticity per unit area of a center portion of the first electrode. | 2014-08-21 |
20140231869 | Silicon Devices/Heatsinks Stack Assembly And A Method To Pull Apart A Faulty Silicon Device In Said Stack Assembly - The invention concerns a silicon devices/heatsinks stack assembly and a method to pull apart a faulty silicon device in said stack assembly. Said silicon devices/heatsinks stack assembly comprises an arrangement of many silicon devices disks, two adjacent silicon devices disks being separated by a flat heatsink device, each silicon device disk and each heatsink comprising a centering hole on its both faces, a centering pin placed between the adjacent centering holes of a silicon device disk and an adjacent heatsink device. Each heatsink device is pierced with two guide holes, at two opposite ends of this one. | 2014-08-21 |
20140231870 | SEMICONDUCTOR STRUCTURE HAVING SILICON DEVICES, COLUMN III-NITRIDE DEVICES, AND COLUMN III-NON-NITRIDE OR COLUMN II-VI DEVICES - A semiconductor structure having a silicon substrate having a <111> crystallographic orientation, an insulating layer disposed over a first portion of the silicon substrate, a silicon layer having a <100> orientation disposed over the insulating layer, and a non-nitride column semiconductor layer or column II-VI semiconductor layer having the same <111> crystallographic orientation as the silicon substrate, the non-nitride column III-V semiconductor layer or column II-VI semiconductor layer being in direct contact with a second portion of the silicon substrate. A column III-nitride is disposed on the surface of the third portion of the substrate. | 2014-08-21 |
20140231871 | METHODS OF CONTAINING DEFECTS FOR NON-SILICON DEVICE ENGINEERING - An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor. | 2014-08-21 |
20140231872 | METHOD FOR INDUCING STRAIN IN FINFET CHANNELS - FinFETs in which a swelled material within the fin, typically an oxide of the fin semiconductor, causes strain that significantly increases charge carrier mobility within the FinFET channel. The concept can be applied to either p-type or n-type FinFETs. For p-type FinFETs the swelled material is positioned underneath the source and drain regions. For n-type FinFETs the swelled material is positioned underneath the channel region. The swelled material can be used with or without strain-inducing epitaxy on the source and drain areas and can provide greater strain than is achievable by strain-inducing epitaxy alone. | 2014-08-21 |
20140231873 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a semiconductor multilayer formed on a substrate, a first ohmic electrode and a Schottky electrode spaced apart from each other on the semicnductor multilayer; and a passivation film covering a top of the semiconductor multilayer. The semiconductor multilayer | 2014-08-21 |
20140231874 | SEMICONDUCTOR DEVICE - A semiconductor device includes a HEMT and a diode. The HEMT includes: a substrate having a GaN layer as a channel layer generating a two-dimensional electron gas and an AlGaN layer as a barrier layer on the GaN layer; a source electrode on the AlGaN layer ohmic contacting the AlGaN layer; a drain electrode on the AlGaN layer apart from the source electrode and ohmic contacting the AlGaN layer; an inter-layer insulating film on the AlGaN layer between the source electrode and the drain electrode; and a gate electrode on the inter-layer insulating film. The substrate includes an active layer region generating the two dimensional electron gas in the GaN layer. The diode includes an anode electrically connected to the gate electrode and a cathode electrically connected to the drain electrode. | 2014-08-21 |
20140231875 | INTEGRATED CIRCUITS WITH ESD PROTECTION DEVICES - An integrated circuit with ESD protection comprises at least one ESD protection circuit block, which comprises a DC blocking capacitor connected in parallel with at least one compound semiconductor enhancement mode FET as an ESD protection device. The ESD protection circuit block that is built in an integrated circuit provides ESD protection while minimizing the generation of unwanted nonlinear signals resulting from the ESD protection. An integrated circuit comprises a high frequency circuit, a switching element, and two ESD protection circuit blocks, in which the high frequency circuit is connected between a first terminal and a second terminal for inputting or outputting the RF signals, the first ESD protection circuit block is connected from a branch node between the first terminal and the high frequency circuit to the switching element, and the second ESD protection circuit block is connected from the switching element to the ground. | 2014-08-21 |
20140231876 | pHEMT and HBT integrated epitaxial structure - An improved pseudomorphic high electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) integrated epitaxial structure, in which the structure comprises a substrate, a pHEMT structure, an etching-stop spacer layer, and an HBT structure. The pHEMT structure comprises a buffer layer, a bottom barrier layer, a first channel spacer layer, a channel layer, a second channel spacer layer, a Schottky spacer layer, a Schottky donor layer, a Schottky barrier layer, an etching-stop layer, and at least one cap layer. By introducing the first channel spacer layer and the second channel spacer layer to reduce the density of the dislocations and to reduce the compressive strain in the pseudomorphic channel layer. | 2014-08-21 |
20140231877 | COLLECTOR-UP BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY - Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region. | 2014-08-21 |
20140231878 | COLLECTOR-UP BIPOLAR JUNCTION TRANSISTORS IN BICMOS TECHNOLOGY - Fabrication methods, device structures, and design structures for a bipolar junction transistor. An emitter is formed in a device region defined in a substrate. An intrinsic base is formed on the emitter. A collector is formed that is separated from the emitter by the intrinsic base. The collector includes a semiconductor material having an electronic bandgap greater than an electronic bandgap of a semiconductor material of the device region. | 2014-08-21 |
20140231879 | Pixel Structure - A pixel structure comprises an epitaxial layer ( | 2014-08-21 |
20140231880 | IMAGING SENSOR - An imaging sensor of the charge transfer type that limits the transmission of radiation from high intensity light sources. The invention addresses potential saturation levels during exposure or stare time and so saturation is never achieved, this provides for a wider dynamic range. | 2014-08-21 |
20140231881 | DEPLETED CHARGE-MULTIPLYING CCD IMAGE SENSOR - In various embodiments, a charge-coupled device includes channel stops laterally spaced away from the channel by fully depleted regions. | 2014-08-21 |
20140231882 | Wireless Processor, Wireless Memory, Information System, And Semiconductor Device - The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna. | 2014-08-21 |
20140231883 | Vertical JFET with Integrated Body Diode - A vertical junction field effect transistor (JFET) includes a drain, a source, a gate, a drift region, and a body diode. The source, gate, drift region, and body diode are all disposed in the same compound semiconductor epitaxial layer. The drain is vertically spaced apart from the source and the gate by the drift region. The body diode is connected between the drain and the source. | 2014-08-21 |
20140231884 | BOOTSTRAP MOS FOR HIGH VOLTAGE APPLICATIONS - A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region. | 2014-08-21 |
20140231885 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING METAL GATE ELECTRODES - Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a sacrificial gate structure over a semiconductor substrate. The sacrificial gate structure includes two spacers and sacrificial gate material between the two spacers. The method recesses a portion of the sacrificial gate material between the two spacers. Upper regions of the two spacers are etched while using the sacrificial gate material as a mask. The method includes removing a remaining portion of the sacrificial gate material and exposing lower regions of the two spacers. A first metal is deposited between the lower regions of the two spacers. A second metal is deposited between the upper regions of the two spacers. | 2014-08-21 |
20140231886 | TWO-DIMENSIONAL MATERIAL STACKED FLEXIBLE PHOTOSENSOR - A flexible photosensor includes a flexible substrate, a gate on the flexible substrate, the gate including a conductive material having a planar structure, a gate insulating layer on the flexible substrate and the gate to at least cover the gate, the gate insulating layer including a non-conductive material having a planar structure, and a channel layer on the gate insulating layer, the channel layer including a semiconductor material having a planar structure. | 2014-08-21 |
20140231887 | Method and Apparatus for Image Sensor Packaging - A backside illuminated image sensor comprises a photodiode and a first transistor in a sensor region and located in a first substrate, wherein the first transistor is electrically coupled to the photodiode. The image sensor further comprises a plurality of logic circuits formed in a second substrate, wherein the second substrate is stacked on the first substrate and the logic circuit are coupled to the first transistor through a plurality of bonding pads, the bonding pads disposed outside of the sensor region. | 2014-08-21 |
20140231888 | Magneto-Electric Voltage Controlled Spin Transistors - The invention relates to a magneto-electric spin-FET including a gate film of chromia and a thin film of a conductive channel material which may be graphene, InP, GaAs, GaSb, PbS, MoS | 2014-08-21 |
20140231889 | SHIFT REGISTER MEMORY AND DRIVING METHOD THEREOF - A shift register memory according to the present embodiment includes a magnetic pillar including a plurality of magnetic layers and a plurality of nonmagnetic layers provided between the magnetic layers adjacent to each other. A stress application part applies a stress to the magnetic pillar. A magnetic-field application part applies a static magnetic field to the magnetic pillar. The stress application part applies the stress to the magnetic pillar in order to transfer magnetization states of the magnetic layers in a stacking direction of the magnetic layers. | 2014-08-21 |
20140231890 | MIM CAPACITOR IN FINFET STRUCTURE - A method of forming a FinFET structure having a metal-insulator-metal capacitor. Silicon fins are formed on a semiconductor substrate followed by formation of the metal-insulator-metal capacitor on the silicon fins by depositing sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride. A polysilicon layer is deposited over the metal-insulator-metal capacitor followed by etching back the polysilicon layer and the metal-insulator-metal capacitor layers from ends of the silicon fins so that the first and second ends of the silicon fins protrude from the polysilicon layer. A spacer may be formed on surfaces facing the ends of the silicon fins followed by the formation of epitaxial silicon over the ends of the silicon fins. Also disclosed is a FinFET structure having a metal-insulator-metal capacitor. | 2014-08-21 |
20140231891 | MIM CAPACITOR IN FINFET STRUCTURE - A FinFET structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride on the sides and horizontal surface of the silicon fins; a polysilicon gate layer over the second layer of titanium nitride on the silicon fins and over the semiconductor substrate such that first and second ends of the silicon fins protrude from the polysilicon layer; spacers adjacent to the polysilicon gate layer; epitaxial silicon over the first and second ends of the silicon fins to form sources and drains, wherein the combination of the first layer of titanium nitride, dielectric layer and second layer of titanium nitride forms a metal-insulator-metal capacitor situated between each silicon fin and the polysilicon layer. | 2014-08-21 |
20140231892 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - First dopant regions and second dopant regions are provided at both sides of the gate structures. Conductive lines cross over the gate structures and are connected to the first dopant regions. Each of the conductive lines includes a conductive pattern and a capping pattern disposed on the conductive pattern. Contact structures are provided between the conductive lines and are connected to the second dopant regions. Each of the contact structures includes a lower contact pattern disposed on the second dopant region and an upper contact pattern disposed on the lower contact pattern. A bottom surface of the upper contact pattern is lower than a top surface of the conductive pattern. | 2014-08-21 |
20140231893 | CAPACITOR AND PREPARATION METHOD THEREOF - A capacitor and a method of fabricating thereof are provided. A structure of low pressure tetraethyl orthosilicate-low pressure silicon nitride-low pressure tetraethyl orthosilicate is used in the capacitor to replace the oxide-nitride-oxide structure of the existing capacitor; the capacitor has a relatively high unit capacitance value. Furthermore, the structure of low pressure tetraethyl orthosilicate—low pressure silicon nitride—low pressure tetraethyl orthosilicate is fabricaited by low pressure chemical vapor deposition method at relatively low temperature; thus the heat produced in the whole process is relatively low, which is insufficient to make the semiconductor device shift or make the gate metal layer or the metallized silicon layer peel off. Accordingly, the capacitor and the method of fabricating the capacitor of the present invention can be well applied in the process of the 0.5 μm PIP capacitor or below 0.5 μm. | 2014-08-21 |
20140231894 | METHOD OF FORMING A DRAM ARRAY OF DEVICES WITH VERTICALLY INTEGRATED RECESSED ACCESS DEVICE AND DIGITLINE - A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate. | 2014-08-21 |
20140231895 | One-Time Programming Device and a Semiconductor Device - A one-time programming device includes a field effect semiconductor transistor with a gate or a channel region of the field effect semiconductor transistor including a shape of a footprint so that in an on-state of the field effect semiconductor transistor a critical electrical field is reached within an area of the channel region, a bulk region or a drain region of the field effect semiconductor transistor due to the shape of the footprint resulting in a damage of a p-n junction between the channel region or the bulk region and the drain region of the field effect semiconductor transistor or resulting in a damage of a gate insulation of the field effect semiconductor transistor after a predetermined programming time. | 2014-08-21 |
20140231896 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage device includes a semiconductor substrate; a first insulating film disposed above the semiconductor substrate; a first electrode film disposed above the first insulating film; a second insulating film disposed above the first electrode film; a second electrode film disposed above the second insulating film; a third electrode film filling a first trench and overlying the second electrode film, the first trench having a first width and a first depth and extending through the second electrode film and the second insulating film and into the first electrode film; and a first barrier metal film and a first metal film disposed above the third electrode film; wherein the third electrode film above the second electrode film has a first thickness equal to or less than ½ of the first width of the first trench. | 2014-08-21 |
20140231897 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a block insulating layer; an organic molecular layer, which is formed between the semiconductor layer and the block insulating layer, and contains first organic molecules and second organic molecules, and in which the first organic molecule has a first alkyl chain or a first alkyl halide chain on the semiconductor layer side and a charge trapping unit on the block insulating layer side, and the second organic molecule has a second alkyl chain or a second alkyl halide chain on the semiconductor layer side and a hydroxy group, an ether group, a carboxyl group or an ester group on the block insulating layer side; and a control gate electrode formed on the block insulating layer. | 2014-08-21 |
20140231898 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a block insulating film; an organic molecular layer, which is formed between the semiconductor layer and the block insulating film, and provided with a first organic molecular film on the semiconductor layer side containing first organic molecules and a second organic molecular film on the block insulating film side containing second organic molecules, and in which the first organic molecule has a charge storing unit and the second organic molecule is an amphiphilic organic molecule; and a control gate electrode formed on the block insulating film. | 2014-08-21 |
20140231899 | METHODS OF MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - Methods of manufacturing three-dimensional semiconductor devices that may include forming a first spacer on a sidewall inside a first opening formed in a first stack structure, forming a sacrificial filling pattern on the spacer to fill the first opening, forming a second stack structure including a second opening exposing the sacrificial filling pattern on the first stack structure, forming a second spacer on a sidewall inside the second opening, removing the sacrificial filling pattern and removing the first spacer and the second spacer. | 2014-08-21 |
20140231900 | NON-VOLATILE MEMORY - A non-volatile memory is provided. The non-volatile memory includes a oxide and polysilicon stack structure and charge storage layers. The oxide and polysilicon stack structure is disposed on a substrate. There are recesses in the substrate at two sides of the oxide and polysilicon stack structure. The oxide and polysilicon stack structure includes an oxide layer and a polysilicon layer. The oxide layer is disposed on the substrate, wherein there is an interface between the oxide layer and the substrate. The polysilicon layer is disposed on the oxide layer. The charge storage layers are disposed in the recesses and extend to a side wall of the oxide and polysilicon stack structure, and a top surface of each of the charge storage layers is higher than the interface. | 2014-08-21 |
20140231901 | Monolithic MOSFET and Schottky Diode for Mobile Phone Boost Converter - A cell phone has a plurality of interconnected electronic components for performing the electrical functions of the phone. A DC/DC converter provides an operating voltage which is applied to power supply terminals of the plurality of interconnected electronic components. The DC/DC converter uses a monolithic semiconductor device containing a power metal oxide semiconductor field effect transistor (MOSFET) and Schottky diode. The semiconductor device has the lateral diffused MOSFET formed on a surface of the semiconductor device. The MOSFET is formed with a plurality conduction fingers. The Schottky diode is also formed on the surface of the semiconductor device and integrated between the plurality of conduction fingers of the MOSFET. The drain of the MOSFET is connected to the anode of the diode on the surface of the monolithic semiconductor device. | 2014-08-21 |
20140231902 | Vertical Tunneling Field-Effect Transistor Cell - A tunneling field-effect transistor (TFET) device is disclosed. The TFET device includes a source contact on the source region, a plurality of gate contacts at a planar portion of a gate stack and a plurality of drain contacts disposed on a drain region. The source contact of the TFET device aligns with other two adjacent source contacts of other two TFET devices such that each source contact locates in one of three angles of an equilateral triangle. | 2014-08-21 |
20140231903 | Semiconductor Device with a Super Junction Structure Having a Vertical Impurity Distribution - A super junction semiconductor device includes a semiconductor portion with parallel first and second surfaces. An impurity layer of a first conductivity type is formed in the semiconductor portion. Between the first surface and the impurity layer a super junction structure includes first columns of the first conductivity type and second columns of a second conductivity type. A sign of a compensation rate between the first and second columns may change along a vertical extension of the columns perpendicular to the first surface. A body zone of the second conductivity type is formed between the first surface and one of the second columns. A field extension zone of the second conductivity type may be electrically connected to the body zone or a field extension zone of the first conductivity type may be connected to the impurity layer. The field extension zone improves the avalanche characteristics of the semiconductor device. | 2014-08-21 |
20140231904 | Super Junction Semiconductor Device with Overcompensation Zones - According to an embodiment, a super junction semiconductor device may be manufactured by introducing impurities of a first impurity type into an exposed surface of a first semiconductor layer of the first impurity type, thus forming an implant layer. A second semiconductor layer of the first impurity type may be provided on the exposed surface and trenches may be etched through the second semiconductor layer into the first semiconductor layer. Thereby first columns with first overcompensation zones obtained from the implant layer are formed between the trenches. Second columns of the second conductivity type may be provided in the trenches. The first and second columns form a super junction structure with a vertical first section in which the first overcompensation zones overcompensate a corresponding section in the second columns. | 2014-08-21 |
20140231905 | SEMICONDUCTOR DEVICE - A trench MOSFET including: an epitaxial layer; a body region on the epitaxial layer, the body region and the epitaxial layer forming a first interface; a trench; a trench bottom oxide in the trench; and polysilicon in the trench, the trench bottom oxide and the polysilicon forming a second interface; where the first and second interfaces are substantially aligned or are at substantially the same level. | 2014-08-21 |
20140231906 | Semiconductor Device - Provided is a semiconductor device in which on-resistance is largely reduced. In a region ( | 2014-08-21 |
20140231907 | METHODS OF INDUCING A DESIRED STRESS IN THE CHANNEL REGION OF A TRANSISTOR BY PERFORMING ION IMPLANTATION/ANNEAL PROCESSES ON THE GATE ELECTRODE - One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that allows implantation of ions into the gate electrode but not into areas of the active region where source/drain regions for the transistor will be formed, performing a gate ion implantation process to form a gate ion implant region in the gate electrode and performing an anneal process. An N-type transistor including sidewall spacer structures positioned adjacent a gate structure, a plurality of source/drain regions for the transistor and a gate implant region positioned in a gate electrode, wherein the gate implant region is comprised of ions of phosphorous, arsenic or an implant material with an atomic size that is equal to or greater than the atomic size of phosphorous at a concentration level that falls within the range of 5e | 2014-08-21 |
20140231908 | High Voltage Transistor Structure and Method - A high voltage transistor structure comprises a first double diffused region and a second double diffused region formed in a first well of a substrate, wherein the first and second double diffused regions are of the same conductivity as the substrate, a first drain/source region formed in the first double diffused region, a first gate electrode formed over the first well and a second drain/source region formed in the second double diffused region. The high voltage transistor structure further comprises a first spacer formed on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer formed on a second side of the first gate electrode and a first oxide protection layer formed between the second drain/source region and the second spacer. | 2014-08-21 |
20140231909 | Super Junction Semiconductor Device Comprising Implanted Zones - In a semiconductor substrate with a first surface and a working surface parallel to the first surface, columnar first and second super junction regions of a first and a second conductivity type are formed. The first and second super junction regions extend in a direction perpendicular to the first surface and form a super junction structure. The semiconductor portion is thinned such that, after the thinning, a distance between the first super junction regions having the second conductivity type and a second surface obtained from the working surface does not exceed 30 μm. Impurities are implanted into the second surface to form one or more implanted zones. The embodiments combine super junction approaches with backside implants enabled by thin wafer technology. | 2014-08-21 |
20140231910 | Manufacturing a Super Junction Semiconductor Device and Semiconductor Device - A super junction semiconductor device includes a semiconductor portion with a first surface and a parallel second surface. A doped layer of a first conductivity type is formed at least in a cell area. Columnar first super junction regions of a second, opposite conductivity type extend in a direction perpendicular to the first surface. Columnar second super junction regions of the first conductivity type separate the first super junction regions from each other. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A distance between the first super junction regions and the second surface does not exceed 30 μm. The on-state or forward resistance of low-voltage devices rated for reverse breakdown voltages below 1000 V can be defined by the resistance of the super junction structure. | 2014-08-21 |
20140231911 | LDMOS DEVICE WITH DOUBLE-SLOPED FIELD PLATE - In one general aspect, an apparatus can include a channel region disposed in a semiconductor substrate, a gate dielectric disposed on the channel region and a drift region disposed in the semiconductor substrate adjacent to the channel region. The apparatus can further include a field plate having an end portion disposed between a top surface of the semiconductor substrate and the gate dielectric The end portion can include a surface in contact with the gate dielectric, the surface having a first portion aligned along a first plane non-parallel to a second plane along which a second portion of the surface is aligned, the first plane being non-parallel to the top surface of the semiconductor substrate and the second plane being non-parallel to the top surface of the semiconductor substrate. | 2014-08-21 |
20140231912 | Super Junction Semiconductor Device with a Nominal Breakdown Voltage in a Cell Area - A super junction semiconductor device includes a super junction structure that is formed in a semiconductor body having a first and a second, parallel surface. The super junction structure includes first areas of the first conductivity type and second areas of a second conductivity type which is the opposite of the first conductivity type. In a cell area surrounded by an edge area, the super junction structure has a first nominal breakdown voltage in a first portion and a second nominal breakdown voltage, which differs from the first nominal breakdown voltage, in a second portion to provide improved avalanche ruggedness. | 2014-08-21 |
20140231913 | Trilayer SIT Process with Transfer Layer for FINFET Patterning - Improved sidewall image transfer (SIT) techniques are provided. In one aspect, a SIT method includes the following steps. An oxide layer is formed on a substrate. A transfer layer is formed on a side of the oxide layer opposite the substrate. A mandrel layer is formed on a side of the transfer layer opposite the oxide layer. The mandrel layer is patterned to form at least one mandrel. Sidewall spacers are formed on opposite sides of the at least one mandrel. The at least one mandrel is removed, wherein the transfer layer covers and protects the substrate during removal of the at least one mandrel. The transfer layer is etched using the sidewall spacers as a hardmask to form a patterned transfer layer. The oxide layer and the sidewall spacers are removed from the substrate. The substrate is etched using the patterned transfer layer as a hardmask. | 2014-08-21 |
20140231914 | FIN FIELD EFFECT TRANSISTOR FABRICATED WITH HOLLOW REPLACEMENT CHANNEL - A method for forming a FinFET comprises forming a raised fin between isolation trenches on a substrate. A plurality of sacrificial features is formed on at least a portion of the raised fin, the sacrificial features including a sacrificial gate dielectric and a sacrificial gate electrode having sidewalls. The sacrificial features on the raised fin are removed to form a hollow channel. Channel material is selectively and epitaxially grown in the hollow channel to form a channel. | 2014-08-21 |
20140231915 | Trilayer SIT Process with Transfer Layer for FINFET Patterning - Improved sidewall image transfer (SIT) techniques are provided. In one aspect, a SIT method includes the following steps. An oxide layer is formed on a substrate. A transfer layer is formed on a side of the oxide layer opposite the substrate. A mandrel layer is formed on a side of the transfer layer opposite the oxide layer. The mandrel layer is patterned to form at least one mandrel. Sidewall spacers are formed on opposite sides of the at least one mandrel. The at least one mandrel is removed, wherein the transfer layer covers and protects the substrate during removal of the at least one mandrel. The transfer layer is etched using the sidewall spacers as a hardmask to form a patterned transfer layer. The oxide layer and the sidewall spacers are removed from the substrate. The substrate is etched using the patterned transfer layer as a hardmask. | 2014-08-21 |
20140231916 | Transistor with coupled gate and ground plane - An integrated circuit includes a silicon substrate, a ground plane above the substrate, a buried insulator layer above the ground plane, a silicon layer above the buried insulator layer and separated from the ground plane by the buried insulator layer, and an FDSOI transistor. The transistor has a channel adapted for being formed in the silicon layer, a source and drain in and/or on the silicon layer, and a gate covering an upper face of the channel and having a lateral portion covering a lateral face of the channel and above the ground plane. A distance between the lateral portion and the ground plane is not more than three nanometers and at least five times less than a thickness of the buried insulator layer between the ground plane and the silicon layer. The ground plane is separated from the gate by the buried insulator layer. | 2014-08-21 |