34th week of 2010 patent applcation highlights part 14 |
Patent application number | Title | Published |
20100213510 | BIDIRECTIONAL SWITCH MODULE - A first semiconductor element having a junction electrode to be connected to a first node of a bidirectional switch circuit is mounted on a first metal base plate to be a heat dissipation plate, and a second semiconductor element having a junction electrode to be connected to a second node of the bidirectional switch circuit is mounted on a second metal base plate to be a heat dissipation plate. The junction electrode of the first semiconductor element has the same potential as that of the first metal base plate, and the junction electrode of the second semiconductor element has the same potential as that of the second metal base plate. Also, the respective metal base plates and non-junction electrodes of the respective semiconductor elements are connected by metal thin wires, respectively, thereby configuring the bidirectional switch circuit. | 2010-08-26 |
20100213511 | Lattice-Mismatched Semiconductor Structures and Related Methods for Device Fabrication - Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures. | 2010-08-26 |
20100213512 | High-Mobility Channel Devices on Dislocation-Blocking Layers - A method of forming an integrated circuit structure includes forming a first recess in the semiconductor substrate; and forming a dislocation-blocking layer in the first recess. The dislocation-blocking layer includes a semiconductor material. Shallow trench isolation (STI) regions are formed, wherein inner portions of the STI regions are directly over portions of the dislocation-blocking layer, and wherein inner sidewalls of the STI regions contact the dislocation-blocking layer. A second recess is formed by removing a portion of the dislocation-blocking layer between two of the inner sidewalls of the STI regions, with the two inner sidewalls facing each other. A semiconductor region is epitaxially grown in the second recess. | 2010-08-26 |
20100213513 | Hyperabrupt Diode Structure And Method For Making Same - A hyperabrupt diode structure includes a substrate formed from a low-ohmic contact material, a graded semiconductor layer comprising gallium arsenide, an offset layer comprising indium gallium phosphide over the graded semiconductor layer, a contact layer comprising gallium arsenide over the offset layer, a first electrical contact on the substrate, the first electrical contact forming a cathode of the hyperabrupt diode structure, and a second electrical contact over the contact layer, the second electrical contact forming an anode of the hyperabrupt diode structure. | 2010-08-26 |
20100213514 | METAL STRUCTURE FOR MEMORY DEVICE - A semiconductor device is provided that includes a substrate, a static random access memory (SRAM) unit cell formed in the substrate, a first metal layer formed over the substrate, the first metal layer providing local interconnection to the SRAM unit cell, a second metal layer formed over the first metal layer, the second metal layer including: a bit line and a complementary bit line each having a first thickness and a Vcc line disposed between the bit line and the complementary bit line, and a third metal layer formed over the second metal layer, the third metal layer including a word line having a second thickness greater than the first thickness. | 2010-08-26 |
20100213515 | Metal or Via Programmable Element - An integrated circuit may include one or more cells, with each cell comprising a first and a second input terminal, a first and a second output terminal, and a number of connection stages configured to couple each input terminal to a corresponding respective output terminal. The stages may include one stage per metal layer of the integrated circuit and one stage per VIA layer of the integrated circuit. Each stage may be configured with a pair of input ports and a pair of output ports. Each output port of a stage may serially connect to a corresponding respective input port of a first adjacent stage, and each input port of the stage may also serially connect to a corresponding respective output port of a second adjacent stage. The pair of input ports may also be configured to programmably connect to the pair of output ports within the same stage, according to one of two different connection patterns, to establish a respective connection within the stage. A combination of the respective connections within the stages may determine which input terminal of the cell connects to which output terminal of the cell. | 2010-08-26 |
20100213516 | SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE - On a surface of a semiconductor substrate, a plurality of terraces formed stepwise by an atomic step are formed in the substantially same direction. Using the semiconductor substrate, a MOS transistor is formed so that no step exists in a carrier traveling direction (source-drain direction). | 2010-08-26 |
20100213517 | HIGH VOLTAGE SEMICONDUCTOR DEVICE - This invention describes implementation of medium/high voltage semiconductor devices with a better voltage-blocking capability versus specific on-resistanσe trade off. This approach can be implemented in baseline and submicron CMOS without any additional process steps. Said devices comprise dielectric regions and semiconductor regions formed between them. Conductive extentions are formed on the dielectric regions, said extentions interacting capacitively with the semiconducter regions. | 2010-08-26 |
20100213518 | Impurity Doped UV Protection Layer - An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples. | 2010-08-26 |
20100213519 | MANUFACTURING METHOD OF SILICON SPIN TRANSPORT DEVICE AND SILICON SPIN TRANSPORT DEVICE - An object of the present invention is to provide a silicon spin transport device manufacturing method and silicon spin transport device whereby improved voltage output characteristics can be obtained. The silicon spin transport device manufacturing method comprises: a first step of patterning a silicon film by wet etching and forming a silicon channel layer; and a second step of forming a magnetization free layer and a magnetization fixed layer, which are apart from each other, on the silicon channel layer. | 2010-08-26 |
20100213520 | Semiconductor integrated circuit device and method of manufacturing the same - Provided is a semiconductor integrated circuit device including a capacitor element with an improved TDDB life. A semiconductor integrated circuit device ( | 2010-08-26 |
20100213521 | Semiconductor devices and methods of forming semiconductor devices - A semiconductor device includes a back bias dielectric including a negative fixed charge, a gate electrode overlapping the back bias dielectric, a semiconductor layer disposed between the gate electrode and the back bias dielectric, and a gate dielectric disposed between the semiconductor layer and the gate electrode, wherein the negative fixed charge accumulates holes at a surface of the semiconductor layer facing the back bias dielectric. | 2010-08-26 |
20100213522 | METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE TO REMEDY BOX UNDERCUT AND STRUCTURE FORMED THEREBY - A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes forming a dielectric material on the upper wall of the trench adjacent to the undercutting of the BOX layer and then etching the dielectric material to form a spacer. The spacer fixes the BOX layer undercut and protects it during subsequent steps of forming a bottle-shaped portion of the trench, forming a buried plate in the deep trench; and then forming a trench capacitor. There is also a semiconductor structure, preferably an SOI eDRAM structure, having a spacer which fixes the undercutting in the BOX layer. | 2010-08-26 |
20100213523 | eDRAM MEMORY CELL STRUCTURE AND METHOD OF FABRICATING - A deep trench structure process for forming a deep trench in a silicon on insulator (SOI) substrate. The SOI substrate has a bulk silicon layer, a buried oxide (BOX) layer and an SOI layer. In the process, the trench fill is recessed only to a level within the SOI layer so as to avoid lateral etching of the BOX layer. The buried strap is then formed followed by the STI oxide. | 2010-08-26 |
20100213524 | Semiconductor memory device and method of manufacturing the same - A semiconductor memory device includes a plurality of active pillars protruding from a semiconductor substrate, a first gate electrode disposed on at least one sidewall of the active pillar, a first gate insulating layer being disposed between the active pillar and the first gate electrode, a second gate electrode disposed on at least one sidewall of the active pillar over the first gate electrode, a second gate insulating layer being disposed between the active pillar and the second gate electrode, first and second body regions in the active pillar adjacent to respective first and second respective electrodes, and first through third source/drain regions in the active pillar arranged alternately with the first and second body regions. | 2010-08-26 |
20100213525 | SEMICONDUCTOR STORAGE DEVICE AND METHODS OF PRODUCING IT - The present invention provides a semiconductor storage device having a memory cell section and a peripheral circuit section each formed using one or more MOS transistors, comprising: a substrate; a dielectric film on the substrate; and a planar semiconductor layer formed on the on-substrate dielectric layer, wherein: the at least one MOS transistor in the memory cell section comprises a selection transistor, the at least one MOS transistor in the peripheral circuit section comprises a first MOS transistor and a second MOS transistor which are different in conductivity type from each other, the first MOS transistor includes a first lower drain or source region formed in the planar semiconductor layer, a first pillar-shaped semiconductor layer formed on the planar semiconductor layer, a first upper source or drain region formed in an upper portion of the first pillar-shaped semiconductor layer, and a first gate electrode formed such that the first gate electrode surrounds a sidewall of the first pillar-shaped semiconductor layer through a first dielectric film, the second MOS transistor includes a second lower drain or source region formed in the planar semiconductor layer, a second pillar-shaped semiconductor layer formed on the planar semiconductor layer, a second upper source or drain region formed in an upper portion of the second pillar-shaped semiconductor layer, and a second gate electrode formed such that the second gate electrode surrounds a sidewall of the second pillar-shaped semiconductor layer through a second dielectric film; and the selection transistor includes a third lower drain or source region formed in the planar semiconductor layer, a third pillar-shaped semiconductor layer formed on the planar semiconductor layer, a third lower source or drain region formed in an upper portion of the third pillar-shaped semiconductor layer, and a third gate electrode formed such that the third gate electrode surrounds a sidewall of the third pillar-shaped semiconductor layer through a third dielectric film, and wherein the semiconductor storage device has a first silicide layer formed thereon to connect at least a part of a surface of the first lower drain or source region of the first MOS transistor and at least a part of a surface of the second lower drain or source region of the second MOS transistor, and a second silicide layer formed on at least a part of a surface of the third lower drain or source region of the selection transistor. | 2010-08-26 |
20100213526 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof. | 2010-08-26 |
20100213527 | Integrated Circuit Memory Devices Having Selection Transistors with Nonuniform Threshold Voltage Characteristics - Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region. | 2010-08-26 |
20100213528 | METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING AN ARRAY STRUCTURE COMPRISING THE SAME DEVICES - The present invention discloses a metal oxide semiconductor (MOS) device and a method for operating an array structure comprising the same devices. The MOS device of the present invention comprises a device layer; an ion-implanted layer formed on the device layer and providing the source, the drain and the channel; and a gate structure formed on the ion-implanted layer. Via applying a bias voltage to the gate, the carrier density in the channel region is different from that in the source region or the drain region; thereby, the MOS device of the present invention can undertake programming, erasing and reading activities. The present invention can simplify the MOS device fabrication process, reduce the operating voltage, and promote the integration density of a 2-dimensional or 3-dimensional MOS device array. | 2010-08-26 |
20100213529 | SEMICONDUCTOR FIELD-EFFECT TRANSISTOR, MEMORY CELL AND MEMORY DEVICE - Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion. | 2010-08-26 |
20100213530 | Nonvolatile Memory Device and Method of Manufacturing the Same - A nonvolatile memory device comprises a gate insulating layer formed on a semiconductor substrate, gate patterns formed on the gate insulating layer, insulating layer spacers defining seams and being coupled together in spaces between the gate patterns, the insulating layer spacers being formed on sidewalls of the gate patterns, a height of the insulating layer spacers being lower than a height of the gate patterns, and an auxiliary layer filling the seams. | 2010-08-26 |
20100213531 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A nonvolatile memory element which is provided with a floating gate electrode and a high withstand voltage transistor which is provided with a thick gate insulating film are formed over one substrate without increase in a driving voltage of the nonvolatile memory element. A stacked film of a first insulating film and a second insulating film is formed between an island-like semiconductor region and a floating gate electrode of the nonvolatile memory element and between an island-like semiconductor region and a gate electrode of the transistor. The first insulating film overlapping with the floating gate electrode is removed, and the insulating film between the island-like semiconductor region and the floating gate electrode is formed thinner than the gate insulating film of the transistor. The transistor includes a conductive film which is formed in the same layer as the floating gate electrode and a conductive film which is formed in the same layer as a control gate electrode, and these two conductive films are electrically connected to each other and function as the gate electrodes of the transistor. | 2010-08-26 |
20100213532 | SEMICONDUCTOR DEVICES - A semiconductor device is provide, which includes a semiconductor region containing Ge as a major component, an insulating film formed on the semiconductor region, and a metallic film formed on the insulating film. At least a portion of the insulating film in contact with the semiconductor region is constituted by an oxide containing at least one rare-earth element M | 2010-08-26 |
20100213533 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film. | 2010-08-26 |
20100213534 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD FOR THE SAME - In a nonvolatile semiconductor memory device provided with memory cell transistors, each of the memory cell transistors has a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and element isolation insulating films respectively. The floating gate electrode on the tunnel insulating film is provided with a first floating gate electrode and a second floating gate electrode formed sequentially from the bottom, the second floating gate electrode being narrower in a channel-width direction than the first one. Levels of upper surfaces of the element isolation insulating films and the first floating gate electrode are the same. The inter-electrode insulating film continuously covers the upper and side surfaces of the floating gate electrode and the upper surfaces of the element isolation insulating films, and is higher in a nitrogen concentration in a boundary portion to the floating gate electrode than in boundary portions to the element isolation insulating films. | 2010-08-26 |
20100213535 | ADJACENT WORDLINE DISTURB REDUCTION USING BORON/INDIUM IMPLANT - Semiconductor devices having reduced parasitic current and methods of malting the semiconductor devices are provided. Further provided are memory devices having reduced adjacent wordline disturb. The memory devices contain wordlines formed over a semiconductor substrate, wherein at least one wordline space is formed between the wordlines. Adjacent wordline disturb is reduced by implanting one or more of indium, boron, and a combination of boron and indium in the surface of the at least one wordline space. | 2010-08-26 |
20100213536 | Nonvolatile Memory Device and Method of Forming the Same - A nonvolatile memory device includes a device isolation pattern, a charge trap layer, and a plurality of word lines. The device isolation pattern defines an active region in a semiconductor substrate and extends in a first direction. The charge trap layer covers the active region and the device isolation pattern. The word lines on the charge trap layer cross the active region and extend in a second direction. The charge trap layer disposed in a first region where the word line and the active region cross each other has a different nitrogen content ratio from the charge trap layer disposed in a second region surrounding the first region. | 2010-08-26 |
20100213537 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory string comprises: a pair of columnar portions; a first insulating layer surrounding a side surface of the columnar portions; a charge storage layer surrounding a side surface of the first insulating layer; a second insulating layer surrounding a side surface of the charge storage layer; and a first conductive layer surrounding a side surface of the second insulating layer. A select transistor comprises: a second semiconductor layer extending from an upper surface of the columnar portions; a third insulating layer surrounding a side surface of the second semiconductor layer; a fourth insulating layer surrounding a side surface of the third insulating layer; and a second conductive layer surrounding a side surface of the fourth insulating layer. The first semiconductor layer is formed continuously in an integrated manner with the second semiconductor layer. The first insulating layer is formed continuously in an integrated manner with the third insulating layer. | 2010-08-26 |
20100213538 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A memory string comprises: a first semiconductor layer having a plurality of columnar portions extending in a perpendicular direction with respect to a substrate, and joining portions joining lower ends of the plurality of columnar portions; a charge storage layer surrounding a side surface of the first semiconductor layer; and a first conductive layer surrounding a side surface of the charge storage layer and functioning as a control electrode of memory cells. A select transistor comprises: a second semiconductor layer extending upwardly from an upper surface of the columnar portions; an insulating layer surrounding a side surface of the second semiconductor layer; a second conductive layer surrounding a side surface of the insulating layer and functioning as a control electrode of the select transistors; and a third semiconductor layer formed on an upper surface of the second semiconductor layer and including silicon germanium. | 2010-08-26 |
20100213539 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; one of a drain region and a source region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and an epitaxial semiconductor layer formed on a top surface of the semiconductor pillar, wherein the other of the source region and the drain region is formed so as to be at least partially in the epitaxial semiconductor layer, and wherein: the other of the source region and the drain region has a top surface having an area greater than that of the top surface of the semiconductor pillar. | 2010-08-26 |
20100213540 | SEMICONDUCTOR DEVICE WITH A GATE HAVING A BULBOUS AREA AND A FLATTENED AREA UNDERNEATH THE BULBOUS AREA AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device with a gate having a bulbous area and a flattened area underneath the bulbous are is presented. The semiconductor device includes a semiconductor substrate, an isolation layer, a gate insulation layer, and gates. The semiconductor substrate has recess parts that have first grooves which have bulbous-shaped profiles and second vertically flattened profile grooves which extend downward from the first grooves. The gates are formed in the recess parts in which the gate insulation layer is double layered in the bulbous profile areas and is single layered in the flattened profile areas. | 2010-08-26 |
20100213541 | SEMICONDUCTOR DEVICE HAVING RECESS CHANNEL STRUCTURE - An integrated circuit device includes a semiconductor substrate including an active region defined by an isolation region and having at least one trench therein, a gate insulating layer formed in the at least one trench, a gate electrode layer having a nano-crystalline structure disposed on the gate insulating layer and a word line on the gate electrode layer in the at least one trench. The device may further include a capping layer on the word line. | 2010-08-26 |
20100213542 | ALTERNATING-DOPING PROFILE FOR SOURCE/DRAIN OF A FET - A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor. | 2010-08-26 |
20100213543 | HIGH VOLTAGE DEVICE - A method of forming a device is presented. The method includes providing a substrate prepared with an active device region. The active device region includes gate stack layers of a gate stack including at least a gate electrode layer over a gate dielectric layer. A first mask is provided on the substrate corresponding to the gate. The substrate is patterned to at least remove portions of a top gate stack layer unprotected by the first mask. A second mask is also provided on the substrate with an opening exposing a portion of the first mask and the top gate stack layer. A channel well is formed by implanting ions through the opening and gate stack layers into the substrate. | 2010-08-26 |
20100213544 | HIGH VOLTAGE DEVICE - A method of forming a device is presented. A substrate prepared with an active device region is provided. The active device region includes gate stack layers of a gate stack that includes at least a gate electrode layer over a gate dielectric layer. An implant mask is formed on the substrate with an opening exposing a portion of a top gate stack layers. Ions are implanted through the opening and gate stack layers into the substrate to form a channel well. The substrate is patterned to at least remove portion of a top gate stack layer unprotected by the implant mask. | 2010-08-26 |
20100213545 | MOS TRANSISTOR WITH A P-FIELD IMPLANT OVERLYING EACH END OF A GATE THEREOF - The present invention provides a method for fabricating a MOS transistor ( | 2010-08-26 |
20100213546 | FIELD-EFFECT TRANSISTOR AND INTEGRATED CIRCUIT INCLUDING THE SAME - A field-effect transistor comprising a movable gate electrode that suppresses a leakage current from the gate electrode, and has a large current drivability and a low leakage current between a source and a drain. The field-effect transistor comprises: an insulating substrate; a semiconductor layer of triangle cross-sectional shape formed on the insulating substrate, having a gate insulation film on a surface, and forming a channel in a lateral direction; fixed electrodes that are arranged adjacent to both sides of the semiconductor layer and in parallel to the semiconductor layer, each of the electrodes having an insulation film on a surface; a source/drain formed at the end part of the semiconductor layer; and the movable gate electrode formed above the semiconductor layer and the fixed electrodes with a gap. | 2010-08-26 |
20100213547 | SEMICONDUCTOR SWITCHING DEVICE EMPLOYING A QUANTUM DOT STRUCTURE - A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickness less than | 2010-08-26 |
20100213548 | Semiconductor Devices with Low Junction Capacitances and Methods of Fabrication Thereof - Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric. | 2010-08-26 |
20100213549 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions and source regions placed alternately with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: the first metal interconnects formed on the source regions are electrically connected to the second metal interconnect through constant size via-holes, and a ratio between the numbers of the via-holes arranged above each of the source regions is controlled to be less than four according to a distance from the ground potential supply line. | 2010-08-26 |
20100213550 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Si | 2010-08-26 |
20100213551 | E-Fuse and Associated Control Circuit - An e-fuse and an e-fuse control circuit are provided. The e-fuse includes a polysilicon layer and a metal silicide layer stacked on the polysilicon layer. The e-fuse operates in an open state when the silicide layer is broken by burning while one portion of the polysilicon layer is exposed. | 2010-08-26 |
20100213552 | Cell Structure for Dual Port SRAM - An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The second transistor includes a second active region comprising a second source and a second drain; and a second gate electrode over the second active region and connected to the first gate electrode, wherein the first source and the second source are electrically connected, and the first drain and the second drain are electrically connected. | 2010-08-26 |
20100213553 | METAL OXIDE SEMICONDUCTOR DEVICES HAVING BURIED GATE CHANNELS AND METHODS FOR FABRICATING THE SAME - Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel layer, oxidizing the first surface of the channel capping layer, and depositing a high-k dielectric layer overlying the channel capping layer. | 2010-08-26 |
20100213554 | GATE STRUCTURE AND METHOD FOR TRIMMING SPACERS - A gate structure includes a gate disposed on a substrate, a first spacer disposed on the substrate and surrounding the gate and a second spacer disposed on the first spacer and surrounding the gate, the second spacer is lower than the first spacer. | 2010-08-26 |
20100213555 | METAL OXIDE SEMICONDUCTOR DEVICES HAVING CAPPING LAYERS AND METHODS FOR FABRICATING THE SAME - Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a silicon oxide layer overlying the semiconductor substrate, forming a metal oxide gate capping layer overlying the silicon oxide layer, depositing a first metal gate electrode layer overlying the metal oxide gate capping layer, and removing a portion of the first metal gate electrode layer and the metal oxide gate capping layer to form a gate stack. | 2010-08-26 |
20100213556 | METAL SOURCE AND DRAIN TRANSISTOR HAVING HIGH DIELECTRIC CONSTANT GATE INSULATOR - The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide. | 2010-08-26 |
20100213557 | MICRO-ELECTRO-MECHANICAL-SYSTEM SENSOR AND METHOD FOR MAKING SAME - The present invention discloses an MEMS sensor and a method for making the MEMS sensor. The MEMS sensor according to the present invention comprises: a substrate including an opening; a suspended structure located above the opening; and an upper structure, a portion of which is at least partially separated from a portion of the suspended structure; wherein the suspended structure and the upper structure are separated from each other by a step including metal etch. | 2010-08-26 |
20100213558 | Magnetic Memory Device - A magnetic memory device is provided. The magnetic memory device includes an invariable pinning pattern and a variable pinning pattern on a substrate. A tunnel barrier pattern is interposed between the invariable pinning pattern and the variable pinning pattern, and the pinned pattern is interposed between the invariable pinning pattern and the tunnel barrier pattern. A storage free pattern is interposed between the tunnel barrier pattern and the variable pinning pattern, and a guide free pattern is interposed between the storage free pattern and the variable pinning pattern. A free reversing pattern is interposed between the storage and guide free patterns. The free reversing pattern reverses a magnetization direction of the storage free pattern and a magnetization direction of the guide free pattern in the opposite directions. | 2010-08-26 |
20100213559 | Solid-state image pickup apparatus and production method thereof - A solid-state image pickup apparatus includes: a substrate in which a charge generation portion that generates a signal charge is formed on a surface layer; a layer covering an upper surface of the substrate; a waveguide formed on the layer covering the upper surface of the substrate at a position corresponding to the charge generation portion; a hollow portion formed on the layer covering the upper surface of the substrate at a position on an outer side of the waveguide; and an optically-transparent layer formed on the layer covering the upper surface of the substrate such that at least the hollow portion becomes airtight. | 2010-08-26 |
20100213560 | PAD DESIGN FOR BACKSIDE ILLUMINATED IMAGE SENSOR - A semiconductor image sensor device includes first and second semiconductor substrates. A pixel array and a control circuit are formed in a first surface of the first substrate. An interconnect layer is formed over the first surface of the first substrate and electrically connects the control circuit to the pixel array. A top conducting layer is formed over the interconnect layer to have electrical connectivity with at least one of the control circuit or the pixel array via the interconnect layer. A surface of a second substrate is bonded to the top conducting layer. A conductive through-silicon-via (TSV) passes through the second substrate, and has electrical connectivity with the top conducting layer. A terminal is formed on an opposite surface of the second substrate, and electrically connected to the TSV. | 2010-08-26 |
20100213561 | Optoelectronic Device with Germanium Photodetector - An optoelectronic device comprises a photodetector feature, an interfacial layer disposed above at least a portion of the photodetector feature, and a vertical contact disposed on at least a portion of the interfacial layer. The photodetector feature comprises germanium and is operative to convert a light signal into an electrical signal. The interfacial layer comprises nickel. Finally, the vertical contact is operative to transmit the electrical signal from the photodetector feature. | 2010-08-26 |
20100213562 | QUAD FLAT NON-LEADED CHIP PACKAGE STRUCTURE - A quad flat non-leaded chip package structure includes a leadframe, a control chip, a light-sensing chip, a first bonding wire, a plurality of second bonding wires, and a molding compound. The leadframe includes a plurality of leads. Besides, the leadframe has an upper surface and a lower surface opposite to the upper surface. The control chip and the light-sensing chip are disposed on the upper surface of the leadframe. The light-sensing chip is electrically connected to the control chip through the first bonding wire. The control chip is electrically connected to the leads through the second bonding wires. The molding compound encapsulates a portion of the leadframe, the control chip, the light-sensing chip, the first bonding wire, and the second bonding wires. In addition, the molding compound fills among the leads. | 2010-08-26 |
20100213563 | SEMICONDUCTOR OPTOELECTRONIC DEVICE AND QUAD FLAT NON-LEADED OPTOELECTRONIC DEVICE - A semiconductor optoelectronic device including a substrate, a control chip, a light-sensing chip and a molding compound is provided. The control chip is disposed on the substrate and electrically connected to the substrate. The light-sensing chip is disposed on the substrate and electrically connected to the substrate and the control chip. The molding compound encapsulates the control chip and a material of the molding compound is an insulating material doped with a non-electro-conductive magnetic conductive material. | 2010-08-26 |
20100213564 | SENSOR CHIP AND METHOD OF MANUFACTURING THE SAME - A sensor chip includes: a semiconductor substrate that is provided with a light receiving portion on a main surface; a light transmissive member that is provided on the main surface of the semiconductor substrate, enclosing a hollow portion above the light receiving portion, to surround upper and periphery of the light receiving portion; and a light transmissive protective member that is provided on the light transmissive member. | 2010-08-26 |
20100213565 | High Speed Backside Illuminated, Front Side Contact Photodiode Array - The present specification discloses front-side contact back-side illuminated (FSC-BSL) photodiode array having improved characteristics such as high speed of each photodiode, uniformity of the bias voltage applied to different photodiode, low bias voltage, reduced resistance of each photodiode, and an associated reduction in noise. The photodiode array is made of photodiodes with front metallic cathode pads, front metallic anode pad, back metallic cathode pads, n+ doped regions and a p+ doped region. The front metallic cathode pads physically contact the n+ doped regions and the front metallic anode pad physically contacts the p+ doped region. The back metallic cathode pads physically contact the n+ doped region. | 2010-08-26 |
20100213566 | REDUCED-CROSSTALK WIREBONDING IN AN OPTICAL COMMUNICATION SYSTEM - Wirebonds are formed to couple an opto-electronic device chip having two or more opto-electronic devices to a signal processing chip. Two or more mutually adjacent wirebond groups, each corresponding to one of the opto-electronic devices, are formed. For example, each wirebond group can include a first wirebond coupling a P-terminal of the opto-electronic device of the wirebond group to the signal processing chip, a second wirebond coupling an N-terminal of the opto-electronic device of the wirebond group to the signal processing chip, and a third wirebond coupling the opto-electronic device chip to the signal processing chip. | 2010-08-26 |
20100213567 | METHOD FOR MANUFACTURING SOLID-STATE IMAGE SENSOR AND SOLID-STATE IMAGE SENSOR - There is provide a divided exposure technology capable of restraining deterioration in the performance of a solid-state image sensor. A photoresist is formed over a semiconductor substrate and subjected to divided exposure. A dividing line for divided exposure is located at least over a region of a semiconductor substrate in which an active region in which a pixel is to be formed is defined. The photoresist is then developed and patterned. By utilizing the patterned photoresist, an element isolation structure for defining the active region in the semiconductor substrate is formed in the semiconductor substrate. | 2010-08-26 |
20100213568 | MICRO-ELECTRO-MECHANICAL-SYSTEM DEVICE WITH GUARD RING AND METHOD FOR MAKING SAME - The present invention discloses a MEMS device with guard ring, and a method for making the MEMS device. The MEMS device comprises a bond pad and a sidewall surrounding and connecting with the bond pad, characterized in that the sidewall forms a guard ring by an etch-resistive material. | 2010-08-26 |
20100213569 | INTEGRATED CIRCUITS HAVING FUSES AND SYSTEMS THEREOF - An integrated circuit includes a fuse over a substrate. The fuse has a first end, a second end, and a central portion between the first end and the second end. A first dummy pattern is disposed adjacent to each side of the central portion of the fuse. | 2010-08-26 |
20100213570 | ANTIFUSE - An antifuse ( | 2010-08-26 |
20100213571 | EDRAM INCLUDING METAL PLATES - A method for forming a memory device is provided by first forming at least one trench in a semiconductor substrate. Next, a lower electrode is formed in the at least one trench, and thereafter a conformal dielectric layer is formed on the lower electrode. | 2010-08-26 |
20100213572 | Dual-Dielectric MIM Capacitors for System-on-Chip Applications - An integrated circuit structure includes a chip having a first region and a second region. A first metal-insulator-metal (MIM) capacitor is formed in the first region. The first MIM capacitor has a first bottom electrode; a first top electrode over the first bottom electrode; and a first capacitor insulator between and adjoining the first bottom electrode and the first top electrode. A second MIM capacitor is in the second region and is substantially level with the first MIM capacitor. The second MIM capacitor includes a second bottom electrode; a second top electrode over the second bottom electrode; and a second capacitor insulator between and adjoining the second bottom electrode and the second top electrode. The second capacitor insulator is different from the first capacitor insulator. The first top electrode and the first bottom electrode may be formed simultaneously with the second top electrode and the second bottom electrode, respectively. | 2010-08-26 |
20100213573 | Semiconductor device - A semiconductor device including a plurality of decoupling capacitors formed on a semiconductor substrate, and a plurality of decoupling capacitor contact plugs disposed between the semiconductor substrate and the plurality of decoupling capacitors, the plurality of decoupling capacitor contact plugs being electrically connected to the plurality of decoupling capacitors and including an array of first decoupling capacitor contact plugs and second decoupling capacitor contact plugs. | 2010-08-26 |
20100213574 | HIGH DIELECTRIC CONSTANT TRANSITION METAL OXIDE MATERIALS - A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred embodiment, a transition metal oxide is deposited over a bottom electrode and implanted with a dopant. In a preferred embodiment, the metal oxide is hafnium oxide or zirconium oxide and the dopant is nitrogen. The dopant can convert the crystal structure of the hafnium oxide or zirconium oxide to a tetragonal structure and increase the dielectric constant of the metal oxide. | 2010-08-26 |
20100213575 | Profile Design for Lateral-Vertical Bipolar Junction Transistor - A lateral-vertical bipolar junction transistor (LVBJT) includes a well region of a first conductivity type over a substrate; a first dielectric over the well region; and a first electrode over the first dielectric. A collector of a second conductivity type opposite the first conductivity type is in the well region and on a first side of the first electrode, and is adjacent the first electrode. An emitter of the second conductivity type is in the well region and on a second side of the first electrode, and is adjacent the first electrode, wherein the second side is opposite the first side. A collector extension region having a lower impurity concentration than the collector adjoins the collector and faces the emitter. The LVBJT does not have any emitter extension region facing the collector and adjoining the emitter. | 2010-08-26 |
20100213576 | METHOD FOR PRODUCING GROUP III NITRIDE CRYSTAL SUBSTRATE, GROUP III NITRIDE CRYSTAL SUBSTRATE, AND SEMICONDUCTOR DEVICE USING GROUP III NITRIDE CRYSTAL SUBSTRATE - Disclosed is a method for producing a group III nitride crystal substrate. A group III nitride crystal is formed by a growth method using a flux. The group III nitride crystal substrate is heat treated at a temperature equal to or higher than the lowest temperature at which the flux contained inside the group III nitride crystal substrate through intrusion into the crystal during the crystal formation can be discharged to outside the group III nitride crystal substrate, and equal to or lower than the highest temperature at which the surface of the group III nitride crystal substrate is not decomposed. | 2010-08-26 |
20100213577 | SEMICONDUCTOR ELECTRONIC DEVICE AND PROCESS OF MANUFACTURING THE SAME - A semiconductor electronic device comprises a substrate; a buffer layer that comprises composite laminations of which a first semiconductor layer, that is formed of a compound semiconductor of a nitride system, that has a lattice constant to be as smaller than that of such the substrate, and that has a coefficient of thermal expansion to be as larger than that of such the substrate, and a second semiconductor layer that is formed of a compound semiconductor of a nitride system are formed as alternately on to such the substrate; a semiconductor operation layer that is formed of a compound semiconductor of a nitride system and that is formed on to such the buffer layer; and a dislocation reduction layer, which comprises a lower layer region and an upper layer region that are formed at any location at an inner side of such the buffer layer and that comprise an interface of a concave and convex shape therebetween, at which a threading dislocation that draws from such the lower layer region toward such the upper layer region is bending at such the interface, wherein such the second semiconductor layer is comprised of a laminated layers as alternately of a third semiconductor layer that has a lattice constant to be as smaller than that of such the substrate and that has a coefficient of thermal expansion to be as larger than that of such the substrate, and of a fourth semiconductor layer that has a lattice constant to be as smaller than that of such the third semiconductor layer and that has a coefficient of thermal expansion to be as larger than that of such the substrate, and an average of such the lattice constants in the second semiconductor layer is to be smaller than that of such the first semiconductor layer, and an average of such the coefficients of thermal expansion in the second semiconductor layer is to be as larger than that of such the substrate. | 2010-08-26 |
20100213578 | METHODS OF FORMING INTEGRATED CIRCUITS AND RESULTING STRUCTURES - Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing one or more levels of semiconductor material on an acceptor substrate, and fabricating circuitry on each level of semiconductor material before disposition of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated. Integrated circuit devices formed by the methods are also disclosed. | 2010-08-26 |
20100213579 | METHODS FOR FABRICATION OF HIGH ASPECT RATIO MICROPILLARS AND NANOPILLARS - Methods for fabrication of high aspect ratio micropillars and nanopillars are described. Use of alumina as an etch mask for the fabrication methods is also described. The resulting micropillars and nanopillars are analyzed and a characterization of the etch mask is provided. | 2010-08-26 |
20100213580 | ACID-SENSITIVE, DEVELOPER-SOLUBLE BOTTOM ANTI-REFLECTIVE COATINGS - Acid-sensitive, developer-soluble bottom anti-reflective coating compositions are provided, along with methods of using such compositions and microelectronic structures formed thereof. The compositions preferably comprise a crosslinkable polymer dissolved or dispersed in a solvent system. The polymer preferably comprises recurring monomeric units having adamantyl groups. The compositions also preferably comprise a crosslinker, such as a vinyl ether crosslinking agent, dispersed or dissolved in the solvent system with the polymer. In some embodiments, the composition can also comprise a photoacid generator (PAG) and/or a quencher. The bottom anti-reflective coating compositions are thermally crosslinkable, but can be decrosslinked in the presence of an acid to be rendered developer soluble. | 2010-08-26 |
20100213581 | DIELECTRIC FILM WITH LOW COEFFICIENT OF THERMAL EXPANSION (CTE) USING LIQUID CRYSTALLINE RESIN - An embodiment of the present invention is a technique to provide a dielectric film material with controllable coefficient of thermal expansion (CTE). A first compound containing a first liquid crystalline component is formed. The first compound is cast into a first film. The first film is oriented in an magnetic or electromagnetic field in a first direction. The first film is cured at a first temperature. | 2010-08-26 |
20100213582 | GLASS-BASED SOI STRUCTURES - Semiconductor-on-insulator (SOI) structures, including large area SOI structures, are provided which have one or more regions composed of a layer ( | 2010-08-26 |
20100213583 | ELECTRONIC PARTS, AND METHOD FOR ARRANGING SHIELDING CASE AND CHIP PARTS - An electronic part ( | 2010-08-26 |
20100213584 | ULTRA WIDEBAND HERMETICALLY SEALED SURFACE MOUNT TECHNOLOGY FOR MICROWAVE MONOLITHIC INTEGRATED CIRCUIT PACKAGE - An ultra wideband hermetically sealed surface mount package for a microwave monolithic integrated circuit (MMIC) is provided including: an integrated circuit; a package body being mounted with the integrated circuit and comprising a plurality of first dielectrics formed in a multilayer, a first line unit mounted to a circuit substrate and is electrically connected with an external circuit, a second line unit upwardly extended from the first line unit and is electrically connected with the first line unit, a third line unit extended to the right angle from the second line unit and is electrically connected with the second line unit, and a bonding unit that electrically connects the third line unit and the mounted integrated circuit; and a package cover being formed on the package body to seal the integrated circuit and comprising a plurality of second dielectrics formed in a multilayer. | 2010-08-26 |
20100213585 | SEMICONDUCTOR DEVICE - A semiconductor device includes first to third semiconductor chips. The second semiconductor chip is stacked over the first semiconductor chip. The third semiconductor chip is stacked over the second semiconductor chip. The second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip. The second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip. | 2010-08-26 |
20100213586 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package is constituted of a semiconductor chip, a rectangular-shaped stage having the semiconductor chip mounted on the surface, a plurality of leads which are aligned in the periphery of the stage and which are electrically connected to the semiconductor chip, and a resin mold which seals the semiconductor chip, the stage, and the leads therein while externally exposing the backside of the stage on the lower surface thereof. In particular, at least one protrusion is further formed on the upper surface or the lower surface of the resin mold at a position within the outer portion of the resin mold disposed outside the sealed portion of the resin mold. The height of the outer portion of the resin mold having the protrusion is larger than the sum of the thickness of the stage and the thickness of the sealed portion of the resin mold. | 2010-08-26 |
20100213587 | ELECTRONIC DEVICE - One embodiment provides a semiconductor assembly including a printed circuit board and a semiconductor package. The semiconductor package includes a lead frame having a die pad and a plurality of leads spaced from the die pad, a chip attached to the die pad on a front face of the lead frame, at least one electrically conductive structure element mechanically coupled to but electrically isolated from the front face of the lead frame, at least one connector electrically connecting the chip to the structure element, at least one connector electrically connecting the structure element to at least one of the leads, and a mold material encasing the semiconductor package except for an end portion of the leads which are electrically connected to the printed circuit board. | 2010-08-26 |
20100213588 | WIRE BOND CHIP PACKAGE - A wire bond chip package includes a chip carrier; a semiconductor die having a die face and a die edge, the semiconductor die being mounted on a die attach surface of the chip carrier, wherein a plurality of input/output (I/O) pads are situated in or on the semiconductor die; a rewiring laminate structure on the semiconductor die, the rewiring laminate structure comprising a plurality of redistribution bond pads; a plurality of bond wires interconnecting the redistribution bond pads with the chip carrier; and a mold cap encapsulating at least the semiconductor die and the bond wires. | 2010-08-26 |
20100213589 | MULTI-CHIP PACKAGE - A multi-chip package includes a chip carrier; a semiconductor die mounted on a die attach surface of the chip carrier, wherein a plurality of input/output (I/O) pads are situated in or on the semiconductor die; a rewiring laminate structure on the semiconductor die, the rewiring laminate structure comprising a plurality of redistribution pads for the I/O pads; at least one bond wire interconnecting at least one of the redistribution pads with the chip carrier; a chip package mounted on at least another of the redistribution pads; and a mold cap encapsulating at least a portion of the bond wire. | 2010-08-26 |
20100213590 | Systems and Methods of Tamper Proof Packaging of a Semiconductor Device - A barrier layer can be attached in a semiconductor package to one or more sensitive devices. The barrier layer can be used to obstruct tampering by a malicious agent attempting to access sensitive information on the sensitive device. The barrier layer can cause the sensitive device to become inoperable if physically tampered. Additional other aspects of the protective packaging provide protection against x-ray and thermal probing as well as chemical and electrical tampering attempts. | 2010-08-26 |
20100213591 | Semiconductor package and method of manufacturing the same - A semiconductor package includes a first package and a second package, a connection terminal disposed between the first and second packages and including a first solder ball and a second solder ball that are vertically stacked, a solder passivation layer with which a surface of at least one of the first and second solder balls is coated, and a ring-shaped short prevention part surrounding a coupling portion between the first and second solder balls. | 2010-08-26 |
20100213592 | Semiconductor Module, Terminal Strip, Method for Manufacturing Terminal Strip, and Method for Manufacturing Semiconductor Module - To provide a semiconductor module, a terminal strip, a method for manufacturing the terminal strip, and a method for manufacturing the semiconductor module in which loop inductance is decreased. | 2010-08-26 |
20100213593 | STACKED SEMICONDUCTOR PACKAGE - A stacked semiconductor package includes an upper unit package and a lower unit package. The lower unit package includes a substrate, a semiconductor chip disposed on an upper surface of the substrate, terminal pads arranged on an upper surface of the semiconductor chip, protrusions formed on the terminal pads, a protective layer formed on the substrate and covering the semiconductor chip and the protrusions, and openings formed in the protective layer and exposing the protrusions. The upper unit package includes a substrate, ball lands provided on a lower surface of the substrate, and solder balls formed on the ball lands. The solder balls of the upper unit package are inserted into the openings of the lower unit package to be connected to the protrusions of the lower unit package. | 2010-08-26 |
20100213594 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - A semiconductor device having a structure in which the structure is laminated in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material of liquid state to the back surface of a semiconductor wafer by a spin coating method, this is dried and a solid-like adhesive layer is formed. Then, a semiconductor wafer is divided into each semiconductor chip by making the above-mentioned reforming area into a division origin. By pasting up this semiconductor chip on the main surface of the other semiconductor chip by the adhesive layer of the back surface, a semiconductor device having a structure in which the semiconductor device is laminated in many stages is manufactured. | 2010-08-26 |
20100213595 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF AND ENCAPSULATING METHOD THEREOF - A semiconductor package, a manufacturing method thereof and an encapsulating method thereof are provided. The semiconductor package includes a substrate, a flip chip, a plurality of conductive parts and a sealant. The substrate has a substrate upper surface. The flip chip has an active surface and a chip surface opposite to the active surface. The conductive parts electrically connect the substrate upper surface and the active surface. The sealant envelops the flip chip, and the space between the substrate upper surface and the active surface is filled with a portion of the sealant. The sealant further has a top surface. wherein, the chip surface is spaced apart from the top surface by a first distance, the substrate upper surface is spaced apart from the active surface by a second distance, and the ratio of the first distance to the second distance ranges from 2 to 5. | 2010-08-26 |
20100213596 | STACK PACKAGE - A stack package includes a substrate having an upper surface and a lower surface which faces away from the upper surface, a lower stack group, an upper stack group, and connection members. The lower stack group is attached to the upper surface of the substrate and includes at least two semiconductor chips which are stacked in a face-up type to form on or more steps. The upper stack group is disposed over the lower stack group and includes at least two semiconductor chips which are stacked in a face-down type in such a way as to form one or more steps whose direction mirrors the direction of the at least one step of the lower stack group. The connection members electrically connect the semiconductor chips of the lower and upper stack groups to the substrate. | 2010-08-26 |
20100213597 | SEMICONDUCTOR ELEMENT MOUNTING BOARD - A semiconductor element mounting board includes: aboard having surfaces; a semiconductor element mounted on one of the surfaces of the board; a first layer into which the semiconductor element is embedded, the first layer being provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer. In such a semiconductor element mounting board, each of the surface layers has rigidity higher than that of each of the first and second layers. It is preferred that in the case where a Young's modulus of each surface layer at 25° C. is defined as X GPa and a Young's modulus of the first layer at 25° C. is defined as Y GPa, the X and the Y satisfy a relation of 0.5≦X−Y≦13. | 2010-08-26 |
20100213598 | CIRCUIT CARRIER AND SEMICONDUCTOR PACKAGE USING THE SAME - A circuit carrier suitable for being connected with a bump is provided. The circuit carrier includes a substrate and at least one bonding pad. The substrate has a bonding pad disposed on a surface thereof for being connected with the bump. A brown-oxide layer is disposed on a surface of the bonding pad. | 2010-08-26 |
20100213599 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a flat plate; a semiconductor chip which is disposed on one main surface of the flat plate and whose surface opposite an element circuit surface is fixedly bonded; a single layer of an insulating material layer formed continuously on the element circuit surface of the semiconductor chip and on the main surface of the flat plate; an opening formed at a position, in the insulating material layer, above an electrode disposed on the element circuit surface of the semiconductor chip; a conductive part formed in the opening so as to be connected to the electrode of the semiconductor chip; a wiring layer formed on the insulating material layer so as to be connected to the conductive part, and partly led out to a peripheral area of the semiconductor chip; and external electrodes formed on the wiring layer. Also adoptable is a structure in which a flat plate having a cavity is used, a semiconductor chip is disposed in the cavity, and an insulating material layer is filled and formed in a gap in the cavity. A semiconductor device high in yields and connection reliability, adaptable to a microscopic pitch of electrodes of a semiconductor chip, and excellent in electric characteristic is obtained at low cost. | 2010-08-26 |
20100213600 | Apparatus having thermal-enhanced and cost-effective 3D IC integration structure with through silicon via interposers - An apparatus having a three-dimensional integrated circuit structure is described herein. The apparatus include an interposer for carrying a plurality of high and low-power chips. The high-power chips are attached and connected to one side of the interposer, while the low-power chips are attached and connected to the other side of the interposer. In generally, the high-power chips produce more heat than does the low-power chip during their operations. The interposer further include through silicon vias and redistribution layers for connecting the chips on both surfaces. In addition, the interposer assembly is attached and connected to a substrate layer, which is in turn attached and connected to a printed circuit board. In order to provide improve thermal management, the interposer surface carrying the high-power chips are oriented away from the circuit board. A heat spreader is attached to the back sides of the high-power chips for dissipating the heat. | 2010-08-26 |
20100213601 | INTEGRATED CIRCUIT MICRO-MODULE - In one aspect, an integrated circuit package composed of a plurality of immediately adjacent stacked layers of cured, planarizing, photo-imageable dielectric is described. At least one interconnect layer is provided between a pair of adjacent dielectric layers. An integrated circuit is positioned within one or more of the dielectric layers such that at least one of the dielectric layers extends over the active surface of the integrated circuit. The integrated circuit is electrically coupled with I/O pads on a surface of the package at least in part through the interconnect layer or electrically conductive vias. In particular embodiments, the package can include thermal pipes, a heat sink, multiple integrated circuits, interconnect layers, conductive vias that electrically connect different components of the package and/or passive devices. In some specific embodiments, the dielectric layers are formed from a suitable epoxy such as SU-8 type. In a method aspect of the invention, the dielectric layers may be formed using a spin-on coating approach and patterned using conventional photolithographic techniques. | 2010-08-26 |
20100213602 | INTEGRATED CIRCUIT MICRO-MODULE - Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a method for forming a microsystem and one or more passive devices in the microsystem. Layers of epoxy are sequentially deposited over a substrate to form multiple planarized layers of epoxy over the substrate. The epoxy layers are deposited by spin coating. At least some of the epoxy layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. An integrated circuit having multiple I/O bond pads is placed on an associated epoxy layer. At least one conductive interconnect layer is formed over an associated epoxy layer. A passive component is formed within at least one of the epoxy layers. The passive component is electrically coupled with the integrated circuit via at least one of the interconnect layers. Multiple external package contacts are formed. The integrated circuit is electrically connected to the external package contacts at least partly through one or more of the conductive interconnect layers. Various embodiments pertain to apparatuses that are formed by performing some or all of the aforementioned operations. | 2010-08-26 |
20100213603 | INTEGRATED CIRCUIT MICRO-MODULE - Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit. | 2010-08-26 |
20100213604 | INTEGRATED CIRCUIT MICRO-MODULE - Various apparatus and methods for improving the dissipation of heat from integrated circuit micro-modules are described. One aspect of the invention pertains to an integrated circuit package with one or more thermal pipes. In this aspect, the integrated circuit package includes multiple layers of a cured, planarizing dielectric. An electrical device is embedded within at least one of the dielectric layers. At least one electrically conductive interconnect layer is embedded within one or more of the dielectric layers. A thermal pipe made of a thermally conductive material is embedded in at least one associated dielectric layer. The thermal pipe thermally couples the electrical device with one or more external surfaces of the integrated circuit package. Various methods for forming the integrated circuit package are described. | 2010-08-26 |
20100213605 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes an electronic component having a pad surface on which an electrode pad is formed, and having a back surface opposite the pad surface, a sealing resin disposed to cover side faces of the electronic component while exposing the pad surface at a first surface thereof and the back surface at a second surface thereof, a multilayer interconnection structure including insulating layers stacked one over another and interconnection patterns, having an upper surface thereof being in contact with the first surface, the electrode pad, and the pad surface, and having a periphery thereof situated outside a periphery of the sealing resin, and another pad disposed on the upper surface of the multilayer interconnection structure outside the periphery of the sealing resin, wherein the interconnection patterns include a first interconnection pattern directly connected to the electrode pad and a second interconnection pattern directly connected to said another pad. | 2010-08-26 |
20100213606 | DIELECTRIC ENHANCEMENTS TO CHIP-TO-CHIP CAPACITIVE PROXIMITY COMMUNICATION - A method for improving signal levels between capacitively-coupled chips in proximity communication (PxC) includes depositing a high permittivity dielectric material layer over a signal pad of a first chip, and placing a second chip in close proximity to the first chip such that faces of the signal pads align to enable for capacitive signal coupling. The high permittivity dielectric material layer that fills at least a portion of a gap between the first chip and the second chip, and improves capacitive coupling between signal pads of the first chip and the second chip by providing for an increased permittivity in the gap between the first chip and the second chip. The increased permittivity ensures that electric fields are substantially confined to a space between the signal pad of the first chip and the signal pad of the second chip. | 2010-08-26 |
20100213607 | INTEGRATED CIRCUIT MICRO-MODULE - Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a wafer level method for packaging micro-systems. A substrate prefabricated with metal vias can be provided. The substrate can also be made by forming holes in a substrate and electroplating an electrically conductive material into the holes to form the vias. Multiple Microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple layers of planarizing, photo-imageable epoxy, one or more interconnect layers and an integrated circuit. Each interconnect layer is embedded in an associated epoxy layer. The integrated circuit is positioned within at least an associated epoxy layer. The interconnect layers of the Microsystems are formed such that at least some of the interconnect layers are electrically coupled with one or more of the metal vias in the substrate. Molding material is applied over the top surface of the substrate and the Microsystems to form a molded structure. Portions of the substrate can be removed. The molded structure can be singulated to form individual integrated circuit packages. Each of the integrated circuit packages contains at least one microsystem. Various embodiments involve forming conductive pads on the top surface of the substrate instead of the metal vias. | 2010-08-26 |
20100213608 | Solder bump UBM structure - Disclosed is an under bump metallization structure including a plurality of metal or metal alloy layers formed on chip bond pads. The disclosed UBM structure has a stress improvement on the semiconductor device because the thickness of the copper-base layer is reduced to between about 0.3 and 10 microns, preferably between about 0.3 and 2 micron. The presence of the pure tin layer prevents oxidation and contamination of the nickel-base layer. It also forms a good solderable surface for the subsequent processes. Also disclosed are semiconductor devices having the disclosed UBM structure and the methods of making the semiconductor devices. | 2010-08-26 |
20100213609 | SOLDER BUMP, SEMICONDUCTOR CHIP, METHOD OF MANUFACTURING THE SEMICONDUCTOR CHIP, CONDUCTIVE CONNECTION STRUCTURE, AND METHOD OF MANUFACTURING THE CONDUCTIVE CONNECTION STRUCTURE - A solder bump and a conductive connection structure are provided which can conductively connect a semiconductor chip and a substrate with high connection reliability. Filler | 2010-08-26 |