35th week of 2009 patent applcation highlights part 43 |
Patent application number | Title | Published |
20090215199 | Caffeine Detection Via Internally-Referenced Two Part Assay - Methods, compositions, and apparatus for detecting the presence of caffeine in a liquid sample are provided. In certain embodiments, an internally referenced competitive assay allows a very precise determination of a threshold value of caffeine for use in semiquantitative types of ligand-receptor assays. By using a detection means that participates in two assays, sensitivity is doubled in the maximum sensitivity range and the range can be adjusted to match the predicted concentration range of an analyte. This format and the materials described herein allow the assay to complete within three minutes. In addition, this format accommodates common attributes of liquid samples for detecting caffeine, such as the inclusion of milk or sugar in a coffee-type beverage. | 2009-08-27 |
20090215200 | Measurement of binding rate of a binding substance and an analyte - A method of measuring the rate of binding of a binding substance and an analyte, for example in an assay such as an immunoassay, uses an initial step of performing ultrasonication sufficient to disrupt binding between the binding substance and the analyte. After cessation of the ultrasonication, measurements are taken to determine the rate of binding at cessation of said ultrasonication or at a predetermined time thereafter The ultrasonication results in knowledge of the precise time of the start of the binding reaction which provides a better rate measurement. | 2009-08-27 |
20090215201 | METHOD FOR CONTROLLING SPATIAL TEMPERATURE DISTRIBUTION ACROSS A SEMICONDUCTOR WAFER - A chuck for a plasma processor comprises a temperature-controlled base, a thermal insulator, a flat support, and a heater. The temperature-controlled base is controlled in operation a temperature below the desired temperature of a workpiece. The thermal insulator is disposed over at least a portion of the temperature-controlled base. The flat support holds a workpiece and is disposed over the thermal insulator. A heater is embedded within the flat support and/or mounted to an underside of the flat support. The heater includes a plurality of heating elements that heat a plurality of corresponding heating zones. The power supplied and/or temperature of each heating element is controlled independently. The heater and flat support have a combined temperature rate change of at least 1° C. per second. | 2009-08-27 |
20090215202 | CONTROLLED EDGE RESISTIVITY IN A SILICON WAFER - An epitaxial silicon wafer is produced with a resistivity in the area adjacent the edge that is greater or less than the resistivity adjacent the center. The wafer may be manufactured by a method wherein one or more process parameters are adjusted during deposition of epitaxial layer to control the edge resistivity. Such process parameters may include using a non-homogeneous temperature and/or a process reactant gas flow across the front surface of the wafer. | 2009-08-27 |
20090215203 | MONITORING OF TEMPERATURE VARIATION ACROSS WAFERS DURING PROCESSING - A method of measuring temperature across wafers during semiconductor processing includes the step of providing a correlation between a peak wafer temperature during a processing step and a change in wafer surface charge or surface potential following the processing step. A first wafer to be characterized for its peak temperature spatial distribution during the processing step is processed through the processing step. The wafer surface charge or surface potential at a plurality of locations on the first wafer are measured following the processing step. A peak temperature spatial distribution for the first wafer is then determined based on the correlation and the wafer surface charge or surface potential measured in the measuring step. | 2009-08-27 |
20090215204 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed. | 2009-08-27 |
20090215205 | SHOWER HEAD STRUCTURE FOR PROCESSING SEMICONDUCTOR - A shower head structure disposed in a device | 2009-08-27 |
20090215206 | System and method for controlling a semiconductor manufacturing process - A semiconductor manufacture and testing device is provided, comprising: a process device configured to perform a semiconductor processing operation on a semiconductor wafer; a testing device configured to perform a testing operation on the semiconductor wafer and generate real-time testing metrics relating to the testing operation; a data storage element configured to store the real-time testing metrics as stored testing metrics; a control and dispatch element configured to receive the stored testing metrics and generate dispatch control signals based on the stored testing metrics and a set of evaluation rules; and a test routing element located between the process element and the testing element, and configured to route the semiconductor wafer either from the process element to the testing element or from the process element around the testing element, based the dispatch control signals. | 2009-08-27 |
20090215207 | Alignment method of two substrates by microcoils - Substrates to be aligned comprise microcoils arranged at the level of their facing surfaces. In an alignment phase, power is supplied to at least the microcoils of the first substrate, whereas the inductance of the microcoils of the second substrate is measured. The microcoils are preferably flat microcoils in the form of a spiral or a serpentine. | 2009-08-27 |
20090215208 | Composition including material, methods of depositing material, articles including same and systems for depositing material - Methods for depositing nanomaterial onto a substrate are disclosed. Also disclosed are compositions useful for depositing nanomaterial, methods of making devices including nanomaterials, and a system and devices useful for depositing nanomaterials. | 2009-08-27 |
20090215209 | Methods of depositing material, methods of making a device, and systems and articles for use in depositing material - Methods for depositing material and/or nanomaterial are disclosed. Also disclosed are methods of making devices including nanomaterials, systems useful for depositing materials and/or nanomaterials, surface treated articles for depositing material and/or nanomaterial onto a substrate, and surface treated transfer surfaces. | 2009-08-27 |
20090215210 | METHOD OF MANUFACTURING LIGHT EMITTING DIODE DEVICE - A method of manufacturing light-emitting diode device has steps of isolating a light-emitting side of an LED chip from a wire-bonding region by disposing partition panels on the wire-bonding region and coating phosphors on the light-emitting side of the LED chip in a phosphor-coating process. The method can be applied to manufacturing LED device having a flip chip structure or a vertical chip structure. According to the method, a white LED device can be directly manufactured without adopting a phosphor package technique, and thereby a whole package process of the white LED device is simplified. | 2009-08-27 |
20090215211 | Method Of Fabricating Microchannel Plate Devices With Multiple Emissive Layers - A method of fabricating a microchannel plate includes defining a plurality of pores extending from a top surface of a substrate to a bottom surface of the substrate where the plurality of pores has a resistive material on an outer surface that forms a first emissive layer. A second emissive layer is formed over the first emissive layer. The second emissive layer is chosen to achieve at least one of an increase in secondary electron emission efficiency and a decrease in gain degradation as a function of time. A top electrode is formed on the top surface of the substrate and a bottom electrode is formed on the bottom surface of the substrate. | 2009-08-27 |
20090215212 | Method for Fabricating A Flat Panel Display - The method for fabricating a flat panel display includes performing a first crystallization process to re-crystallize an amorphous silicon layer on a glass substrate to make the amorphous silicon layer become a polysilicon layer, forming a patterned absorbing layer to cover an active area pattern of a driving TFT and to expose portions of the polysilicon layer, performing a second crystallization process to re-crystallization the exposed portions of the polysilicon layer so that the exposed portions of the polysilicon layer has a different grain structure from the grain structure of the driving TFT, removing the patterned absorbing layer, and removing portions of the polysilicon layer to form an active area of the driving TFT and an active area of a switching TFT area in the exposed portions of the polysilicon layer of each sub-pixel. | 2009-08-27 |
20090215213 | Microelectromechanical device having a common ground plane and method for making aspects thereof - The present invention relates to MEM switches. More specifically, the present invention relates to a system and method for making MEM switches having a common ground plane. One method for making MEM switches includes: patterning a common ground plane layer on a substrate; forming a dielectric layer on the common ground plane layer; depositing a DC electrode region through the dielectric layer to contact the common ground plane layer; and depositing a conducting layer on the DC electrode region so that regions of the conducting layer contact the DC electrode region, so that the common ground plane layer provides a common ground for the regions of the conducting layer | 2009-08-27 |
20090215214 | Method of Sealing a Cavity - Embodiments disclosed herein generally include methods of sealing a cavity in a device structure. The cavity may be opened by etching away sacrificial material that may define the cavity volume. Material from below the cavity may be sputter etched and redeposited over and in passageways leading to the cavity to thereby seal the cavity. Material may be sputter etched from above the cavity and redeposited in the passageways leading to the cavity as well. The sputter etching may occur in a substantially inert atmosphere. As the sputter etching is a physical process, little or no sputter etched material will redeposit within the cavity itself. The inert gases may sweep out any residual gases that may be present in the cavity after the cavity has been opened. Thus, after the sputter etching, the cavity may be substantially filled with inert gases that do not negatively impact the cavity. | 2009-08-27 |
20090215215 | METHOD AND APPARATUS FOR MANUFACTURING MULTI-LAYERED ELECTRO-OPTIC DEVICES - A method is provided for producing a hybrid multi-junction photovoltaic device. The method begins by providing a plurality of planar photovoltaic semi-transparent modules. Each of the modules is a fully functional, thin-film, photovoltaic device and includes first and second conductive layers and at least first and second semiconductor layers disposed between the conductive layers. The first and second semiconductor layers define a junction at an interface therebetween. The method continues by disposing the modules one on top of another and hybridly adhering them to each other. At least one of the modules is configured to convert a first spectral portion of optical energy into an electrical voltage and transmit a second spectral portion of optical energy to another of the junctions that is configured to convert at least part of the second spectral portion of optical energy into an electrical voltage. | 2009-08-27 |
20090215216 | Packaging method of image sensing device - A packaging method for an image sensing device is disclosed. The packaging method includes the steps of a) mounting an image sensing module, having a light-receiving region exposed, on a substrate; b) connecting the image sensing module and the substrate via a plurality of bonding wires; c) forming a protecting layer on the light-receiving region of the image sensing module; d) forming a molding layer to seal the plurality of bonding wires; e) flattening the protecting layer and the molding layer; f) removing the protecting layer to expose the light-receiving region of the image sensing module; and g) forming a transparent lid. | 2009-08-27 |
20090215217 | SOLID-STATE IMAGING DEVICE AND METHOD FOR PRODUCING THE SAME - A method for producing a solid-state imaging device, which including: a photoelectric conversion section; a charge transfer section having a charge transfer electrode; and an antireflection film covering a light-receiving region in the photoelectric conversion section, wherein forming the antireflection film includes: forming a sidewall on a lateral wall of the charge transfer electrode after forming the charge transfer electrode; forming an antireflection film on a substrate surface where the sidewall is formed; forming a resist on the antireflection film; melting and flattening the resist to expose the antireflection film on the charge transfer electrode; removing the antireflection film by using the resist as the mask; removing the sidewall; covering the charge transfer electrode with an insulating film; and forming a light-shielding film that reaches a level lower than the top surface of the antireflection film, and that surrounds the periphery of the antireflection film. | 2009-08-27 |
20090215218 | METHOD FOR MAKING SOLAR CELL HAVING CRYSTALLINE SILICON P-N HOMOJUNCTION AND AMORPHOUS SILICON HETEROJUNCTIONS FOR SURFACE PASSIVATION - A thin silicon solar cell is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer at temperatures below approximately 400 degrees Celsius to reduce the loss of passivation properties of the amorphous silicon. A final layer of transparent conductive oxide is formed on both sides at approximately 165 degrees Celsius. Metal contacts are applied to the transparent conductive oxide. The low temperatures and very thin material layers used to fabricate the outer layers of used to fabricate the outer layers of the solar cell protect the thin wafer from excessive stress that may lead to deforming the wafer. | 2009-08-27 |
20090215219 | METHOD FOR MANUFACTURING SOLAR CELL - A method for manufacturing a solar cell having a single crystal silicon substrate and an amorphous silicon layer provided at least on one side surface of the single crystal silicon substrate is provided. The method includes the steps of: (a) forming an intrinsic amorphous silicon layer by coating a first liquid containing silicon atoms on one surface of the single crystal silicon substrate, and sintering the first liquid coated; and (b) forming an impure amorphous silicon layer on the intrinsic amorphous silicon layer. | 2009-08-27 |
20090215220 | SOLID-STATE IMAGE CAPTURING DEVICE, IMAGE CAPTURING DEVICE, AND MANUFACTURING METHOD OF SOLID-STATE IMAGE CAPTURING DEVICE - A solid-state image capturing device, includes a semiconductor board, upon which same semiconductor board are disposed in a predetermined order: a first detecting unit for detecting a first wavelength region component within an electromagnetic wave; and a second detecting unit for detecting a second wavelength region component which is longer wavelength side than at least the first wavelength region component, wherein in the depth direction from the surface of the semiconductor board, a valid region where a first electroconductive type dopant of the second detecting unit is formed reaches a portion deeper than a valid region where a first electroconductive type dopant of the first detecting unit is formed. | 2009-08-27 |
20090215221 | Image sensor and method for manufacturing the same - An image sensor may include a photo diode, a transfer transistor configured to transfer a photo charge generated by the photo diode to a floating diffusion region and buried channel transistors electrically coupled to the transfer transistor, wherein each of the transistors have a buried channel. The noise of the image sensor may be reduced because a channel of the buried-channel transistors in the active pixel region may be formed apart from a defected surface of a substrate when the buried-channel transistors are turned on. | 2009-08-27 |
20090215222 | Manufacturing method of semiconductor device - When a thin film transistor is manufactured by using a printing method, the precision of alignment between a first electrode and a second electrode becomes a problem. If it is manufactured by using photolithography, a photomask for each layer is necessary, resulting in the cost being increased. The essence of the present invention is that not only processing the gate shape is carried out over the substrate by using a resist pattern formed by exposing using a photo-mask for the gate pattern but also processing the source-drain electrodes is carried out by lifting-off. As a result, alignment between the source-drain electrode and the gate electrode is carried out. | 2009-08-27 |
20090215223 | ELECTROLUMINESCENT DEVICE - An optical device comprising an anode, a cathode comprising barium, strontium or calcium, and a layer of organic semiconducting material between the anode and the cathode wherein a layer of hole transporting and electron blocking material is located between the anode and the layer of organic semiconducting material. | 2009-08-27 |
20090215224 | COATING METHODS AND APPARATUS FOR MAKING A CIGS SOLAR CELL - A method for manufacturing a thin film solar cell involves applying an inductively-coupled-plasma during the deposition of selenium. A precursor thin film is formed. The precursor thin film can include copper, indium, and gallium. The inductively-coupled-plasma is applied to the selenium as the selenium is deposited into the precursor thin film to produce the thin film. The selenium is deposited into precursor thin film by evaporation, sputtering, or using a reactive gas. An inert gas is used as a carry and discharge gas. The precursor thin film and the selenium are deposited using a deposition system. The deposition system includes an inductively-coupled-plasma device. The inductively-coupled-plasma device includes a quartz plate, a plasma discharge coil, and an inlet system. The deposition can be an in-line system, a roll-to-roll system, or a hybrid system. | 2009-08-27 |
20090215225 | TELLURIUM COMPOUNDS USEFUL FOR DEPOSITION OF TELLURIUM CONTAINING MATERIALS - Precursors for use in depositing tellurium-containing films on substrates such as wafers or other microelectronic device substrates, as well as associated processes of making and using such precursors, and source packages of such precursors. The precursors are useful for deposition of chalcogenide thin films in the manufacture of nonvolatile Phase Change Memory (PCM), by deposition techniques such as chemical vapor deposition (CVD) and atomic layer deposition (ALD). | 2009-08-27 |
20090215226 | Method of Detaching a Thin Semiconductor Circuit From Its Base - In order to provide a method of detaching a thin semiconductor circuit ( | 2009-08-27 |
20090215227 | Chip Scale Package Fabrication Methods - Embodiments of the present invention includes a method of assembling a chip scale package (CSP). The method comprises adding bumps, sawing the saw streets from the front of a wafer, molding the front of the wafer, grinding the back of the wafer, sawing the saw streets from the back of the wafer, molding the back of the wafer, and sawing between devices to form a plurality of packaged devices. Sawing the saw streets from the front of the wafer establishes a first cut. Molding the front of the wafer includes using a first mold compound such that the mold compound fills in the first cut. Sawing the saw streets from the back of the wafer establishes a second cut. | 2009-08-27 |
20090215228 | WAFER LEVER FIXTURE AND METHOD FOR PACKAGING MICRO-ELECTRO-MECHANICAL-SYSTEM DEVICES - A fixture for packaging MEMS devices includes a base, a first material layer, an insulating layer and a second material layer. The base defines units, each including a notch. The first material layer is disposed on the base and the notches. The insulating layer is disposed on a part of the first material layer and exposes the other part of the first material layer located on the notches. The second material layer is disposed on the other part of the first material layer and formed with caps, whereby the caps are physically connected to the MEMS devices, and the MEMS devices are corresponding to the units of the base, wherein there is a first connecting force between the first and second material layers, there is a second connecting force between the caps and the MEMS devices, and the second connecting force is greater than the first connecting force. | 2009-08-27 |
20090215229 | Board on chip package and method of manufacturing the same - A ball grid array type board on chip package may include an integrated circuit chip having an active surface that supports a plurality of contact pads. An interposer may be adhered to the active surface of the integrated circuit chip. At least one hole may be provided through the interposer to expose the contact pads. A board, which may have a first surface supporting a plurality of metal lines, may have a second surface adhered to the interposer. The board may have an opening through which the contact pads may be exposed. A plurality of bonding wires may connect the contact pads to the metal lines through the opening. | 2009-08-27 |
20090215230 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The radiation performance of a resin sealed semiconductor package is enhanced and further the fabrication yield thereof is enhanced. A drain terminal coupled to the back surface drain electrode of a semiconductor chip is exposed at the back surface of an encapsulation resin section. Part of the following portion and terminal is exposed at the top surface of the encapsulation resin section: the first portion of a source terminal coupled to the source pad electrode of the semiconductor chip and a gate terminal coupled to the gate pad electrode of the semiconductor chip. The remaining part of the second portion of the source terminal and the gate terminal is exposed at the back surface of the encapsulation resin section. When this semiconductor device is manufactured, bonding material and a film member are placed between the drain terminal and the semiconductor chip. At the same time, paste-like bonding material and a film member are placed between the source terminal | 2009-08-27 |
20090215231 | METHOD OF MANUFACTURING ELECTRONIC COMPONENT BUILT-IN SUBSTRATE - In a method of manufacturing an electronic component built-in substrate of the present invention, a mounted body including a first insulating layer, a stopper metal layer formed under the first insulating layer of a portion corresponding to a component mounting region and a second insulating layer formed on a lower surface of the first insulating layer and covering the stopper metal layer is prepared, and a concave portion is obtained by penetration-processing a portion of the first insulating layer, which corresponds to the component mounting region to form an opening portion, while using the stopper metal layer as a stopper. Also, the stopper metal layer in the concave portion is removed, then an electronic component is mounted on the concave portion, and then a third insulating layer is formed on the electronic component. | 2009-08-27 |
20090215232 | SCHOTTKY BARRIER TUNNEL TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained. | 2009-08-27 |
20090215233 | PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING ARRAY SUBSTRATE USING THE SAME - A photoresist composition includes a binder resin, a photo acid generator, an acryl resin having four different types of monomers, and a solvent. | 2009-08-27 |
20090215234 | Semiconductor device, design method and structure - A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation region. At least a first conductive line can comprise a semiconductor material formed over and in contact with the first diffusion region and the second diffusion region. A portion of the first conductive line in contact with the first diffusion region is doped to an opposite conductivity type as the first diffusion region. At least a second conductive line comprising a semiconductor material is formed in parallel with the first conductive line and over and in contact with the first diffusion region and the second diffusion region. A portion of the second conductive line can be in contact with the first diffusion region and doped to a same conductivity type as the first diffusion region. A portion of the second conductive line in contact with the second diffusion region can be doped to a same conductivity type as the second diffusion region. | 2009-08-27 |
20090215235 | Arrangement with Two Transistors and Method for the Production Thereof - A transistor and a method for the fabrication of transistors with different gate oxide thicknesses is proposed, in which for the doping of the source, the typical LDD implantation, which is formed after the fabrication of the gate electrode, is replaced by a doping step, which is generated before applying the gate stack. In this way that is already a component of the remaining process sequence in the fabrication of the transistor doping can be used. | 2009-08-27 |
20090215236 | RELAXED-PITCH METHOD OF ALIGNING ACTIVE AREA TO DIGIT LINE - According to one aspect of the invention, a memory device is disclosed. The memory device comprises a substantially linear active area comprising a source and at least two drains defining a first axis. The memory device further comprises at least two substantially parallel word lines, at least a portion of a first word line located between a first drain and the source, and at least a portion of a second word line located between a second drain and the source, which word lines define a second axis. The memory device further comprises a digit line coupled to the source, wherein the digit line forms a substantially zig-zag pattern. | 2009-08-27 |
20090215237 | Method of forming lateral trench MOSFET with direct trench polysilicon contact - A lateral trench MOSFET includes a trench containing a device segment and a gate bus segment. The gate bus segment of the trench is contacted by a conductive plug formed in a dielectric layer overlying the substrate, thereby avoiding the need for the conventional surface polysilicon bridge layer. The conductive plug is formed in a substantially vertical hole in the dielectric layer. The gate bus segment may be wider than the device segment of the trench. A method includes forming a shallow trench isolation (STI) while the conductive material in the trench is etched. | 2009-08-27 |
20090215238 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH ENLARGED RECESSED GATE ELECTRODES - A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed. | 2009-08-27 |
20090215239 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A trench gate type power transistor of high performance is provided. A trench gate as a gate electrode is formed in a super junction structure comprising a drain layer and an epitaxial layer. In this case, the gate electrode is formed in such a manner that an upper surface of the epitaxial layer becomes higher than that of a channel layer formed over the drain layer. Then, an insulating film is formed over each of the channel layer and the epitaxial layer and thereafter a part of the insulating film is removed to form side wall spacers over side walls of the epitaxial layer. Subsequently, with the side wall spacers as masks, a part of the channel layer and that of the drain layer are removed to form a trench for a trench gate. | 2009-08-27 |
20090215240 | SEMICONDUCTOR DEVICE WITH STRAINED TRANSISTORS AND ITS MANUFACTURE - A semiconductor device has: a semiconductor substrate made of a first semiconductor material; an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor material; and a p-channel field effect transistor formed in the semiconductor substrate and having p-type source/drain regions made of a third semiconductor material different from the first semiconductor material, wherein the second and third semiconductor materials are different materials. The semiconductor device having n- and p-channel transistors has improved performance by utilizing stress. | 2009-08-27 |
20090215241 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES - A polysilazane perhydride solution, prepared by dispesing polysilazane perhydride in a solvent containing carbon, is applied on a semiconductor substrate ( | 2009-08-27 |
20090215242 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having a first element isolation trench with a first opening width and a second element isolation trench with a second opening width larger than the first opening width, the first and second element isolation trenches having respective inner surfaces, the second element isolation trench having opposed sidewalls and bottom, a first element-isolating insulation film formed on the inner surfaces of the first and second element isolation trenches, a second element-isolating insulation film formed on the first element-isolating insulation film so as to fill the first element isolation trench and further formed on the first element-isolating insulation film formed on the sidewall of the second element isolation trench, and a third element-isolating insulation film provided on the second element-isolating insulation film and the first element-isolating insulation film formed on the bottom of the second element isolation trench, so as to fill the second element isolation trench. | 2009-08-27 |
20090215243 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching. | 2009-08-27 |
20090215244 | Package Having Exposed Integrated Circuit Device - A package ( | 2009-08-27 |
20090215245 | Wafer dividing method - A method of dividing a wafer having a plurality of streets, which are formed in a lattice pattern on the front surface, and having devices, which are formed in a plurality of areas sectioned by the plurality of streets, into individual devices along the streets, comprising: a protective member-affixing step for affixing a protective member for protecting devices onto the front surface of the wafer; a deteriorated layer-forming step for applying a laser beam of a wavelength having permeability for the wafer from the rear surface side of the wafer along the streets to form a deteriorated layer along the streets in an area where it does not reach the final thickness of each device from the front surface of the wafer and the rear surface of the wafer in the inside of the wafer; a groove-forming step for cutting areas corresponding to the streets from the rear surface side of the wafer where the deteriorated layer has been formed along the streets to form a groove reaching the deteriorated layer; a dividing the wafer into individual devices along the streets where the deteriorated layer and the groove have been formed by exerting external force to the wafer; and a grinding the rear surface of the wafer which has been divided into individual devices until the final thickness of each device is achieved. | 2009-08-27 |
20090215246 | METHOD FOR BREAKING ADHESIVE FILM MOUNTED ON BACK OF WAFER - A method for breaking an adhesive film mounted on the back of a wafer having a plurality of streets formed in a lattice pattern on the face of the wafer, and having devices formed in a plurality of regions demarcated by the plurality of streets, the devices being divided individually, is adapted to break the adhesive film along the outer peripheral edges of the individual devices, with the adhesive film being stuck to the surface of a dicing tape mounted on an annular frame. The method comprises: a laser processing step of projecting a laser beam with a pulse width of 100 picoseconds or less onto the adhesive film through gaps between the individually divided devices to form deteriorated layers in the adhesive film along the outer peripheral edges of the individual devices; and an adhesive film breaking step of exerting external force on the adhesive film having the deteriorated layers formed therein, to break the adhesive film along the deteriorated layers. | 2009-08-27 |
20090215247 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Illumination devices ( | 2009-08-27 |
20090215248 | AlxInyGa1-x-yN MIXTURE CRYSTAL SUBSTRATE, METHOD OF GROWING SAME AND METHOD OF PRODUCING SAME - Seeds are implanted in a regular pattern upon an undersubstrate. An Al | 2009-08-27 |
20090215249 | METHOD OF FORMING AN EMBEDDED SILICON CARBON EPITAXIAL LAYER - Methods for forming embedded epitaxial layers containing silicon and carbon are disclosed. Specific embodiments pertain to the formation embedded epitaxial layers containing silicon and carbon on silicon wafers. In specific embodiments an epitaxial layer of silicon and carbon is non-selectively formed on a substrate or silicon wafer, portions of this layer are removed to expose the underlying substrate or silicon wafer, and an epitaxial layer containing silicon is formed on the exposed substrate or silicon wafers. In specific embodiments, gates are formed on the resulting silicon-containing epitaxial layers. | 2009-08-27 |
20090215250 | Plasma immersion ion implantation process with reduced polysilicon gate loss and reduced particle deposition - In plasma immersion ion implantation of a polysilicon gate, a hydride of the dopant is employed as a process gas to avoid etching the polysilicon gate, and sufficient argon gas is added to reduce added particle count to below 50 and to reduce plasma impedance fluctuations to 5% or less. | 2009-08-27 |
20090215251 | PLASMA IMMERSION ION IMPLANTATION PROCESS WITH CHAMBER SEASONING AND SEASONING LAYER PLASMA DISCHARGING FOR WAFER DECHUCKING - In a plasma immersion ion implantation process, the thickness of a pre-implant chamber seasoning layer is increased (to permit implantation of a succession of wafers without replacing the seasoning layer) without loss of wafer clamping electrostatic force due to increased seasoning layer thickness. This is accomplished by first plasma-discharging residual electrostatic charge from the thick seasoning layer. The number of wafers which can be processed using the same seasoning layer is further increased by fractionally supplementing the seasoning layer after each wafer is processed, which may be followed by a brief plasma discharging of the supplemented seasoning before processing the next wafer. | 2009-08-27 |
20090215252 | Methods of Depositing Materials Over Substrates, and Methods of Forming Layers over Substrates - The invention includes methods of utilizing supercritical fluids to introduce precursors into reaction chambers. In some aspects, a supercritical fluid is utilized to introduce at least one precursor into a chamber during ALD, and in particular aspects the supercritical fluid is utilized to introduce multiple precursors into the reaction chamber during ALD. The invention can be utilized to form any of various materials, including metal-containing materials, such as, for example, metal oxides, metal nitrides, and materials consisting of metal. Metal oxides can be formed by utilizing a supercritical fluid can be utilized to introduce a metal-containing precursor into reaction chamber, with the precursor then forming a metal-containing layer over a surface of a substrate. Subsequently, the metal-containing layer can be reacted with oxygen to convert at least some of the metal within the layer to metal oxide. | 2009-08-27 |
20090215253 | Method of Forming a Nitrogen-Enriched Region within Silicon-Oxide-Containing Masses - The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer. Source/drain regions are formed within the semiconductive substrate, and are gatedly connected to one another by the at least one conductive layer. The invention also encompasses transistor structures. | 2009-08-27 |
20090215254 | Design support system,computer readable medium, semiconductor device designing method and semiconductor device manufacturing method - A design support system which supports designing a semiconductor device is provided. The design support system includes a gate film information acquisition section and a maximum allowable antenna ratio setting section. The gate film information acquisition section acquires information on the thickness of the gate insulating film of a semiconductor device which has been designed. The gate insulating film thickness refers to a physical film thickness. The maximum allowable antenna ratio setting section sets maximum allowable antenna ratios for a gate electrode according to the film thickness information acquired by the gate film information acquisition section. Hence, a designer designing a semiconductor device can set concrete values when changing maximum allowable antenna ratios according to the thickness of the gate insulating film. | 2009-08-27 |
20090215255 | Methods Of Forming Dispersions Of Nanoparticles, And Methods Of Forming Flash Memory Cells - Some embodiments include methods of forming dispersions of nanoparticles. The nanoparticles are incorporated into first coordination complexes in which the nanoparticles are coordinated to hydrophobic ligands, and the first coordination complexes are dispersed within a non-polar solvent. While the first coordination complexes are within the non-polar solvent, the ligands are reacted with one or more reactants to convert the first coordination complexes into second coordination complexes that contain hydrophilic ligands. The second coordination complexes are then extracted from the non-polar solvent into water, to form a mixture of the second coordination complexes and the water. In some embodiments, the mixture may be dispersed across a semiconductor substrate to form a uniform distribution of the nanoparticles across the substrate. In some embodiments, the nanoparticles may then be incorporated into flash memory devices as charge-trapping centers. | 2009-08-27 |
20090215256 | Inverted T-Shaped Floating Gate Memory and Method for Fabricating the Same - A memory device having a floating gate with a non-rectangular cross-section is disclosed. The non-rectangular cross-section may be an inverted T shape, a trapezoid shape, or a double inverted T shape. Methods are disclosed for producing a floating gate memory device having an improved coupling ratio due to an increased surface area of the floating gate. The memory device has a floating gate having a cross-sectional shape, such as an inverted T shape, such that a top contour is not a flat line segment. | 2009-08-27 |
20090215257 | SEMICONDUCTOR DEVICES HAVING A TRENCH IN A SIDE PORTION OF A CONDUCTING LINE PATTERN AND METHODS OF FORMING THE SAME - A semiconductor device having a trench in the side portion of a conducting line pattern and methods of forming the same. The semiconductor device provides a way of preventing an electrical short between the conducting line pattern and a landing pad adjacent to the conducting line pattern. There are disposed two conducting line patterns on a semiconductor substrate. Each of the conducting line patterns includes a conducting line and a conducting line capping layer pattern stacked thereon. Each of the conducting line patterns has a trench between the conducting line capping layer pattern and the conducting line. Conducting line spacers are formed between the conducting line patterns. One conducting line spacer covers a portion of a sidewall of one of the conducting line patterns, and the remaining conducting line spacer covers an entire sidewall of the remaining conducting line pattern. A landing pad is disposed between the conducting line patterns. | 2009-08-27 |
20090215258 | Semiconductor device manufacturing method - There is provide a semiconductor device manufacturing method, including: preparing a substrate; laminating an insulation layer on the substrate; laminating a first underlying metal layer on the insulation layer; forming rewiring on the first underlying metal layer; removing exposed portions of the first underlying metal layer; laminating a second underlying metal layer on the rewiring and the insulation layer; forming a column electrode on the rewiring via the second underlying metal layer; and removing exposed portions of the second underlying metal layer. | 2009-08-27 |
20090215259 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a semiconductor package and a method of manufacturing the same. The semiconductor package includes a semiconductor chip that includes metal pads provided on a predetermined area of an upper side of a semiconductor substrate, where element structures used to manufacture a semiconductor element are formed, and bump electrodes connected to the metal pads; and a passivation film that is provided on an entire surface of the semiconductor chip other than upper surface of the bump electrodes. Therefore, it is possible to avoid difficulties in performing an epoxy underfill process used in a conventional flip chip bonding, and complexity and high cost resulting from the use of a molding compound process and a solder ball process. It is also possible to prevent damages to the lateral surface of the semiconductor chip due to an absence of the passivation film on the lateral surface of the semiconductor chip in a conventional wafer level package. | 2009-08-27 |
20090215260 | METHODS OF FORMING A BARRIER LAYER IN AN INTERCONNECT STRUCTURE - Methods of forming a barrier layer for an interconnection structure are provided. In one embodiment, a method for forming an interconnect structure includes providing a substrate having a first conductive layer disposed thereon, incorporating oxygen into an upper portion of the first conductive layer, depositing a first barrier layer on the first conductive layer, and diffusing the oxygen incorporated into the upper portion of the first conductive layer into a lower portion of the first barrier layer. In another embodiment, a method for forming an interconnection structure includes providing a substrate having a first conductive layer disposed thereon, treating an upper surface of the first conductive layer with an oxygen containing gas, depositing a first barrier layer on the treated conductive layer, and depositing a second conductive layer on the first barrier layer while driving a portion of oxygen atoms from the treated conductive layer into the first barrier layer. | 2009-08-27 |
20090215261 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect. | 2009-08-27 |
20090215262 | ATOMIC LAYER DEPOSITION SYSTEMS AND METHODS INCLUDING SILICON-CONTAINING TANTALUM PRECURSOR COMPOUNDS - The present invention provides atomic layer deposition systems and methods that include at least one compound of the formula (Formula I): Ta(NR | 2009-08-27 |
20090215263 | METHOD FOR INCREASING ETCH RATE DURING DEEP SILICON DRY ETCH - A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias. | 2009-08-27 |
20090215264 | PROCESS FOR SELECTIVE GROWTH OF FILMS DURING ECP PLATING - Methods of controlling deposition of metal on field regions of a substrate in an electroplating process are provided. In one aspect, a dielectric layer is deposited under plasma on the field region of a patterned substrate, leaving a conductive surface exposed in the openings. Electroplating on the field region is reduced or eliminated, resulting in void-free features and minimal excess plating. In another aspect, a resistive layer, which may be a metal, is used in place of the dielectric. In a further aspect, the surface of the conductive field region is modified to change its chemical potential relative to the sidewalls and bottoms of the openings. | 2009-08-27 |
20090215265 | Low-stain polishing composition - The invention is an aqueous composition useful for chemical mechanical polishing of a patterned semiconductor wafer containing a copper interconnect metal. The aqueous composition includes an oxidizer, an inhibitor for the copper interconnect metal, 0.001 to 15 weight percent of a water soluble modified cellulose, non-saccaride water soluble polymer, 0 to 15 complexing agent for the copper interconnect metal, 0 to 15 weight percent phosphorus compound, 0.05 to 20 weight percent of an acid compound that is capable of complexing copper ions, and water; and the solution has an acidic pH. | 2009-08-27 |
20090215266 | Polishing Copper-Containing patterned wafers - An aspect of the invention provides a method for polishing a patterned semiconductor wafer containing a copper interconnect metal with a polishing pad. The method includes the following: a) providing an aqueous polishing solution, the polishing solution containing an benzotriazole (BTA) inhibitor and a copper complexing compound and water; b) polishing the patterned wafer with the aqueous polishing solution and the polishing pad in a manner that dissolves copper into Cu | 2009-08-27 |
20090215267 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: polishing a semiconductor substrate to expose a polysilicon film on the semiconductor substrate using a chemical mechanical polishing method; cleaning the semiconductor substrate using a first acid cleaning solution; cleaning the semiconductor substrate with an ultrasonic wave using a second cleaning solution after cleaning the semiconductor substrate with said first acid cleaning solution; and cleaning the semiconductor substrate using a third cleaning solution, which is alkaline, after cleaning the semiconductor substrate with an ultrasonic wave. | 2009-08-27 |
20090215268 | POLISHING PROCESS FOR PRODUCING DAMAGE FREE SURFACES ON SEMI-INSULATING SILICON CARBIDE WAFERS - A polishing mixture and related method of polishing a material wafer surface, such as silicon carbide, are disclosed. The polishing mixture comprises; an abrasive and an oxidizer mixed in an acidic solution. Alumina may be used as the abrasive and the polishing mixture may have a pH less than or equal to seven (7). | 2009-08-27 |
20090215269 | INTEGRATED CHEMICAL MECHANICAL POLISHING COMPOSITION AND PROCESS FOR SINGLE PLATEN PROCESSING - Chemical mechanical polishing (CMP) compositions and single CMP platen process for the removal of copper and barrier layer material from a microelectronic device substrate having same thereon. The process includes the in situ transformation of a Step I slurry formulation, which is used to selectively remove and planarize copper, into a Step II slurry formulation, which is used to selectively remove barrier layer material, on a single CMP platen pad. | 2009-08-27 |
20090215270 | Polishing liquid and polishing method - A polishing liquid is provided which has good storage stability and is capable of inhibiting generation of scratching caused by aggregation of solid abrasive grains or the like during use. A polishing method using the polishing liquid is also provided. The polishing liquid includes: (a) an aqueous solution A including colloidal silica particles in an amount of from 5 mass % to 40 mass % with respect to the total mass of the aqueous solution A, and having a pH of from 1 to 7; and (b) an aqueous solution B including a quaternary ammonium cation, wherein the aqueous solution A and the aqueous solution B are separately prepared and mixed to provide the polishing liquid immediately before used in polishing. | 2009-08-27 |
20090215271 | Polishing composition and method for high silicon nitride to silicon oxide removal rate ratios - The invention provides a chemical-mechanical polishing composition comprising a cationic abrasive, a cationic polymer, an inorganic halide salt, and an aqueous carrier. The invention further provides a method of chemically-mechanically polishing a substrate with the aforementioned polishing composition. The polishing composition exhibits selectivity for removal of silicon nitride over removal of silicon oxide and polysilicon. | 2009-08-27 |
20090215272 | DOUBLE MASK SELF-ALIGNED DOUBLE PATTERNING TECHNOLOGY (SADPT) PROCESS - A method for providing features in an etch layer is provided by forming an organic mask layer over the inorganic mask layer, forming a silicon-containing mask layer over the organic mask layer, forming a patterned mask layer over the silicon-containing mask layer, etching the silicon-containing mask layer through the patterned mask, depositing a polymer over the etched silicon-containing mask layer, depositing a silicon-containing film over the polymer, planarizing the silicon-containing film, selectively removing the polymer leaving the silicon-containing film, etching the organic layer, and etching the inorganic layer. | 2009-08-27 |
20090215273 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - In a method of fabricating a semiconductor device, a charge storage layer is etched using an etching gas by which a tunnel insulating layer is less etched than the charge storage layer. Thus, it is possible to prevent the tunnel insulating layer formed below the charge storage layer from being damaged when the charge storage layer is patterned. The method of fabricating a semiconductor device includes providing a semiconductor substrate on which a tunnel insulating layer and a charge storage layer formed of an insulating material are formed; forming a stack layer on the charge storage; patterning the stack layer to expose a portion of the charge storage layer; and etching the exposed charge storage layer using as etching gas hydrogen bromide (HBr) gas, chloride (Cl | 2009-08-27 |
20090215274 | Plasma processing apparatus and plasma processing method - The plasma processing apparatus includes a holding table disposed in a processing chamber, for holding thereon a target substrate; a dielectric plate disposed at a position facing the holding table, for introducing a microwave into the processing chamber; a plasma igniting unit for carrying out plasma ignition in a state in which an electric field is generated inside the processing chamber by the introduced microwave, thereby generating the plasma inside the processing chamber; and a control unit, which includes an elevating mechanism, for performing control operations to alter a distance between the holding table and the dielectric plate to a first distance, to drive the plasma igniting unit, to alter the distance between the holding table and the dielectric plate to a second distance different from the first distance, and to carry out the plasma process on the semiconductor substrate. | 2009-08-27 |
20090215275 | Defect Etching of Germanium - The present invention provides an etching solution for revealing defects in a germanium layer, a method for revealing defects in a germanium layer using such an etching solution and to a method for making such an etching solution. The etching solution according to embodiments of the present invention is able to exhibit an etch rate of between 4 nm·min | 2009-08-27 |
20090215276 | PHOTOELECTROCHEMICAL CELL WITH CARBON NANOTUBE-FUNCTIONALIZED SEMICONDUCTOR ELECTRODE - Photoelectrochemical cells and methods are provided, in particular, to the functionalization of semiconductor surfaces such that its semiconducting and light generating properties are maintained and the surface becomes stable in wet environments. In particular the preferred embodiments relate to unstable semiconductor materials which have photocurrent generating properties, and to methods for the functionalization of surfaces with metallic carbon nanotubes (CNTs). | 2009-08-27 |
20090215277 | DUAL CONTACT ETCH STOP LAYER PROCESS - A dual CESL process includes: (1) providing a substrate having thereon a first device region, a second device region and a shallow trench isolation (STI) region between the first and second device regions; (2) forming a first-stress imparting film with a first stress over the substrate, wherein the first-stress imparting film does not cover the second device region; and (3) forming a second-stress imparting film with a second stress over the substrate, wherein the second-stress imparting film does not cover the first device region, an overlapped boundary between the first- and second-stress imparting films is created directly above the STI region, and wherein the overlapped boundary is placed in close proximity to the second device region in order to induce the first stress to a channel region thereof in a transversal direction. | 2009-08-27 |
20090215278 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Prior to a step of providing a stress layer covering a first transistor, a second transistor and a gate structure, another silicon oxide film is formed over the second transistor to form a silicon oxide film with a predetermined thickness over the second transistor. By a step of removing the portion of the stress layer over the second transistor and the gate structure and leaving the portion of the stress layer over the first transistor, the silicon oxide film over the second transistor is prevented from becoming excessively thinner than the silicon oxide film over the first transistor. The source region and the drain region of the second transistor can be prevented from being shaved because of thinness of the silicon oxide film over the second transistor when removing silicon oxide films over the first transistor and second transistor. | 2009-08-27 |
20090215279 | ORGANIC/INORGANIC HYBRID THIN FILM PASSIVATION LAYER FOR BLOCKING MOISTURE/OXYGEN TRANSMISSION AND IMPROVING GAS BARRIER PROPERTY - The present invention relates to an organic/inorganic hybrid thin film passivation layer comprising an organic polymer passivation layer prepared by a UV/ozone curing process and an inorganic thin film passivation layer for blocking moisture and oxygen transmission of an organic electronic device fabricated on a substrate and improving gas barrier property of a plastic substrate; and a fabrication method thereof. Since the organic/inorganic hybrid thin film passivation layer of the present invention converts the surface polarity of an organic polymer passivation layer into hydrophilic by using the UV/ozone curing process, it can improve the adhesion strength between the passivation layer interfaces, increase the light transmission rate due to surface planarization of the organic polymer passivation layer, and enhance gas barrier property by effectively blocking moisture and oxygen transmission. | 2009-08-27 |
20090215280 | Passivation of Wide Band-Gap Based Semiconductor Devices with Hydrogen-Free Sputtered Nitrides - A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer. | 2009-08-27 |
20090215281 | HDP-CVD SION FILMS FOR GAP-FILL - The present invention pertains to methods of depositing low stress/high index multi-layer films on a substrate using an HDP-CVD process. The multi-layer films include two lining layers and a bulk gap-fill layer and the HDP-CVD process employs a reduced substrate bias power during deposition of at least the second lining layer. Deposition of the three layers occurs at reduced deposition temperatures which further reduces the stress of the multi-layer film. The lower stress results in less defectivity which improves the films ability to maintain optical confinement of radiation. | 2009-08-27 |
20090215282 | PROCESSES FOR CURING SILICON BASED LOW-K DIELECTRIC MATERIALS - Processes for curing silicon based low k dielectric materials generally includes exposing the exposing the silicon based low k dielectric material to ultraviolet radiation in an inert atmosphere having an oxidant in an amount of about 10 to about 500 parts per million for a period of time and intensity effective to cure the silicon based low k dielectric material so to change a selected one of chemical, physical, mechanical, and electrical properties and combinations thereof relative to the silicon based low k dielectric material prior to the ultraviolet radiation exposure. Also disclosed herein are silicon base low k dielectric materials substantially free of sub-oxidized SiO species. | 2009-08-27 |
20090215283 | CONNECTOR - A connector includes a plug and a receptacle. The plug includes a plurality of conductive terminals and a first magnet. The receptacle is detachably coupled to the first part. The receptacle defines a plurality of insertion holes and includes a second magnet. The plurality of insertion holes are for providing electrical connection by engaging with the plurality of conductive terminals. The second magnet is for maintaining a magnetic force repulsive to the first magnet when the first part and the second part are coupled together. | 2009-08-27 |
20090215284 | USB CONNECTOR AND USB DEVICE - A USB connector for connecting with a USB female comprises metal legs, a connecting line, a substrate and a rotating shaft assembly. One end of the metal legs connects with one end of the connecting line. The metal legs are formed on a surface of the substrate. The connecting line is fixed to the surface of the substrate. The rotating shaft assembly is fixed to the surface of the substrate. The present invention also provides a USB device. According to the USB connector and the USB device of the present invention, the metal legs are formed on the surface of the substrate so as to ensure the connecting strength of the metal legs. Since the size of the USB connector depends mainly on the substrate and as long as the thickness meets a requirement of inserting the USB connector into the USB female, the thickness of the USB connector and further the thickness of the USB device are reduced without compromising the function of the USB connector. Compared with the conventional USB products, the thickness of the USB device according to the present invention is greatly reduced so that the USB device takes less space and easy to carry. It not only meets the people's requirement for exquisite and compact electronic products, but also improves the practicality and aesthetics of the USB device. | 2009-08-27 |
20090215285 | CIRCUIT CARD CONNECTOR ARRANGEMENT FOR IMPROVED CARD INSERTION/REMOVAL DETECTION - A circuit card connector arrangement is provided, wherein one of the connectors on the card is recessed relative to the other connectors. Using this arrangement, insertion and extraction detection of the card into another card is optimized without the need for a short pin on the other card. The recessed connector is the last connector on the card to make electrical contact with the other card upon insertion and the first connector to lose electrical contact with the other card upon extraction. Since the degree of recess and the choice of which connector is recessed is made by the designer of the inserted card rather than dependent on the design of the main card or board, such as a backplane, onto which the card is inserted, greater flexibility is possible in the design of the card and of the insertion/extraction circuitry on the card. In addition, insertion and extraction can be detected even if the main board does not have a short pin, such as occurs in some legacy system. | 2009-08-27 |
20090215286 | ADAPTER FOR A COAXIAL CABLE - An adapter for connecting a multi-core cable to a coaxial cable is provided. Adapters according to an exemplary embodiment of the present invention may be used in an arrangement comprising several adapters that are connected to each other using of a coaxial cable. Adapters and arrangements according to an exemplary embodiment of the present invention may allow a cost-effective conversion of existing mobile radio stations to modern RRH technology. | 2009-08-27 |
20090215287 | Substrate Connecting Member and Connecting Structure - A substrate connecting member connects two circuit boards connected together while maintaining high reliability of the junctions between itself and the circuit boards even if the circuit boards are warped by temperature change of an impact load. The substrate connecting member includes a frame member made of an insulating resin; slit grooves formed in at least one of the inner and outer surfaces of frame side portions composing the frame member, the slit grooves being formed throughout the entire length of the frame side portions in the direction perpendicular to the thickness direction of the frame side portions; and connection conductor portions having connection terminals provided on the top and bottom surfaces, respectively, of the frame side portions in the thickness direction and connecting conductors each connecting connection terminals. | 2009-08-27 |
20090215288 | CONNECTOR - A connector for electrically connecting with a first circuit board and a second circuit board, the connector includes a female connector and a male connector. The female connector includes a housing, a moveable side electrode capable of moving in the housing and an elastic member biasing the moveable side electrode, the moveable side electrode having a recess. The male connector includes a projection with a tip end being fitted into the recess of the moveable side electrode. | 2009-08-27 |
20090215289 | LARGE ARRAY SURFACE MOUNT TECHNOLOGY CONNECTOR CRADLE ASSEMBLY - A large array connector assembly for containing a plurality of wafers is disclosed. The large array connector assembly includes a plurality of guide blocks that includes first and second guide blocks. The first guide block being located at a first end of the assembly. The second guide block being located at a second end of the assembly. A first plate is mechanically coupled to a first portion of the first guide block and a first portion of the second guide block. The first plate includes a plurality of slots each for receiving a tab extending from a corresponding wafer so as to substantially prevent movement of the corresponding wafer in first and second directions while allowing a given degree of movement in a third direction. A second plate is mechanically coupled to a second portion of the first guide block and a second portion of the second guide block. | 2009-08-27 |
20090215290 | Cable connector assembly - A cable connector assembly ( | 2009-08-27 |
20090215291 | Socket Contact and PGA IC Socket - A socket contact that makes contact with a lead pin is provided on a mating electronic component, wherein this socket contact comprises a retention section that is press-fit in a contact cavity provided in a housing, a base section that extends downward from this retention section, and a pair of resilient contact pieces that extend from either side edge of this base section in mutually facing directions. The paired resilient contact pieces respectively comprise end sections that extend backward from the side edges of the base section, and lead pin contact sections that extend upward and forward at an inclination from the rear ends of the base section and that are also formed with an inclination so as to approach each other toward the tip ends thereof, and after the lead pin is inserted into the contact cavity toward the rear ends of the base end parts, the lead pin moves forward so as to contact the lead pin contact section in a position to the rear side of the retention section. | 2009-08-27 |
20090215292 | ELECTRICAL PRINTED CIRCUIT BOARD WITH A SCREWLESS TERMINAL CONNECTION - A printed circuit board (PCB) assembly includes a PCB and a screwless terminal connection having a conductor rail and a clamping spring. The PCB has a recess on an edge. The conductor rail has a base part soldered to the PCB and bridging the PCB recess. The base part includes an end extending past the PCB edge. The clamping spring includes three spring legs. The first leg contacts the base part and is between the base part and the PCB recess. The first leg includes an end extending past the PCB edge and contacting the end of the base part. The second leg extends from the first leg through the PCB recess and is beneath the PCB. The third leg includes a clamping aperture and extends upward from the second leg above the PCB. The ends of the base part and the first leg extend through the clamping aperture. | 2009-08-27 |
20090215293 | Electronic Part Connector - To provide a connector that incorporates a built-in electronic part, which allows for easy assembly for obtaining a required connection structure, ensures connection reliability, and prevents dislodging of the electronic part even when used in locations involving frequent vibrations. | 2009-08-27 |
20090215294 | Separable connector with interface undercut - Separating connector assemblies of a separable connector system. The separable connector assemblies include one or more pairs of connectors configured to engage and disengage one another in electrical connection and disconnection operations, respectively. An operator can disengage the connectors by pushing the connectors together and then pulling the connectors apart. Pushing the connectors together shears interface adhesion between the connectors, making it easier for the operator to pull the connectors apart. One of the connectors can include a nose end having an undercut segment configured to not engage an interior surface of the other connector when the connectors are engaged. Limiting the surface area of the nose end that interfaces with the interior surface of the other connector reduces surface adhesion and a pressure drop when separating the connectors, making separation easier to perform. | 2009-08-27 |
20090215295 | MODULAR SLIM CONNECTOR - A floating type electrical connecting device, comprises: first and second electrical connectors. The first electrical connector includes a first insulating housing, and a plurality of first conductive terminals. The first insulating housing has a first mating surface, a plugging surface located on an opposite side of the first mating surface, two side surfaces respectively connected at opposite left and right sides of the first mating surface and the plugging surface, and a plurality of first terminal grooves extending from the mating surface to the plugging surface through the first insulating housing. In addition, a vertical lateral protruding edge is formed at each side surface adjacent to the first mating surface, and protruding from the side surface. The second electrical connector includes a second insulating housing, and a plurality of second conductive terminals. The second insulating housing has two sliding grooves respectively for receiving the two lateral protruding edges. | 2009-08-27 |
20090215296 | IMPLANTABLE ELECTRICAL CONNECTOR - An implantable connector for connecting components of implantable medical devices. The connector comprises first and second connector halves electrically coupled to the implantable components. A sealing membrane is provided to seal the electrical connection between the first and second connector halves. The sealing membrane is configured to be ruptured with a minimal amount of force so that the connector halves may be readily disconnected from each other. | 2009-08-27 |
20090215297 | INTERNALLY-SEALED ELECTRICAL CONNECTOR - An internally-sealed pass-through electrical connector includes electrical conductors for carrying electrical signals through the electrical connector, a connector body or shell surrounding the connector, and an organic adhesive material within the body or shell that fills space around the conductors and between the conductors and the connector body. The connector body includes a metal portion, such as an aluminum portion, that has a roughened surface to better allow the adhesive to adhere to it. The roughened surface may be a grit blasted surface. The connector body may also include a plastic portion, such as a molded lead organizer, to aid in positioning the leads. The adhesive may have a coefficient of thermal expansion that is matched to that of the metal portion of the connector body or shell. The organic adhesive may be an epoxy material. The electrical connector may have any of a variety of configurations. | 2009-08-27 |
20090215298 | Sealed Electrical Connector - This connector includes an insulative housing having a plurality of terminal accommodating chambers, a grommet formed with a plurality of cable passages, a grid having a plurality of passages in correspondence with the passages and a closing member mounted at the rear side of the grid for selectively closing the passage to a first predetermined group of chambers, said closing member including a plate, which is formed with through-holes in correspondence with a second predetermined group of chambers. The closing member further includes at least one plug projecting from the plate in correspondence with the first group of chambers, said plugs being provided to be inserted in the respective passages of the seal, and thus sealingly close said passages. | 2009-08-27 |