35th week of 2009 patent applcation highlights part 60 |
Patent application number | Title | Published |
20090216904 | Method for Accessing Domain Name Related Reputation - Systems and methods of the present invention allow for tracking of domain name related reputation by a domain name Registering Entity (e.g. Registry, Registrar, etc.). In a preferred embodiment, the Registering Entity maintains a database with reputation data that can be accessed by the requesters. The Registering Entity may update reputation data based on a variety of events related to the domain name. The reputation data may be tracked on the domain name itself, URLs, domain name purchaser or registrant, or email addresses associated with the domain name. The reputation data may include various categories, such as email practices, website content, privacy policies and practices, fraudulent activities, domain name related complaints, overall reputation, etc. The registrant may opt for a reputation service while registering domain name. The requester may decide whether to allow email messages or to visit URLs based on the domain name related reputation. | 2009-08-27 |
20090216905 | System for Tracking Domain Name Related Reputation - Systems and methods of the present invention allow for tracking of domain name related reputation by a domain name Registering Entity (e.g. Registry, Registrar, etc.). In a preferred embodiment, the Registering Entity maintains a database with reputation data that can be accessed by the requesters. The Registering Entity may update reputation data based on a variety of events related to the domain name. The reputation data may be tracked on the domain name itself, URLs, domain name purchaser or registrant, or email addresses associated with the domain name. The reputation data may include various categories, such as email practices, website content, privacy policies and practices, fraudulent activities, domain name related complaints, overall reputation, etc. The registrant may opt for a reputation service while registering domain name. The requester may decide whether to allow email messages or to visit URLs based on the domain name related reputation. | 2009-08-27 |
20090216906 | INTER-DOMAIN CONTEXT TRANSFER USING CONTEXT TRANSFER MANAGERS - A method and apparatus for improved context transfer in heterogeneous networks is presented. Context information is collected from source entities in a first access network by a context transfer manager and transmitted to a context transfer manager of a second access network which forwards the context information to target entities therein, in one of the context transfer managers at least a part of the context information is translated from a format supported in the first access network to another format supported in the second access network. The method may be carried out proactively preceding a handover or reactively following a handover. In one embodiment, context transfer within one access domain is performed directly between access routers, whereas context transfer between different access domains is performed via the context managers. In another embodiment, beacons from access points are counted in order to determine candidates for a pending handover. | 2009-08-27 |
20090216907 | SECURE BLOCK READ AND WRITE PROTOCOL FOR REMOTELY STORED FILES - A file transfer system including a client and a server capable of updating portions of the file stored on the server. The system is capable of uploading portions of a file before the file has been specified at the client side. The files are stored in raw at the client and the server, which preserves the block list mapping. The file transfer protocol is capable of compressing and encrypting transferred data. As a result, the partial file writes are possible while maintaining current bandwidth usage. The write request data structure is provided with additional features in the form of flags and fields to provide reliable transmission of partial file data. | 2009-08-27 |
20090216908 | Personal Computing Environment With Virtual Computing Device - Systems and methods of providing synchronization of providing a device mesh and a virtual computing device are disclosed herein. A selection of a plurality of computer devices, such as PDAs, cellphone, laptops, and the like, can be received from a user. The data at the virtual computing device and the plurality of devices can be synchronized. Access to all applications available in each computing device in the plurality of computing devices can be provided at the virtual computing device. Access to all data available in each computing device in the plurality of computing devices can be provided at the virtual computing device. Access to the virtual computing device can be provided via a data network. | 2009-08-27 |
20090216909 | Setting time from a NFS server - An apparatus and a method for setting a system time of a client from a network file system (NFS) server is described. In one embodiment, the client creates a file on the (NFS) server and reads the last-modified time attribute of the file. The client adjusts its system time accordingly based on the last-modified time attribute of the file. The file is then deleted from the NFS server. | 2009-08-27 |
20090216910 | COMPUTING INFRASTRUCTURE - An affordable, highly trustworthy, survivable and available, operationally efficient distributed supercomputing infrastructure for processing, sharing and protecting both structured and unstructured information. A primary objective of the SHADOWS infrastructure is to establish a highly survivable, essentially maintenance-free shared platform for extremely high-performance computing (i.e., supercomputing)—with “high performance” defined both in terms of total throughput, but also in terms of very low-latency (although not every problem or customer necessarily requires very low latency)—while achieving unprecedented levels of affordability at its simplest, the idea is to use distributed “teams” of nodes in a self-healing network as the basis for managing and coordinating both the work to be accomplished and the resources available to do the work. The SHADOWS concept of “teams” is responsible for its ability to “self-heal” and “adapt” its distributed resources in an “organic” manner. Furthermore, the “teams” themselves are at the heart of decision-making, processing, and storage in the SHADOWS infrastructure. Everything that's important is handled under the auspices and stewardship of a team. | 2009-08-27 |
20090216911 | Method and system for intuitive coding to enter text expansions - The present invention relates generally to a keyboarding productivity system for expanding a number of characters entered into a computing device. The present invention expands a first predefined set of characters to a second predefined set of characters, an expansion associated with a matching code. A user of the present invention inputs a user entry into a program that accepts user input. The present invention then compares the user entry to at least one code to identify a matching code that matches the user entry. The present invention then expands the user entry to the expansion associated with the matching code. If a matching code is not found, the present invention allows the user entry to remain as input. | 2009-08-27 |
20090216912 | Default Peripheral Device Selection Based on Location - In accordance with one or more aspects of the default peripheral device selection based on location, a current location of a computing device is obtained. A mapping record of default peripheral devices to locations is accessed to identify a default peripheral device corresponding to the current location of the computing device, and the identified default peripheral device is returned as a current default peripheral device for the computing device. Additionally, an identification of a peripheral device to be a default peripheral device can be received. A mapping of the current location of the computing device to the identified default peripheral device can also be stored. | 2009-08-27 |
20090216913 | Data processing system for keeping isolation between logical partitions - When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed. | 2009-08-27 |
20090216914 | Information Processing Apparatus and Information Processing Method - The present invention relates to an information processing apparatus capable of accurately controlling DMA transfer of a plurality of pieces of data present in a memory with a simple hardware configuration, and an information processing method for use therewith. A memory | 2009-08-27 |
20090216915 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MERGING DATA - A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining if the data exists in a local cache memory that is in local communication with the input/output device, fetching the data to the local cache memory from a remote cache memory or a main memory if the data does not exist in the local cache memory, merging the data according to the request to obtain a merged data, and storing the merged data in the local cache, wherein the merging of the data is performed without using a memory controller within a control flow or a data flow of the merging of the data. A corresponding system and computer program product. | 2009-08-27 |
20090216916 | METHOD AND APPARATUS FOR INPUTTING/OUTPUTTING DATA USING VIRTUALIZATION TECHNIQUE - A method and apparatus for inputting and outputting data by using a virtualization technique are provided. The method includes generating a virtual operating system (OS) for the external device, which is connected to a host, based on OS information stored in the external device, setting a partial area of a storage of the host as virtual storage for the external device, and storing the data in the virtual storage or a memory of the external device in response to a request for inputting and outputting the data from the virtual OS. | 2009-08-27 |
20090216917 | DEVICE AND METHOD FOR ARBITRATING BETWEEN DIRECT MEMORY ACCESS TASK REQUESTS - A method for arbitrating between direct memory access task requests, the method includes receiving multiple DMA task requests; the method is characterized by selecting a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. A device that includes an interface, that is adapted to receive DMA task requests; the device is characterized by including an arbiter that is adapted to select a DMA task request out of the multiple DMA task requests in response to timing deadlines associated with the DMA tasks. | 2009-08-27 |
20090216918 | METHOD AND SYSTEM FOR TRACKING - A system for tracking using electronic addresses is disclosed. The system stores an identification code, an electronic address, and a counter. The electronic address is made up of either single values or pairs of single values. A pair of single values for at least one of value of the counter is made up of a pseudonumber and a unique address value. The pseudonumber is able to be disentangled to produce a second pair of single values for a different value of the counter, thereby producing a tracking history. | 2009-08-27 |
20090216919 | CHANNEL DEVICE, INFORMATION PROCESSING SYSTEM AND DATA TRANSFER METHOD - A channel device equipped with a data buffer unit storing data transferred between a storage device and an input-output device, a transfer controller transferring continuous data between the storage device and the data buffer unit using channel startup information. The storage device transfer controller transfers first data between the storage device and the data buffer unit using first transfer information stored in the address list and transfers the second data using second transfer information and total transfer amount information stored in the address list after the first data is transferred and an input-output device transfer controller transfers the continuous data between the data buffer unit and the input-output device. | 2009-08-27 |
20090216920 | Dis-Aggregated and Distributed Data-Center Architecture Using a Direct Interconnect Fabric - A data center has several dis-aggregated data clusters that connect to the Internet through a firewall and load-balancer. Each dis-aggregated data cluster has several dis-aggregated compute/switch/disk chassis that are connected together by a mesh of Ethernet links. Each dis-aggregated compute/switch/disk chassis has many processing nodes, disk nodes, and I/O nodes on node cards that are inserted into the chassis. These node cards are connected together by a direct interconnect fabric. Using the direct interconnect fabric, remote I/O and disk nodes appear to the operating system to be located on the local processor's own peripheral bus. A virtual Ethernet controller and a virtual generic peripheral act as virtual endpoints for the local processor's peripheral bus. I/O and disk node peripherals are virtualized by hardware without software drivers. Rack and aggregation Ethernet switches are eliminated using the direct interconnect fabric, which provides a flatter, dis-aggregated hierarchy. | 2009-08-27 |
20090216921 | BRIDGE, PROCESSOR UNIT, INFORMATION PROCESSING APPARATUS, AND ACCESS CONTROL METHOD - There is provided a technique of accessing a memory of a processor from a peripheral device, thereby the security is ensured while efficiency is being pursued. An address converter | 2009-08-27 |
20090216922 | USB Driver Apparatus, USB External Apparatus, USB System Having the Same and USB Connect Apparatus Using Light Guide - Provided are a USB driver apparatus using an optical waveguide, a USB external apparatus connected to the same, and a USB system and a USB connection apparatus including the same. The USB driver apparatus includes an optical USB port connected to the USB terminal of the external apparatus and configured to exchange data with the USB terminal using an optical signal; a USB interface part configured to input and output data through the optical USB port; and a photoelectric converter connected between the optical USB port and the USB interface part and configured to convert an optical signal into an electrical signal and vice versa, wherein the optical USB port and the photoelectric converter are connected to each other through the optical waveguide to transmit data as an optical signal. Therefore, it is possible to largely increase a data transmission speed of the USB system. | 2009-08-27 |
20090216923 | MANAGING RECOVERY OF A LINK VIA LOSS OF LINK - A computer program product, apparatus and method for managing recovery of a link in a multi-tasking multi-processor environment. An exemplary embodiment includes shutting off timers for a failed channel associated with the communications link, storing a loss of link condition in a data structure, disabling communications on the failed channel and sending an external notification of the loss of link condition. | 2009-08-27 |
20090216924 | Interconnection system - An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths are arranged and operated so as to control the power consumption and data skew properties of the system. A configurable switching element may be used to form the interconnections at nodes, where a control signal and other information is used to manage the power status of other aspects of the configurable switching element. Time delay skew of data being transmitted between nodes of the network may be altered by exchanging the logical and physical line assignments of the data at one or more nodes of the network. A method of laying out an interconnecting motherboard is disclosed which reduces the complexity of the trace routing. | 2009-08-27 |
20090216925 | PSEUDO-FULL DUPLEX COMMUNICATION USING A HALF DUPLEX COMMUNICATION PROTOCOL - In a communication system having a master-slave arrangement communicating with each other using the RS485 protocol, an FPGA with a buffer memory is provided in the master and slave, respectively, to handle the actual communication. The CPUs of the master and slave transfer data to and from the respective buffer memory. The master's FPGA initiates and maintains communication with the slave's FPGA. The masters FPGA and the slave's FPGA communicate with each other using the RS485 protocol by transmitting requests, acknowledgements and data. From the standpoint of the CPUs of the master and slave, the communication appears to be full duplex, although the actual communication between the FPGAs is half duplex. One particular application of the communication method is a KVM switch system where the KVM switch acts as the master and the computers connected to the KVM switch act as slaves. | 2009-08-27 |
20090216926 | APPARATUS TO IMPROVE BANDWIDTH FOR CIRCUITS HAVING MULTIPLE MEMORY CONTROLLERS - An apparatus for improving bandwidth for circuits having a plurality of memory controllers employing a first memory controller, a second memory controller, a first busy read output signal circuit, a first busy write output signal circuit, a second busy read output signal circuit, and a second busy write output signal circuit. The first busy read output signal indicates when the first memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the first memory controller. The first busy write output signal indicates when the first memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the first memory controller. The second busy read output signal indicates when the second memory controller releases the address bus for a next external access subsequent to a read access to the data bus by the second memory controller. The second busy write output signal indicates when the second memory controller releases the data bus for a next external access subsequent to a write access to the data bus by the second memory controller. | 2009-08-27 |
20090216927 | MANAGING RECOVERY AND CONTROL OF A COMMUNICATIONS LINK VIA OUT-OF-BAND SIGNALING - A computer program product, apparatus and method for managing recovery and control of a communications link via out-of-band signaling. An exemplary embodiment includes sending a command, sending an invalidate request to a buffer associated with the command and receiving a response to the invalidate request at least one of prior to the command reaching the recipient and after the command reaching the recipient. | 2009-08-27 |
20090216928 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A NEW QUIESCE STATE - A system, method and computer program product for providing a new quiesce state. The method includes receiving a quiesce request at a system controller from an initiating processor. The quiesce request is sent to a plurality of processors. Notification is received at the system controller that the processors have finished purging their translation look aside buffers (TLBs). A fast quiesce reset command is received at the system controller from the initiating processor once updates to the system resources are complete. It is indicated to the processors that the block translation restriction can be dropped in response to receiving the fast quiesce reset command, thereby allowing the processors to continue processing without block translation restrictions. | 2009-08-27 |
20090216929 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A PROGRAMMABLE QUIESCE FILTERING REGISTER - A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is identified. It is determined if the quiesce interruption request can be filtered by the processor. The determining is responsive to the filtering zone and to contents of a programmable filtering register for indicating exceptions to filtering performed by the receiving processor. The quiesce interruption request is filtered in response to determining that the request can be filtered. | 2009-08-27 |
20090216930 | INFORMATION PROCESSING APPARATUS AND CONTROL METHOD THEREOF - An information processing apparatus connected with an IO device, having a processing unit, a channel device transferring data between the information processing apparatus and the IO device having a activation controller activating the channel device, a storage device having a predetermined area storing a result operation executed by the channel device, an interrupt controller controlling an interrupt required by the channel device to the processing unit, a channel device controller controlling the channel device and a driver writing a request for a first interrupt in the area of the storage device through the channel device and requiring the first interrupt to the processing unit by using the interrupt controller, wherein the processing unit executes driver commands for reading information stored in the area and requesting the first interrupt when the processing unit detects the request for the first interrupt. | 2009-08-27 |
20090216931 | Information processing apparatus, method for controlling the same, and recording medium including program - An information processing apparatus includes a card slot to which a card-type medium is inserted, a determination unit configured to determine an operation mode, from among a first, second and third operation modes, which attains the highest speed of data communication between the information processing apparatus and the card type medium on the basis of a first, second and third communication speeds and the interruption-preventing maximum data size, and a data communication unit configured to perform data communication between the information processing apparatus and the card-type medium in the operation mode which attains the highest speed of the data communication and which is selected from among the first to third operation modes by the determination unit. | 2009-08-27 |
20090216932 | DATA PROCESSING APPARATUS - A data processing apparatus includes: a system bus; a processor connected to the system bus in slave connection, the processor having a command register configured to retain a DMA request command corresponding to a resource on the system bus and be accessed through the system bus; and a DMA controller connected to the system bus in bus-mastering connection, the DMA controller being configured to read out the DMA request command retained in the command register and control DMA transfer between the resource on the system bus and the processor based on the DMA request command. | 2009-08-27 |
20090216933 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PIPELINE ARBITRATION - A method for pipeline arbitration including receiving a first request for a shared chip interface from a first pipeline, determining whether a response bus of the shared chip interface is needed by the first request, and if it is determined that the response bus is not needed by the first request, concluding that the first request needs just an address bus of the shared chip interface, arbitrating the first request with a second request for the shared chip interface received from a second pipeline for access to the address bus, sending the first request to the address bus if the first request wins the arbitration over the second request, and rejecting the first request if the second request wins the arbitration over the first request. A corresponding system and computer program product. | 2009-08-27 |
20090216934 | Common storage in scalable computer systems - A computer system comprises a plurality of processing modules, each operable to provide a service to an external entity. Each processing module has a processor and a memory. A storage module is provided, operable to store information required by the processing modules to provide the service. A switching module is also provided, operable to provide a switching service between the processing module and storage module and between the processing module and an external entity. | 2009-08-27 |
20090216935 | Memory device for a user profile - A memory device for a user profile of a plurality of electronic devices or functional units in a motor vehicle is used for providing data corresponding to the user profile in the vehicle without a user having to make corresponding settings. As a result of being stored in the memory device, the user profile can be used in different vehicles. | 2009-08-27 |
20090216936 | DATA READING METHOD FOR FLASH MEMORY AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data reading method suitable for a flash memory storage system having a flash memory is provided, wherein the flash memory is substantially divided into a plurality of blocks and these blocks are grouped into at least a data area and a spare area. The data reading method includes: respectively determining whether the blocks in the data area are frequently read blocks; allocating a buffer storage area corresponding to the frequently read block and copying data stored in the frequently read block to the buffer storage area; and reading the data from the buffer storage area corresponding to the frequently read block when the data stored in the frequently read block is to be read. As described above, data loss caused by read disturb can be effectively prevented. | 2009-08-27 |
20090216937 | MEMORY CONTROLLER, MEMORY SYSTEM, AND ACCESS CONTROL METHOD OF FLASH MEMORY - A memory controller adds dummy data to write data by referring to instruction information about a descriptor transfer of the write data if a size of the write data to be written according to a data-write request information does not match a page size unit, thereby adjusting the size of the write data to the page size unit and then outputs the write data. | 2009-08-27 |
20090216938 | Management Of Non-Volatile Memory Systems Having Large Erase Blocks - A non-volatile memory system of a type having blocks of memory cells erased together and which are programmable from an erased state in units of a large number of pages per block. If the data of only a few pages of a block are to be updated, the updated pages are written into another block provided for this purpose. The valid original and updated data are then combined at a later time, when doing so does not impact on the performance of the memory. If the data of a large number of pages of a block are to be updated, however, the updated pages are written into an unused erased block and the unchanged pages are also written to the same unused block. By handling the updating of a few pages differently, memory performance is improved when small updates are being made. | 2009-08-27 |
20090216939 | Emulation of abstracted DIMMs using abstracted DRAMs - One embodiment of the present invention sets forth an abstracted memory subsystem comprising abstracted memories, which each may be configured to present memory-related characteristics onto a memory system interface. The characteristics can be presented on the memory system interface via logic signals or protocol exchanges, and the characteristics may include any one or more of, an address space, a protocol, a memory type, a power management rule, a number of pipeline stages, a number of banks, a mapping to physical banks, a number of ranks, a timing characteristic, an address decoding option, a bus turnaround time parameter, an additional signal assertion, a sub-rank, a number of planes, or other memory-related characteristics. Some embodiments include an intelligent register device and/or, an intelligent buffer device. One advantage of the disclosed subsystem is that memory performance may be optimized regardless of the specific protocols used by the underlying memory hardware devices. | 2009-08-27 |
20090216940 | Method for accessing a first-in-first-out (FIFO) buffer and a FIFO controller therefor - A method of for accessing a first-in-first-out (FIFO) buffer is provided. The method comprises the following two steps. Firstly, issue a request to access a memory when the amount of the data buffered in the FIFO buffer is more than a threshold. Second, pop the data buffered in the FIFO buffer out to access the memory when the request is granted. If the FIFO buffer is a single-port FIFO buffer, the threshold is set based on the burst length of one burst of data. If the FIFO buffer is a dual-port FIFO buffer, the threshold is set based on the speed at which the data is pushed into the FIFO buffer and the speed at which the data is popped out of the FIFO buffer. | 2009-08-27 |
20090216941 | Method for saving computer data - The invention relates to a method for saving computer data which consist in transferring the data to be saved from a client computer to a buffer storage formed by the hard disc of a backup server, organised in a plurality of volumes of predetermined size, and in then transferring the data from said buffer storage onto a final medium (for example magnetic cartridge). The invention is characterised in that it consists in recording on said permanent medium, after transferring the volumes from the buffer storage onto the final medium, a single sequence of data specific to each of said volumes (basic data), the method further comprising a step which consists in constituting a database wherein are recorded the basic data. | 2009-08-27 |
20090216942 | EFFICIENT MEMORY MANAGEMENT FOR HARD DISK DRIVE (HDD) READ CHANNEL - Efficient memory management for hard disk drive (HDD) read channel. The memory management presented herein can be broadly applied to any interface in which data is provided from a first location to a second location. A number of buffer units are employed, arranged into a number of slices, in which data is selectively written so that the information can be provided to the memory management architecture at a first rate, stored in the memory management architecture, and then output from the memory management architecture at a second rate. This ensures appropriate interfacing of information while also performing appropriate rate adjustment. The data is partitioned into a number of portions, and each portion also includes multiple subsets. On a subset basis, information of a first portion is provided to a first slice's buffer units, and information of a second portion is provided to a second slice's buffer units. | 2009-08-27 |
20090216943 | Data storage device and data management method in data storage device - Embodiments of the present invention improve efficiency in saving log data in a hard disk drive (HDD) equipped with a magnetic disk and a flash memory,. In an aspect of one embodiment of the present invention, a HDD creates a segment table to associate an address of user data in a flash memory with an LBA in a magnetic disk. The HDD updates the segment table in a DRAM and saves it to the flash memory at a specific timing. The HDD creates journals indicating the update of the segment table and saves it to the flash memory. The latest segment table can be restored using the segment table and the journals in the flash memory. | 2009-08-27 |
20090216944 | EFFICIENT VALIDATION OF WRITES FOR PROTECTION AGAINST DROPPED WRITES - A write cache provides for staging of data units written from a processor for recording in a disk. The order in which destages and validations occur is controlled to make validations more efficient. The data units are arranged in a circular queue according to their respective disk storage addresses. Each data unit is tagged with a state value of 1, 0, or −1. A destaging pointer is advanced one-by-one to each data unit like the hand of a clock. Each data unit pointed to is evaluated as a destage victim. The first step is to check its state value. A data unit newly brought into the write cache will have its state value reset to 0. It will stay that way until it receives an overwrite x command or the destage pointer clocks around to x. If an overwrite x, the state value is set to 1, in a way, indicating recent use of the data unit and postponing its destaging and eviction. If the destage pointer clocks around to x when the state was 0, then it's time to destage x and the state value is changed to −1. A write to the disk occurs and a later read will be used to verify the write. If the state value was already 1 when the destage pointer clocks around to x, the state value is reset to 0. If the destage pointer clocks around to x when the state is −1, the associated data is read from the disk and validated to be same as the copy in cache. If not, the destage of x is repeated, and the state value remains as −1. Otherwise, if the associated read for validation did return a success, then data unit x is evicted from the write cache. | 2009-08-27 |
20090216945 | STORAGE SYSTEM WHICH UTILIZES TWO KINDS OF MEMORY DEVICES AS ITS CACHE MEMORY AND METHOD OF CONTROLLING THE STORAGE SYSTEM - Provide is a storage system including one or more disk drives, and one or more cache memories for temporarily storing data read from the disk drives or data to be written to the disk drives, in which: the cache memories includes volatile first memories and non-volatile second memories; and the storage system receives a data write request, stores the requested data in the volatile first memories, selects one of memory areas of the volatile first memories if a total capacity of free memory areas contained in the volatile first memories is less than a predetermined threshold, write data stored in the selected memory area in the non-volatile second memories, and changes the selected memory area to a free memory area. Accordingly, there can be realized capacity enlarging of the cache memory using a non-volatile memory device while realizing a high speed similar to that of a volatile memory device. | 2009-08-27 |
20090216946 | RAID1 SYSTEM AND READING METHOD FOR ENHANCING READ PERFORMANCE - Concerning the operations of a redundant array of independent disks 1 system, a reading process is carried out by skipping the even-address storage units in a first storage device, sequentially fetching the data of the odd-address storage units in the first storage device for forming a first data stream, skipping the odd-address storage units in a second storage device, sequentially fetching the data of the even-address storage units in the second storage device for forming a second data stream, and merging the first data stream and the second data stream for generating a readout data stream. | 2009-08-27 |
20090216947 | SYSTEM, METHOD AND PROCESSOR FOR ACCESSING DATA AFTER A TRANSLATION LOOKASIDE BUFFER MISS - Data is accessed in a multi-level hierarchical memory system. A request for data is received, including a virtual address for accessing the data. A translation buffer is queried to obtain an absolute address corresponding to the virtual address. Responsive to the translation buffer not containing an absolute address corresponding to the virtual address, the absolute address is obtained from a translation unit. A directory look-up is performed with the absolute address to determine whether a matching absolute address exists in the directory. A fetch request for the requested data is sent to a next level in the multi-level hierarchical memory system. Processing of the fetch request by the next level occurs in parallel with the directory lookup. The requested data is received in the primary cache to make the requested data available to be written to the primary cache. | 2009-08-27 |
20090216948 | METHOD FOR SUBSTANTIALLY UNINTERRUPTED CACHE READOUT - A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring operations. The memory device outputs cached data from a first page while data from a second page is fetched into sense amplifier circuitry. When the outputting of the first page reaches a predetermined transfer point, a portion of the fetched data from the second page is transferred into the cache at the same time the remainder of the cached first page is being output. The remainder of the second page is transferred into the cache after all of the data from the first page is output while the outputting of the first portion of the second page begins with little or no interruption. | 2009-08-27 |
20090216949 | METHOD AND SYSTEM FOR A MULTI-LEVEL VIRTUAL/REAL CACHE SYSTEM WITH SYNONYM RESOLUTION - Method and system for a multi-level virtual/real cache system with synonym resolution. An exemplary embodiment includes a multi-level cache hierarchy, including a set of L1 caches associated with one or more processor cores and a set of L2 caches, wherein the set of L1 caches are a subset of the set of L2 caches, wherein the set of L1 caches underneath a given L2 cache are associated with one or more of the processor cores. | 2009-08-27 |
20090216950 | Push for Sharing Instruction - In one embodiment, a system comprises a first processor, a main memory system, and a cache hierarchy coupled between the first processor and the main memory system. The cache hierarchy comprises at least a first cache. The first processor is configured to execute a first instruction, including forming an address responsive to one or more operands of the first instruction. The system is configured to push a first cache block that is hit by the first address in the first cache to a target location within the cache hierarchy or the main memory system, wherein the target location is unspecified in a definition of the first instruction within an instruction set architecture implemented by the first processor, and wherein the target location is implementation-dependent. | 2009-08-27 |
20090216951 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR HANDLING SHARED CACHE LINES IN A MULTI-PROCESSOR ENVIRONMENT - A system, method, and computer program product for handling shared cache lines to allow forward progress among processors in a multi-processor environment is provided. A counter and a threshold are provided a processor of the multi-processor environment, such that the counter is incremented for every exclusive cross interrogate (XI) reject that is followed by an instruction completion, and reset on an exclusive XI acknowledgement. If the XI reject counter reaches a preset threshold value, the processor's pipeline is drained by blocking instruction issue and prefetching attempts, creating a window for an exclusive XI from another processor to be honored, after which normal instruction processing is resumed. Configuring the preset threshold value as a programmable value allows for fine-tuning of system performance. | 2009-08-27 |
20090216952 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MANAGING CACHE MEMORY - A method for managing cache memory including receiving an instruction fetch for an instruction stream in a cache memory, wherein the instruction fetch includes an instruction fetch reference tag for the instruction stream and the instruction stream is at least partially included within a cache line, comparing the instruction fetch reference tag to a previous instruction fetch reference tag, maintaining a cache replacement status of the cache line if the instruction fetch reference tag is the same as the previous instruction fetch reference tag, and upgrading the cache replacement status of the cache line if the instruction fetch reference tag is different from the previous instruction fetch reference tag, whereby the cache replacement status of the cache line is upgraded if the instruction stream is independently fetched more than once. A corresponding system and computer program product. | 2009-08-27 |
20090216953 | METHODS AND SYSTEMS FOR DYNAMIC CACHE PARTITIONING FOR DISTRIBUTED APPLICATIONS OPERATING ON MULTIPROCESSOR ARCHITECTURES - Software, systems and methods are described which provide cache management capabilities. The number of cache sets to be used in each partition of the cache memory space is based on a number of cache pages in each partition and an associativity level associated with the set associative cache. The cache sets can be numbered based on the partition number, a total number of partitions and a cache page index. Cache management according to these exemplary embodiments reduces problems associated with cache trashing in multiprocessor environments sharing common data structures in set associative caches. | 2009-08-27 |
20090216954 | APPARATUS, SYSTEM, AND METHOD FOR SELECTING A SPACE EFFICIENT REPOSITORY - An apparatus, system, and method are disclosed for selecting a space efficient repository. A cache receives write data. A destage module destages the data sequentially to a coarse grained repository such as a stride level repository and destages a directory entry for the data to a coarse grained directory such as a stride level directory if the data satisfies a repository policy. In addition, the destage module destages the data to a fine grained repository such as a track level repository overwriting an existing data instance and destages the directory entry to a fine grained directory such as a track level directory if the data does not satisfy the repository policy. | 2009-08-27 |
20090216955 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR LRU COMPARTMENT CAPTURE - A two pipe pass method for least recently used (LRU) compartment capture in a multiprocessor system. The method includes receiving a fetch request via a requesting processor and accessing a cache directory based on the received fetch request, performing a first pipe pass by determining whether a fetch hit or a fetch miss has occurred in the cache directory, and determining an LRU compartment associated with a specified congruence class of the cache directory based on the fetch request received, when it is determined that a fetch miss has occurred, and performing a second pipe pass by using the LRU compartment determined and the specified congruence class to access the cache directory and to select an LRU address to be cast out of the cache directory. | 2009-08-27 |
20090216956 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR ENHANCING TIMELINESS OF CACHE PREFETCHING - A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses. The system also includes a confidence counter. The system further includes eager prefetching control logic for performing a method when the stride size is less than a cache line size. The method includes adjusting the confidence counter in response to the stride pattern detector detecting the stride pattern, comparing the confidence counter to a confidence threshold, and requesting a cache prefetch in response to the confidence counter reaching the confidence threshold. The system may also include selection logic to select between the eager prefetching control logic and standard stride prefetching control logic. | 2009-08-27 |
20090216957 | Managing the storage of data in coherent data stores - A data processing apparatus is disclosed that comprises: at least one processor; at least one data store for storing data processed by said at least one processor; a shared data store for storing data processed by said at least one processor and at least one further device; and coherency control circuitry responsive to a write request from said at least one further device to determine if data related to an address targeted by said write request is stored in said at least one data store, and if it is forcing an eviction of said stored data from said at least one data store to said shared data store prior to performing said write to said shared data store; wherein said data is stored in said at least one data store in conjunction with an indicator indicating if said stored data is consistent with data stored in a corresponding address in a further data store, and said stored data is evicted whether said stored data is indicated as being consistent or inconsistent. | 2009-08-27 |
20090216958 | Hardware accelerator interface - A data processing system in the form of an integrated circuit | 2009-08-27 |
20090216959 | Multi Port Memory Controller Queuing - The present invention is generally directed to a method, system, and program product wherein at least one command in a first queue is transferred to a second queue. When the first queue can no longer accept command(s) and a second queue is able to accept command(s), the second queue accepts the command(s) that the first queue can not. When the first queue is able to accept command(s), and there are command(s) in the second memory port that should have been in the first queue, the command(s) in the second queue are transferred to the first queue. | 2009-08-27 |
20090216960 | Multi Port Memory Controller Queuing - The present invention is generally directed to a method, system, and program product wherein at least two memory ports associated within a memory controller are capable of transferring commands between one another in unbalanced memory configurations. When the first memory port can no longer accept commands and a second memory port is able to accept commands, the second memory port accepts the commands that the first memory port can not. When the first memory port is able to accept commands, and there are commands in the second memory port that should have been in the first memory port, the commands in the second memory port are transferred to the first memory port. | 2009-08-27 |
20090216961 | MULTI-PORT SEMICONDUCTOR MEMORY DEVICE FOR REDUCING DATA TRANSFER EVENT AND ACCESS METHOD THEREFOR - A multiport semiconductor memory device includes at least three port units coupled respectively to corresponding processors, a shared memory area accessed in common by the processors through the port units, and a data path control unit for controlling a data path between the shared memory area and the port units to perform a data communication between the processors through the shared memory area. | 2009-08-27 |
20090216962 | PRIORITIZATION OF MULTIPLE CONCURRENT THREADS FOR SCHEDULING REQUESTS TO SHARED MEMORY - A “request scheduler” provides techniques for batching and scheduling buffered thread requests for access to shared memory in a general-purpose computer system. Thread-fairness is provided while preventing short- and long-term thread starvation by using “request batching.” Batching periodically groups outstanding requests from a memory request buffer into larger units termed “batches” that have higher priority than all other buffered requests. Each “batch” may include some maximum number of requests for each bank of the shared memory and for some or all concurrent threads. Further, average thread stall times are reduced by using computed thread rankings in scheduling request servicing from the shared memory. In various embodiments, requests from higher ranked threads are prioritized over requests from lower ranked threads. In various embodiments, a parallelism-aware memory access scheduling policy improves intra-thread bank-level parallelism. Further, rank-based request scheduling may be performed with or without batching. | 2009-08-27 |
20090216963 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING A SHARED MEMORY TRANSLATION FACILITY - A system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined if the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations. In response to determining that the memory address refers to the SMO, it is determined if the configuration has access to the SMO. In response to determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the plurality of configurations is allowed. | 2009-08-27 |
20090216964 | VIRTUAL MEMORY INTERFACE - The embodiments that are described herein provide random access to individual data storage locations of a group of buffers, which may be scattered in the memory. These embodiments provide a virtual memory interface that applies virtual addresses in a flat memory linear addressing space as indices into the physical memory addresses that are ordered into a sequence in accordance with the group of buffers. In this way, these embodiments enable a device (e.g., a processor) to directly and sequentially access all of the scattered physical memory locations of a fragmented data item, such as a packet, without having to perform any memory segmentation or paging processes. In some embodiments, these accesses include both read and write accesses to the scattered data storage locations. | 2009-08-27 |
20090216965 | Storage device and access instruction sending method - A storage device for storing data sent from a host apparatus comprises a plurality of processors sending to a cache memory controller an access instruction relating to transmission of the data, based on an access request relating to the transmission of the data, the access request being sent from the host apparatus; and an access instruction sending unit exclusively sending to the cache memory the access instruction sent from the plurality of processors, wherein the access instruction sending unit includes a plurality of storage units for storing an access instruction which requires a response, and wherein when the access instruction which requires a response is stored in all of the storage units, the access instruction sending unit sends only an access instruction which requires a response to the cache memory controller. | 2009-08-27 |
20090216966 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR STORING EXTERNAL DEVICE RESULT DATA - A method, system, and computer program product for storing result data from an external device. The method includes receiving the result data from the external device, the receiving at a system. The result data is stored into a store data buffer. The store data buffer is utilized by the system to contain store data normally generated by the system. A special store instruction is executed to store the result data into a memory on the system. The special store instruction includes a store address. The executing includes performing an address calculation of the store address based on provided instruction information, and updating a memory location at the store address with contents of the store data buffer utilizing a data path utilized by the system to store data normally generated by the system. | 2009-08-27 |
20090216967 | COMPUTER, RECORDING MEDIUM RECORDING DUMP PROGRAM, AND DUMP METHOD - A computer dumps information stored in a storage space used by a program, into a file when the program ends abnormally, by determining a priority representative of an order in which the information is dumped into the file, for storage areas which are predetermined areas into which the storage space is divided; compressing the information stored in each storage area in decreasing the order of priority and outputting the compressed information to the file in an order in which the information is compressed. | 2009-08-27 |
20090216968 | Method and apparatus for storing sequential sample data as memories for the purpose of rapid memory recognition using mathematic invariants - The invention described herein provides a method and apparatus for storing information in a memory structure and determining mathematical invariants in the memory structure. These invariants are then used to predict nested data patterns given only a few data elements or given incomplete data elements. The method uses a Memory Recognition Engine (MRE) that memorizes everything it processes. The MRE method can be applied to any problem where data sequences are involved that generate patterns only or nested patterns. | 2009-08-27 |
20090216969 | Remote data mirroring system - A method for data protection includes accepting data for storage from one or more data sources ( | 2009-08-27 |
20090216970 | APPARATUS, SYSTEM, AND METHOD FOR VIRTUAL MACHINE BACKUP - An apparatus, system, and method are disclosed for a virtual machine backup. A name module establishes an administrative machine name for a virtual machine. A space module associates at least one administrative name space with the administrative machine name. A backup module backs up files belonging to the virtual machine using a backup proxy, wherein the files are segregated under the administrative machine name and are accessible using only a secure key belonging to the virtual machine and without using a backup proxy secure key. A mask module masks out pathname components for each backup file pathname so that the backup file pathname is equivalent to a virtual machine file pathname. | 2009-08-27 |
20090216971 | Storage System and Copy Method - In a storage system, one or more storage apparatuses provide a management computer with a first volume for storing data from the management computer, provide a host computer with a second volume for storing data from the host computer, and manage a volume address for the one or more storage apparatuses to manage the first volume and the second volume in the one or more storage apparatuses. The management computer issues a command specifying an arbitrary volume address to the one or more storage apparatuses, and designates, when receiving a normal response from the arbitrary volume address, a volume with the arbitrary volume address as the second volume. | 2009-08-27 |
20090216972 | STORAGE SYSTEM, COPY METHOD, AND PRIMARY STORAGE APPARATUS - A storage system having a primary storage apparatus for storing data from a host computer in a primary logical volume, and a secondary storage apparatus connected to the primary storage apparatus, for providing a secondary logical volume for storing a copy of the data, the storage system comprising: a search unit for checking whether or not data exists in each primary slot area formed by partitioning a storage area in the primary logical volume into predetermined storage areas; a transmission unit for sending, if no data is held in the primary slot area, a notice indicating no data stored to the secondary storage apparatus; and a data write unit for writing, when the notice is received from the primary storage apparatus, zero data in the secondary slot area. | 2009-08-27 |
20090216973 | COMPUTER SYSTEM, STORAGE SUBSYSTEM, AND DATA MANAGEMENT METHOD - To prevent, when data is erased from a storage system that stores differential of updated data, a large amount of differential data from being created, a storage subsystem provides a first storage area which stores data, and includes a second storage area which stores a replication of data stored in the first storage area. When the data stored in the first storage area is updated, the data is replicated to the second storage area before the data is updated. When a request to erase the data stored in the first storage area is received, replication of unupdated data to the second storage area is suspended and the data stored in the first storage area is erased based on the request to erase the data. | 2009-08-27 |
20090216974 | MICROCOMPUTER - A microcomputer includes a first CPU, a first bus, a first memory, a second CPU, a second bus, and a second memory. The first memory and the second memory are arranged in address spaces individually managed by the first CPU and the second CPU corresponding to the memories. An address translation circuit is provided. When a task so programmed to have a data area in the first memory is transferred to the second memory and executed by the second CPU, the address translation circuit carries out the following processing: the address translation circuit translates an address outputted from the second CPU so that access to the first memory by the task becomes access to the second memory. As a result, the number of access cycles is reduced and degradation in computing capability is avoided when a task is transferred between CPUs for load sharing. | 2009-08-27 |
20090216975 | EXTENDING SERVER-BASED DESKTOP VIRTUAL MACHINE ARCHITECTURE TO CLIENT MACHINES - A server-based desktop-virtual machines architecture may be extended to a client machine. In one embodiment, a user desktop is remotely accessed from a client system. The remote desktop is generated by a first virtual machine running on a server system, which may comprise one or more server computers. During execution of the first virtual machine, writes to a corresponding virtual disk are directed to a delta disk file or redo log. A copy of the virtual disk is created on the client system. When a user decides to “check out” his or her desktop, the first virtual machine is terminated (if it is running) and a copy of the delta disk is created on the client system. Once the delta disk is present on the client system, a second virtual machine can be started on the client system using the virtual disk and delta disk to provide local access to the user's desktop at the client system. This allows the user to then access his or her desktop without being connected to a network. | 2009-08-27 |
20090216976 | COMPUTER SYSTEM ALLOWING ANY COMPUTER TO COPY ANY STORAGE AREA WITHIN A STORAGE SYSTEM - A computer system having a plurality of host computers and a storage system is provided which allows any one host computer to perform a global copy operation on any arbitrary or all storage areas in the storage system. To this end, storage areas provided by the disk devices are grouped into groups by allocating group numbers to a plurality of specified storage areas. The copy operation can be performed by specifying desired groups. Each of the groups is made up of sub-groups and the sub-groups are defined for each computer to assure a consistency of copy order of the sub-groups. | 2009-08-27 |
20090216977 | Storage System and Snapshot Data Preparation Method in Storage System - The present invention is devised so that snapshot data preparation processing does not end abnormally as a result of the pool region becoming full with saved data from the primary logical volume during snapshot data preparation. When the CHA receives a snapshot data preparation request, the CHA checks whether or not update information is present in the logical volume that is the object of this data preparation. If such information is present (YES in S | 2009-08-27 |
20090216978 | METHOD AND APPARATUS FOR INCREASING AN AMOUNT OF MEMORY ON DEMAND WHEN MONITORING REMOTE MIRRORING PERFORMANCE - A method and storage system for increasing an amount of memory in a queuing area on. The storage system includes first and second storage subsystems connected to each other via a path. A primary volume in the first storage subsystem and a remote secondary volume in the second storage subsystem are mirrored and operated in the asynchronous mode. A queuing area having memory is provided in the second storage subsystem for temporarily storing data transferred to the second storage subsystem from the first storage subsystem in response to a write input/output (I/O) issued by a host to write data in the primary volume. Data temporarily stored in the memory is retrieved and stored in the remote secondary volume. An unused area of the queuing area is monitored and the memory increased if the unused area becomes less than a predetermined amount. | 2009-08-27 |
20090216979 | Method and system for secured drive level access for storage arrays - The present disclosure provides a methodology by which disk level access for storage drives of a storage array may be highly secured based on permission settings applied to the driver interface of the storage drives. Based on specific set of access rules, a security component applies security profiles to permit/deny access to an individual storage drive, sets the storage drive with a first security level, monitors for a triggering event, and sets the storage drive to a second (more restrictive) security access level in response to the triggering event. In addition, the security component generates an alert in response to the triggering event. Thus, disk level access permissions are applied at a driver interface layer and permissions are applied based on administrator-defined policies. The present disclosure provides for complete lock-down of data permissions, management and/or restriction of IO loads, and protection of “read-only” data integrity from overwrites. | 2009-08-27 |
20090216980 | INFORMATION STORAGE SYSTEM - A storage media and a storage area of a storage apparatus are associated, and the storage media is used to manage the contents of the storage apparatus. A storage media for storing files is detachably mounted on an information processing apparatus, the information processing apparatus is connected to a storage apparatus via the Internet, the storage apparatus stores files corresponding to the files stored in the storage media, the storage media and the storage apparatus authenticate each other via the Internet, and the information processing apparatus reads files from or writes files into the storage media or the storage apparatus on the condition that the foregoing authentication is successful. | 2009-08-27 |
20090216981 | POWER EFFICIENT FLOW CONTROL MODEL FOR USB ASYNCHRONOUS TRANSFERS - Embodiments comprising a memory and a USB host controller coupled to the memory. The power efficiency of a USB during asynchronous transfers is increased by limiting usage of an asynchronous schedule stored in the memory when servicing a scheduled asynchronous transfer endpoint. Other embodiments may be described and claimed. | 2009-08-27 |
20090216982 | SELF-LOCKING MASS STORAGE SYSTEM AND METHOD OF OPERATION THEREOF - A method of operation of a self-locking mass storage system includes: providing storage media and an inactivity timer; timing a period of read/write inactivity of the storage media using the inactivity timer; comparing the period of read/write inactivity against a preset maximum idle time; locking access to the storage media when the period of read/write inactivity exceeds the preset maximum idle time; and, resetting the period of read/write inactivity following read/write activity while the self-locking mass-storage system is in an unlocked state. | 2009-08-27 |
20090216983 | METHOD AND SYSTEM FOR ACCESSING MEMORY USING AN AUXILIARY MEMORY - A method and system for accessing memory using an auxiliary memory is presented. According to the invention store and following load instructions accessing same memory locations are identified and a temporal difference is determined. The store instructions comprise an indication for the time interval lapsing until a data element, which is stored by the store instructions, is loaded by a load operation for the first time. Based on this indication the store instruction is given access directly to the main memory or is routed to main memory through an auxiliary memory. | 2009-08-27 |
20090216984 | OPTIMIZATIONS OF A PERFORM FRAME MANAGEMENT FUNCTION ISSUED BY PAGEABLE GUESTS - Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests. | 2009-08-27 |
20090216985 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR DYNAMIC SELECTIVE MEMORY MIRRORING - Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections of the memory are mirrored in the reserved memory. | 2009-08-27 |
20090216986 | APPARATUS AND METHOD FOR MANAGING LOGICAL VOLUME IN DISTRIBUTED STORAGE SYSTEMS - A logical volume management apparatus includes a first storage unit that stores configuration information on a first stage logical volume, and a second storage unit that stores configuration information on a second stage logical volume. An access unit finds a storage area in the second stage logical volume that corresponds to the first stage logical volume, and accesses a storage area in a storage device that corresponds to the determined storage area. A logical volume generation unit generates a new second stage logical volume, and a storage area extension unit extends a storage area of the first stage logical volume stored in the configuration information on the first stage logical volume to a desired storage capacity, and makes the new second stage logical volume generated by the logical volume generation unit correspond to the first stage logical volume. | 2009-08-27 |
20090216987 | METHOD AND APPARATUS FOR ALLOCATING HOST MEMORY FOR A MEMORY-LESS ADD-ON DEVICES - Methods and apparatus for allocating host memory for use by a host channel adapter (HCA) with insufficient on-board memory are disclosed. In one embodiment, a method includes determining when a host memory arrangement which has a host memory updates a system address map associated with the host memory, and obtaining control from a system basic-input-output-system (BIOS) associated with an operating system (OS) of the host memory arrangement when the system address map is updated. The method also includes allocating a first memory block in the host memory using an add-on device after obtaining control from the host memory arrangement. The system address map is updated by the add-on device to indicate that the first memory block has been allocated to the add-on device. Finally, the method includes returning the control to the system BIOS after updating the system address map. | 2009-08-27 |
20090216988 | LOW OVERHEAD MEMORY MANAGEMENT SYSTEM AND METHOD - A block of contiguous data storage locations of a memory is divided into pools of memory chunks. The memory chunks in same ones of the pools have equal chunk sizes. The memory chunks in different ones of the pools have different chunk sizes. In each of the pools, the memory chunks are addressable by respective chunk base physical addresses in a respective linear contiguous sequence that starts from a respective pool base physical address. The physical addresses of the memory chunks are translated into corresponding internal handles and vice versa, where each of the internal handles is smaller in size than its corresponding physical address. For each of the pools, an associated pool queue comprising respective ones of the internal handles to allocatable ones of the memory chunks in the pool is maintained. | 2009-08-27 |
20090216989 | Storage apparatus and storage area allocation method - A storage apparatus is provided with a storage area for storing data sent from a host computer, and a virtual/logical volume to which a dynamically variable storage area is allocated from within the storage area, the volume being provided to the host computer, and this storage apparatus is configured to include: a pool area generation unit for generating a plurality of pool areas composed from the storage area; a setting unit for setting, for each of the plurality of pool areas generated by the pool area generation unit, an allocation unit size for allocating a storage area from within the storage area provided by the pool area to the virtual/logical volume; a selecting unit for selecting, when data to be stored in the storage area is sent from the host computer, a pool area from among the plurality of pool areas having the allocation unit size set by the setting unit, in accordance with the size of the sent data; and an allocation unit for allocating a storage area from within the storage area provided by the pool area selected by the selecting unit to the virtual/logical volume. | 2009-08-27 |
20090216990 | DYNAMIC TRANSACTIONAL INSTANTIATION OF SYSTEM CONFIGURATION USING A VIRTUAL FILE SYSTEM LAYER - A virtual configuration system, comprising a virtualization engine and a configuration engine, for the dynamic instantiation of configuration files is disclosed. A mechanism is disclosed that allows for transactional updates to a repository of configuration settings comprising multiple files. Configuration entries are stored in a first memory location and a copy of the entries is stored in a second memory location. A virtual configuration file that includes a virtual configuration for each entry is created and used to provide the operating system with path and location information regarding the configuration entries. Simultaneously and during run-time of the computer, the configuration entries stored in the second memory location can be modified. Once the modifications are complete, a second virtual configuration file is created referencing the configuration entries stored at the second memory location. The first virtual configuration file is thereafter atomically replaced by the second virtual configuration file. | 2009-08-27 |
20090216991 | METHOD AND APPARATUS TO COMBINE SCATTERED BUFFER ADDRESSES INTO A CONTIGUOUS VIRTUAL ADDRESS SPACE - A method of combining scattered buffer addresses into a contiguous virtual address space comprises; receiving a plurality of read completion data portions corresponding to a single read request, storing the plurality of read completion data portions in a memory device such that an individual read completion data portion is stored in an individual address of the memory device, storing a valid indicator for a memory device address which contains the individual read completion data portion in an external storage location, storing a tag indicator associated with the read request for the individual read completion portion in an external storage location associated with the memory device address containing the individual read completion data portion, storing a sequence number associated with an individual read completion data portion in an external storage location associated with the memory device address containing the individual read completion data portion; and outputting an individual read completion data portion from the memory device to an external device. | 2009-08-27 |
20090216992 | DYNAMIC ADDRESS TRANSLATION WITH TRANSLATION EXCEPTION QUALIFIER - What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame. | 2009-08-27 |
20090216993 | System and Method of Data Forwarding Within An Execution Unit - In an embodiment, a method is disclosed that includes, comparing, during a write back stage at an execution unit, a write identifier associated with a result to be written to a register file from execution of a first instruction to a read identifier associated with a second instruction at an execution pipeline within an interleaved multi-threaded (IMT) processor having multiple execution units. When the write identifier matches the read identifier, the method further includes storing the result at a local memory of the execution unit for use by the execution unit in the subsequent read stage. | 2009-08-27 |
20090216994 | PROCESSOR, METHOD AND COMPUTER PROGRAM PRODUCT FOR FAST SELECTIVE INVALIDATION OF TRANSLATION LOOKASIDE BUFFER - A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each comparator associated with a respective output of each TLB set output for each TLB port, wherein each of the comparators is adapted for identifying mappings for invalidation; and logic for invalidating each identified mapping. A method and a computer program product are provided. | 2009-08-27 |
20090216995 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING QUIESCE FILTERING FOR SHARED MEMORY - A system, method and computer program product for providing quiesce filtering for shared memory. The method includes receiving a shared-memory quiesce request at a processor. The request includes a donor zone. The processor includes translation look aside buffer one (TLB | 2009-08-27 |
20090216996 | Parallel Processing - A system and methods comprising a plurality of leaf nodes in communication with one or more branch nodes, each node comprising a processor. Each leaf node is arranged to obtain data indicative of a restriction A| | 2009-08-27 |
20090216997 | DYNAMICALLY MANAGING THE COMMUNICATION-PARALLELISM TRADE-OFF IN CLUSTERED PROCESSORS - In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached. | 2009-08-27 |
20090216998 | Apparatus for and Method of Processor to Processor Communication for Coprocessor Functionality Activation - A novel and useful mechanism enabling a processor in a multiprocessor complex to function as a coprocessor to execute a specific function. The method includes a mechanism for activating a coprocessor to function as a coprocessor as well as a mechanism to execute a coprocessor request on the system. The present invention also provides a mechanism for efficient processor to processor communication for processors coupled to a common bus. Overall system performance is enhanced by significantly reducing the use of hardware interrupts for processor to processor communication. | 2009-08-27 |
20090216999 | Automated Execution Of Virtual Appliances - Methods and apparatus, including computer program products, are provided for selecting a processor, such as a hardware provider, for executing a virtual appliance. In one aspect, there is provided a computer-implemented method. The method may include receiving information representative of whether one or more processors are capable of executing at least one of a plurality of virtual appliances. The received information may further including one or more costs to execute the at least one virtual appliance at one of the processors. One of the processors may be selected based on the received information. The selection enables the processor to execute the at least one virtual appliance. Related apparatus, systems, methods, and articles are also described. | 2009-08-27 |
20090217000 | CLOCK SIGNALS IN DIGITAL SYSTEMS - A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip. | 2009-08-27 |
20090217001 | System and Method for Handling Load and/or Store Operations in a Superscalar Microprocessor - The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data. | 2009-08-27 |
20090217002 | SYSTEM AND METHOD FOR PROVIDING ASYNCHRONOUS DYNAMIC MILLICODE ENTRY PREDICTION - A system and method for asynchronous dynamic millicode entry prediction in a processor are provided. The system includes a branch target buffer (BTB) to hold branch information. The branch information includes: a branch type indicating that the branch represents a millicode entry (mcentry) instruction targeting a millicode subroutine, and an instruction length code (ILC) associated with the mcentry instruction. The system also includes search logic to perform a method. The method includes locating a branch address in the BTB for the mcentry instruction targeting the millicode subroutine, and determining a return address to return from the millicode subroutine as a function of the an instruction address of the mcentry instruction and the ILC. The system further includes instruction fetch controls to fetch instructions of the millicode subroutine asynchronous to the search logic. The search logic may also operate asynchronous with respect to an instruction decode unit. | 2009-08-27 |
20090217003 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR REDUCING CACHE MEMORY POLLUTION - A method for reducing cache memory pollution including fetching an instruction stream from a cache line, preventing a fetching for the instruction stream from a sequential cache line, searching for a next predicted taken branch instruction, determining whether a length of the instruction stream extends beyond a length of the cache line based on the next predicted taken branch instruction, continuing preventing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream does not extend beyond the length of the cache line, and allowing the fetching for the instruction stream from the sequential cache line if the length of the instruction stream extends beyond the length of the cache line, whereby the fetching from the sequential cache line and a resulting polluting of a cache memory that stores the instruction stream is minimized. A corresponding system and computer program product. | 2009-08-27 |