35th week of 2015 patent applcation highlights part 66 |
Patent application number | Title | Published |
20150244299 | TRACKING CIRCUIT AND METHOD FOR TRACKING AN ORIENTATION OF A ROTOR OF A MOTOR DURING A LOSS OF SOURCE POWER TO A MOTOR DRIVE - A tracking circuit for tracking an orientation of a motor rotor during a loss of source power to a motor drive includes an electrical energy store for generating a drive signal during periods of source power loss, and a phase locked loop, which is arranged to receive as inputs the drive signal and an induced signal generated during rotor rotation during the periods of source power loss, so that drive signal variations become locked to induced signal variations. The method stores electrical energy in the store during periods of source power supply to the motor drive and generates a drive signal from the electrical energy store during periods of source power loss to the motor drive. The method may vary the drive signal in dependence of an induced signal generated by rotor rotation during a source power loss to the motor drive, to track rotor orientation. | 2015-08-27 |
20150244300 | MOTOR SPEED CONTROL SYSTEM AND METHOD THEREOF - A motor speed control system includes a motor, a control module and a displaying module. The motor includes a rotor and a stator. The rotor includes at least one induction rotor portion. The stator includes at least one induction stator portion. The induction rotor portion is corresponding to the induction stator portion. The control module is electrically connected to the rotor and the stator. The control module controls an induction rotor current of the induction rotor portion and an induction stator current of the induction stator port on to produce a rotor speed. The control module decreases or turns off the induction rotor current to keep the rotor speed at a predetermined value according to a rotational inertia of the rotor and the induction stator current when the rotor speed reaches the predetermined value. The displaying module displays the rotor speed and variable currents. | 2015-08-27 |
20150244301 | ELECTRIC VEHICLE AND CONTROL METHOD THEREFOR - A hybrid vehicle includes a battery, a boosting converter, first and second inverters, a first inverter connected to the first inverter, a second motor generator connected to the second inverter, and a control unit configured to start and suspend the boosting converter. The control unit increases one or both of carrier frequencies F | 2015-08-27 |
20150244302 | ELECTRIC POWER STEERING APPARATUS - An object of the present invention is to provide an electric power steering apparatus capable of stably performing drive of FETs of an inverter by means of a simplified constitution and control. | 2015-08-27 |
20150244303 | Method and System for Controlling Synchronous Machine As Generator/Starter - A synchronous brushless machine having a single exciter field stator winding. The single exciter field stator winding is energized by a high frequency alternating current to provide a single excitation field to magnetically couple with the exciter field armature winding in both the starter mode and the generator mode. With a higher excitation frequency relative to the main armature current frequency, a steady main field voltage can be achieved which improves stability control while in the starter mode. In one or more configurations, the single exciter field stator winding is driven by a H-bridge converter. | 2015-08-27 |
20150244304 | SOLAR PHOTOVOLTAIC FACILITY - A solar photovoltaic facility including: a construction having practically cylindrical shape and an utility space internally; a solar panel provided on cylindrical sidewall of the construction; a guide partially encompassing the construction and is practically concentric with the construction in plan view; a reflector movably guided by the guide and reflecting the sunlight towards the solar panel; a driving actuator which moves the reflector to a position in a direction opposite to the azimuth of the sun viewed from the construction; and an entrance installed on the sidewall of the construction within a range where the construction does not face the guide and accessible to the utility space. | 2015-08-27 |
20150244305 | BYOE_Bring Your OWN Enegi_Consumer Rechargeable Household Batteries_Pawabox-iPak - This model is somewhat similar to that of cooking gas; whereby consumers take empty cylinders to a nearby dealer to be refilled. That enables the consumer to be able to avoid the cost of maintaining huge stockpiles of gas themselves. It will also usher in the era of “distributed generation” of electricity; as opposed to the current model of “centralized generation”, whereby, electricity is generated hundreds, sometimes thousands of miles away and transmitted by high transmission wires to the end user, with several megawatts of electricity being “lost” in the process. Also, countries that have the centralized distribution model, are constantly faced with the spectre of “grid failure”, which “distributed generation” avoids. | 2015-08-27 |
20150244306 | Solar Power Generation, Distribution, and Communication System - A solar panel is disclosed that can be daisy-chained with other solar panels. The solar panel automatically generates output alternative current (AC) power that is in parallel with input AC power coming into the solar panel when the solar panel senses the input AC power so that the solar panel operates as a slave in this state. The solar panel automatically generates standalone AC output power when the solar panel fails to detect input AC power coming into the solar panel where the solar panel operates as a master in this state. The solar panel generates the standalone output AC power without any reliance on input AC power generated by a utility grid and/or other AC power sources external to the solar panel. | 2015-08-27 |
20150244307 | MODULAR STRUCTURAL SYSTEM FOR SOLAR PANEL INSTALLATION - A support structure (SS) and method for mounting SS and solar equipment on pitched roofs. Preassembled SS is installable/ removable, as a single module for reduced cost, installation time, and hazards. Optional housing for battery, electronics, and wireless equipment, is disposed in portion of preassembled SS that resides in protected interior of building. An elevated attach point on the SS optionally accepts cellular and high-frequency transceivers (for mesh network). SS penetrates roof, not on leak-prone roof face, but at roof apex using a main support coupleable to internal building structure. An interface member on the main support has a shape that is conformal to the roof apex to provide a weatherproof seal, load support, and a fulcrum to absorb equipment torque. Padded-standoffs support equipment weight on roof. Optionally, SS frame tubing acts as wire-conduit or SS frame is configured as power conductor for low-voltage, parallely-coupled, independently-troubleshootable, solar panels. | 2015-08-27 |
20150244308 | Lateral Movement Solar Panel Mounting System - Solar panel array with a plurality of solar panels on support system attached at corners or off such corners for foundation structure needs and irregularities secured to roof by lag bolt with mount channel and flashing pre-assembled into mount by crimp for positive seal and mount riser height adjustable can include bilateral or quadrilateral mounts, a coupler seat to affix panel to mount and lateral movement seat for solar panel, and different clamps including wedge clamps, top restraints, lip end clamps, side support clamps, compression clamps, etc. | 2015-08-27 |
20150244309 | SOLAR PANEL UNIT - A solar panel unit ( | 2015-08-27 |
20150244310 | Micro-Concentrator Solar Array Using Micro-Electromechanical Systems (MEMS) Based Reflectors - A method and apparatus for focusing light onto a plurality of solar cells. The apparatus comprises a plurality of solar cells, a plurality of groups of reflectors corresponding to the plurality of solar cells, and a control module in communication with the plurality of solar cells and the plurality of groups of reflectors. The control module includes control logic for monitoring an electrical output from the plurality of solar cells and repositioning the plurality of groups of reflectors when the electrical output is below a selected threshold. | 2015-08-27 |
20150244311 | Solar Generation Panel Washing Device - A solar generation panel washing device is provided with a pair of upper and lower fixed guide rails for providing along an upper end and a lower end respectively of a solar generation panel. Also provided is a moving frame for movement in a horizontal direction over the fixed guide rails, the moving frame being provided with a pair of left and right moving guide rails over which a cleaner element is for moving in a vertical direction. Washing an entire surface of the panel is possible through the movement in a vertical direction by the cleaner element and the movement in a horizontal direction by the moving frame. Rotary motion of one of the moving guide rails is transferred into reciprocating motion of the cleaner element in the vertical direction by a non-contact power transfer mechanism of magnetic members respectively provided to the moving guide rails and the cleaner element. | 2015-08-27 |
20150244312 | POWER CONVERTER, SOLAR ENERGY DEVICE AND SOLAR ENERGY POWER CONVERSION METHOD - A power converter includes a plurality of converters, a control device, and a signal adjustment device. The converters are connected to the photoelectric conversion cells respectively. The control device generates a base signal based on electrical power output from at least one type of photoelectric conversion cell out of plurality types of photoelectric conversion cells. The base signal is a signal that is a base for a plurality of control signals to control the converters individually so that electrical power output from the photoelectric conversion cells reaches a maximum power point of each of the photoelectric conversion cells. The signal adjustment device multiplies the base signal by a constant, and supplies a signal generated by the multiplication by the constant, as the control signal, to the converter which is a signal supply destination. | 2015-08-27 |
20150244313 | System and Method for Managing the Power Output of a Photovoltaic Cell - A solar cell management system for increasing the efficiency and power output of a solar cell and methods for making and using the same. The management system provides an electric field across an individual solar cell, an array of solar cells configured as a panel, or a group of solar panels. The imposed electric field exerts a force on both the electrons and holes created by light incident on the solar cell and accelerates the electron-hole pairs towards the electrodes of the solar cell. Compared to conventional solar cells, these accelerated electron-hole pairs travel a shorter distance from creation (by incident optical radiation) and spend less time within the solar cell material, therefore the electron-hole pairs have a lower likelihood of recombining within the cells' semiconductor's material. This reduction in the electron-hole recombination rate results in an overall increase in the solar cells' efficiency and greater power output. | 2015-08-27 |
20150244314 | PSEUDO SUNLIGHT IRRADIATION APPARATUS AND METHOD FOR EVALUATING SOLAR BATTERY MODULE - The present invention aims to provide a pseudo sunlight irradiation apparatus capable of artificially reproducing the daily path of the sun and reproducing the daily insolation. A pseudo sunlight irradiation apparatus ( | 2015-08-27 |
20150244315 | METHOD AND SYSTEM FOR APPLYING ELECTRIC FIELDS TO MULTIPLE SOLAR PANELS - A solar cell management system for increasing the efficiency and power output of a solar cell and methods for making and using the same. The management system provides an electric field across one or more solar cells. The imposed electric field exerts a force on both the electrons and holes created by light incident on the solar cell and accelerates the electron-hole pairs towards the electrodes of the solar cell. The solar cell management system considers variations in configuration of solar cells to maximize the power output of the solar cells. The accelerated electron-hole pairs have a lower likelihood of recombining within the cells' semiconductor's material. This reduction in the electron-hole recombination rate results in an overall increase in the solar cells' efficiency and greater power output. | 2015-08-27 |
20150244316 | Dynamically Setting a Threshold Output Level for a Solar Array - A method and apparatus for managing a solar array. Light is measured using a threshold sensor to generate sensor data. A selected threshold is computed for an electrical output generated by a plurality of solar cells in the solar array based on the sensor data using control logic in a control module. | 2015-08-27 |
20150244317 | LOW-NOISE VOLTAGE-CONTROLLED OSCILLATOR - A low-noise and big tuning range voltage-controlled oscillator. Wherein a current source circuit is used for generating working current of the voltage-controlled oscillator, a resonance circuit is used for generating an oscillating signal of the voltage-controlled oscillator, the resonance circuit is an inductance and capacitance type resonance circuit, wherein capacitance adopts a metal oxide semiconductor (MOS) capacitive reactance tube or a reverse diode to increase the tuning range of the circuit, a negative resistance circuit is used for generating negative resistance to counteract positive resistance generated by the resonance circuit, and a feedback circuit is used for feeding back the oscillating signal generated by the resonance circuit to the current source circuit to add a new current to the current source so as to improve the use efficiency of the voltage controlled oscillator. Therefore, the voltage controlled oscillator has larger output voltage amplitude. Tho larger the output voltage amplitude of the voltage controlled oscillator is, the better the phase noise performance is. | 2015-08-27 |
20150244318 | OSCILLATION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME - When an external clock signal exceeding a power supply voltage is input to a first terminal, a voltage of a bulk of a P type MOS transistor becomes higher than a power supply voltage, but a current does not flow from the bulk of the P type MOS transistor to a first power supply line since a first diode is provided in a forward direction with respect to a direction of a current flowing from a first power supply line to the bulk of the P type MOS transistor. Therefore, it is possible to reliably prevent a reverse current from flowing from the first terminal to the first power supply line. | 2015-08-27 |
20150244319 | COMPLEMENTARY COLPITTS VOLTAGE CONTROLLED OSCILLATOR WITH LOW POWER AND LOW PHASE NOISE - A complementary Colpitts voltage-controlled oscillator having the properties of low power and low phase noise are disclosed. The disclosed complementary Colpitts voltage-controlled oscillator includes: a first circuit composed as a PMOS Colpitts voltage-controlled oscillator having a first PMOS transistor, a first current source, a first capacitor, a second capacitor, and a first inductor but with the first inductor removed; a second circuit composed as an NMOS Colpitts voltage-controlled oscillator having a first NMOS transistor, a second current source, a third capacitor, a fourth capacitor, and a second inductor but with the second inductor removed; and a first transformer and a second transformer arranged between the first circuit and the second circuit. | 2015-08-27 |
20150244320 | RESONATOR HAVING DISTRIBUTED TRANSCONDUCTANCE ELEMENTS - An apparatus comprises a resonator including a plurality of switched impedances spatially distributed within the resonator and a corresponding plurality of transconductance elements distributed within respective distances among the switched impedances. The resonator has a given desired resonant frequency and a given amplitude of response. Combined pairs of the switched impedances and transconductance elements have respective parasitic resonant frequencies which are higher than the given desired resonant frequency and have respective amplitudes of response which are lower than the given amplitude of response. The apparatus may be a voltage controlled oscillator or an active filter. | 2015-08-27 |
20150244321 | RECEPTION CIRCUIT, AND RECEPTION APPARATUS - There is provided a reception circuit that includes a local signal generation section, a duty-cycle correction section, an oscillation signal generation section, and a mixture section. The local signal generation section is configured to generate a local signal, the local signal being different in frequency from a modulated reception signal. The duty-cycle correction section is configured to correct a duty cycle of the generated local signal to be a predetermined value. The oscillation signal generation section is configured to generate a plurality of oscillation signals, the oscillation signals being generated using the duty-cycle-corrected local signal to vary in phase. The mixture section is configured to mix the reception signal with each of the oscillation signals. | 2015-08-27 |
20150244322 | BIAS CIRCUITS AND METHODS FOR STACKED DEVICES - Embodiments of the present disclosure include a bias circuit for generating bias voltages to stacked transistors. In one embodiment, stacked transistors are coupled between an input transistor and an output node. A modulated power supply voltage and an input signal produce a voltage at the output node. The modulated power supply voltage is provided as an input to the bias circuit. Bias voltages are generated that change with the power supply voltage. In one embodiment, particular transistors in the stack are biased so that their control terminals are effectively short circuited when the power supply voltage is reduced. | 2015-08-27 |
20150244323 | HARMONIC REJECTION POWER AMPLIFIER - A power amplifier is provided that generates timing signals which respectively turn on or off switches for respectively opening or closing current paths for current sources and which have same duty ratio and different phases and that adjusts current values for the current sources based on phase differences among the timing signals. | 2015-08-27 |
20150244324 | POWER AMPLIFICATION DEVICE AND TRANSMITTER - A power amplification device includes: a first power-amplifier array including a plurality of first switching elements that constitute a class-D power amplifier for a higher bits; a second power-amplifier array including a plurality of second switching elements that constitute a class-D power amplifier for a lower bits; and a capacitor array including a plurality of capacitance elements. The second switching elements have a larger on-resistance than the first switching elements. The first power-amplifier array is arranged between the second power-amplifier array and the capacitor array. | 2015-08-27 |
20150244325 | LOAD CURRENT SENSOR FOR ENVELOPE TRACKING MODULATOR - An apparatus and method for sensing load current of an envelope tracking (ET) modulator enables load impedance of a power amplifier to be measured. Impairments associated with the load impedance characteristic can be suppressed by calibration and predistortion instead of by feedback (as done in the prior art). The ET modulator provides a switching regulator that can be reconfigured as a linear regulator for the purpose of sensing the load current. This allows the ET modulator to be operated open-loop, thereby eliminating the power consumption overhead resulting from utilization of a loop filter and error amplifier (used in the prior art) and achieving a higher overall efficiency. | 2015-08-27 |
20150244326 | ADAPTIVE BIAS CIRCUIT AND POWER AMPLIFIER - A bias circuit may include an envelope detecting unit detecting an envelope of an input signal, a source voltage generating unit generating a source voltage using a power supply voltage, and an envelope amplifying unit receiving the power supply voltage and the source voltage as a driving voltage and amplifying an envelope signal detected by the envelope detecting unit to generate a first bias voltage. | 2015-08-27 |
20150244327 | AMPLIFIER CIRCUIT, BIASING BLOCK WITH OUTPUT GAIN COMPENSATION THEREOF, AND ELECTRONIC APPARATUS - An exemplary embodiment of the present disclosure illustrates an amplifier circuit comprising an amplifier block and a biasing block. The amplifier block is used to receive an input signal and amplify the input signal to generate an output signal. The a biasing block coupled to the amplifier block is used to provide biasing voltages to bias the amplifier block, and compensate an output gain of the amplifier block before the output gain of the amplifier block is compressed, so as to extend a P1 dB compression point of the amplifier block, wherein the biasing currents are substantially independent to temperature and/or system voltage variation. | 2015-08-27 |
20150244328 | PPA Linearization - A linearization circuit improves the linearity of a power amplifier based on an envelope of an input RF signal. The linearization circuit comprises an RF signal generation circuit, a replica circuit, and an adaptive amplifier. The RF signal generation circuit generates the RF signal from a phase and an amplitude of an input digital signal. The replica circuit extracts the envelope from the RF signal and generates a sensing voltage based on the extracted envelope. The adaptive amplifier generates an adaptive bias voltage for the power amplifier based on the sensing voltage, and applies the adaptive bias voltage to the power amplifier and to the replica circuit to improve the linearity of the power amplifier by regulating the power amplifier and the replica circuit according to the envelope. | 2015-08-27 |
20150244329 | Technique for Extremely High Order IM Correction - A method for correcting high order IM products is described. The method includes creating a modified input signal by increasing one or more portions of an input signal (such as the whole time domain signal for example). The input signal consists of a desired signal and other non-linear products. Each of the one or more portions includes high order IM products. A pre-distorted signal is created by pre-distorting the modified input signal in accordance with a finite signal plan. An output signal is generated by amplifying the pre-distorted signal. Apparatus and computer-readable media are also described. | 2015-08-27 |
20150244330 | AMPLIFIER APPARATUS AND SOFT-START METHOD THEREOF - An amplifier apparatus includes a differential input pair, a current source, and a load. The differential input pair includes first and second transistors, and an auxiliary transistor. A control terminal of the first transistor receives a reference voltage. A first terminal of the second transistor is coupled to the first terminal of the first transistor, and a control terminal of the second transistor receives an input voltage. A first terminal of the auxiliary transistor is coupled to a first terminal of the first transistor, a second terminal of the auxiliary transistor is coupled to a second terminal of the first transistor, a control terminal of the auxiliary transistor receives a control voltage, and a base terminal thereof receives a power supply voltage. The current source and load are respectively coupled to the first terminals and second terminals of the first and second transistors. | 2015-08-27 |
20150244331 | MICROWAVE POWER AMPLIFICATION APPARATUS AND METHOD THEREOF - Period-one nonlinear dynamics of semiconductor lasers are utilized to provide an apparatus for photonic microwave power amplification in radio-over-fiber links through optical modulation depth improvement. The microwave power amplification apparatus includes a microwave-modulated optical signal generation module and a microwave power amplification module. The amplification capability of the present microwave power amplification apparatus covers a broad microwave range, from less than 25 GHz to more than 60 GHz, and a wide gain range, from less than 10 dB to more than 30 dB. The microwave phase quality is mainly preserved while the microwave power is largely amplified, improving the signal-to-noise ratio up to at least 25 dB. The bit-error ratio at 1.25 Gb/s is better than 10 | 2015-08-27 |
20150244332 | CURRENT MIRROR, CONTROL METHOD, AND IMAGE SENSOR - There is provided a current mirror that includes at least one bias amplifier configured to adjust a gate line voltage by feeding currents to the gate line to make constant gate-source voltages of a plurality of FETs (Field Effect Transistors), the gate line connecting gates of the FETs each being a load component in the current mirror. | 2015-08-27 |
20150244333 | ADAPTIVE RAIL VOLTAGE REGULATION ON POWER SUPPLIES - The system comprises a Digital Signal Processing module, a Power Supply Unit and an audio amplifier. In the Digital Signal Processing module, the level of the digital audio signal is detected for adjusting the rail voltage in the amplifier. The digital audio signal is delayed by the Digital Signal Processing module prior to transforming and feeding it into the audio amplifier for amplification in order to stabilize the rail voltage after adjustment of the rail voltage to an increased level. Further in order to decrease the power consumption, especially in battery driven amplifiers, an adjustment of the rail voltage to a reduced level is delayed by a second predetermined time length (S_Hold) of 1 to 5 seconds as this reduces the number of adjustments of the rail voltage. | 2015-08-27 |
20150244334 | AMPLIFICATION DEVICE AND RADIO COMMUNICATION APPARATUS EQUIPPED WITH AMPLIFICATION DEVICE - An amplification transistor has a collector to which a voltage converted by a DC/DC converter is supplied. An output voltage of the DC/DC converter is determined based on an input impedance of a rear-stage circuit block. For example, a voltage of the DC/DC converter is set such that an output waveform of an amplifier circuit becomes appropriate for the input impedance of the rear-stage circuit block (generally 50 [Ω]) in a targeted modulation scheme (mode) or frequency (band) to be used, without having to use an output matching circuit. | 2015-08-27 |
20150244335 | DRIVE CIRCUIT - A drive circuit includes a signal source that outputs an AC signal, a voltage generator circuit that includes a differential amplifier that generates a first AC voltage with a constant amplitude from the AC signal and outputs the first AC voltage to one end of an external load, and a voltage-to-current converter circuit that is connected to another end of the external load and supplies an AC current with a constant amplitude in opposite phase to the first AC voltage to the external load in accordance with the AC signal. | 2015-08-27 |
20150244336 | WIRELESS MICROPHONE MUTE CONTROL OVERRIDE - An audio system is configured to support a number of wireless microphones, and each of the wireless microphones has one or more touch sensitive mute switches and a touch sensitive mute guard band switch. The mute guard band switch is connect to an electrically conductive surface that is proximate to a microphone peripheral surface that a user is likely to touch when they move the microphone. Logical instructions running in conjunction with a DSP associated with the microphone cause the audio system to override any mute commands it receives from any of the mute switches during the time that the guard band switch is activated. | 2015-08-27 |
20150244337 | METHOD AND APPARATUS FOR AUTOMATICALLY CONTROLLING GAIN BASED ON SENSITIVITY OF MICROPHONE IN ELECTRONIC DEVICE - The present disclosure relates to a method and an apparatus for automatically controlling a gain in an electronic device based on a sensitivity of microphone. The method according to an embodiment of the present disclosure includes outputting a reference audio to a speaker and obtaining a sound signal output by the speaker through a microphone, comparing a parameter of the obtained sound signal with a stored parameter, and adjusting a gain of the microphone based on a result of the comparing. | 2015-08-27 |
20150244338 | WIRELESS COMMUNICATION DEVICE, METHOD AND POWER AMPLIFIER OF THE SAME - A wireless communication device that includes a power amplifier and an antenna is provided. The power amplifier includes a first and a second power amplifying paths, a first and a second selection circuits, first matching circuits and second matching circuits. The first and the second power amplifying paths receive a first and a second input signals respectively. The first selection circuit selects one of the first matching circuits according to a frequency band of the first input signal to perform a first matching process to generate a first output signal. The second selection circuit selects one of the second matching circuits according to a frequency band of the second input signal to perform a second matching process to generate a second output signal. The antenna is coupled to the power amplifier to transmit the first and/or the second output signals. | 2015-08-27 |
20150244339 | ELECTROMAGNETIC INTERFERENCE FILTER ASSEMBLY - An assembly and method for providing electromagnetic interference isolation. The assembly includes an enclosure which has a first panel and a second panel. Bus bars extend through the first panel and the second panel. A mounting plate is positioned between the first panel and the second panel. The mounting plate has locating members thereon. A plurality of inductive cores are positioned proximate the locating members, the inductive cores having openings through which the bus bars extend. The inductive cores are precisely positioned in the enclosure to facilitate the electromagnetic interference isolation. | 2015-08-27 |
20150244340 | ADJUSTABLE HARMONIC FILTERING DEVICE - The present invention is related to an adjustable harmonic filtering device, mainly comprising a first connecting port, a second connecting port, a harmonic filtering unit, and an adjusting unit, in which a passive network is presented between the first connecting port and the second connecting port, as well as the harmonic filtering unit is connected to the passive network. The harmonic filtering unit comprises a first inductor and a first capacitor. The adjusting unit is adjacent to the first inductor of the harmonic filtering unit, and induced electromagnetically therewith. Thus, frequency-band of the harmonic, to be filtered out by the harmonic filtering unit, may be changed, allowing for reducing loss of signal occurring in the process of transmission between the first connecting port and the second connecting port effectively. | 2015-08-27 |
20150244341 | Impedance Matching for Inductive Power Transfer Systems - Methods and apparatuses for improved efficiency of power transfer across an inductive charging interface by adaptively changing the impedance of the receive coil in response to changes in load conditions during inductive power transfer are disclosed. | 2015-08-27 |
20150244342 | HIGH FREQUENCY MATCHING SYSTEM - An impedance adjustment apparatus of the invention performs impedance matching using characteristic parameters, even where a high frequency power source of variable frequencies is used. The apparatus is applicable to a power supply system using a high frequency power source of variable frequencies. Characteristic parameters obtained by targeting a portion of combinations of position information (C) of a variable capacitor and output frequency information (F) of the power source are stored in a memory. A T-parameter acquisition unit acquires characteristic parameters corresponding to (C | 2015-08-27 |
20150244343 | LATERALLY-COUPLED ACOUSTIC RESONATORS - An apparatus, comprises a piezoelectric layer, a first acoustic resonator comprising first and second electrodes formed on opposite sides of the piezoelectric layer, and a second acoustic resonator comprising first and second electrodes formed on opposite sides of the piezoelectric layer and acoustically coupled to the first acoustic resonator. | 2015-08-27 |
20150244344 | SELF-POWERED SENSING AND TRANSMITTING DEVICE AND METHOD OF FABRICATING THE SAME - A self-powered sensing and transmitting circuit ( | 2015-08-27 |
20150244345 | TUNABLE FILTER STRUCTURES AND DESIGN STRUCTURES - Tunable filter structures, methods of manufacture and design structures are disclosed. The method of forming a filter structure includes forming a piezoelectric resonance filter over a cavity structure. The forming of the piezoelectric resonance filter includes: forming an upper electrode on one side of a piezoelectric material; and forming a lower electrode on an opposing side of the piezoelectric material. The method further includes forming a micro-electro-mechanical structure (MEMS) cantilever beam at a location in which, upon actuation, makes contact with the piezoelectric resonance filter. | 2015-08-27 |
20150244346 | BULK ACOUSTIC WAVE RESONATORS HAVING DOPED PIEZOELECTRIC MATERIAL AND FRAME ELEMENTS - A bulk acoustic wave (BAW) resonator includes a first electrode; a second electrode; and a piezoelectric layer disposed between the first and second electrodes. The piezoelectric layer includes a piezoelectric material doped with at least one rare earth element. In an embodiment, the BAW resonator includes a recessed frame element disposed over a surface of at least one of the first and second electrodes. In another embodiment, the BAW resonator includes a raised frame element disposed over a surface of at least one of the first and second electrodes. In yet another embodiment, the BAW resonator includes both the raised and recessed frame elements. | 2015-08-27 |
20150244347 | BULK ACOUSTIC WAVE RESONATOR HAVING DOPED PIEZOELECTRIC LAYER - In accordance with a representative embodiment, a bulk acoustic wave (BAW) resonator comprises: a first electrode having a first electrode thickness; a second electrode having a second electrode thickness; and a piezoelectric layer having a piezoelectric layer thickness and being disposed between the first and second electrodes, the piezoelectric layer comprising a piezoelectric material doped with at least one rare earth element. For a particular acoustic coupling coefficient (kt | 2015-08-27 |
20150244348 | SAW FILTER WITH IMPROVED STOP BAND SUPPRESSION - A filter working with surface acoustic waves comprises a piezoelectric substrate (SU), a first transducer (IDT | 2015-08-27 |
20150244349 | Efficient Drift Avoidance Mechanism for Synchronous and asynchronous Digital Sample Rate Converters - A device, comprising a first interpolator that is configured to (a) receive, at a first clock rate, a first signal having a first sampling rate and (b) output, at a second clock rate, a second signal having a first desired sampling rate average; wherein the first interpolator comprises: a first buffer for storing the first signal; and a first fractional sampling ratio circuit that is configured to generate a first pattern of fixed point values, wherein an average value of the first pattern corresponds to a first desired sampling rate ratio between the first desired sampling rate average and the first sampling rate. | 2015-08-27 |
20150244350 | MULTI-PHASE SIGNAL GENERATOR AND MULTI-PHASE SIGNAL GENERATING METHOD THEREOF - A multi-phase signal generator and a multi-phase signal generating method thereof. The multi-phase signal generator includes a signal generator, a first comparator, a second comparator and a logic operation circuit. The signal generator generates a periodic signal. The first comparator receives the periodic signal and respectively compares the periodic signal with a first reference voltage and a second reference voltage to generate a first output signal. The second comparator receives the periodic signal and compares the periodic signal with a first threshold voltage to generate a second output signal. The logic operation circuit performs logic operations on the first output signal and the second output signal so as to generate a plurality of first phase output signals. | 2015-08-27 |
20150244351 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS AND POWER CONSUMPTION REDUCTION METHOD THEREOF - A semiconductor integrated circuit apparatus includes a plurality of circuit blocks configured to include a plurality of latch circuits connected via a data path, and a chopper to output a clock to have operations of the latch circuits synchronized; and an amplitude adjustment circuit configured to be capable of adjusting an amplitude of the clock of each of the circuit blocks to a voltage different from each other. | 2015-08-27 |
20150244352 | POWER REDUCTION DEVICE AND METHOD - Embodiments of the invention provide a power reduction device and method. According to at least one embodiment, there is provided a power reduction device, which includes an internal reset generating unit outputting an internal reset signal when a power supplying voltage is lowered from a normal state to a lower threshold voltage or less, and a power controlling unit outputting a power down signal after a predetermined time elapses when the internal reset signal is output from the internal reset generating unit. According to at least one embodiment, a power down mode in a chip is operated when a power lower than a reference is provided for a long time, thereby making it possible to reduce a current consumed in the chip. | 2015-08-27 |
20150244353 | DUTY CYCLE CONTROLLER - In one aspect, a duty cycle controller includes a first port configured to receive a voltage bias signal, a second port configured to receive an input voltage signal, a third port configured to provide an output signal of the duty cycle controller having a duty cycle and a n-bit digital-to-analog converter (DAC) configured to receive the voltage bias signal and to provide a DAC output signal to a comparator. The DAC output signal has a peak value. The duty cycle controller also includes the comparator configured to compare the DAC output signal from the n-bit DAC with the input voltage signal to provide a comparator output signal. The comparator output signal is used to provide the output signal of the duty cycle controller and the duty cycle changes with changes to the input voltage signal. | 2015-08-27 |
20150244354 | OSCILLATORS - A circuit may include a delay element, a voltage adjust line, and a controllable capacitance. The delay element may have a delay and may include an input and an output. The input may be coupled to the output. The voltage adjust line may be configured to provide an adjusting voltage to the delay element to adjust the delay of the delay element. The controllable capacitance may be coupled to the output of the delay element and may be configured such that a change of the controllable capacitance adjusts the delay of the delay element. | 2015-08-27 |
20150244355 | LOW-POWER OFFSET-STORED LATCH - A low-power offset-stored CMOS latch includes, for example, a common current source that is arranged to provide a predetermined bias current for an offset storage phase and enable transistors that are arranged to couple a resolution bias current during a resolution period to a respective input pair device. The low-power offset-stored CMOS latch optionally includes current scaling to provide a resolution bias current that is larger than the predetermined bias current of the offset storage phase. | 2015-08-27 |
20150244356 | POWER-UP SIGNAL GENERATION CIRCUIT - A power-up signal generation circuit includes a control signal generation unit suitable for generating first and second control voltages based on a power-up signal, a level tracing voltage generation unit suitable for generating a level tracing voltage whose voltage level varies based on the first and second control voltages, and a power-up signal generation unit suitable for generating the power-up signal based on the level tracing voltage, and providing a feedback on the power-up signal to the control signal generation unit. | 2015-08-27 |
20150244357 | DELAY LINE CIRCUIT WITH VARIABLE DELAY LINE UNIT - A delay line circuit comprises a plurality of delay units configured to receive an input signal and modify the input signal to produce a first output signal. The delay line circuit also comprises a variable delay line unit that comprises an input end configured to receive the first output signal; an output end configured to output a second output signal; a first line between the input end and the output end, the first line comprising, in series, a first inverter, a second inverter, a first speed control unit, and a third inverter; a second line between the input end and the output end, the second line comprising, in series, a fourth inverter, a second speed control unit, a fifth inverter, and a sixth inverter. The delay line circuit is also configured to selectively transmit the received first output signal through one of the first line or the second line. | 2015-08-27 |
20150244358 | SEMICONDUCTOR DEVICES AND METHODS PROVIDING NON-LINEAR COMPENSATION OF FIELD-EFFECT TRANSISTORS - Semiconductor devices and methods are disclosed including switch circuitry providing improved switching performance. A semiconductor die includes a semiconductor substrate, at least one field-effect transistor (FET) formed on the semiconductor substrate, and a compensation circuit connected to a respective source of each of the at least one FET, the compensation circuit configured to compensate a non-linearity effect generated by the at least one FET. | 2015-08-27 |
20150244359 | Dual-Voltage Detector Having Disable Outputs Within Separate Voltage Domain and Related Methods - Dual-voltage detectors and related methods are disclosed that receive control signals from a first supply voltage domain and provide multiple disable outputs within a separate supply voltage domain. The disclosed embodiments detect a power supply status in one supply voltage domain (e.g., 1.2 volts, ground) and then assert low voltage disable or reset signals to downstream circuitry within a different supply voltage domain that is powered with different supply voltages (e.g., 1.8 volts, 0.9 volts, ground). In certain embodiments, the dual-voltage detectors provide two disable signals to stacked output drivers that are used to tri-state the stacked output drivers to place them in a high-impedance (HIGH-Z) state, for example, during power-up or power-down operations. | 2015-08-27 |
20150244360 | INPUT/OUTPUT CIRCUIT - A circuit includes a first power node configured to carry a voltage K·V | 2015-08-27 |
20150244361 | GATE DRIVING CIRCUIT AND DISPLAY PANEL USING THE SAME - An embodiment according to the present invention discloses a gate driving circuit and display panel using the same. The circuit includes a driving unit, a control unit, a first negative voltage input, a driving voltage input and a control signal input. Three inputting ends of the driving unit are connected to the different inputs when the status of the driving unit is changed according to the sequence of first cut-off status/first driving status/second driving status/second cutoff status. The benefit of the solution is to prevent circuit invalid due to the drain current generating when the oxide thin film transistor works in the depletion mode. | 2015-08-27 |
20150244362 | SYSTEM AND METHOD FOR PROTECTION OF SPACECRAFT ELECTRONICS - A system and method for protecting an electronics module on a spacecraft in space are Described. The system includes a non-radiation hardened electronics module electrically connected to a power supply, with a switch connected between the power supply and the electronics module. The switch can disconnect the electronics module from the power supply in response to an event signal. A sensor which is capable of detecting a solar proton event is connected to the switch. The sensor emits the event signal upon detection of the solar proton event. | 2015-08-27 |
20150244363 | LINE RECEIVER CIRCUIT WITH ACTIVE TERMINATION - A circuit for receiving digital signals over a transmission line. A feedback circuit is coupled to an input node of the transmission line and adjusts the input impedance of the receiver circuit to match the characteristic impedance of the transmission line. The feedback circuit includes a first current source controlled by a first voltage and having a first transconductance, and a second current source controlled by the first voltage and having a second transconductance equal to the first transconductance times a first scaling factor. The feedback circuit includes a first resistance element having a resistance equal to the first scaling factor plus one, times the characteristic impedance of the transmission line, and is coupled between the outputs of the first and second current sources. Finally, the feedback circuit also includes a differential amplifier that compares the output of the first current source to a reference value then generates the first voltage output to control each of the first and second current sources. | 2015-08-27 |
20150244364 | NONVOLATILE MEMORY WITH CHIP-SELECT/DEVICE-ADDRESS TRIGGERED ON-DIE TERMINATION - A non-volatile memory device determines, based at least partly on a first multi-bit device address received via a signaling interface and an incoming chip-select signal, whether the device is to participate in a memory access transaction by receiving or outputting data via an I/O node of the signaling interface. Based at least in part on that determination, on-die termination circuitry within the non-volatile memory device switchably couples or decouples a termination resistance between the I/O node and a supply voltage node during a data transmission phase of the memory access transaction. | 2015-08-27 |
20150244365 | NONVOLATILE MEMORY WITH COMMAND-DRIVEN ON-DIE TERMINATION - On-die termination circuitry within a non-volatile memory device applies a first termination resistance to an I/O node in response to a data storage command indicating that a data signal conveyed on a bidirectional signaling line is to be received within the non-volatile memory device via the I/O node, and applies a second termination resistance to the I/O node in response to information indicating that another memory device is to output a data signal onto the bidirectional signaling line. | 2015-08-27 |
20150244366 | INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - An integrated circuit (IC) includes at least one unit cell. The at least one unit cell includes a first bit circuit configured to process a first bit signal, a second bit circuit configured to process a second bit signal, a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage, and a second well biased to a second voltage that is different from the first voltage. Each of the first and second bit circuits includes at least one transistor from among a plurality of transistors disposed in the first well. | 2015-08-27 |
20150244367 | Method and Apparatus for Equalizing a Level Shifted Signal - A method and apparatus are provided for equalizing an output of a level shifter so as to obtain a symmetrical transition. In one implementation, a transition equalizing inverter includes: an NMOS for establishing a high-to-low transition for an equalized signal in response to a low-to-high transition of an asymmetrical signal; a delay circuit for outputting a delayed signal in response to the asymmetrical signal; and a PMOS for establishing a low-to-high transition for the equalized signal in response to a high-to-low transition of the delayed signal, wherein a delay introduced by the delay circuit offsets a timing mismatch between a low-to-high transition and a high-to-low transition of the asymmetrical signal. In an embodiment, the delay circuit comprises a transmission gate. A corresponding method is also provided. | 2015-08-27 |
20150244368 | BIAS CIRCUIT FOR A SWITCHED CAPACITOR LEVEL SHIFTER - A noise resistant switch control circuit is provided. The circuit includes a low pass filter configured to couple to a first terminal of a switch and a first voltage clamp coupled to the low pass filter. The first voltage clamp is configured to couple to a control terminal of the switch and limit a voltage of the control terminal relative to the first terminal to within a first clamping range. The circuit includes a second voltage clamp coupled to an input terminal of the switch control circuit. The second voltage clamp is configured to couple to the control terminal of the switch. The second voltage clamp is further configured to reduce a level of a control voltage coupled to the second voltage clamp. The circuit includes a bias device configured to couple to the control terminal of the switch and to impress a biasing voltage to the control terminal. | 2015-08-27 |
20150244369 | Circuit Arrangements and Methods of Operating the Same - In various embodiments, a circuit arrangement may be provided. The circuit arrangement may include a level shifting stage configured to be coupled to a first reference voltage, the level shifting stage having an output node. The circuit arrangement may further include a first input electrode in electrical connection with the level shifting stage. The circuit arrangement may also include a second input electrode in electrical connection with the level shifting stage. The circuit arrangement may further include a load having a first end and a second end, the first end coupled to the level shifting stage and the second end for coupling to a second reference voltage. In addition, the circuit arrangement may include a bypass circuit element connected in parallel to the load. The bypass circuit element may be configured to allow current to flow through upon application of an external voltage for bypassing the load. | 2015-08-27 |
20150244370 | On-Die Termination - Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals. | 2015-08-27 |
20150244371 | LEVEL CONVERSION CIRCUIT AND METHOD - A level conversion circuit is provided for generating an output signal having one of a higher output level and a lower output level in response to an input signal having one of a higher input level and a lower input level. The level conversion circuit has input circuitry which, in response to a transition of the input signal between the higher and lower input levels, output a rising transition of a temporary output signal on the output line towards the higher input level. Output control circuitry detects the rising transition of the temporary output signal and pulls the output signal to the higher output level. This arrangement allows for fast level conversion without a DC leakage path. | 2015-08-27 |
20150244372 | SINGLE SUPPLY LEVEL SHIFTER WITH IMPROVED RISE TIME AND REDUCED LEAKAGE - A single supply level shifter converts an input logic level signal IN into level shifted OUT and OUT_X. An IN inverter generates OUT at an OUT Node. The IN inverter is coupled at an INT node to a V | 2015-08-27 |
20150244373 | Nonvolatile Programmable Logic Switch - A nonvolatile programmable logic switch of an embodiment includes: a cell including: a first memory including a first terminal connected to a first wiring line, and a second terminal; a second memory including a third terminal connected to a second wiring line, and a fourth terminal connected to the second terminal of the first memory; a first transistor, of which one of a source and a drain is connected to the second and fourth terminals, the other of the source and the drain is connected to a third wiring line, and a gate is connected to a fourth wiring line; and a second transistor, of which one of a source and a drain is connected to the second and fourth terminals, the other of the source and the drain is connected to a gate of a pass transistor, and a gate is connected to a fifth wiring line. | 2015-08-27 |
20150244374 | SECURITY SHIELD ASSEMBLY - A security shield assembly has a printed circuit board having a plurality of layers, the plurality of layers including an electrically conductive penetration sensor layer, dielectric layers, and at least one signal layer. An electronic unit is mounted to the printed circuit board and electrically connected to the signal layer. | 2015-08-27 |
20150244375 | TEMPERATURE THRESHOLD CIRCUIT WITH HYSTERESIS - A circuit for determining a threshold indication of temperature with respect to a threshold temperature. The circuit includes a timer circuit and a temperature sensor circuit having an counter whose output has a relationship to temperature. At the end of a period determined by the timer circuit, a comparator circuit compares the count of the counter with an indication of the threshold temperature to determine a state of the threshold indication. In response to a change in state of the threshold indication, the circuit changes one of the count time or the counter output's relationship to temperature to provide a hysteresis for the threshold indication. | 2015-08-27 |
20150244376 | GRAY CODE COUNTER - One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PPL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator. | 2015-08-27 |
20150244377 | COMPENSATED OSCILLATOR - An oscillator includes a compensated current source that adjusts an output current based on process, supply voltage, and temperature (“PVT”) variations of an integrated circuit device. The oscillator generates an output signal having a frequency based, in part, on the output current of the compensated current source. Accordingly, the output signal has a relatively low sensitivity to PVT variations. | 2015-08-27 |
20150244378 | RELIABLE CRYSTAL OSCILLATOR START-UP - The method concerns the reliable start-up of a crystal oscillator where the drive levels the crystal is subjected to are kept low in order to avoid over-driving the crystal. After applying a start-up value of a parameter controlling the drive level where the drive level associated with the start-up value is rather high such that reliable start-up is ensured the parameter is modified step-wise so as to reduce the drive level until the crystal oscillator ceases to operate regularly. To assess whether this is the case, the frequency of the crystal oscillator is compared with the frequency of an auxiliary oscillator. A safety margin is added to the parameter and the result stored in a non-volatile memory as an operating value. The crystal oscillator is then restarted with the start-up value and after a delay the operating value is applied. | 2015-08-27 |
20150244379 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device includes first and second circuits disposed separately from each other. The first circuit may include: a counting unit suitable for generating count codes, each bit of which is cyclically changing, wherein the count codes include a number of toggles of a sampling signal toggling with a preset frequency representing a distance of single round trip of the sampling signal between the first and second circuits; and a pulse generation unit suitable for generating a measurement pulse according to the count codes representing the distance, wherein the pulse generation unit determines a pulse width of the measurement pulse according to the distance. | 2015-08-27 |
20150244380 | SYNCHRONOUS PROCESSING SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT - A synchronous processing system having semiconductor integrated circuits. One of the semiconductor integrated circuits as a master chip includes a first synchronization controller and a first counter controller that allows a counter in the master chip to perform counting synchronously with a clock pulse in response to a synchronization control signal from the first synchronization controller. Another semiconductor integrated circuit as a slave chip includes a second synchronization controller that receives the synchronization control signal from the master chip, and a second counter controller that allows a counter in the slave chip to perform counting synchronously with the clock pulse in response to the synchronization control signal received. Each of the first and second counter controllers allows the counter to stop counting if the synchronization control signal is not supplied at the time point that a count value of the counter has reached a predetermined value. | 2015-08-27 |
20150244381 | DELAY-LOCKED LOOP WITH DUAL LOOP FILTERS FOR FAST RESPONSE AND WIDE FREQUENCY AND DELAY RANGE - A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal. | 2015-08-27 |
20150244382 | ATOMIC CELL, MANUFACTURING METHOD FOR ATOMIC CELL, QUANTUM INTERFERENCE DEVICE, ATOMIC OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT - An atomic cell includes an internal space in which alkali metals are encapsulated, a coating film formed on the wall surface of the internal space, holes that allow the internal space and the outside to communicate with each other, and coating members having surfaces that face the internal space along openings of the holes on the internal space side and formed of a coating material having a characteristic same as or similar to a characteristic of the coating film. | 2015-08-27 |
20150244383 | ANALOG-DIGITAL CONVERTER - An analog-digital converter with successive approximation includes a capacitor array for being loaded by applying a given input signal potential and for providing a sampling potential, wherein capacitors of the capacitor array are serially coupled with switches. A decision latch is included for evaluating the sampling potential in a number of consecutive decision steps. The analog-digital converter also includes a logic unit for selectively changing the sampling potential by selectively switching switches associated to the capacitors of the capacitor array for each decision step based on an evaluation result of a previous decision step, wherein the switches are respectively coupled with a calibration switch. | 2015-08-27 |
20150244384 | INTERCONNECT STRUCTURES FOR MINIMIZING CLOCK AND OUTPUT TIMING SKEWS IN A HIGH SPEED CURRENT STEERING DAC - A digital-to-analog converter (DAC) system includes a DAC and a clock interconnect module. The DAC includes a plurality of segments and a plurality of drivers. Each of the plurality of segments receives driver signals from a respective one of the plurality of drivers and generates a positive output and a negative output based on the driver signals. Each of the plurality of drivers receives a respective one of a plurality of clock signals and outputs the driver signals based on the respective one of the plurality of clock signals. The clock interconnect module includes an interconnect loop. A clock input is connected to a first portion of the interconnect loop and the plurality of clock signals are output from a second portion of the interconnect loop connected to the plurality of drivers. An output interconnect module receives the positive outputs and the negative outputs generates a differential output signal. | 2015-08-27 |
20150244385 | CIRCUIT INTERFACING SINGLE-ENDED INPUT TO AN ANALOG TO DIGITAL CONVERTER - In embodiments, a circuit includes a single-ended input coupled to a first input of a differential filter. The differential filter is coupled to an analog to digital converter (ADC), and the single-ended input includes an input DC bias voltage level and an input signal. A reference generator circuit is coupled to a second input of the differential filter. The reference generator circuit generates a reference bias voltage. The differential filter includes a first filter coupled to the singled ended input and to the ADC and a second filter coupled to the reference generator circuit and to the ADC. The first filter is configured to receive the input DC bias voltage level and input signal. The second filter is configured to receive the reference bias voltage. | 2015-08-27 |
20150244386 | BACKGROUND DAC CALIBRATION FOR PIPELINE ADC - A circuit includes a track and hold (T/H) block to track an analog input signal during a track phase and to hold the analog input signal during a hold phase. A pipelined converter stage includes an analog to digital converter (ADC) receives the analog input signal from the T/H block and generates a digital output signal corresponding to the analog input signal. A digital to analog converter (DAC) element in the pipelined converter stage receives the digital output signal from the ADC and generates a current output signal representing an analog value for a portion of the analog input signal. A detector monitors the current output signal of the DAC element with respect to a predetermined reference current during the track phase and generates a trim signal if the current output signal is different from the predetermined reference current. | 2015-08-27 |
20150244387 | System and method for enhancing dynamic range of a beamforming multi-channel digital receiver - A system and method for enhancing a dynamic range of a beamforming multi-channel digital receiver are described. The receiver comprises a plurality of receiving channels, each including an analog-to-digital converter configured for converting an analog input signal generated by antenna elements into a digital signal. A “spatial” dither signal is used to decorrelate the quantization noise of the analog-to-digital converters. A dither signal is generated and split into a predetermined number of coherent dithering signals. The method includes providing predetermined time delays to the coherent dithering signals, and adding the delayed coherent dithering signals to the input signals in each receiving channel, correspondingly, thereby creating a dither signal equivalent to a signal arriving from a certain specific direction out-of-field-of-view of the antenna array. Removing of the dither signal based on the direction of arrival, is implemented during beamforming signal processing, thus enhancing the dynamic range of electromagnetic signals arriving within a field-of-view of the antenna array. | 2015-08-27 |
20150244388 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGE CAPTURING SYSTEM - In a first sensitivity level, an AD converter performs AD conversion selectively using, in accordance with the level of the analog signal, any one of a first reference signal and a second reference signal that have mutually different slopes, and in a second sensitivity level that is different from the first sensitivity level, the AD converter performs AD conversion only using a third reference signal. | 2015-08-27 |
20150244389 | INTEGRATING ANALOG-DIGITAL CONVERTER - Provided is an integrating analog-digital converter. According to the present examples, the resistance against external noise is improved by incorporating a differential amplifier into an integrating analog-digital converter. Some examples also include a section where an input voltage and a reference voltage are simultaneously blocked such that switching noise may be minimized and a reference voltage may also be stably supplied. Further, examples are designed to manage a residue, which may be generated when an integral operation to an analog input value is finished, to be processed not in an additional converter but in control logic itself, thereby reducing a size of a circuit device. | 2015-08-27 |
20150244390 | METHOD FOR TRIMMING SEGMENT CURRENTS IN CURRENT STEERING DAC BASED ON MOST BACK GATE VOLTAGE MODULATION - A digital-to-analog converter (DAC) system includes a DAC and a current trimming module. The DAC includes a plurality of segments and a plurality of drivers. Each of the plurality of segments receives driver signals from a respective one of the plurality of drivers, receives segment currents from a respective one of a plurality of segment current sources, and generates an output current based on the driver signals and the segment currents. The current trimming module stores a plurality of trim coefficients and adjusts respective threshold voltages associated with the plurality of segment current sources based on the plurality of trim coefficients. | 2015-08-27 |
20150244391 | RAMP SIGNAL GENERATOR USING PROGRAMMABLE GAIN AMPLIFIER - According to an embodiment of the inventive concept disclosed in this application, a ramp signal generator may include a ramp signal generation unit suitable for generating a ramp signal, a gain amplification control unit suitable for outputting a gain amplification control signal for controlling a voltage gain in response to a control signal from a control unit; and a programmable gain amplifier (PGA) suitable for controlling the voltage gain by amplifying the ramp signal provided from the ramp signal generation unit in response to the gain amplification control signal from the gain amplification control unit. | 2015-08-27 |
20150244392 | METHOD, SYSTEM AND APPARATUS FOR DUAL MODE OPERATION OF A CONVERTER - Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal. | 2015-08-27 |
20150244393 | MULTIPLE BIT SIGMA-DELTA MODULATOR WITH A COMMON MODE COMPENSATED QUANTIZER - A quantizer for an analog to digital converter has an input for receiving an analog input signal. A detector senses a common mode voltage component of the input signal. A reference voltage source produces a plurality of reference voltages. A voltage source biases the reference voltage source in response to the sensed common mode voltage component. Therefore, the common mode voltage in the input signal establishes the common mode voltage of the reference voltage source. A plurality of comparators are connected to the reference voltage source, wherein each of the plurality of comparators compares the input signal to one of the plurality of reference voltages and produces a output bit denoting a result of the comparing. | 2015-08-27 |
20150244394 | TERNARY LINE CODE DESIGN FOR CONTROLLED DECISION FEEDBACK EQUALIZER ERROR PROPAGATION - A method of line coding is disclosed that limits error propagation in a decision feedback equalizer (DFE) of a receiving device. A communications device receives a set of bits to be transmitted over a channel and divides the set of bits into a plurality of blocks based, at least in part, on a line coding scheme. The device then encodes each of the blocks of bits into a corresponding block of symbols based on the line coding scheme. Specifically, the line coding scheme has a non-uniform coding efficiency, wherein a first bit or a last bit of each block of bits is mapped to a single data symbol. For some embodiments, the line coding scheme may be a ternary line coding scheme that maps a block of 3k+1 bits to a corresponding block of 2k+1 symbols, where k is an integer greater than 1. | 2015-08-27 |
20150244395 | COMPLEX DIGITAL SIGNAL COMPRESSION DEVICE, METHOD AND COMPUTER-READABLE STORAGE MEDIUM, COMPLEX DIGITAL SIGNAL EXPANSION DEVICE, METHOD AND COMPUTER-READABLE STORAGE MEDIUM, AND COMMUNICATION DEVICE - An object of the present invention is to provide the compression device and the expansion device of a complex digital signal, which further raise the compression ratio of the compression digital signal. The compression device of the present invention comprises: first section that acquires a first phase and a second phase, wherein with a complex digital signal being inputted into the complex digital signal compression device, the first phase is a phase, in polar coordinates, which the complex digital signal has, and it is assumed that the complex digital signal inputted into the complex digital signal compression device is expressed as a sum of two complex digital signals with an equal amplitude, phases of which are centered at the first phase and are shifted by a phase that equals to the second phase in the positive and negative direction respectively; and second section that compresses the first phase and the second phase respectively by performing quantization. The expansion device of the present invention comprises third section and fourth section which perform the inverse processing of the second section and the first section, respectively, mentioned above. | 2015-08-27 |
20150244396 | RUN LENGTH ENCODING WITH NON-SEQUENTIAL INPUT - A method for updating a run length encoded (RLE) stream includes: receiving an element having an insertion value to be inserted into the RLE stream at an insertion position, the insertion value having one of a plurality of values, the RLE stream having elements arranged in runs, and each of the elements having one of the values; identifying a run containing the insertion position; determining whether the insertion value is the same as the value of the element at the insertion position; when the insertion value is different from the value of the element at the insertion position: determining whether the insertion position is adjacent to one or more matching runs of the runs, each element of the matching runs having a same value as the insertion value; and extending one of the matching runs when the insertion position is adjacent to only one of the matching runs. | 2015-08-27 |
20150244397 | Method Of Efficient FEC Decoder Scheduling And Receiver Pipeline Flow Control And Apparatus Using The Same - Various embodiments of a technique of efficient FEC decoder scheduling and receive pipeline flow control are provided. In one aspect, a method may involve a communication device receiving a frame. The method may also involve the method processing the frame. In processing the frame, the method may involve the communication device dynamically adjusting allocation of time for decoding each codeword in the frame by a decoder of the communication device. | 2015-08-27 |
20150244398 | BIT INTERLEAVER AND BIT DE-INTERLEAVER - A method for bit interleaving is provided. A method includes mapping a set of bits | 2015-08-27 |