35th week of 2012 patent applcation highlights part 13 |
Patent application number | Title | Published |
20120217529 | LIGHT EMITTING ELEMENT AND IMAGE DISPLAY APPARATUS USING THE LIGHT EMITTING ELEMENT - A light emitting element which can emit light in a uniform polarization state at a high efficiency and a higher luminance level is realized. The light emitting element of the present invention is a light emitting element including an active layer for generating light, the light emitting element including: a polarizer layer including a first region that transmits polarized light in a first direction and reflects other light from among the light generated at the active layer, and a second region that transmits polarized light in a second direction orthogonal to the first direction and reflects other light; a wave plate layer including a third region and a fourth region that allow the lights exited from the first region and the second region to enter, and to exit as light in the same polarization state; and a reflection layer that reflects the lights reflected at the first region and the second region. | 2012-08-30 |
20120217530 | Semiconductor Light Emitting Diodes Having Multiple Bond Pads and Current Spreading Structures - A light emitting device includes a diode region comprising a first face and opposing edges, and a bond pad structure comprising at least three bond pads along only one of the opposing edges of the first face. | 2012-08-30 |
20120217531 | SEMICONDUCTOR LIGHT EMITTING DEVICE, SEMICONDUCTOR LIGHT EMITTING APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a stacked structure body and an electrode. The stacked structure body has a first conductivity type first semiconductor layer including a nitride-based semiconductor, a second conductivity type second semiconductor layer including a nitride-based semiconductor, and a light emitting layer provided between the first and second semiconductor layers. The electrode has first, second and third metal layers. The first metal layer is provided on the second semiconductor layer and includes silver or silver alloy. The second metal layer is provided on the first metal layer and includes at least one element of platinum, palladium, rhodium, iridium, ruthenium, osmium. The third metal layer is provided on the second metal layer. A thickness of the third metal layer along a direction from the first toward the second semiconductor layer is equal to or greater than a thickness of the second metal layer. | 2012-08-30 |
20120217532 | RESIN COMPOSITION FOR OPTICAL SEMICONDUCTOR ELEMENT HOUSING PACKAGE, AND OPTICAL SEMICONDUCTOR LIGHT-EMITTING DEVICE OBTAINED USING THE SAME - The present invention relates to a resin composition for forming an insulating resin layer for optical semiconductor element housing package having a concave portion in which a metal lead frame and an optical semiconductor element mounted thereon are housed, in which the resin composition includes the following ingredients (A) to (D), and the ingredients (C) and (D) are contained in a blend ratio (C)/(D) of 0.26 to 3.0 as a weight ratio thereof: (A) an epoxy resin; (B) an acid anhydride curing agent; (C) a white pigment; and (D) an inorganic filler. | 2012-08-30 |
20120217533 | SEMICONDUCTOR LIGHT EMITTING DEVICE WITH A CONTACT FORMED ON A TEXTURED SURFACE - A device includes a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure includes an n-contact region and a p-contact region. A cross section of the n-contact region comprises a plurality of first regions wherein portions of the light emitting layer and p-type region are removed to expose the n-type region. The plurality of first regions are separated by a plurality of second regions wherein the light emitting layer and p-type region remain in the device. The device further includes a first metal contact formed over the semiconductor structure in the p-contact region and a second metal contact formed over the semiconductor structure in the n-contact region. The second metal contact is in electrical contact with at least one of the second regions in the n-contact region. | 2012-08-30 |
20120217534 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT - Disclosed is a semiconductor light emitting element ( | 2012-08-30 |
20120217535 | Method of Encapsulating a Flexible Optoelectronic Multi-Layered Structure - The invention relates to a method of encapsulating a flexible optoelectronic multi-layered structure ( | 2012-08-30 |
20120217536 | NITRIDE BASED LIGHT EMITTING DEVICE WITH EXCELLENT CRYSTALLINITY AND BRIGHTNESS AND METHOD OF MANUFACTURING THE SAME - Disclosed is a nitride-based light emitting device capable of improving crystallinity and brightness. The nitride-based light emitting device includes a growth substrate, a lattice buffer layer formed on the growth substrate, a p-type nitride layer formed on the lattice buffer layer, a light emitting active layer formed on the p-type nitride layer, and an n-type ZnO layer formed on the light emitting active layer. The lattice buffer layer is formed of powders of a material having a Wurtzite lattice structure. The lattice buffer layer is formed of ZnO powders, thereby minimizing generation of dislocations during nitride growth. A method of manufacturing the same is also disclosed. | 2012-08-30 |
20120217537 | NITRIDE BASED LIGHT EMITTING DEVICE USING PATTERNED LATTICE BUFFER LAYER AND METHOD OF MANUFACTURING THE SAME - Disclosed is a method of manufacturing a nitride-based light emitting device, in which a patterned lattice buffer layer is formed to minimize dislocation density upon growth of a nitride layer and an air gap is formed to enhance brightness of the light emitting device. The method includes depositing a material having a Wurtzite lattice structure on a substrate to form a deposition layer, forming an etching pattern on a surface of the deposition layer to form a patterned lattice buffer layer, and growing a nitride layer on the patterned lattice buffer layer. During the growth of the nitride layer, the patterned lattice buffer layer is removed to form an air gap at a portion of the nitride layer from which the patterned lattice buffer layer is removed. A nitride-based light emitting device manufactured thereby is also disclosed. | 2012-08-30 |
20120217538 | NITRIDE BASED LIGHT EMITTING DEVICE USING WURTZITE POWDER AND METHOD OF MANUFACTURING THE SAME - Disclosed is a nitride-based light emitting device using powders of a material having a Wurtzite lattice structure, such as ZnO powders. The nitride-based light emitting device includes a growth substrate, a lattice buffer layer formed on the growth substrate, and a light emitting structure formed on the lattice buffer layer and having a plurality of nitride layers stacked therein, wherein the lattice buffer layer is formed of powders of a material having a Wurtzite lattice structure. The lattice buffer layer is formed of ZnO powders, thereby minimizing occurrence of dislocations caused by a difference in lattice constant between a nitride layer and the growth substrate during growth of the nitride layer. A method of manufacturing the same is also disclosed. | 2012-08-30 |
20120217539 | Semiconductor Component with Improved Dynamic Behavior - Disclosed is a semiconductor component that includes a semiconductor body, a first emitter region of a first conductivity type in the semiconductor body, a second emitter region of a second conductivity type spaced apart from the first emitter region in a vertical direction of the semiconductor body, a base region of one conductivity type arranged between the first emitter region and the second emitter region, and at least two higher doped regions of the same conductivity type as the base region and arranged in the base region. The at least two higher doped regions are spaced apart from one another in a lateral direction of the semiconductor body and separated from one another only by sections of the base region. | 2012-08-30 |
20120217540 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device having a semiconductor body, a source metallization arranged on a first surface of the semiconductor body and a trench including a first trench portion and a second trench portion and extending from the first surface into the semiconductor body is provided. The semiconductor body further includes a pn-junction formed between a first semiconductor region and a second semiconductor region. The first trench portion includes an insulated gate electrode which is connected to the source metallization, and the second trench portion includes a conductive plug which is connected to the source metallization and to the second semiconductor region. | 2012-08-30 |
20120217541 | IGBT WITH INTEGRATED MOSFET AND FAST SWITCHING DIODE - A power semiconductor device comprising a trench IGBT, a trench MOSFET and a fast switching diode for reduction of turn-on loss is disclosed. The inventive semiconductor power device employs a fast switching diode instead of body diode in the prior art. Furthermore, the inventive semiconductor power device further comprises an additional ESD protection diode between emitter metal and gate metal. | 2012-08-30 |
20120217542 | BIDIRECTIONAL SWITCH - A bidirectional switch includes a semiconductor element and a substrate potential stabilizer. The semiconductor element includes a first ohmic electrode and a second ohmic electrode, and a first gate electrode and a second gate electrode, which are sequentially formed on the first ohmic electrode between the first ohmic electrode and the second ohmic electrode. The substrate potential stabilizer sets a potential of the substrate lower than higher one of a potential of the first ohmic electrode or a potential of the second ohmic electrode. | 2012-08-30 |
20120217543 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - At least one kind of impurity selected from, for example, Fe, C, B, Ti, Cr is introduced into at least a buffer layer of a compound semiconductor layered structure from a rear surface of the compound semiconductor layered structure to make a resistance value of the buffer layer high. | 2012-08-30 |
20120217544 | COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a source electrode and a drain electrode provided over the nitride semiconductor stacked structure; a gate electrode provided between the source electrode and the drain electrode, over the nitride semiconductor stacked structure; a field plate provided at least partially between the gate electrode and the drain electrode; and a plurality of insulation films and formed over the nitride semiconductor stacked structure, wherein a number of interfaces of the plurality of insulation films is smaller between the field plate and the drain electrode than in the vicinity of the gate electrode. | 2012-08-30 |
20120217545 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of producing a semiconductor device, includes: forming a semiconductor layer on a substrate; forming an a recess in the semiconductor layer by dry etching with a gas containing fluorine components, the recess having an opening portion on the surface of the semiconductor layer; forming a fluorine-containing region by heating the semiconductor layer and thus diffusing, into the semiconductor layer, the fluorine components attached to side surfaces and a bottom surface of the recess; forming an insulating film on an inner surface of the recess and on the semiconductor layer; and forming an electrode on the insulating film in a region in which the recess is formed. | 2012-08-30 |
20120217546 | SEMICONDUCTOR DEVICE - An aspect of the present invention inheres in a semiconductor device includes a semiconductor region, a source electrode and a drain electrode, which are provided on a main surface of the semiconductor region, a gate electrode exhibiting normally-off characteristics, the gate electrode being provided above the main surface of the semiconductor region while interposing a p-type material film therebetween, and being arranged between the source electrode and the drain electrode, and a fourth electrode that is provided on the main surface of the semiconductor region, and is arranged between the gate electrode and the drain electrode. | 2012-08-30 |
20120217547 | FIELD EFFECT TRANSISTOR WITH REDUCED GATE LEAKAGE CURRENT - Disclosed is an HJFET | 2012-08-30 |
20120217548 | THIN-FILM HETEROSTRUCTURE THERMOELECTRICS IN A GROUP IIA AND IV-VI MATERIALS SYSTEM - Embodiments of a thin-film heterostructure thermoelectric material and methods of fabrication thereof are disclosed. In general, the thermoelectric material is formed in a Group IIa and IV-VI materials system. The thermoelectric material includes an epitaxial heterostructure and exhibits high heat pumping and figure-of-merit performance in terms of Seebeck coefficient, electrical conductivity, and thermal conductivity over broad temperature ranges through appropriate engineering and judicious optimization of the epitaxial heterostructure. | 2012-08-30 |
20120217549 | ASYMMETRIC SEMICONDUCTOR MEMORY DEVICE HAVING ELECTRICALLY FLOATING BODY TRANSISTOR - Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side. | 2012-08-30 |
20120217550 | GAS SENSOR - A MISFET-type hydrogen gas sensor having low power consumption which can be operated for one year or longer at a low voltage power source (for example, 1.5 to 3 V) is achieved. A sensor FET is formed in a MEMS region | 2012-08-30 |
20120217551 | JUNCTION FIELD EFFECT TRANSISTOR WITH REGION OF REDUCED DOPING - A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced doping compared to a body region of the drain. The region of reduced doping and the body region can be defined by the same mask and doping step, but the mask is shaped to provide a lesser amount and thus less depth of doping for the region of reduced doping. | 2012-08-30 |
20120217552 | METAL LINE STRUCTURE AND MANUFACTURING METHOD FOR TRENCH - Exemplary metal line structure and manufacturing method for a trench are provided. In particular, the metal line structure includes a substrate, a target layer, a trench and a conductor line. The target layer is formed on the substrate. The trench is formed in the target layer and has a micro-trench formed at the bottom thereof. A depth of the micro-trench is not more than 50 angstroms. The conductor line is inlaid into the trench. | 2012-08-30 |
20120217553 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - The present invention provides a semiconductor structure, comprising: a substrate; a gate formed on the substrate, and a source and drain formed in the substrate and disposed at two sides of the gate; raised portions formed on the source and the drain, respectively, a height of the raised portions being approximate to a height of the gate; and a metal silicide layer and contact holes formed on the raised portions and on the gate. By virtue of the raised portions added to the source/drain in an embodiment of the present invention, the height difference between the gate and the source/drain may be decreased, such that the formation of the contact holes becomes much easier. | 2012-08-30 |
20120217554 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are provided which can increase the effective channel area and maintain a transistor characteristic. Since the semiconductor device comprises a recess filled with a gate spacer, a gate threshold voltage can be maintained even though the ion-implanting concentration of the active region is not uniform. The semiconductor device comprises: a device isolation film that defines an active region formed over a semiconductor substrate; a line-type recess with a given depth formed to be extended along a first direction to intersect at the active region; and a gate formed to be extended along a second direction to intersect at the active region, wherein a spacer including a high K material is disposed at sidewalls. | 2012-08-30 |
20120217555 | SEMICONDUCTOR DEVICE - A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode. | 2012-08-30 |
20120217556 | SEMICONDUCTOR DEVICE - A semiconductor device featuring a semiconductor chip having a first main surface and a second, opposing main surface and including a MOSFET having source and gate electrodes formed on the first main surface and a drain electrode thereof formed on the second main surface, first and second conductive members acting as lead terminals for the source and gate electrodes, respectively, are disposed over the first main surface, each of the first and second conductive members has a part overlapped with the chip in a plan view, a sealing body sealing the chip and parts of the first and second conductive members such that a part of the first conductive member is projected outwardly from a first side surface of the sealing body and parts of the first and second conductive members are projected outwardly from the opposing second side surface of the sealing body in a plan view. | 2012-08-30 |
20120217557 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate of a compound semiconductor material; a buffer layer, a channel layer, and a Schottky junction forming layer sequentially disposed on the semiconductor substrate, the buffer layer, the channel layer, and the Schottky junction forming layer each being compound semiconductor materials; a source electrode and a drain electrode located on the Schottky junction forming layer; and a gate electrode disposed between the source and drain electrodes and forming a Schottky junction with the Schottky junction forming layer. The carrier density in the channel layer varies with distance from a top surface of the channel layer and is inversely proportional to the third power of depth into the channel layer from the top surface of the channel layer. The buffer layer has a lower electron affinity than the channel layer and is a different compound semiconductor material from the channel layer. | 2012-08-30 |
20120217558 | IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A solid-state imaging device includes: a substrate which is formed of a semiconductor and includes a first surface and a second surface which face opposite sides; a gate insulation film which is formed on a trench formed in the substrate to penetrate the first surface and the second surface; and a gate electrode which is embedded in the trench through the gate insulation film to be exposed to a second surface side of the substrate. A step difference is formed from the second surface of the substrate to a tip end surface of the gate electrode on the second surface side. | 2012-08-30 |
20120217559 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes an active region protruding from a substrate. The active region includes first and second doped regions therein and a trench therein separating the first and second doped regions. A buried gate structure extends in a first direction along the trench between first and second opposing sidewalls thereof. A conductive interconnection plug is provided on the first doped region adjacent the first sidewall of the trench, and a conductive landing pad is provided on the second doped region adjacent the second sidewall of the trench. The landing pad has a width greater than that of the second doped region of the active region along the first direction. A conductive storage node contact plug is provided on the landing pad opposite the second doped region. The storage node contact plug has a narrower width than the landing pad along the first direction. | 2012-08-30 |
20120217560 | Semiconductor Memory Devices Including Support Patterns - A capacitor dielectric can be between the storage node and the electrode layer. A supporting pattern can be connected to the storage node, where the supporting pattern can include at least one first pattern and at least one second pattern layered on one another, where the first pattern can include a material having an etch selectivity with respect to the second pattern. | 2012-08-30 |
20120217561 | Structure And Method For Adjusting Threshold Voltage Of The Array Of Transistors - A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate. | 2012-08-30 |
20120217562 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device capable of maximizing a channel area in a pillar and a method of manufacturing the same are provided. The semiconductor device includes a pillar disposed on a semiconductor substrate and having first to fourth side surfaces, a first bit line disposed in the first side surface, a storage node junction region disposed in the third side surface facing the first side surface, and a gate disposed in the second side surface or a fourth side surface facing the second surface. | 2012-08-30 |
20120217563 | METHOD AND SYSTEM FOR PROVIDING CONTACT TO A FIRST POLYSILICON LAYER IN A FLASH MEMORY DEVICE - A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor. | 2012-08-30 |
20120217564 | SEMICONDUCTOR CHARGE STORAGE APPARATUS AND METHODS - Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described. | 2012-08-30 |
20120217565 | PROCESS FOR OBTAINING AN ARRAY OF NANODOTS - A process for obtaining an array of nanodots ( | 2012-08-30 |
20120217566 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - An object is to suppress reading error even in the case where writing and erasing are repeatedly performed. Further, another object is to reduce writing voltage and erasing voltage while increase in the area of a memory transistor is suppressed. A floating gate and a control gate are provided with an insulating film interposed therebetween over a first semiconductor layer for writing operation and erasing operation and a second semiconductor layer for reading operation which are provided over a substrate; injection and release of electrons to and from the floating gate are performed using the first semiconductor layer; and reading is performed using the second semiconductor layer. | 2012-08-30 |
20120217567 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - This semiconductor memory device comprises a semiconductor substrate, a plurality of tunnel insulator films formed on the substrate along a first direction and a second direction orthogonal to the first direction, a plurality of charge accumulation layers formed on the tunnel insulator films, respectively, a plurality of element isolation regions formed on the substrate, the element isolation regions including a plurality of trenches formed along the first direction between the tunnel insulator films, a plurality of element isolation films filled in the trenches, a plurality of inter-poly insulator films formed over the element isolation regions and on the upper and side surfaces of the charge accumulation layers along the second direction in a stripe shape, a plurality of air gaps formed between the element isolation films filled in the trenches and the inter-poly insulator films and a plurality of control gate electrodes formed on the inter-poly insulator films. | 2012-08-30 |
20120217568 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a silicon-containing substrate, a plurality of memory cells, and an insulating film. The substrate includes silicon. The plurality of memory cells is provided on the substrate with a spacing therebetween. The insulating film is provided on a sidewall of the memory cell. The insulating film includes a protrusion protruding toward an adjacent one of the memory cells above a void portion is provided between the memory cells. | 2012-08-30 |
20120217569 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a tunneling insulating film, a floating gate, a leak suppression unit, an inter-gate insulating film, and a control gate. The substrate includes silicon. The tunneling insulating film is provided on the substrate. The floating gate is provided on the tunneling insulating film. The leak suppression unit is provided on the floating gate. The inter-gate insulating film is provided on the leak suppression unit. The control gate is provided on the inter-gate insulating film. The dielectric constant of the leak suppression unit is higher than a dielectric constant of the inter-gate insulating film. | 2012-08-30 |
20120217570 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device includes: a lower pillar protruding from a substrate in a vertical direction and extending in a first direction by a trench formed in the first direction; an upper pillar protruding on the lower pillar in a second direction perpendicular to the first direction; a buried bit line junction region disposed on one sidewall of the lower pillar; a buried bit line contacting the buried bit line junction region and filling a portion of the trench; an etch stop film disposed on an exposed surface of the buried bit line; a first interlayer dielectric film recessed to expose a portion of an outer side of at least the upper pillar disposed on the etch stop film; a second interlayer dielectric film disposed on the first interlayer dielectric film; and a gate surrounding the exposed outer side of the upper pillar and crossing the buried bit line. | 2012-08-30 |
20120217571 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction. | 2012-08-30 |
20120217572 | Flash Memory Device With an Array of Gate Columns Penetrating Through a Cell Stack - A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge. | 2012-08-30 |
20120217573 | NON-VOLATILE MEMORY (NVM) CELL FOR ENDURANCE AND METHOD OF MAKING - A first dielectric is formed over a semiconductor layer, a first gate layer over the first dielectric, a second dielectric over the first gate layer, and a third dielectric over the second dielectric. An etch is performed to form a first sidewall of the first gate layer. A second etch is performed to remove portions of the first dielectric between the semiconductor layer and the first gate layer to expose a bottom corner of the first gate layer and to remove portions of the second dielectric between the first gate layer and the third dielectric layer to expose a top corner of the first gate layer. An oxide is grown on the first sidewall and around the top and bottom corners to round the corners. The oxide is then removed. A charge storage layer and second gate layer is formed over the third dielectric layer and overlapping the first sidewall. | 2012-08-30 |
20120217574 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a semiconductor substrate having an active layer in which an element region and a contact region are formed, a support substrate supporting the active layer, and a buried insulation layer interposed between the active layer and the support substrate. A transistor clement is formed in the clement region, the transistor clement having a transistor buried impurity layer formed within the active layer. The semiconductor device further includes a substrate contact having a contact buried impurity layer formed within the contact region and a through contact extending from the surface of the active layer to the support substrate through the contact buried impurity and the buried insulation layer, the contact buried impurity layer being in the same layer as the transistor buried impurity layer. | 2012-08-30 |
20120217575 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing semiconductor device. The method can include preparing a semiconductor layer having a drain layer, and a drift region provided from a surface to an inside of the drain layer, the drift region having a first trench extending from a surface to an inside of the drift region. The method can include implanting impurities into the drift region through an opening of the first trench to form a source region for an exposed face of the drift region exposed on an inside wall of the first trench, and implanting impurities into the drift region through the opening of the first trench to form a base region between the source region and the drift region. The method can include forming gate electrode. | 2012-08-30 |
20120217576 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. According to the semiconductor device and the method for forming the same, a contact hole spacer is formed only over a contact hole sidewall such that a lower part of a contact plug is formed to have large critical dimension and therefore contact resistance is increased, and an upper spacer is not lost in a process of forming a contact hole sidewall spacer so as to prevent a Self Align Contact (SAC) failure from occurring. The semiconductor device includes a contact hole formed over a semiconductor substrate, a first conductive layer formed at a bottom region of the contact hole and a lower part of sidewalls of the contact hole, a spacer formed over the sidewalls of the contact hole, and a second conductive layer buried in the contact hole including the first conductive layer and the spacer. | 2012-08-30 |
20120217577 | SEMICONDUCTOR DEVICE - A trench-gate vertical-channel type power MOSFET has an advantage of a low on-state resistance. With increasing miniaturization, fluctuations in on-state resistance have posed a problem. In addition, a structural limitation in miniaturization also has posed a problem. These problems are not only those of a single power MOSFET but also are important ones in integrated circuit devices, such as IGBT using a similar structure, obtained by integrating CMOS and such a power active device on a single chip. The invention provides a semiconductor device having a trench-gate vertical-channel type power active device, such as trench-gate vertical-channel type power MOSFET, in which the width of the interlayer insulating film is made almost equal to that of the trench and a portion of the source region is comprised of a polysilicon member. | 2012-08-30 |
20120217578 | METHOD AND SYSTEM FOR METAL GATE FORMATION WITH WIDER METAL GATE FILL MARGIN - A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion. | 2012-08-30 |
20120217579 | High voltage device and manufacturing method thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having a P (or N) type well and an isolation structure for defining a device region; a drift region, located in the device region, having a first region and a second region wherein the first region is an N (or P) type region, and the second region is a P (or N) type region or an N (or P) type region with different dopant concentration from the first region, and from top view, the first region and the second region include sub-regions distributed in the drift region; an N (or P) type source and drain; and a gate on a surface of the substrate, between the source and drain in the device region. | 2012-08-30 |
20120217580 | SEMICONDUCTOR DEVICE WITH IMPROVED ON-RESISTANCE - A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone. | 2012-08-30 |
20120217581 | SEMICONDUCTOR DEVICE LIMITING ELECTRICAL DISCHARGE OF CHARGE - A semiconductor device includes a source region embedded in the surface of the second semiconductor region, a drain region embedded in the surface of the first semiconductor region separated from the second semiconductor region, a gate electrode located on the second semiconductor region, an insulation film located on the first semiconductor region between the second semiconductor region and the drain region, a voltage dividing element dividing the voltage between the gate electrode and the drain region, and a charge transfer limiting element limiting transfer of charge from the voltage dividing element to the drain region. | 2012-08-30 |
20120217582 | SOI Semiconductor Device Comprising a Substrate Diode with Reduced Metal Silicide Leakage - When forming substrate diodes in SOI devices, superior diode characteristics may be preserved by providing an additional spacer element in the substrate opening and/or by using a superior contact patterning regime on the basis of a sacrificial fill material. In both cases, integrity of a metal silicide in the substrate diode may be preserved, thereby avoiding undue deviations from the desired ideal diode characteristics. In some illustrative embodiments, the superior diode characteristics may be achieved without requiring any additional lithography step. | 2012-08-30 |
20120217583 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the structure are provided. The semiconductor structure has a STI structure which has a top surface higher than or as high as that of source/drain stressors. A dummy gate and a spacer are added on the STI structure. The method comprises: providing a semiconductor substrate; embedding a STI structure in the semiconductor substrate in order to form isolated active areas; forming a gate stack on the active area, and forming a dummy gate on the STI structure; forming a first spacer on sidewalls of the dummy gate, wherein a part of the first spacer lands on the active area; and embedding source/drain stressors in the semiconductor substrate and at opposite sides of the gate stack, wherein the top surface of the STI structure is higher than or as high as that of the source/drain stressor. | 2012-08-30 |
20120217584 | SEMICONDUCTOR MEMORY DEVICE - In one embodiment, a semiconductor memory device includes a substrate, and device regions in the substrate to extend in a first direction. The device further includes select gates on the substrate to extend in a second direction, and a contact region provided between the select gates and including contact plugs on the respective device regions. The contact region includes partial regions, in each of which N contact plugs are disposed on N successive device regions to be arranged on a straight line being non-parallel to the first and second directions, where N is an integer of 2 or more. The contact region includes the partial regions of at least two types whose values of N are different. Further, each of the contact plugs has a planar shape of an ellipse, and is arranged so that a major axis of the ellipse is tilted with respect to the first direction. | 2012-08-30 |
20120217585 | Structure and Method for Manufacturing Asymmetric Devices - A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures. | 2012-08-30 |
20120217586 | INTEGRATED CIRCUITS WITH RESISTORS AND METHODS OF FORMING THE SAME - A method of forming an integrated circuit includes forming at least one transistor over a substrate. The at least one transistor includes a first gate dielectric structure disposed over a substrate. A work-function metallic layer is disposed over the first gate dielectric structure. A conductive layer is disposed over the work-function metallic layer. A source/drain (S/D) region is disposed adjacent to each sidewall of the first gate dielectric structure. At least one resistor structure is formed over the substrate. The at least one resistor structure includes a first doped semiconductor layer disposed over the substrate. The at least one resistor structure does not include any work-function metallic layer between the first doped semiconductor layer and the substrate. | 2012-08-30 |
20120217587 | POST CMP PLANARIZATION BY CLUSTER ION BEAM ETCH - The embodiments of mechanisms described enables improved planarity of substrates, which is crucial for patterning and device yield improvement. Chemical-mechanical polishing (CMP) is used to remove film to planarize the substrate before the final thickness is reached or before all removal film is polished. The substrate is then measured for its topography and film thickness. The topography and thickness data are used by the gas cluster ion beam (GOB) etch tool to determine how much film to remove on a particular location. GOB etch enables removal of final layer to meet the requirements of substrate uniformity and thickness target. The mechanisms enable improved planarity to meet the requirement of advanced processing technologies. | 2012-08-30 |
20120217588 | Structure and Method to Enabling A Borderless Contact To Source Regions and Drain Regions Of A Complementary Metal Oxide Semiconductor (CMOS) Transistor - A semiconductor device that includes a gate structure on a channel region of a semiconductor substrate. A first source region and a first drain region are present in the semiconductor substrate on opposing sides of the gate structure. At least one spacer is present on the sidewalls of the gate structure. The at least one spacer includes a first spacer and a second spacer. The first spacer of the at least one spacer is in direct contact with the sidewall of the gate structure and is present over an entire width of the first source region and the first drain region. The second spacer of the at least one spacer extends from the first spacer of the at least one spacer and has a length that covers an entire length of a first source region and a first drain region. | 2012-08-30 |
20120217589 | Semiconductor structure and method for manufacturing the same - A method for manufacturing a semiconductor structure comprises: providing a substrate ( | 2012-08-30 |
20120217590 | Filling Narrow Openings Using Ion Beam Etch - Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening. Furthermore, the method includes performing a first angled etching process to at least partially remove the first layer of first fill material from above the semiconductor device by at least partially removing a first portion of the first layer proximate an inlet of the opening without removing a second portion of the first layer proximate the bottom of said opening, and forming a second layer of second fill material above the semiconductor device by forming the second layer inside the opening and above the first layer. | 2012-08-30 |
20120217591 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND POWER SUPPLY APPARATUS - A semiconductor device includes an electrode material diffusion suppression layer provided either between a gate electrode and a gate insulation film, between Al-containing ohmic electrodes and an Au interconnection, and below the gate electrode and above the Al-containing ohmic electrodes, the electrode material diffusion suppression layer having a structure wherein a first the TaN layer, a Ta layer, and a second the TaN layer are stacked in sequence. | 2012-08-30 |
20120217592 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - It is provided a method for forming a semiconductor device, the semiconductor device comprising a PMOS device, wherein forming the PMOS device comprises: removing the sidewall spacer so as to form a void; and filling the void with an assistant layer, the assistant layer having a first compressive stress. Alternatively, a gate is formed in the PMOS device, the gate having a second compressive stress; the sidewall spacer is removed, so as to form a void; and the void is filled with an assistant layer. A semiconductor device comprising a PMOS device, the PMOS device comprising: an assistant layer, the assistant layer being formed on a semiconductor substrate, the assistant layer surrounding both a gate and a gate dielectric layer, or surrounding the gate and positioned on the gate dielectric layer, wherein the assistant layer has a first compressive stress, or the assistant layer has a first compressive stress and the gate has a second compressive stress, so as to produce a compressive stress in the channel region of the PMOS device. This helps to improve the device performance | 2012-08-30 |
20120217593 | SENSOR MOUNTED IN FLIP-CHIP TECHNOLOGY AT A SUBSTRATE EDGE - The sensor assembly comprises a substrate ( | 2012-08-30 |
20120217594 | MAGNETIC RANDOM ACCESS MEMORY - According to one embodiment, a magnetic random access memory includes a semiconductor substrate, an MTJ element formed from a perpendicular magnetization film and arranged above the semiconductor substrate, and a stress film including at least one of a tensile stress film arranged on an upper side of the MTJ element to apply a stress in a tensile direction with respect to the semiconductor substrate and a compressive stress film arranged on a lower side of the MTJ element to apply a stress in a compressive direction with respect to the semiconductor substrate. | 2012-08-30 |
20120217595 | MAGNETIC LATCH MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A STTMRAM element includes a magnetization layer made of a first free layer and a second free layer, separated by a non-magnetic separation layer (NMSL), with the first and second free layers each having in-plane magnetizations that act on each other through anti-parallel coupling. The direction of the magnetization of the first and second free layers each is in-plane prior to the application of electrical current to the STTMRAM element and thereafter, the direction of magnetization of the second free layer becomes substantially titled out-of-plane and the direction of magnetization of the first free layer switches. Upon electrical current being discontinued to the STTMRAM element, the direction of magnetization of the second free layer remains in a direction that is substantially opposite to that of the first free layer. | 2012-08-30 |
20120217596 | MAGNETIC TUNNEL JUNCTION AND METHOD FOR FABRICATING THE SAME - A magnetic tunnel junction includes a first magnetic layer, a tunnel insulating layer and a second magnetic layer. The first magnetic layer is formed on a substrate. The tunnel insulating layer is formed on the first magnetic layer. The second magnetic layer is formed on the tunnel insulating layer, where the second magnetic layer is shaped to be narrower at a center than at ends. | 2012-08-30 |
20120217597 | DEVICE FOR INCREASING THE MAGNETIC FLUX DENSITY - A device for increasing the magnetic flux density includes a semiconductor body and a first magnetic sensor integrated into the semiconductor body, whereby a housing section, which forms a cavity, is arranged above the sensor on the semiconductor surface and the cavity is filled with a ferromagnetic material and the material comprises a liquid. | 2012-08-30 |
20120217598 | MAGNETIC TUNNEL JUNCTION HAVING COHERENT TUNNELING STRUCTURE - A magnetic tunnel junction includes an amorphous ferromagnetic reference layer having a first reference layer side and an opposing second reference layer side. The first reference layer side has a greater concentration of boron than the second reference layer side. A magnesium oxide tunnel barrier layer is disposed on the second side of the amorphous ferromagnetic reference layer. The magnesium oxide tunnel barrier layer has a crystal structure. An amorphous ferromagnetic free layer is disposed on the magnesium oxide tunnel barrier layer. | 2012-08-30 |
20120217599 | MAGNETIC MEMORY DEVICES WITH THIN CONDUCTIVE BRIDGES - A magnetic memory device includes a free layer and a guide layer on a substrate. An insulating layer is interposed between the free layer and the guide layer. At least one conductive bridge passes through the insulating layer and electrically connects the free layer and the guide layer. A diffusion barrier may be interposed between the guide layer and the insulating layer. The device may further include a reference layer having a fixed magnetization direction on a side of the free layer opposite the insulating layer and a tunnel barrier between the reference layer and the free layer. Related fabrication methods are also described. | 2012-08-30 |
20120217600 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device according to embodiments includes forming a photodiode layer, which is an active region including a photodiode, on a main surface of a first substrate, forming a wiring layer, which includes a wire and a dielectric layer covering the wire, on the photodiode layer, and forming a dielectric film on the wiring layer. The manufacturing method of the semiconductor device according to the embodiments further includes bonding a second substrate to the dielectric film of the first substrate so that a crystal orientation of the photodiode layer matches a crystal orientation of the second substrate. | 2012-08-30 |
20120217601 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - A solid-state imaging device includes a plurality of photoelectric conversion portions each provided to correspond to each of a plurality of pixels in a semiconductor substrate and receiving incident light through a light sensing surface, and a pixel separation portion that is embedded into a trench provided on a side portion of the photoelectric conversion portion and electrically separates the plurality of pixels in a side of an incident surface of the semiconductor substrate into which the incident light enters. The pixel separation portion is formed by an insulation material which absorbs the incident light entering the light sensing surface. | 2012-08-30 |
20120217602 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - A solid-state imaging device includes a plurality of photoelectric conversion portions each provided in a semiconductor substrate and receives incident light through a light sensing surface, and a pixel separation portion provided to electrically separate a plurality of pixels. At least a pinning layer and a light shielding layer are provided in an inner portion of a trench provided on a side portion of each of the photoelectric conversion portions in an incident surface side, the trench includes a first trench and a second trench formed to be wider than the first trench in a portion shallower than the first trench, the pinning layer is formed in an inner portion of the first trench to cover an inside surface of the second trench, and the light shielding layer is formed to bury an inner portion of the second trench at least via the pinning layer. | 2012-08-30 |
20120217603 | SOLID STATE IMAGE PICKUP DEVICE AND CAMERA - A solid state image pickup device which can prevent color mixture by using a layout of a capacitor region provided separately from a floating diffusion region and a camera using such a device are provided. A photodiode region is a rectangular region including a photodiode. A capacitor region includes a carrier holding unit and is arranged on one side of the rectangle of the photodiode region as a region having a side longer than the one side. In a MOS unit region, an output unit region including an output unit having a side longer than the other side which crosses the one side of the rectangle of the photodiode region is arranged on the other side. A gate region and the FD region are arranged between the photodiode region and the capacitor region. | 2012-08-30 |
20120217604 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, ELECTRONIC APPARATUS, AND SEMICONDUCTOR DEVICE - A solid-state imaging device includes a semiconductor layer where a pixel is formed in a pixel region and a semiconductor element is formed in a side opposite to where incident light is incident, a wiring layer provided on the semiconductor layer to cover the semiconductor element, a support substrate provided to oppose the wiring layer in a wiring layer surface opposite to the semiconductor layer, and an adhesion layer which adheres the wiring layer and the support substrate, where the wiring layer includes a pad electrode and an opening is formed so the pad electrode is exposed, a convex section is provided where the pad electrode is formed in at least a wiring layer surface opposing the support substrate or a support substrate surface opposing the wiring layer, and the adhesion layer is formed thinner at the formation portion of the pad electrode than a portion of the pixel region. | 2012-08-30 |
20120217605 | SEMICONDUCTOR DEVICE - A semiconductor device having a solid-state image sensor which can prevent inter-pixel crosstalk more reliably. The device includes: a semiconductor substrate having a main surface; a first conductivity type impurity layer located over the main surface of the substrate; a photoelectric transducer including a first conductivity type impurity region and a second conductivity type impurity region which are joined to each other over the first conductivity type impurity layer; and transistors which configure a unit pixel including the photoelectric transducer and are electrically coupled to the photoelectric transducer. At least part of the area around the photoelectric transducer in a plan view contains an air gap and also has an isolation insulating layer for electrically insulating the photoelectric transducer and a photoelectric transducer adjacent to it from each other. The isolation insulating layer abuts on the top surface of the first conductivity type impurity layer. | 2012-08-30 |
20120217606 | METHOD OF MANUFACTURING SOLID-STATE IMAGING ELEMENT, SOLID-STATE IMAGING ELEMENT AND ELECTRONIC APPARATUS - A method of manufacturing a solid-state imaging element includes: manufacturing an element chip in which photoelectric conversion units are arranged on a main surface side; preparing a base configured using a material with an expansion coefficient greater than the element chip and having an opening of which the periphery of the opening is shaped as a flat surface; expanding the base by heating, mounting the element chip on the flat surface of the base in a state where the opening of the base is covered; and three-dimensionally curving a portion corresponding to the opening in the element chip by cooling and contracting the base in a state where the element chip is fixed to the flat surface of the expanded base. | 2012-08-30 |
20120217607 | WIRING BOARD WITH BUILT-IN IMAGING DEVICE AND METHOD FOR MANUFACTURING SAME - A wiring board with a built-in imaging element includes a substrate having an accommodation portion and a first surface and a second surface on the opposite side of the first surface, an imaging device having a light receiver and positioned in the accommodation portion of the substrate such that the light receiver faces the first surface of the substrate, and a buildup structure formed on the first surface of the substrate and having insulation layers and conductive layers. The buildup structure has an opening portion formed such that the light receiver of the imaging device is exposed from the opening portion of the buildup structure, and the insulation layers in the buildup structure include a first insulation layer formed on the first surface of the substrate. | 2012-08-30 |
20120217608 | THERMOELECTRIC DEVICE USING SEMICONDUCTOR TECHNOLOGY - An integrated thermoelectric device in semiconductor technology comprising a hot side arranged in proximity to a heat source, and a cold side, providing a signal according to the temperature difference between the hot and cold sides. The hot and cold sides are arranged in such a way that their temperatures tend to equal out when the temperature of the heat source varies, i.e. when the sensor is in poor operating conditions. A measuring circuit provides useful information according to a continuously variable portion of the signal from a time when the temperature of the heat source varies. If the temperature of the heat source ceases to vary, the temperatures of the hot and cold sides eventually equal out and the signal is annulled and ceases to vary. The distance between the hot and cold sides can be less than 100 μm. | 2012-08-30 |
20120217609 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device includes a stacked body with a recessed gas passage formed therein, a heater disposed in the stacked body, the heater being exposed on a bottom surface of the gas passage, and a plurality of thermal sensors disposed in the stacked body in such a manner that the plurality of thermal sensors sandwich the heater therebetween in an extending direction of the gas passage, the plurality of thermal sensors being exposed on the bottom surface of the gas passage. An acceleration sensor having a high affinity to the ordinary semiconductor manufacturing process can be provided. | 2012-08-30 |
20120217610 | Bonded Semiconductor Structure With Pyramid-Shaped Alignment Openings and Projections - A bonded semiconductor structure is formed in a method that first forms a female semiconductor structure with pyramid-shaped openings and a male semiconductor structure with pyramid-shaped projections, and then inserts the projections into the openings to align the male semiconductor structure to the female semiconductor structure for bonding. | 2012-08-30 |
20120217611 | INTEGRATED CIRCUITS INCLUDING CONDUCTIVE STRUCTURES THROUGH A SUBSTRATE AND METHODS OF MAKING THE SAME - An integrated circuit includes a substrate having a first surface and a second surface. At least one conductive structure continuously extends through the substrate. At least one sidewall of the at least one conductive structure is spaced from a sidewall of the substrate by an air gap. | 2012-08-30 |
20120217612 | VERTICAL FLOATING BODY STORAGE TRANSISTORS FORMED IN BULK DEVICES AND HAVING BURIED SENSE AND WORD LINES - A semiconductor device comprises a memory area including floating body transistors in the form of pillar structures, which are formed in a bulk architecture. The pillar structures may be appropriately addressed on the basis of a buried word line and a buried sense region or sense lines in combination with an appropriate bit line contact regime. | 2012-08-30 |
20120217613 | Programmable Fuse - According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure. | 2012-08-30 |
20120217614 | POWER CONVERTOR DEVICE AND CONSTRUCTION METHODS - In one aspect, the present invention relates generally to integrated circuit (IC) packages and more specific to some embodiments of IC power convertor technologies. In particular, IC packages that have a high degree of scalability to handle high voltage or current levels, good heat dissipation properties, flexible adaptability to generate packages operable at a wide range of current levels and having a wide range of power adaptability, lends itself to rapid inexpensive prototyping, the ability to adapt various substrates and IC devices to one another without extensive retooling or custom designing of components, as well as other advantages. | 2012-08-30 |
20120217615 | GRAIN BOUNDARY-INSULATED SEMICONDUCTOR CERAMIC, SEMICONDUCTOR CERAMIC CAPACITOR, AND METHOD FOR PRODUCING SEMICONDUCTOR CERAMIC CAPACITOR - A grain boundary-insulated semiconductor ceramic contains a SrTiO | 2012-08-30 |
20120217616 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MOUNTING STRUCTURE - A semiconductor device includes a plurality of functional element chips, an electric connection member joined to two of the functional element chips, a first wire and a resin configured to cover the functional element chips, the electric connection member and the first wire. One of the two functional element chips may be a first semiconductor chip having first and second major surface electrodes facing toward the same direction and a first rear surface electrode facing in a direction opposite to a direction in which the first major surface electrode faces. The electric connection member may be joined to the first major surface electrode. The first wire may be joined to the second major surface electrode. The first wire may include a portion overlapping with the electric connection member in a thickness direction of the first semiconductor chip. | 2012-08-30 |
20120217617 | Semi-Polar Wurtzite Group III Nitride Based Semiconductor Layers and Semiconductor Components Based Thereon - Semipolar wurtzite Group III nitride-based semiconductor layers and semiconductor components based thereon are described. Group III nitride layers have a broad range of applications in electronics and optoelectronics. Such layers are generally grown on substrates such as sapphire, SiC and, more recently, Si(111). The layers obtained are generally polar or have c-axis orientation in the direction of growth. For many applications in the field of optoelectronics, as well as acoustic applications in SAWs, the growth of non-polar or semipolar Group III nitride layers is interesting or necessary. The process according to the invention permits simple and inexpensive growth of polarisation-reduced Group III nitride layers without prior structuring of the substrate. | 2012-08-30 |
20120217618 | Silicon-Germanium Hydrides and Methods for Making and Using Same - The present invention provides novel silicon-germanium hydride compounds, methods for their synthesis, methods for their deposition, and semiconductor structures made using the novel compounds. | 2012-08-30 |
20120217619 | SEMICONDUCTOR DEVICE WITH TRIANGLE PRISM PILLAR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a triangle prism pillar having a first, a second, and a third sidewall surface, a bit line contacted with the first sidewall surface of the pillar, and a word line adjacent to the second sidewall surface of the pillar over the bit line. | 2012-08-30 |
20120217620 | SEMICONDUCTOR APPARATUS - The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR | 2012-08-30 |
20120217621 | STRUCTURE AND METHOD FOR HARD MASK REMOVAL ON AN SOI SUBSTRATE WITHOUT USING CMP PROCESS - A hard mask material is removed from an SOI substrate without using a chemical mechanical polish (CMP) process. A blocking material is deposited on a hard mask material after a deep trench reactive ion etch (RIE) process. The blocking material on top of the hard mask material is removed. A selective wet etching process is used to remove the hard mask material. Trench recess depth is effectively controlled. | 2012-08-30 |
20120217622 | Method for Imparting a Controlled Amount of Stress in Semiconductor Devices for Fabricating Thin Flexible Circuits - Imparting a controlled amount of stress in an assembly comprising a semiconductor circuit on a substrate comprises depositing a tensile stressed metal film stressor layer onto the surface of the circuit. Establishing a fracture region below electrically active regions of the circuit, adhering a foil handle to the assembly and pulling it away from the assembly induces mechanical fracture in the fracture region below the electrically active regions. The mechanical fracture propagates parallel and laterally to the surface of the substrate and below the circuit to produce a thin flexible circuit on a residual substrate. The circuit is under compressive strain that is changed by modifying the stressor layer or residual substrate. Individualized circuits or a circuit may also be defined above the fracture by dividing the circuit into preselected regions with surrounding trenches before fracture. We harvest the circuit(s) by pulling the foil handle away from the assembly. | 2012-08-30 |
20120217623 | INTER-LEVEL DIELECTRIC LAYER, SEMICONDUCTOR DEVICE HAVING SAID INTER-LEVEL DIELECTRIC LAYER AND METHOD FOR MANUFACTURING THE SAME - The present invention discloses an inter-level dielectric layer for a semiconductor device, a method for manufacturing the same and a semiconductor device having said inter-level dielectric layer. The method lies in forming non-interconnected holes within a dielectric layer, and these holes may be filled with porous low-k dielectric material with a much lower dielectric constant, or forming holes within the dielectric layer by filling the upper parts of the holes. The inter-level dielectric layer in such a structure has a much lower dielectric constant, reduces RC delay between devices of integrated circuits and also is easy to integrate; besides, since the holes within the dielectric layer are non-interconnected, they shall not cause change to the dielectric constant of the dielectric material or a short circuit between wires, thus the device shall have better stability and reliability which thence improve performance of the circuit. | 2012-08-30 |
20120217624 | CONNECTION USING CONDUCTIVE VIAS - In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias. | 2012-08-30 |
20120217625 | INTEGRATED CIRCUIT MICRO-MODULE - One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna. | 2012-08-30 |
20120217626 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, includes: placing a seal layer including a connection conductive film on the surface so that the connection conductive film is in contact with an electrode of a semiconductor element and a lead; electrically coupling the electrode and the lead through the connection conductive film; and sealing the semiconductor element by the seal layer. | 2012-08-30 |
20120217627 | PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME - A package structure is provided that includes a metal plate; a semiconductor chip having an active surface, electrode pads disposed on the active surface, conductive bumps disposed on the electrode pads, and an inactive surface opposing the active surface and attached with the metal plate by a thermal conductive adhesive; an encapsulant formed on the metal plate for encapsulating a perimeter of the semiconductor chip, with the active surface of the semiconductor chip being exposed thereon; a first dielectric layer formed on the encapsulant and the active surface of the semiconductor chip, and having wiring trenches for exposing the conductive bumps; and a first wiring layer formed in the wiring trenches of the first dielectric layer and electrically connected to the conductive bumps. The wiring layer, through the electrical connection of the conductive bumps with the semiconductor chip prevents the use of bonding wires as a conductive pathway. | 2012-08-30 |
20120217628 | METAL BUMPS FOR COOLING DEVICE CONNECTION - The mechanisms for forming metal bumps to connect to a cooling device (or a heat sink) described herein enable substrates with devices to dissipate heat generated more efficiently. In addition, the metal bumps allow customization of bump designs to meet the needs of different chips. Further, the usage of metal bumps between the semiconductor chip and cooling device enables advanced cooling by passing a cooling fluid between the bumps. | 2012-08-30 |