35th week of 2012 patent applcation highlights part 17 |
Patent application number | Title | Published |
20120217929 | VIDEO GAME CONTROLLER CHARGING SYSTEM HAVING A DOCKING STRUCTURE - A video game controller charging system is provided. The video game controller charging system includes a base; at least one structure on the base for providing physical support to at least one video game controller while it is being charged; and at least one DC port on the base configured to couple to and provide DC power to a power input port of the at least one video game controller. The video game controller charging system may also include a current detector, a charging status indicator, at least one docking bay, and/or an AC-to-DC converter adapted to convert externally supplied power to the DC power provided to the power input port of at least one video game controller. The base of a charging station may include a recess having at least one electrical contact and a power input for connection to a power supply. | 2012-08-30 |
20120217930 | HOLDER FOR COMPACT ELECTRIC DEVICE - A holder that holds a compact electric device includes a contact fitting that resiliently contacts a contact arranged in a surface of the electric device. A holding element is coupled to the contact fitting and supported by the holder. An urging portion urges the contact fitting from the holder to the contact of the electric device. | 2012-08-30 |
20120217931 | METHOD OF CHARGING A BATTERY ARRAY - The method of charging a battery array performs constant current and constant voltage charging of a battery array while detecting the voltage of each battery. The battery array is a plurality of series connected batteries. The charge method detects the voltage of each battery cell at a prescribed sampling rate. When the voltage of any battery cell exceeds a preset maximum specified voltage, charging power is reduced for constant current, constant voltage charging of the battery array. | 2012-08-30 |
20120217932 | CONNECTING ELECTRICAL STORAGE DEVICES IN PARALLEL - A circuit and a method for connecting a first electrical storage device and a second electrical storage device in parallel is disclosed. The first electrical storage device and the second electrical storage device have in each case a no-load voltage U | 2012-08-30 |
20120217933 | CONTROL APPARATUS FOR SECONDARY BATTERY AND CONTROL METHOD FOR SECONDARY BATTERY - Provided are a control apparatus for a secondary battery and a control method for a secondary battery, which suppress decreases in released power and absorbed power. When a power storage device is requested to release power, a limit for power supply to a power consuming body is set relatively higher, and when the power storage device is requested to absorb power, the limit for power supply to the power consuming body is set relatively lower. When the power storage device is requested to release power, a command value PD for released power is calculated by adding supplied power PS to a requested value PE for released power. When the power storage device is requested to absorb power, a command value PC for charged power is calculated by subtracting the supplied power PS from a requested value PA for absorbed power. | 2012-08-30 |
20120217934 | Charging Management Method and Apparatus for Storage Battery - In order to reasonably adjust charging current of a storage battery according to temperature, realize quick, safe and reliable charging of the storage battery, and effectively prolong the service life of the storage battery, the present invention provides a charging management method and apparatus for a storage battery. The method comprises the following steps: monitoring discharge capacity of a storage battery, and determining discharge depth of the storage battery according to the discharge capacity and total capacity of the storage battery (S | 2012-08-30 |
20120217935 | Circuits and Methods for Automatic Power Source Detection - Embodiments of the present invention include circuits and methods for sensing resistance. In one embodiment the present invention includes a method comprising detecting a voltage at an input of a regulator received from a power adapter, determining a maximum current capability of the power adapter, and charging a battery coupled to an output of the regulator using said detected voltage and said maximum current as inputs to said regulator. In one embodiment, the detected voltage is used to configure a voltage used to determine if or when a voltage received from a power adapter drops below some threshold. | 2012-08-30 |
20120217936 | POWER MANAGEMENT CIRCUIT - The present invention discloses a power management circuit, including: a first voltage regulator, which converts an input voltage to an output voltage; a second voltage regulator coupled between the output voltage and a battery; and a voltage difference control circuit, which receives the output voltage and a voltage of the battery, and outputs a voltage difference control signal to control the first voltage regulator. The voltage difference control circuit includes: a battery reference voltage determination circuit, which generates a battery reference voltage related to the battery voltage, and an error amplifier, which receives the output voltage and the battery reference voltage and generates the voltage difference control signal. | 2012-08-30 |
20120217937 | DRIVE CIRCUIT FOR SWITCHING ELEMENT - A drive circuit is used for driving a switching element. The drive circuit includes a detection unit and an integrated circuit. The detection unit detects a state of a controlled switching element and outputs a voltage signal corresponding to a detection result of the state. The integrated circuit receives the voltage signal via an input terminal for the detection result and controls the switching element based on the received voltage signal. The input terminal includes at least two input terminals that are connected to each other so as to receive the same voltage signal from the detection unit. | 2012-08-30 |
20120217938 | MULTI-PATH POWER FACTOR CORRECTION - A method of multi-path power factor correction includes providing a plurality of energy transfer paths from a voltage-varying input to an output; delivering a first fraction of available input energy to one or more energy storage networks at the input of at least one of the plurality of energy transfer paths; delivering a second fraction of available input energy to the output; and adjusting the first fraction and second fraction for facilitating outputting a substantially constant output and for controlling the energy drawn from the input. | 2012-08-30 |
20120217939 | REFERENCE VOLTAGE STABILIZATION APPARATUS AND METHOD - A reference voltage stabilization apparatus is disclosed, having an input node for receiving a reference voltage, an output node for coupling with a load, a voltage buffer coupled between the input node and the output node, a charge storage device coupled with the output node, and a charging/discharging circuit coupled with the charge storage device for charging or discharging the charge storage device. The voltage buffer and the charged/discharged charge storage device are coupled with the load so that the voltage at the load equals the reference voltage after a period of time. | 2012-08-30 |
20120217940 | DELAY COMPENSATION SYSTEMS AND METHODS FOR DC TO DC CONVERTERS - A control system for a DC to DC converter includes a predicted state generator module, a voltage estimation module, an error module, and a pulse width modulation (PWM) module. During a prior sampling period, the predicted state generator module generates a predicted capacitor voltage and a predicted capacitor current for a current sampling period. The voltage estimation module generates an estimated value of an output voltage of the DC to DC converter during the current sampling period based on the predicted capacitor current, the predicted capacitor voltage, a delay value, and a duty cycle value for the prior sampling period. The error module generates a voltage error value based on difference between a measured value of the output voltage and the estimated value. The PWM module controls the duty cycle of the DC to DC converter based on the voltage error value. | 2012-08-30 |
20120217941 | CONTROL CIRCUIT AND METHOD FOR A RIPPLE REGULATOR SYSTEM - A control circuit and method for a ripple regulator system generate a ripple signal in-phase and synchronous with an inductor current of the ripple regulator system, and extract a ripple information proportional to the amplitude of the ripple signal. The ripple signal is used for triggering control in PWM signal generation to make the ripple regulator system have small ripples and better loop stability simultaneously. The ripple information is used to improve the output offset of the ripple regulator system that is caused by the ripple signal. | 2012-08-30 |
20120217942 | SEMICONDUCTOR CIRCUIT AND SWITCHING POWER SUPPLY APPARATUS - The power supply apparatus realizes a high-speed response, a stable operation, and a low output ripple with low power consumption. The first stage switching regulator receives an input voltage and forms a first voltage. The second stage switching regulator receives the first voltage and forms a second voltage. The second stage switching regulator includes an N-phase (N is two or more) switching regulator, and the first voltage is set to be N times a target value of the second voltage. The input voltage is set to be higher than the first voltage. | 2012-08-30 |
20120217943 | DC/DC Converter Cell and Circuit with Feedback Capability, and Method for its Operation - A DC/DC converter circuit having feedback capability with a first converter device whose two inputs form the inputs of the DC/DC converter circuit and can be connected to a DC voltage source. The DC/DC converter circuit has a DC voltage-coupled second converter device whose outputs form the outputs of the DC/DC converter circuit and can be connected to a DC voltage sink, wherein the second converter device is in the form of a DC/DC converter cell or of a DC/DC converter cell arrangement having two DC/DC converter cells. | 2012-08-30 |
20120217944 | CURRENT DETECTOR OF INDUCTIVE LOAD - A current detector of an inductive load includes: an inductive load | 2012-08-30 |
20120217945 | SYSTEMS AND METHODS FOR FEED-FORWARD CONTROL OF LOAD CURRENT IN DC TO DC BUCK CONVERTERS - A feed-forward control system for load current in a direct current (DC) to DC converter includes a current normalization module, a feed-forward generation module, and a duty cycle generation module. The current normalization module generates a normalized load current by matching a gain of a measured load current to a gain of an inductor current. The feed-forward generation module that generates a load current feed-forward (LCFF) signal based on the normalized load current. The duty cycle generation module generates a duty cycle for the DC to DC converter based on a commanded output voltage and the LCFF signal. | 2012-08-30 |
20120217946 | CONTROL FOR SWITCHING BETWEEN PWM AND PFM OPERATION IN A BUCK CONVERTER - Mode control circuitry is disclosed for use in a buck switching voltage regulator capable of operating in a pulse width modulation (PWM) mode and a pulse frequency modulation (PFM) mode, with the regulator including an inductor having first and second opposite inductor terminals, a first transistor switch connected between the first inductor terminal and a power input terminal and a second transistor switch connected between the first inductor terminal and a circuit common. Current sensing circuitry is provided to sense inductor current through the second switching transistor when the second switching transistor is switched to an ON state and to produce a current sense signal which is integrated over time starting when the second switching transistor is switched to an ON state and to produce a sense signal. The mode switching circuitry switches between the PWM and PFM modes in response to the sense signal. | 2012-08-30 |
20120217947 | DC-DC DOWN-CONVERTER WITH TIME CONSTANT COMPARISON REGULATION SYSTEM - A voltage converter device includes a voltage regulator having a supply terminal for receiving a supply voltage and an output terminal for providing a regulated voltage. A voltage multiplier is for receiving the regulated voltage and providing a boosted voltage higher in absolute value than the regulated voltage. The voltage multiplier includes circuitry for providing a clock signal that switches periodically between the regulated voltage and a reference voltage, and a sequence of capacitive stages that alternately accumulate and transfer electric charge according to the clock signal for generating the boosted voltage from the regulated voltage. The voltage regulator includes a power transistor and a regulation transistor each having a first conduction terminal, a second conduction terminal and a control terminal. | 2012-08-30 |
20120217948 | ENERGY CONVERSION DEVICE AND RELATED DISTRIBUTION METHOD - A method for distributing the total power of an energy conversion device between at least two converters in the energy conversion device is disclosed. The sum of the conversion powers of the converters is the total power of the conversion device. The energy conversion device converts energy between a first electrical entity and a second electrical entity, where the two converters correspond to at least two portions of a ring, the portions being proportional to a predetermined power value of the respective converters thereof, the combination of the at least two portions forming the whole ring. The total power of the conversion device corresponds to an arc of the ring between the positions of a first slider and a second slider moveable around the ring, and the distribution of power between the converters is determined by the positions of the first and second sliders. | 2012-08-30 |
20120217949 | DC VOLTAGE BOOSTER APPARATUS - A DC voltage booster apparatus includes a booster coil, a first capacitor, a switching device, and a second capacitor. The booster coil includes a first end and a second end. The first end of the booster coil is connected to a DC power supply source. The second end of the booster coil is connected to a rectifier diode. The first capacitor is connected between the rectifier diode and a ground. The first capacitor includes a smoothing capacitor. The switching device is disposed between the second end of the booster coil and the ground. The second capacitor is connected in parallel with the rectifier diode. | 2012-08-30 |
20120217950 | Method And Circuit For Catching Excess Current - Data may be encoded onto a direct current power line by modulating the current on that direct current power line. One method of modulating the current is by placing an inductor on the power line and then using a controlled transistor that turns on and turns off. The inductor will ensure that current keeps flowing but the transistor will induce changes in the current pattern. The excess current from when transistor is turned off must be diverted. Furthermore, to create symmetrical current changes, the inductor should be reverse biased. Thus, a circuit is created that sinks the excess current from when the transistor is turned off and used to reverse bias the inductor. | 2012-08-30 |
20120217951 | SUPPLY INDEPENDENT CURRENT REFERENCE GENERATOR IN CMOS TECHNOLOGY - A current reference generator including a current network, a bias network, and a loop amplifier. The current network includes first and second transistors of a first conductivity type and third, fourth and fifth transistors of a second conductivity type. The first, third and fifth transistors are series-coupled between voltage supply lines forming a first current path, and the second and fourth transistors are series-coupled between the supply lines forming a second current path. The control terminals of the first and second transistors are coupled together and the control terminals of the third and fourth transistors are coupled together. The bias network biases the fifth transistor. The loop amplifier is coupled to the current network and is operative to maintain constant current level through the first and second current paths independent of voltage variations of the supply lines and at very low supply voltage. | 2012-08-30 |
20120217952 | CIRCUIT ARRANGEMENT FOR FREQUENCY DETERMINATION - A device and a method for frequency analysis. The frequency of an output signal is divided, and an auxiliary signal with a known frequency is subtracted from the low-frequency signal to define a low-frequency differential signal. The output frequency is determined on the basis of the frequency of the low-frequency differential signal. | 2012-08-30 |
20120217953 | Methods for Sensing Cycle and Phase Difference of AC Signals - The present disclosure discloses methods for sensing a cycle and a phase difference of an AC signal. A method for sensing the cycle of an AC signal may comprise the steps of: determining sample points in waveforms of the AC signal according to a fixed time interval; sampling N continuous sample points as one group of initial samples, in which the product of N and the fixed time interval is larger than or equal to the minimum cycle of the AC signal; sampling a plurality of groups of samples as a plurality of groups of target samples; calculating the cross-correlation between each group of the plurality of groups of target samples and the group of initial samples; and providing the time interval between the group of initial samples and a group of the target samples that has the highest cross-correlation as the cycle of the AC signal. | 2012-08-30 |
20120217954 | CURRENT METER WITH VOLTAGE AWARENESS - The flexibility of a branch circuit monitor is improved by a signal conditioning unit that outputs a voltage in response to an input voltage and which is configurable to output the same range of output voltages in response to input voltages varying over different ranges. | 2012-08-30 |
20120217955 | Circular Vertical Hall Magnetic Field Sensing Element and Method With a Plurality of Continuous Output Signals - A circular vertical Hall (CVH) sensing element and an associated method provide a plurality of output signals from a respective plurality of vertical Hall elements in the CVH sensing element at the same time. | 2012-08-30 |
20120217956 | HIGH RESOLUTION ABSOLUTE ORIENTATION ROTARY MAGNETIC ENCODER - A rotary encoder includes a magnet disposed on a rotational axis of the encoder. The magnet is polarized transversely to the rotational axis. A first magnetic sensor is disposed on the rotational axis proximate the on-axis magnet. A magnet ring is disposed rotationally coaxially with the rotational axis and has a selected diametric distance from the axis. The magnet ring has a plurality of alternatingly polarized magnets. A number of pole pairs in the magnet ring is selected to match an angular resolution of the first magnetic sensor. A second magnetic sensor is disposed proximate the magnet ring. | 2012-08-30 |
20120217957 | ANGULAR POSITION SENSOR AND ASSEMBLY COMPRISING A ROTARY SYSTEM AND SUCH A SENSOR - The invention relates to a sensor ( | 2012-08-30 |
20120217958 | PORTABLE ELECTRONIC DEVICE ADAPTED TO COMPENSATE FOR GYROSCOPE BIAS - According to one aspect, there is provided a method for compensating for gyroscope bias on a portable electronic device having a gyroscope, and at least one of an accelerometer and a magnetometer. The method includes determining a first attitude matrix and a second attitude matrix using data from the accelerometer and the magnetometer, determining a difference between the first attitude matrix and the second attitude matrix, estimating a rotational velocity based on the difference between the first attitude matrix and the second attitude matrix, and compensating for an output from the gyroscope to generate a compensated output that compensates for the gyroscope bias using the estimated rotational velocity. | 2012-08-30 |
20120217959 | ELECTRONIC CIRCUIT, INTEGRATED CIRCUIT, AND MAGNETIC FIELD DETECTION DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - An electronic circuit for detecting magnetism includes: a detection unit in which at least three detection blocks including at least one magnetic field detection element are arranged, wherein by selecting first and second detection blocks from among the at least three detection blocks based on a detection target object, a distance between the first and second detection blocks becomes a distance suitable for the detected target object; a control unit configured to select the first and second detection blocks; and a switching unit configured to connect the selected first and second detection blocks to an output of the electronic circuit based on a control operation of the control unit. | 2012-08-30 |
20120217960 | 3-D MAGNETIC SENSOR - One embodiment of the present invention relates to a magnetic field sensor comprising a squat soft-magnetic body disposed on a surface of a substrate comprising a magnetic sensor array having a plurality of spatially diverse magnetic sensor elements disposed in a predetermined configuration. In the presence of an external magnetic field the squat soft-magnetic body becomes magnetized to generate a reactionary magnetic field. The plurality of magnetic sensor elements are respectively configured to measure a magnetic field value of a superposition of the external magnetic field and the reactionary magnetic field along a first axis (e.g., a z-axis), resulting in a plurality of spatially diverse measurements of the magnetic field component along the first axis. The plurality of spatially diverse measurements may be used to compute magnetic field components of the external magnetic field along a plurality of axes (e.g., x-axis, y-axis, and z-axis). | 2012-08-30 |
20120217961 | MAGNETIC SENSOR - A magnetic sensor includes a plurality of magnetoresistance effect elements and soft magnetic bodies. Each of the magnetoresistance effect elements is formed by stacking a magnetic layer and a non-magnetic layer on a substrate so as to exhibit a magnetoresistance effect. The magnetoresistance effect element is configured such that element portions and electrode layers are alternately disposed. A soft magnetic body is disposed on one and the other sides of each of the element portions in the Y direction, and the soft magnetic bodies are displaced from each other in the X direction. With this arrangement, an external magnetic field applied in the X1 direction is changed into an external magnetic field in the Y direction when passing through the soft magnetic bodies, and the changed external magnetic field flows into the element portions. | 2012-08-30 |
20120217962 | MAGNETIC SENSOR AND MANUFACTURING METHOD THEREFOR - A magnetic sensor having no sensitivity differences between sensitivity axes, and an easy manufacturing method therefor are provided. The method includes a process of forming first stacked films for a magnetoresistive element on a substrate. This element has a sensitivity axis in a certain direction and includes a self-pinned ferromagnetic pinned layer in which first and second ferromagnetic films are antiferromagnetically coupled through an antiparallel coupling layer, a nonmagnetic intermediate layer, and a soft magnetic free layer. The method further includes a process of removing a region of the first stacked films from the substrate. The remaining region of the films includes at least a region to be left to form the element. The method furthermore includes a process of forming second stacked films for a magnetoresistive element, which has a sensitivity axis in a direction different from the certain direction and has the same structure, on the exposed substrate. | 2012-08-30 |
20120217963 | MAGNETIC CORE, CURRENT SENSOR PROVIDED WITH THE MAGNETIC CORE, AND CURRENT MEASURING METHOD - A magnetic core to be used in a current sensor includes a first open end plane, which has a first element holding hole for holding a magnetoelectric conversion element formed therein, and a second open end plane, which has a second element holding hole for holding the magnetoelectric conversion element formed therein, and which faces the first open end plane. With such configuration, the magnetic core can improve the detection sensitivity of the current sensor. | 2012-08-30 |
20120217964 | CURRENT SENSOR, TABLE TAP WITH CURRENT SENSOR, AND MAGNETIC SUBSTANCE COVER FOR CURRENT SENSOR - A current sensor including: a current bar through which a current flows; a magnetic substance core configured to cover at least a part of the current bar; a magnetic field measurement element that measures a magnetic field generated by the current flowing through the current bar; a substrate to which the magnetic substance core and the magnetic field measurement element are fixed; and a magnetic substance cover that covers the magnetic substance core, and aligns the magnetic substance core by being fixed to the substrate; wherein slits corresponding to a width of the current bar are formed on side surfaces of the magnetic substance cover, and the current bar is aligned with the magnetic substance cover by protruding from the slits. | 2012-08-30 |
20120217965 | MAGNETIC RESONANCE TOMOGRAPHY SYSTEM - The present embodiments relate to a magnetic resonance tomography system that includes antenna elements and a controller for selection of the antenna elements. The controller is configured to select antenna elements that surround a field of view of the magnetic resonance tomography system in succession one after the other. | 2012-08-30 |
20120217966 | METHOD FOR COMPENSATING FOR EDDY CURRENT FIELDS IN MAGNETIC RESONANCE IMAGES - A method for compensating for eddy current fields in magnetic resonance images acquired using a magnetic resonance apparatus is provided. A global component of the eddy current fields corresponding to a zeroth order and a first order is compensated globally using a change in control parameters of at least one device of the magnetic resonance apparatus that is suitable for compensating for the global components (e.g., a reference oscillator and/or a gradient coil). In order to correct local higher-order eddy current fields in a volume of interest characterized by a prominent point, the residual eddy current fields remaining following compensation of the global component are developed around the point. Correction values for the control parameters are determined from the zeroth- and/or first-order local components of the development and are taken into account in the control of the magnetic resonance apparatus for magnetic resonance image acquisition. | 2012-08-30 |
20120217967 | MAGNETIC RESONANCE IMAGING APPARATUS - In a magnetic resonance imaging apparatus according to an embodiment, a measuring unit moves a couchtop on which a subject is placed to at least one position of a plurality of positions in an imaging space, adjusts shim coil current value supplied to the shim coil, and measures first shim coil current value when a static magnetic field is uniformized. On the basis of the first shim coil current value and at least one of subject information and an imaging condition, a calculator calculates second shim coil current value position of the plurality of positions and at which the measuring unit has measured no shim coil current value. | 2012-08-30 |
20120217968 | Measurement Of Formation Parameters Using Rotating Directional Em Antenna - A logging tool and method to make subsurface measurements is disclosed, wherein the tool is placed within a borehole penetrating a formation. The tool has a transmitter antenna and a receiver antenna spaced apart along a longitudinal axis of the tool, and at least one of the transmitter or receiver antennas has a dipole moment that is non-coaxial with the longitudinal axis of the tool. The at least one non-coaxial antenna can rotate relative to the other antenna. Energy is transmitted from the transmitter antenna and a signal associated with the transmitted energy is measured at the receiver antenna while the at least one non-coaxial antenna rotates relative to the other antenna. | 2012-08-30 |
20120217969 | LED PROBE - A probe includes a main body and a sensor circuit board. The main body includes a through hole capable of accommodating an LED under test and an accommodation space capable of accommodating the sensor circuit board. The main body is made of opaque material. The sensor circuit board includes a light sensor, a body and a connector. The light sensor is opposite to the through hole. The probe separates the light sensor and the LED under test from ambient light, thereby enhancing the precision of test results. | 2012-08-30 |
20120217970 | PROTECTIVE DEVICE WITH AUTOMATED SELF-TEST - The present invention is directed to an electrical wiring device that includes a test circuit that is configured to generate a recurring simulated fault signal. A detection circuit is configured to generate a test detection signal in response to the recurring simulated fault signal. An end-of-life monitor circuit is configured to generate an end-of-life detection signal if the test detection signal is not generated within a first predetermined period of time. At least one indicator is configured to emit an indication signal in response to the end-of-life detection signal. A response mechanism is configured to decouple the plurality of line terminals from the plurality of load terminals after a second predetermined period of time has elapsed following the end-of-life detection signal. | 2012-08-30 |
20120217971 | NFC SYSTEM PROVIDING BATTERY POWER LEVEL MEASUREMENT FEATURES AND RELATED METHODS - A Near Field Communication (NFC) system may include a battery including a battery casing, at least one battery cell carried by the battery casing, at least one power measurement circuit carried by the battery casing and configured to measure a power level of the at least one battery cell, and a first NFC circuit carried by the battery casing and configured to communicate the power level measurement via NFC communication. The NFC system may further include a mobile wireless communications device including a portable housing, a second NFC circuit carried by the portable housing, and a controller carried by the portable housing and configured to cause the second NFC circuit to receive the power level measurement from the first NFC circuit based upon proximity therewith. | 2012-08-30 |
20120217972 | METHOD FOR SETTING THE PERIOD FOR MEASURING VOLTAGE LEVEL OF A BATTERY IN A MOBILE DEVICE AND MOBILE DEVICE ADAPTED THERETO - A method and apparatus for setting a period for measuring voltage level of a battery are provided. The method includes determining whether the period for measuring the battery voltage level has elapsed, measuring battery voltage level when the period for measuring voltage level has elapsed, extracting and displaying a remaining battery capacity based on the measured battery voltage level, and setting the period for measuring battery voltage level based on the measured battery voltage level. | 2012-08-30 |
20120217973 | System and Method for Flash Bypass - A solar photovoltaic panel is disclosed that includes a photovoltaic cell, a local management unit connected between the cell and a string bus, and a bypass device connected to the cell that is operable to bypass the local management unit when conducting a flash test. The panel preferably further includes a transient detector connected to the cell that is operable to sense an output from the cell having a predetermined transient rise time. The transient detector and the bypass device may be contained within a junction box integrated into the panel and may include the local management unit within the junction box. The transient detector may include a switch connected to a circuit that electrically bypasses the local management unit when the switch is turned on as a result of an output transient rise time less than the predetermined time, thus facilitating a flash test of the photovoltaic panel. | 2012-08-30 |
20120217974 | METHOD AND APPARATUS FOR PROBING A WAFER - A semiconductor wafer resting on a contact element has a spatially distributed force applied to its frontside and an equal and opposing force applied to its backside. The contact element comprises a solid immersion lens (SIL), and has an area less than the area of the wafer, but no less than the larger of the area of an optical collection area and an electrical probe assembly. The equal and opposing forces cause the wafer to conform to the shape of the contact element. Measurements, including electrical testing, optical probing and wafer characterization are performed on the wafer. | 2012-08-30 |
20120217975 | INDUCTIVE MONITORING OF A POWER TRANSMISSION LINE OF AN ELECTRICAL NETWORK - A method includes inductively coupling an electrical sensor to a transmission line associated with a node of an electrical network, and capturing power transmission information associated with the node through the electrical sensor. The method also includes communicating, through an electrical sensing device including the electrical sensor, information associated with a location of a power outage and/or a sub-optimal performance in the node to a processing node and/or a central control node associated with the electrical network. | 2012-08-30 |
20120217976 | CIRCUIT FOR DETECTION OF FAILED SOLDER-JOINTS ON ARRAY PACKAGES - A circuit for detecting changes in resistance at a solder joint connecting a constant voltage source supplying a first voltage and a pin of an array package during operation of the array package includes: a test circuit for applying a second voltage different from the first voltage at a side of the solder joint opposite the constant voltage source; and a monitoring circuit for monitoring an output of the test circuit, wherein the test circuit is configured to output the first voltage when the resistance at the solder joint is below a threshold value, and to output a voltage other than the first voltage when the resistance at the solder joint is above the threshold value, and wherein the monitoring circuit is configured to indicate a failure of the solder joint connection when the voltage other than the first voltage is output by the test circuit. | 2012-08-30 |
20120217977 | TEST APPARATUS FOR PCI-E SIGNALS - A test apparatus includes a sending chip, a receiving chip, first and second peripheral component interconnect express (PCI-E) buses between the sending and receiving chips, first to fourth pads, and first and second terminal resistors. Each pad includes first and second areas laid with copper and a void third area between the first and second areas. The first and second areas of the first and second pads are connected to the first and second PCI-E buses. The first areas of the third and fourth pads are connected to the first and second PCI-E buses. A first end of the first terminal resistor is connected to the second area of the third pad, a second end of the first terminal resistor is grounded. A first end of the second terminal resistors is connected to the second area of the fourth pad, a second end of the second terminal resistor is grounded. | 2012-08-30 |
20120217978 | BACKGROUND NOISE MEASUREMENT AND FREQUENCY SELECTION IN TOUCH PANEL SENSOR SYSTEMS - A touch panel sensor system that can dynamically measure noise and automatically switch to a frequency with minimal noise is described. The touch panel sensor system includes a sensor configured to detect a change in capacitance associated with a touch upon a touch panel. The system also includes a drive module configured to generate a drive signal having a first waveform characteristic (e.g., signal having a periodic waveform characteristic) during a first phase (e.g., sensor phase) and a second drive signal having a second waveform characteristic (e.g., constant voltage signal) during a second phase (e.g., noise detection phase). The first and second drive signals are configured to drive the sensor. The system also includes a measuring module coupled to the sensor that is configured to measure noise having the first waveform characteristic (e.g., periodic waveform characteristic) during the second phase. | 2012-08-30 |
20120217979 | ELECTROMAGNETIC GENERATING DEVICE FOR TESTING ELECTROMAGNETIC COMPATIBILITY - An electromagnetic generating device is used for testing an electromagnetic interference of electronic elements of an electronic device. The electromagnetic generating device includes a power source and a detector. The power source includes a power output. The detector includes a first magnetic guiding portion, a second guiding portion, and an electronic coil. The first magnetic guiding portion is connected to the second magnetic guiding portion. The electronic coil surrounds the second magnetic guiding portion. The electronic coil includes an input coupled to the power output of the power source, and an output being grounded. | 2012-08-30 |
20120217980 | TEST DEVICE AND TEST METHOD FOR MEASURING A PHASE NOISE OF A TEST SIGNAL - A test device for measuring a phase noise of a test signal includes a delayer configured to delay the test signal to provide a delayed test signal, a first combiner, a second combiner, and a phase noise determinator. The first combiner is configured to combine a first signal with the delayed test signal to provide a first combiner output signal. The first signal is based on the test signal or a signal identical to the test signal. The second combiner is configured to combine a second signal with the delayed test signal, wherein the second signal is phase-shifted with respect to the first signal to provide a second combiner output signal. The second signal is based on the test signal. The phase noise determinator is configured to provide phase noise information that depends on the first combiner output signal and the second combiner output signal. | 2012-08-30 |
20120217981 | CIRCUITS, DEVICES AND METHODS HAVING PIPELINED CAPACITANCE SENSING - Capacitance sensing circuits, systems and method can include sample and hold (S/H) circuits that can retain analog values for one set of capacitance sensors, and sequentially convert such analog values into digital values while analog values for another set of capacitance sensors values are generated. | 2012-08-30 |
20120217982 | Capacitive Sensing Button On Chip - An embodiment of an integrated circuit device may comprise an integrated circuit package, a sensor element attached within the integrated circuit package, a capacitance sensor coupled with the sensor element and situated within the integrated circuit package, wherein the capacitance sensor is configured to measure a capacitance of the sensor element, and an output pin positioned at the exterior of the integrated circuit package, wherein the output pin is configured to carry a signal based on the measured capacitance of the sensor element. | 2012-08-30 |
20120217983 | HEAT SPREADER FLATNESS DETECTION - A heat spreader includes a plurality of sensors that indicate that the heat spreader is flat against and in thermal contact with a plurality of chips when the heat spreader is loaded upon a chip stack. One or more nodes within the sensors are connected by electric conductors. The resistances of the conductors may be compared to determine if the nodes within the sensors are relatively flat. Sensor flatness may be indicated to a higher level electronic device such as a visual display. The display may ultimately be viewed by a user to determine whether the heat spreader is flat and in thermal contact with the plurality of chips when the heat spreader is loaded upon the chip stack. | 2012-08-30 |
20120217984 | RESISTANCE-MEASURING CIRCUIT AND ELECTRONIC DEVICE USING THE SAME - A resistance-measuring circuit includes a controller for outputting a PWM signal and further for adjusting the duty cycle of the PWM signal, and a sampling circuit for processing the PWM signal and transmitting the processed PWM signal to the sensor. The sampling circuit samples the signal outputted from the sensor to generate a sampled signal with the voltage thereof changing according to any change in the duty cycle of the PWM signal, and further transmits the sampled signal to the controller. The controller obtains the real-time duty cycle of the PWM signal when the voltage of the sampled signal reaches a threshold voltage, and further calculates the exact resistance of the sensor according to the obtained real-time duty cycle of the PWM signal and the threshold voltage. An electronic device with the resistance-measuring circuit is also provided. | 2012-08-30 |
20120217985 | TEST APPARATUS AND TEST METHOD - There is provided a test apparatus that is capable of applying, to a device under test, a current that rises within a short period. A test apparatus for testing a device under test, includes a current source that supplies the device under test with a current, a dummy load that has an electrical characteristic corresponding to an electrical characteristic of the device under test, and a switching section that switches whether the current source is connected to the dummy load or the device under test. Here, after connecting the current source to the dummy load, the switching section disconnects the current source from the dummy load and connects the current source to the device under test when a voltage applied to the dummy load reaches a voltage within a predetermined range. | 2012-08-30 |
20120217986 | MODULE ASSEMBLY HOLDING WORKBOARD - A module assembly holding workboard is provided and includes a base having a central portion to support a computing module, a first wing at a first side of the central portion to support a first adapter and a second wing at a second side of the central portion to support a second adapter, the first and second adapters being coupled to the computing module via first and second conductive elements and a plurality of routing channel elements fixedly disposed at the first and second wings to retain the first and second conductive elements. | 2012-08-30 |
20120217987 | NON-DESTRUCTIVE DETERMINATION OF THE MOISTURE CONTENT IN AN ELECTRONIC CIRCUIT BOARD USING COMPARISON OF CAPACITANCE MEASUREMENTS ACQUIRED FROM TEST COUPONS, AND DESIGN STRUCTURE/PROCESS THEREFOR - Two test coupons are utilized in an apparatus, method and design process/structure for determining the moisture content in an electronic circuit board (e.g., a printed circuit board (PCB) or panel). The first coupon has a laminate stack-up with voltage planes separated from each other by dielectric material. These voltage planes include etched clearances with neither plated through holes (PTHs) nor drilled holes extending therethrough. The second coupon is substantially identical to the first coupon except that each of the voltage planes of the first coupon includes PTHs extending through etched clearances corresponding to the etched clearances of the first coupon. In one embodiment, an alarm indicating unacceptably high moisture content is generated if a delta capacitance calculated as a difference between capacitance measurements acquired from the respective coupons is greater than a threshold. Preferably, the alarm notifies a user that at least one aqueous process related to PTH formation is implicated. | 2012-08-30 |
20120217988 | FLEXIBLE TEST FIXTURE - A system for testing an electronic circuit board (ECB) having a plurality of test points in a pre-defined arrangement on a measurement device having a plurality of resources includes an interface fixture having a plurality of contact pads arranged in an array on a first surface. The contact pads can be electrically coupled to the plurality of resources of the measurement system according to a pre-defined pattern, where at least two of the contact pads are electrically coupled to one of the plurality of resources in a many-to-one relationship. The system also includes a test fixture removably attached to the first surface of the interface fixture. The test fixture includes an upper probe plate having a plurality of openings and a lower probe plate parallel to the upper probe plate. | 2012-08-30 |
20120217989 | ARCHITECTURE, SYSTEM, METHOD, AND COMPUTER-ACCESSIBLE MEDIUM FOR EXPEDITED-COMPACTION FOR SCAN POWER REDUCTION - Exemplary method, computer-accessible medium, and test configuration can be provided for testing at least one flip-flop. For example, the exemplary test configuration can include at least one scan-out channel having a plurality of regions and a plurality of compactors associated with the plurality of regions. | 2012-08-30 |
20120217990 | TERMINATION CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - The semiconductor device includes a termination control unit configured to generate a termination enable signal and termination resistance information in response to termination activation information, dynamic activation information, normal resistance information, and dynamic resistance information wherein the termination enable signal is activated when a delay lock loop is inactivated, and a termination unit configured to be controlled in response to the termination enable signal and terminate an interface pad by using a resistance value determined by the termination resistance information. | 2012-08-30 |
20120217991 | IMPEDANCE CONTROL CIRCUIT AND INTEGRATED CIRCUIT CHIP INCLUDING THE SAME - A circuit, including a first impedance unit having an impedance value based on a first impedance code and configured to drive a first node coupled with a resistor with a first voltage, a first code generation unit configured to generate the first impedance code so that an impedance value of the first impedance unit and an impedance value of the resistor are at a ratio of X:Y, dummy impedance units that receive the first impedance code and drive a second node with the first voltage, a second impedance unit having an impedance value based on a second impedance code and configured to drive the second node with a second voltage, and a second code generation unit configured to generate the second impedance code so that an overall impedance value of the dummy impedance units and an impedance value of the second impedance unit are at a ratio of X:Y | 2012-08-30 |
20120217992 | OUTPUT CIRCUIT FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE HAVING OUTPUT CIRCUIT, AND METHOD OF ADJUSTING CHARACTERISTICS OF OUTPUT CIRCUIT - To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased. | 2012-08-30 |
20120217993 | SPIN TORQUE MAGNETIC INTEGRATED CIRCUITS AND DEVICES THEREFOR - Spin torque magnetic integrated circuits and devices therefor are described. In an example, a spin torque magnetic device for a logic circuit includes a majority gate structure. An output is coupled to the majority gate structure. Three inputs are also coupled to the majority gate structure. | 2012-08-30 |
20120217994 | Self-reconfigurable memristor-based analog resonant computer - An apparatus which provides a self-reconfigurable analog resonant computer employing a fixed electronic circuit schematic which performs computing logic operations (for example OR, AND, NOR, and XOR Boolean logic) without physical re-wiring and whose components only include passive circuit elements such as resistors, capacitors, inductors, and memristor devices. The computational logic self-reconfiguration process in the circuit takes place as training input signals, which are input causing the impedance state of the memristor device to change. Once the training process is completed, the circuit is probed to determine whether the desired logic operation has been programmed. | 2012-08-30 |
20120217995 | Reconfigurable memristro-based computing logic - An apparatus for reconfigurable computing logic implemented by an innovative memristor based computing architecture. The invention employs a decoder to select memristor devices whose ON/OFF impedance state will determine the reconfigurable logic output. Thus, the resulting circuit design can be electronically configured and re-configured to implement any multi-input/output Boolean logic computing functionality. Moreover, the invention retains its configured logic state without the application of a current or voltage source. | 2012-08-30 |
20120217996 | NONVOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME - A nonvolatile logic circuit includes logic configuration electrodes and input electrodes. The nonvolatile logic circuit is programmable to any one of the logics between the input signals selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR) by changing applied voltages to the logic configuration electrodes. | 2012-08-30 |
20120217997 | NONVOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME - A nonvolatile logic circuit includes logic configuration electrodes and input electrodes. The nonvolatile logic circuit is programmable to any one of the logics between the input signals selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR) by changing applied voltages to the logic configuration electrodes. | 2012-08-30 |
20120217998 | PLD ARCHITECTURE FOR FLEXIBLE PLACEMENT OF IP FUNCTION BLOCKS - In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block. | 2012-08-30 |
20120217999 | Low Voltage Differential Signal Driving Circuit and Digital Signal Transmitter - A low voltage differential signal (LVDS) driving circuit and a digital signal transmitter with the LVDS driving circuit are provided. The LVDS driving circuit includes a positive differential output terminal and a negative differential output terminal and a transition accelerator. A differential output signal is provided by the positive and negative differential output terminals. When the differential output signal transits from low to high, the transition accelerator couples the positive differential output terminal to a high voltage source and couples the negative differential output terminal to a low voltage source. When the differential output signal transits from high to low, the transition accelerator couples the positive differential output terminal to the low voltage source and couples the positive output terminal to the high voltage source. | 2012-08-30 |
20120218000 | SEMICONDUCTOR INTEGRATED CIRCUIT - Each of a plurality of inverters includes: a first transistor having one end connected to a first terminal; and a second transistor having one end connected to a second terminal and the other end connected to the other end of the first transistor. The first transistors included in the inverters located at either odd-number orders or even-number orders counted from an input terminal side of an inverter chain circuit become conductive when a pre-charge signal has a first state to pre-charge the other end of the first transistors, and become non-conductive when the pre-charge signal has a second state. | 2012-08-30 |
20120218001 | Techniques for Phase Detection - A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase. | 2012-08-30 |
20120218002 | SYSTEM AND METHOD FOR ON-CHIP JITTER AND DUTY CYCLE MEASUREMENT - An apparatus for measuring time interval between two edges of a clock signal and includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first incremental delay at each tap to the first edge. Second multi-tap delay module provides a second incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has first and second input terminals. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval. | 2012-08-30 |
20120218003 | Systems and Methods for Current Sensing - Systems and methods for current sensing are described. The described systems and methods utilize a comparator for generating a current sense signal based on comparing an output current of a circuit against a reference current. The reference current is generated by using a current sourcing circuit that is connected to a controllable current source. | 2012-08-30 |
20120218004 | POWER SUPPLY APPARATUS FOR TEST APPARATUS - A first A/D converter converts an analog observed value, which corresponds to a power supply signal supplied to a power supply terminal of a DUT, into a digital observed value. By means of digital calculation processing, a digital signal processing circuit generates a control value that is adjusted such that the digital observed value matches a predetermined reference value. A first D/A converter supplies, via a power supply line to the power supply terminal of the DUT, an analog power supply signal obtained by performing digital/analog conversion of the control value. A load estimating unit applies a test signal containing a predetermined frequency component via the power supply line to a node via which the power supply terminal is to be connected, and generates a control parameter for the digital signal processing circuit according to the test signal and the observed signal. | 2012-08-30 |
20120218005 | Semiconductor Device Having On-Chip Voltage Regulator - A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage. | 2012-08-30 |
20120218006 | INTERNAL VOLTAGE GENERATING CIRCUIT - An internal voltage generating circuit includes a drive signal generating unit, a drive signal controlling unit, and a driving unit. The drive signal generating unit is configured to compare an internal voltage with first and second reference voltages and generate a first pull-up drive signal and a first pull-down drive signal. The drive signal controlling unit is configured to buffer the first pull-up drive signal and the first pull-down drive signal and generate a second pull-up drive signal and a second pull-down drive signal, wherein the second pull-up drive signal and the second pull-down drive signal are deactivated when the first pull-up drive signal and the first pull-down drive signal are activated. The driving unit is configured to drive the internal voltage in response to the second pull-up drive signal and the second pull-down drive signal. | 2012-08-30 |
20120218007 | INPUT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - An input circuit includes a first differential amplification circuit receiving input from a first power source and an output of a first buffer circuit to output to an input of the first buffer circuit, a second differential amplification circuit receiving input from a second external power source and an output of a second buffer circuit to output to an input of the second buffer circuit, a first resistance coupled between the output of the first differential amplification circuit and the input of the first buffer circuit, and a second resistance coupled between the output of the second differential amplification circuit and the input of the first buffer circuit. The first resistance and the second resistance are arranged at symmetric positions to a node on a signal line from the input signal terminal to the output signal terminal. | 2012-08-30 |
20120218008 | TRI-STATE DRIVER CIRCUITS HAVING AUTOMATIC HIGH-IMPEDANCE ENABLING - Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The output stage receives the delayed input signal and further receives the complement of the input signal. The output stage couples an output node to a first voltage in response to a complement of the input signal having a first logic level and couples the output to a second voltage in response to the complement of the input signal having a second logic level. The output stage further decouples the output from the first or second voltage in response to receiving the delayed input signal to provide a high-impedance at the output node. | 2012-08-30 |
20120218009 | CONTROL CIRCUIT OF TRANSISTOR AND METHOD - A control circuit, which controls a transistor including a gate and a field plate, includes: a detecting circuit which detects a driving timing to drive the transistor; a timing controlling circuit which controls a first driving timing to drive the gate and a second driving timing to drive the field plate, in response to the driving timing; and a driving circuit which drives the gate in response to the first driving timing, and drives the field plate in response to the second driving timing. | 2012-08-30 |
20120218010 | SEMICONDUCTOR SWITCH - A semiconductor switch includes: a switch section, provided on a substrate, switching connection states among a plurality of terminals; a positive voltage generator generating a positive potential higher than a supply potential supplied from a power-supply line; a driver, connected to an output line of the positive voltage generator, supplying a control signal to the switch section in response to a terminal switching signal; and a voltage controller, provided on the same substrate, controlling to connect the output line of the positive voltage generator to the power-supply line for a first period corresponding to a change in the connection states, and controlling to disconnect the output line from the power-supply line after the first period. | 2012-08-30 |
20120218011 | GATE DRIVER FOR ENHANCEMENT-MODE AND DEPLETION-MODE WIDE BANDGAP SEMICONDUCTOR JFETS - A DC-coupled two-stage gate driver circuit for driving a junction field effect transistor (JFET) is provided. The JFET can be a wide bandgap junction field effect transistor (JFET) such as a SiC JFET. The driver includes a first turn-on circuit, a second turn-on circuit and a pull-down circuit. The driver is configured to accept an input pulse-width modulation (PWM) control signal and generate an output driver signal for driving the gate of the JFET. | 2012-08-30 |
20120218012 | ON-CHIP POWER-UP CONTROL CIRCUIT - A power-up control circuit utilizes on-chip circuits, multiple voltages, a ring oscillator and counter, and edge and level detection circuits to guarantee reset during power-up conditions and continues the reset state with a variable length counter to guarantee a predictable reset. In addition, a clean start-up after a logical power-down condition is provided. | 2012-08-30 |
20120218013 | NONLINEAR AND CONCURRENT DIGITAL CONTROL FOR A HIGHLY DIGITAL PHASE-LOCKED LOOP - A phase-locked loop circuitry includes an oscillator circuitry having an input and an output. A phase detector circuit is connected to the output of the oscillator circuitry and has outputs thereof. A digital loop filter circuit is connected to the outputs of the phase detector circuitry and has outputs thereof. The outputs of the digital loop filter circuit are coupled, through a summing circuit, to the input of the oscillator circuitry. Values associated with the outputs of the digital loop filter circuit are updated concurrently based upon values associated with the outputs of the phase detector circuitry. One output of the digital loop filter circuitry has a high-pass transfer function. | 2012-08-30 |
20120218014 | Methods and Devices for Multiple-Mode Radio Frequency Synthesizers - Methods and devices provide for determining whether to operate a radio frequency synthesizer in a first mode of operation or a second mode of operation based on a reference frequency signal. The radio frequency synthesizer includes a digitally-controlled oscillator configured to generate an oscillator signal having an output frequency. A digital frequency locked-loop is configured to control the output frequency of the oscillator signal in a first mode of operation based on a first control signal. A digital phase locked-loop is configured to control the output frequency of the oscillator signal in a second mode of operation based on a second control signal. A controller determines whether to operate in the first mode or second mode based on a reference frequency signal. The controller generates the first or second control signal based on the determination of operating in the first or second mode, respectively. | 2012-08-30 |
20120218015 | DUTY CYCLE CORRECTION SYSTEMS AND METHODS - Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the duty cycle adjustor. First and second phase detectors have first inputs coupled to the duty cycle adjustor through an inverter and second inputs coupled to the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter. | 2012-08-30 |
20120218016 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING PLURAL DELAY PATHS AND CONTROLLER CAPABLE OF BLOCKING SIGNAL TRANSMISSION IN DELAY PATH - A semiconductor integrated circuit device, includes a plurality of delay paths which are connected in parallel between synchronous operation circuits operating in synchronism with a clock signal and which enable transmission of a signal, a delay detection unit that detects respective delay times in the plurality of delay paths, and a control unit that selects one delay path from the plurality of delay paths based on a detection result of the delay detection unit, and controls blocking of signal transmission in the delay paths other than the selected one delay path. The control unit selects, as one delay path, a delay path whose delay time is a middle value among the plurality of delay paths. | 2012-08-30 |
20120218017 | Channel Reception Characteristics Through Clock Rate Adjustment - A method, apparatus and system are described for adjusting the frequency of one or more clock signals used by a device. The one or more clock signals are adjusted by a determined amount when a channel quality metric of an RF channel in use by the device indicates a degradation in the reception quality. | 2012-08-30 |
20120218018 | CIRCUIT AND METHOD FOR PROCESSING SIGNALS GENERATED BY A PLURALITY OF SENSORS - An electronic circuit includes a plurality of sensing elements configured to generate a plurality of sensing element signals. The electronic circuit also includes a control signal generator configured to generate a plurality of control signals. The electronic circuit also includes a combining circuit. The combining circuit includes a plurality of switching circuits. Each switching circuit is configured to generate a respective switching circuit output signal being representative of either a non-inverted or an inverted respective one of the plurality of sensing element signals depending upon the first state or the second state of a respective one of the plurality of control signals. The combining circuit also includes a summing circuit coupled to receive the switching circuit output and configured to generate a summed output signal corresponding to a sum of the switching circuit output signals. | 2012-08-30 |
20120218019 | INTERNAL VOLTAGE GENERATING CIRCUIT AND TESTING METHOD OF INTEGRATED CIRCUIT USING THE SAME - An internal voltage generating circuit of a semiconductor device includes a normal reference voltage generating unit configured to generate a normal reference voltage having a constant voltage level without regard to PVT variations, a test reference voltage generating unit configured to generate a test reference voltage by dividing a voltage level between an external power supply voltage and the normal reference voltage at a set ratio, an operation reference voltage generating unit configured to generate an operation reference voltage by selecting one of the normal reference voltage and the test reference voltage in response to a test signal, and an internal voltage generating unit configured to generate an internal voltage whose voltage level is determined based on the level of the operation reference voltage. | 2012-08-30 |
20120218020 | CALIBRATION FOR MIXED-SIGNAL INTEGRATOR ARCHITECTURE - A mixed signal correlator utilizes coherent detection within a capacitance measurement application. In some applications, the mixed signal correlator is used to measure capacitance of a touch screen display. An external capacitor whose capacitance is measured is kept small for improved sensitivity and can be used for a variety of applications having varied integration periods for measurement. The external capacitor is kept small and can be used for varied applications by adjusting the output voltage within a range that is less than the supply voltage, and maintaining a count of the adjustments to later reconstruct an actual output voltage for the integration period. An output is a weighted sum of an analog integrator output and a digital counter output. | 2012-08-30 |
20120218021 | Threshold Computation Apparatus and Threshold Computation Program - A threshold computation apparatus obtains estimated interference power for an uplink from a terminal to a base station; a predetermined communication quality value necessary for the uplink; a maximum value of transmission power of the terminal; and transmission power of the base station for a downlink from the base station to the terminal. The apparatus subtracts a logarithmic value of the maximum value of the transmission power of the terminal from a logarithmic value of the transmission power of the base station for the downlink; adds a logarithmic value of the communication quality value and a logarithmic value of the estimated interference power to a result of the subtraction; and determines a result of the addition to be a logarithmic value of received power at the terminal; and computes a threshold based on the logarithmic value of the received power at the terminal and predetermined conditions. | 2012-08-30 |
20120218022 | Accurate Current Sensing with Heat Transfer Correction - In one embodiment, a current sensing circuit corrects for the transient and steady state temperature measurement errors due to physical separation between a resistive sense element and a temperature sensor. The sense element has a temperature coefficient of resistance. The voltage across the sense element and a temperature signal from the temperature sensor are received by processing circuitry. The processing circuitry determines a power dissipated by the sense element, which may be instantaneous or average power, and determines an increased temperature of the sense element. The resistance of the sense element is changed by the increased temperature, and this derived resistance Rs is used to calculate the current through the sense element using the equation I=V/R or other related equation. The process is iterative to continuously improve accuracy and update the current. | 2012-08-30 |
20120218023 | SYSTEMS AND METHODS FOR INITIALIZING A VOLTAGE BUS AND MEDICAL DEVICES INCORPORATING SAME - Systems, apparatus, and methods are provided for initializing a voltage bus. An exemplary system includes an input interface, a voltage bus, discharge circuitry coupled to the voltage bus, connection circuitry coupled between the voltage bus and the input interface, and a control module coupled to the connection circuitry and the discharge circuitry. The control module activates the discharge circuitry prior to activating the connection circuitry. | 2012-08-30 |
20120218024 | Integrated Circuit Die Stacks With Translationally Compatible Vias - An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die. | 2012-08-30 |
20120218025 | ELECTRONIC COMPONENTS WITH REACTIVE FILTERS - An electronic component comprising a half bridge adapted for operation with an electrical load having an operating frequency is described. The half bridge comprises a first switch and a second switch each having a switching frequency, the first switch and the second switch each including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first switch and the second terminal of the second switch are both electrically connected to a node. The electronic component further includes a filter having a 3 dB roll-off frequency, the 3 dB roll-off frequency being less than the switching frequency of the switches but greater than the operating frequency of the electrical load. The first terminal of the filter is electrically coupled to the node, and the 3 dB roll-off frequency of the filter is greater than 5 kHz. | 2012-08-30 |
20120218026 | METHOD OF GENERATING MULTIPLE CURRENT SOURCES FROM A SINGLE REFERENCE RESISTOR - A differential voltage controlled current source generating one or more output currents is based upon a single external resistor. The differential voltage controlled current source may generate an output current that is proportional to a received differential voltage and a bias current with the use of a single external resistor. The technique may be used to generate multiple accurate and process independent current sources. The current sources may be a zero temperature coefficient (ZTC) current, a proportional to absolute temperature (PTAT) current, or an inversely proportional to absolute temperature (NTAT) current. The output of the current sources may be inversely proportional to the resistance of the external resistor. | 2012-08-30 |
20120218027 | System and Methods for Improving Power Handling of an Electronic Device - There is provided an electronic device that includes a heatsink and a set of IGBTs coupled to the heatsink and configured to deliver power to a field exciter and a battery. The electronic device also includes a temperature sensor disposed in the heatsink and a controller. The controller is configured to receive a temperature reading from the temperature sensor and, based on the temperature reading, determine a junction temperature for at least one of the IGBTs of the set of IGBTs. The controller is also configured to de-rate an output power provided by each of the IGBTs based, at least in part, on the junction temperature. | 2012-08-30 |
20120218028 | CAPACITIVE TOUCH PANEL, TOUCH SENSOR STRUCTURE AND A METHOD FOR MANUFACTURING THE CAPACITIVE TOUCH PANEL - A capacitive touch panel comprises: a substrate and a touch sensor. The touch sensor is disposed on the substrate and includes a plurality of conductive elements, an input bus, and an output bus. The conductive elements are arranged to form a sensing matrix on same surface of the substrate. The input bus is electrically connected to one end of a first axis of the sensing matrix. The output bus is electrically connected to one end of a second axis of the sensing matrix. By this means, the present disclosure can achieve the purpose of simplifying the architecture of the capacitive touch panel. | 2012-08-30 |