35th week of 2022 patent applcation highlights part 54 |
Patent application number | Title | Published |
20220278196 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION THEREOF - Embodiments of the present disclosure relate to forming a nanosheet multi-channel device with an additional spacing layer and a hard mask layer. The additional spacing layer provides a space for an inner spacer above the topmost channel. The hard mask layer functions as an etch stop during metal gate etch back, providing improve gate height control. | 2022-09-01 |
20220278197 | SEMICONDUCTOR DEVICE AND METHOD - An embodiment includes a device having a first set of nanostructures on a substrate, the first set of nanostructures including a first channel region, a second set of nanostructures on the substrate, the second set of nanostructures including a second channel region, a gate dielectric layer wrapping around each of the first and second sets of nanostructures, a first work function tuning layer on the gate dielectric layer of the first set of nanostructures, the first work function tuning layer wrapping around each of the first set of nanostructures, a glue layer on the first work function tuning layer, the glue layer wrapping around each of the first set of nanostructures, a second work function tuning layer on the glue layer of the first set of nanostructures and on the gate dielectric layer of the second set of nanostructures, and a fill layer on the second work function tuning layer. | 2022-09-01 |
20220278198 | Semiconductor Structures and Methods Thereof - In one example aspect, the present disclosure is directed to a device. The device includes an active region on a semiconductor substrate. The active region extends along a first direction. The device also includes a gate structure on the active region. The gate structure extends along a second direction that is perpendicular to the first direction. Moreover, the gate structure engages with a channel on the active region. The device further includes a source/drain feature on the active region and connected to the channel. A projection of the source/drain feature onto the semiconductor substrate resembles a hexagon. | 2022-09-01 |
20220278199 | CONTACT STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD - A device includes a fin extending from a semiconductor substrate, a gate stack over and along a sidewall of the fin, an isolation region surrounding the gate stack, an epitaxial source/drain region in the fin and adjacent the gate stack, and a source/drain contact extending through the isolation region, including a first silicide region in the epitaxial source/drain region, the first silicide region including NiSi | 2022-09-01 |
20220278200 | HYBRID CHANNEL SEMICONDUCTOR DEVICE AND METHOD - A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip. | 2022-09-01 |
20220278201 | SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME - A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, parallel to an upper surface of the substrate on the first portion. | 2022-09-01 |
20220278202 | SEMICONDUCTOR DEVICE - A semiconductor device is provided, including: a semiconductor substrate; a first-conductivity-type drift region provided in the semiconductor substrate; a trench portion provided from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate, and extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the trench portion in an array direction orthogonal to the extending direction; a second-conductivity-type base region provided in the mesa portion above the drift region and in contact with the trench portion; and a second-conductivity-type floating region provided in the mesa portion below the base region, in contact with the trench portion, and provided in at least a part of the mesa portion in the array direction. | 2022-09-01 |
20220278203 | STEEP SLOPED VERTICAL TUNNEL FIELD-EFFECT TRANSISTOR - The current disclosure describes a vertical tunnel FET device including a vertical P-I-N heterojunction structure of a P-doped nanowire gallium nitride source/drain, an intrinsic InN layer, and an N-doped nanowire gallium nitride source/drain. A high-K dielectric layer and a metal gate wrap around the intrinsic InN layer. | 2022-09-01 |
20220278204 | SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE PATTERN - A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen. | 2022-09-01 |
20220278205 | Silicon Carbide Transistor Device - A silicon carbide transistor device includes a silicon carbide semiconductor and a silicon carbide epitaxial layer formed at a top surface of the substrate. A source structure is formed in a top surface of the silicon carbide epitaxial layer and includes a p-well region, an n-type source region and a p-type contact region. A source contact structure is formed over and electrically connected to a top surface of the source structure. A planar gate structure includes a gate dielectric and a gate runner adjacent a p-type channel region. The gate dielectric covers the channel region, at least part of the source structure and at least part of the source contact structure. The gate runner is electrically insulated from the channel region and the source structure and the source contact structure by the gate dielectric and overlaps the channel region. | 2022-09-01 |
20220278206 | BIAXIALLY ORIENTED SiC COMPOSITE SUBSTRATE AND SEMICONDUCTOR DEVICE COMPOSITE SUBSTRATE - A biaxially oriented SiC composite substrate includes a first biaxially oriented SiC layer that contains a threading screw dislocation and a basal plane dislocation, and a second biaxially oriented SiC layer that is formed continuously from the first biaxially oriented SiC layer and that contains 1×10 | 2022-09-01 |
20220278207 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device includes a semiconductor layer, a crystal defect region formed in the semiconductor layer, and an insulating layer formed on the semiconductor layer, composed of an insulator containing silicon, and including, in the insulator, an Si—H bond in which a dangling bond of silicon atom is hydrogen-terminated. | 2022-09-01 |
20220278208 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ASSOCIATED MEMORY DEVICE - A method includes providing a substrate including a channel region, the substrate comprising a two-stage structure having a first surface, a second surface higher than the first surface and a third surface connected between the first surface and the second surface; covering the substrate from a top thereof with an oxide layer; forming a ferroelectric material strip on a topmost surface of the oxide layer; and forming a gate strip covering the ferroelectric material strip and the oxide layer from a top of the gate strip. | 2022-09-01 |
20220278209 | HIGH VOLTAGE FIELD EFFECT TRANSISTORS WITH METAL-INSULATOR-SEMICONDUCTOR CONTACTS AND METHOD OF MAKING THE SAME - A semiconductor structure includes a high voltage field effect transistor having metal-insulator-semiconductor active region contact structures and a low voltage field effect transistor having metal-semiconductor active region contact structures, and at least one of a smaller gate dielectric thickness or a smaller gate length than the high voltage field effect transistor. | 2022-09-01 |
20220278210 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND ELECTRONIC APPARATUS - A semiconductor device includes: a semiconductor layer including a channel layer; a contact region provided at a predetermined size in a thickness direction of the semiconductor layer, and having an impurity concentration that is higher than an impurity concentration of the surrounding semiconductor layer; a gate electrode facing the channel layer, and provided on the semiconductor layer and spaced from the contact region; and an electrode that is in contact with the semiconductor layer and electrically coupled to the channel layer via the contact region, and extending more on at least the gate electrode side than the contact region. | 2022-09-01 |
20220278211 | Protective Liner for Source/Drain Contact to Prevent Electrical Bridging While Minimizing Resistance - One or more active region structures each protrude vertically out of a substrate in a vertical direction and each extend horizontally in a first horizontal direction. A source/drain component is disposed over the one or more active region structures in the vertical direction. A source/drain contact is disposed over the source/drain component in the vertical direction. The source/drain contact includes a bottom portion and a top portion. A protective liner is disposed on side surfaces of the top portion of the source/drain contact but not on side surfaces of the bottom portion of the source/drain contact. | 2022-09-01 |
20220278212 | SEMICONDUCTOR DEVICES HAVING GATE RESISTORS WITH LOW VARIATION IN RESISTANCE VALUES - Power semiconductor devices include a semiconductor layer structure comprising an active area with a plurality of unit cell transistors and an inactive gate pad area, a gate resistor layer on an upper side of the semiconductor layer structure, an inner contact that is directly on the upper side of the gate resistor layer, and an outer contact that is directly on the upper side of the gate resistor layer. The outer contact encloses the inner contact within the inactive gate pad area of the semiconductor device. | 2022-09-01 |
20220278213 | Backside Vias in Semiconductor Device - Methods of forming backside vias connected to source/drain regions of long-channel semiconductor devices and short-channel semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a second transistor structure adjacent the first transistor structure; a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a second dielectric layer on the backside of the second transistor structure; a first contact extending through the first dielectric layer and electrically coupled to a first source/drain region of the first transistor structure; and a second contact extending through the second dielectric layer and electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact. | 2022-09-01 |
20220278214 | SEMICONDUCTOR DEVICES WITH LINERS AND RELATED METHODS - Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region. | 2022-09-01 |
20220278215 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD - A semiconductor storage device includes a first stacked body including first insulating films and first conductive films that are alternately stacked in a first direction. A first columnar body and a second columnar body extend within the first stacked body in the first direction. A second conductive film is provided above the first stacked body, and extends in a third direction intersecting the first direction and the second direction. A third insulator is adjacent to the second conductive film and extends in the third direction. A third conductive film is adjacent to the third insulator and extends in the third direction. A third columnar body is provided on the first columnar body. A fourth columnar body is provided on the second columnar body. A thickness of a third semiconductor portion in the first direction is greater than a thickness of the second conductive film in the first direction. | 2022-09-01 |
20220278216 | THREE-DIMENSIONAL MEMORY DEVICE INCLUDING DISCRETE CHARGE STORAGE ELEMENTS AND METHODS FOR FORMING THE SAME - A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and memory opening fill structures located in the memory opening and including a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner. A subset of the insulating layers a lower insulating sublayer, an upper insulating sublayer overlying the lower insulating sublayer, and a center insulating sublayer located between and in contact with the lower insulating sublayer and the upper insulating sublayer. | 2022-09-01 |
20220278217 | HIGH DIELECTRIC CONSTANT METAL GATE MOS TRANSISTOR AND METHOD FOR MAKING THE SAME - The present application discloses a high dielectric-constant metal gate MOS transistor and a method for making the same. The gate structure is formed by stacking a gate dielectric layer and a metal gate; the top surface of the metal gate is arranged to be lower than the top surface of the zeroth interlayer film, and a first groove is formed on the top surface of the metal gate; a gate top plug formed by stacking a first barrier layer and a first oxide layer is formed in the first groove, the first barrier layer is arranged on the bottom surface and the side surfaces of the first groove, and the first oxide layer fully fills the first groove; and the first barrier layer is made of a material that blocks oxygen ions or fluorine ions from diffusing into the high dielectric-constant layer of the gate structure. | 2022-09-01 |
20220278218 | METAL GATE CAP - The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer. | 2022-09-01 |
20220278219 | METHOD OF FABRICATING DIODE STRUCTURE - A method of manufacturing a diode structure includes forming a first stack on a silicon layer on a substrate. A first sidewall spacer extending along and covering a sidewall of the first stack is formed. The silicon layer is selectively etched to a first predetermined depth, thereby forming a second stack. The remaining silicon layer includes a silicon base. A second sidewall spacer extending along and covering a sidewall of the second stack is formed. The silicon base is selectively etched to form a third stack on the substrate. With the second sidewall spacer as a mask, lateral plasma ion implantation is performed. Defects at the interface between two adjacent semiconductor layers can be reduced by the method. | 2022-09-01 |
20220278220 | MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE - A manufacturing method of the semiconductor structure including the following is provided. Gate structures are formed on a substrate. Each gate structure includes a gate, a first spacer, and a second spacer. The gate is disposed on the substrate. The first spacer is disposed on a sidewall of the gate. The second spacer is disposed on the first spacer. In a region between two adjacent gate structures, the first spacers are separated from each other, and the second spacers are separated from each other. A protective layer is formed between the two adjacent gate structures. The protective layer covers lower portions of the second spacers and exposes upper portions of the second spacers. A part of the upper portions of the second spacers is removed using the protective layer as a mask to enlarge a distance between the upper portions of the second spacers. The protective layer is removed. | 2022-09-01 |
20220278221 | ION IMPLANTATION TO CONTROL FORMATION OF MOSFET TRENCH-BOTTOM OXIDE - Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming an oxide layer over the device structure including within each of the plurality of trenches and over a top surface of the device structure, and implanting a first portion of the oxide layer using an ion implant delivered to the device structure at a non-zero angle of inclination relative to a perpendicular extending from a top surface of the device structure. The method may further include removing the oxide layer from the top surface of the device structure and from a sidewall of each of the plurality of trenches, wherein a second portion of the oxide layer remains along a bottom of each of the plurality of trenches. | 2022-09-01 |
20220278222 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer. | 2022-09-01 |
20220278223 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a p-type semiconductor layer on the buffer layer, a gate electrode on the p-type semiconductor layer, a source electrode and a drain electrode adjacent to two sides of the gate electrode on the barrier layer, a hard mask on the barrier layer and around the p-type semiconductor layer, the source electrode, and the drain electrode, and a passivation layer on the hard mask. | 2022-09-01 |
20220278224 | Etching Back and Selective Deposition of Metal Gate - A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate. | 2022-09-01 |
20220278225 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer. | 2022-09-01 |
20220278226 | Method of Making Nanosheet Local Capacitors and NVM Devices - A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a capacitor or nonvolatile memory cell in a single nanosheet process flow by forming a nanosheet transistor stack ( | 2022-09-01 |
20220278227 | VERTICAL TUNNELING FIELD-EFFECT TRANSISTORS - Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs. | 2022-09-01 |
20220278228 | METHODS OF MANUFACTURE OF ADVANCED WAFER BONDED HETEROJUNCTION BIPOLAR TRANSISTORS - Methods of manufacturing heterojunction bipolar transistors are described herein. An exemplary method can include providing an emitter/base stack comprising a substrate, a base over the substrate, and/or an emitter over the base. The exemplary method further can include forming a collector. The exemplary method also can include wafer bonding the base to the collector. Other embodiments are also disclosed herein. | 2022-09-01 |
20220278229 | SEMICONDUCTOR DEVICE - A doping concentration distribution in an accumulation region in a depth direction of a semiconductor substrate has a maximum portion at which a doping concentration reaches a maximum value, an upper gradient portion in which the concentration decreases from the maximum portion to a base region, a lower gradient portion in which the concentration decreases from the maximum portion to a drift region, and a kink portion at which a differential value of the doping concentration distribution exhibits an extreme value in a region except a region in which the differential value exhibits a maximum value or a minimum value. | 2022-09-01 |
20220278230 | ELECTROSTATIC PROTECTION ELEMENT - An electrostatic protection element including: a first impurity layer of second conductivity type formed on a semiconductor substrate of first conductivity type; a second impurity layer of the first conductivity type formed within the first impurity layer; a first contact layer of the first conductivity type formed in a region within the first impurity layer other than at the second impurity layer; a second and a third contact layer both of the second conductivity type and formed within the second impurity layer; and multilayer wiring connected through a stack structure to the first, the second, and the third contact layer, wherein the stack structure includes at least a first layer wiring connected to each of the first, the second, and the third contact layer, and a second layer wiring connected to the first layer wiring directly above each of the first, the second, and the third contact layer. | 2022-09-01 |
20220278231 | SWITCHING ELEMENT - A switching element includes a semiconductor substrate, a gate insulating film, and a gate electrode that is disposed inside the trench. The semiconductor substrate further includes: an n-type source region, a p-type body region, an n-type drift region, a p-type first electric field reduced region, and a p-type connection region. When a permittivity of the connection region is ε (F/cm), a critical electric field strength of the connection region is Ec (V/cm), an elementary charge is e (C), an area density of p-type impurity when viewed in a plan view of the connection region located below the trench is Q (cm | 2022-09-01 |
20220278232 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes first and second electrodes, first, second, and third semiconductor regions, an insulating part, a conductive part, and a gate electrode. The first semiconductor region is provided on the first electrode and is electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating part is provided on the first electrode. The conductive part is provided in the insulating part and is arranged with the first semiconductor region. The gate electrode is provided in the insulating part. The gate electrode is positioned above the conductive part and is arranged with the second semiconductor region. The second electrode is provided on the third semiconductor region and the insulating part, and is electrically connected to the third semiconductor region. | 2022-09-01 |
20220278233 | DEPFET TRANSISTOR AND METHOD OF MANUFACTURING A DEPFET TRANSISTOR - The invention relates to a DEPFET comprising: a semiconductor substrate ( | 2022-09-01 |
20220278234 | THIN FILM TRANSISTOR - The present disclosure relates to a thin film transistor, and more particularly, to a thin film transistor in which a metal oxide thin film is used as an active layer. A thin film transistor including a gate insulating film and an active layer formed between source and drain electrodes, wherein the active layer includes: a first metal oxide thin film; a second metal oxide thin film provided between the first metal oxide thin film and the gate insulating film and having lower electrical conductivity than the first metal oxide thin film; and a third metal oxide thin film provided between the first metal oxide thin film and the source and drain electrodes and having lower electrical conductivity than the first metal oxide thin film. | 2022-09-01 |
20220278235 | SEMICONDUCTOR DEVICE - A semiconductor device with little characteristic variation is provided. A transistor includes an oxide semiconductor; a first conductor and a second conductor over the oxide semiconductor; a first insulator over the first conductor; a second insulator over the second conductor; a third insulator that is positioned over the first insulator and the second insulator and provided with a first opening overlapping with a region between the first conductor and the second conductor; a fourth insulator positioned over the oxide semiconductor and between the first conductor and the second conductor; and a third conductor over the fourth insulator. A capacitor includes the second conductor; the third insulator provided with a second opening reaching the second conductor; a fifth insulator positioned inside the second opening; and a fourth conductor over the fifth insulator. A plug is positioned to penetrate the first insulator, the third insulator, the first conductor, and the oxide semiconductor. The plug is electrically connected to the first conductor. The first insulator and the second insulator are each formed using a metal oxide including an amorphous structure. | 2022-09-01 |
20220278236 | SEMICONDUCTOR DEVICE - A semiconductor device having favorable characteristics is provided. A semiconductor device having stable electrical characteristics is provided. An island-shaped insulating layer containing an oxide is provided in contact with a bottom surface of a semiconductor layer containing a metal oxide that exhibits semiconductor characteristics. The insulating layer containing an oxide is provided in contact with a portion of the semiconductor layer to be a channel formation region and is not provided under portions to be low-resistance regions. | 2022-09-01 |
20220278237 | SOLID-STATE IMAGE PICKUP UNIT AND ELECTRONIC APPARATUS - A solid-state image pickup unit includes: a substrate made of a first semiconductor; a substrate made of a first semiconductor; a photoelectric conversion device provided on the substrate and including a first electrode, a photoelectric conversion layer, and a second electrode in order from the substrate; and a plurality of field-effect transistors configured to perform signal reading from the photoelectric conversion device. The plurality of transistors include a transfer transistor and an amplification transistor, the transfer transistor includes an active layer containing a second semiconductor with a larger band gap than that of the first semiconductor, and one terminal of a source and a drain of the transfer transistor also serves the first electrode or the second electrode of the photoelectric conversion device, and the other terminal of the transfer transistor is connected to a gate of the amplification transistor. | 2022-09-01 |
20220278238 | METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a substrate having a first active area and a second active area in proximity to the first active area. A trench isolation region is between the first active area and the second active area. A source line region is disposed in the first active area and adjacent to the trench isolation region. An erase gate is disposed on the source line region. A floating gate is disposed on a first side of the erase gate. A first control gate is disposed on the floating gate. A first word line is disposed adjacent to the floating gate and the first control gate and insulated therefrom. A second control gate is disposed on a second side of the erase gate and directly on the trench isolation region. A second word line is disposed adjacent to the second control gate and insulated therefrom. | 2022-09-01 |
20220278239 | SEMICONDUCTOR DEVICE STRUCTURE - A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a first fin structure over the substrate, and a FeFET device over a first region of the substrate. The FeFET includes a first gate stack across the first fin structure. The semiconductor device structure also includes first gate spacer layers alongside the first gate stack, and a ferroelectric layer over the first gate stack. At least a portion of the ferroelectric layer is located between upper portions of the first gate spacer layers and is adjacent to the first gate stack. | 2022-09-01 |
20220278240 | THIN FILM TRANSISTOR, GATE DRIVER INCLUDING THE SAME, AND DISPLAY DEVICE INCLUDING THE SAME - Disclosed are a thin film transistor having an oxide semiconductor layer which is applicable to a flat display device requiring high-speed driving due to ultra-high definition, a gate driver including the same, and a display device including the same. The thin film transistor includes a first oxide semiconductor layer formed of iron-indium-zinc oxide (FIZO) and a second oxide semiconductor layer formed of indium-gallium-zinc oxide (IGZO), thus being capable of exhibiting effects, such as high reliability and high electron mobility. | 2022-09-01 |
20220278241 | Tuning method for active metamaterials using IGZO Schottky diodes - A tuning method for active metamaterials using IGZO Schottky diodes, wherein the IGZO Schottky diode comprises a substrate, a Schottky electrode, amorphous IGZO active layer, and an ohmic electrode from the bottom up. The method comprises steps as follows: (1) Metamaterials are used as the Schottky electrodes, and amorphous IGZO active layers are used to fully cover the capacitive gap structures in the metamaterials; such capacitive structures in the metamaterials are bonded to the amorphous IGZO active layers to form Shottky barriers; (2) The resulting IGZO Schottky diodes from step (1) are used to tune the metamaterials dynamically. | 2022-09-01 |
20220278242 | COMPOSITE ETCH STOP LAYERS FOR SENSOR DEVICES - A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer. | 2022-09-01 |
20220278243 | SOLAR CELL STRING, SOLAR CELL MODULE, SOLAR CELL SHEET AND MANUFACTURING METHOD THEREFOR - A solar cell ( | 2022-09-01 |
20220278244 | PHOTOVOLTAIC GLASS PANE AND METHOD OF PRODUCING A PHOTOVOLTAIC GLASS PANE - A photovoltaic glass pane includes a glass panel, and one or more photovoltaic cells arranged on or in the glass panel. Each of the one or more photovoltaic cells has a light receiving surface to be exposed to light from a light source and being comprised of a semiconducting material having a spectral response to the light. A spectral conversion layer is arranged between the light receiving surface and the light source and is configured to convert photons from the light source of a first energy into photons of a second energy. The spectral response to the photons of the second energy is higher than the spectral response to the photons of the first energy. | 2022-09-01 |
20220278245 | Method For Manufacturing Of A Photovoltaic Module - The present disclosure relates to a method for manufacturing a photovoltaic module. The module includes at least a front layer, a back layer, and a solar cell arrangement encapsulated between the front and back layers. The solar cell arrangement includes a plurality of photovoltaic cells joined to a polymeric foil and electrical connections between the cells. In some embodiments, the photovoltaic cells are crystalline silicon photovoltaic cells. The method includes the steps of providing the solar cell arrangement and then injection molding at least part of the front and/or back layer onto the solar cell arrangement. | 2022-09-01 |
20220278246 | BIFACIAL CRYSTALLINE SILICON SOLAR PANEL WITH REFLECTOR - Bifacial crystalline solar cells and associated solar panel systems are provided. The cells include a p-type crystalline silicon layer and a barrier layer. The panels include at least two rows of cells. The cells in each row are connected to one another in series. The rows are connected in parallel. A reflector is used to reflect light towards the underside of the panel. A long axis of the reflector is arranged to be parallel to the rows of cells. | 2022-09-01 |
20220278247 | LIGHT DETECTING DEVICE, OPTICAL DEVICE AND METHOD OF MANUFACTURING THE SAME - The present disclosure provides a light detecting device. The light detecting devices includes an insulating layer, a silicon layer, a light detecting layer, N first doped regions and M second doped regions. The silicon layer is disposed over the insulating layer. The light detecting layer is disposed over the silicon layer and extends within at least a portion of the silicon layer. The first doped regions have a first dopant type and are disposed within the light detecting layer. The second doped regions have a second dopant type and are disposed within the light detecting layer. The first doped regions and the second doped regions are alternatingly arranged. M and N are integers equal to or greater than 2. | 2022-09-01 |
20220278248 | SUBSTRATE STRUCTURING METHODS - The present disclosure relates to methods and apparatus for structuring a semiconductor substrate. In one embodiment, a method of substrate structuring includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portions of the resist layer are then transferred onto the substrate by micro-blasting to form desired features in the substrate while unexposed or un-ablated portions of the resist layer shield the rest of the substrate. The substrate is then exposed to an etch process and a de-bonding process to remove the resist layer and release the carrier. | 2022-09-01 |
20220278249 | NEAR-INFRARED LIGHT EMITTING SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING SAME - Provided are: a near infrared light-emitting semiconductor element that does not contain any harmful elements and that makes it possible to obtain near infrared light of a stable wavelength in a narrow band regardless of the operating environment; and a method for producing the near infrared light-emitting semiconductor element. GaN is used in the method for producing a near infrared light-emitting semiconductor element, and an active layer added in order to substitute Tm with Ga is formed on GaN in a reaction container at a growth rate of 0.1-30 μm/h without removal from said reaction container using an organometallic vapor phase growth method under temperature conditions of 600-1400° C. in a series of formation steps including formation of a p-type layer and an n-type layer. GaN is used in the near infrared light-emitting semiconductor element, and said near infrared light-emitting semiconductor element includes an active layer sandwiched between an n-type layer and a p-type layer on a substrate. An organometallic vapor phase growth method is used to add the active layer to the GaN in order to substitute Tm with Ga. | 2022-09-01 |
20220278250 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element includes: a first light emitting part comprising: a first n-side nitride semiconductor layer; a first active layer located on the first n-side nitride semiconductor layer; and a first p-side nitride semiconductor layer located on the first active layer; and a second n-side nitride semiconductor layer. A bonding face of the first light emitting part and a bonding face of the second n-side nitride semiconductor layer are directly bonded. At least one void is present between the bonding face of the first light emitting part and the bonding face of the second n-side nitride semiconductor layer. | 2022-09-01 |
20220278251 | LIGHT-EMITTING DIODE CHIP - A light-emitting diode chip is provided and includes: a first doping-type semiconductor layer, a second doping-type semiconductor layer, and a multiple quantum well structure layer formed between the first doping-type semiconductor layer and the second doping-type semiconductor layer. The multiple quantum well structure layer includes multiple first quantum well structures and at least one second quantum well structure stacked in a distance direction of the first and second doping-type semiconductor layers. The first quantum well structures are used to emit first color light, and the at least second well structure is used to emit second color light different from the first color light. A total number of well layer of the at least one second quantum well structure is 1/15˜⅕ of a total number of well layer of the first quantum well structures located between the at least one second quantum well structure and the second doping-type semiconductor layer. | 2022-09-01 |
20220278252 | LIGHT-EMITTING DIODE CHIP AND ULTRAVIOLET LIGHT-EMITTING DEVICE INCLUDING THE SAME - A light-emitting diode (LED) chip includes a substrate and an epitaxial structure. The epitaxial structure includes a first semiconductor layer, an active layer and a second semiconductor layer that are sequentially disposed on the substrate in such order. The second semiconductor layer has a light-emitting surface that is opposite to the active layer and that is formed with a microstructure. The microstructure includes a plurality of first protrusions that are separately disposed on the light-emitting surface, and a plurality of second protrusions that are disposed on the first protrusions and on the light-emitting surface between any two adjacent ones of the first protrusions. | 2022-09-01 |
20220278253 | PIXEL AND DISPLAY DEVICE COMPRISING SAME - A display device includes a substrate including a display area and a non-display area; and at least one pixel provided in the display area, and including a pixel circuit layer. The display element layer includes at least one transistor, and a display element layer including at least one light emitting element emitting light, and a first electrode and a second electrode spaced apart from each other, disposed on the substrate, and each extending in a first direction, and the at least one light emitting element is electrically connected to each of the first and the second electrodes. The first electrode has at least two widths in an extension direction of the first electrode. The second electrode has at least two widths in an extension direction of the second electrode. | 2022-09-01 |
20220278254 | DISPLAY DEVICE USING SEMICONDUCTOR LIGHT-EMITTING ELEMENT, AND MANUFACTURING METHOD THEREFOR - The present invention provides a display device using a semiconductor light-emitting element and a manufacturing method therefor, the display device transferring semiconductor light-emitting elements on a temporary substrate, and then directly implementing, through a stack process, the structure of a wiring substrate on the temporary substrate on which the semiconductor light-emitting elements are arrayed, thereby enabling the semiconductor light-emitting elements and the wiring substrate to be electrically connected. | 2022-09-01 |
20220278255 | Active / Passive Control of Micro LED Performance Through Sidewall Gating - Display structures and methods of operation with micro light emitting diode (LED) sidewall gating are described. In an embodiment, a display structure includes a vertically oriented micro LED mounted on a display substrate, in which the micro LED includes a p-n diode with top and bottom electrode sides, and a sidewall gate electrode spanning a sidewall of the p-n diode where the active layer is included. In various embodiments, a bias may be applied to the sidewall gate electrode while driving the micro LED to deplete a minority carrier concentration from the sidewall of the p-n diode. | 2022-09-01 |
20220278256 | LUMINESCENT NANOSTRUCTURE, PRODUCTION METHOD THEREOF, AND LIGHT EMITTING DEVICE INCLUDING THE SAME - A luminescent nanostructure, a production method for making the luminescent nanostructure, and an electronic device including the luminescent nanostructure. The luminescent nanostructure includes a semiconductor nanocrystal including a Group 13 metal nitride. The luminescent nanostructure has an aspect ratio of greater than or equal to about 1, and an organic compound having an M-O moiety, wherein M is Ti, Al, Zr, Sn, or Si that is bound to at least a portion of the surface of the luminescent nanostructure. | 2022-09-01 |
20220278257 | PHOSPHOR SUBSTRATE, LIGHT EMITTING SUBSTRATE, AND LIGHTING DEVICE - A phosphor substrate having at least one light emitting element mounted on one surface, and includes an insulating substrate, an electrode layer disposed on one surface of the insulating substrate and bonded to the light emitting element, and a phosphor layer which is disposed on one surface of the insulating substrate and includes a phosphor in which a light emission peak wavelength, in a case where light emitted by the light emitting element is used as excitation light, is in a visible light region, in which a surface of the electrode layer facing an outer side in a thickness direction of the insulating substrate is a flat surface, and at least a part of the phosphor layer is disposed around a bonded portion of the electrode layer with the light emitting element. | 2022-09-01 |
20220278258 | METHOD FOR INCREASING THE LIGHT OUTPUT OF MICROLED DEVICECS USING QUANTUM DOTS - Illumination devices based on quantum dot technology and methods of making such devices are described. An illumination device includes a substrate having a plurality of microLEDs, a beam splitter, and a film having a plurality of quantum dots. The beam splitter includes a plurality of layers and is disposed between the substrate and the film having the plurality of quantum dots. | 2022-09-01 |
20220278259 | RADIATION EMITTING SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING A RADIATION EMITTING SEMICONDUCTOR CHIP - A radiation emitting semiconductor chip may include a semiconductor layer sequence having an active region configured to generate electromagnetic radiation, a first dielectric mirror layer arranged above the semiconductor layer sequence, and a second dielectric mirror layer arranged above the first dielectric mirror layer. The first dielectric mirror layer may have at least one first recess. A first current spreading layer may be arranged in the first recess and above the first dielectric mirror layer. The second dielectric mirror layer may have at least one second recess extending up to the first current spreading layer. The first recess may not overlap with the second recess in lateral direction in plan view. Furthermore, a method for producing a radiation emitting semiconductor chip is disclosed. | 2022-09-01 |
20220278260 | DISPLAY APPARATUS USING SEMICONDUCTOR LIGHT EMITTING DEVICE - The present disclosure is applicable to a display apparatus-related technology field, and relates to, for example, a display apparatus using a micro light emitting diode (LED), which is a semiconductor light emitting device. The present invention provides a display apparatus using a light emitting device operated in an active matrix scheme, the display apparatus comprising: a substrate; a pixel area layer configuring multiple pixel areas, which are arranged on the substrate and each of which includes a light emitting area and a pixel transistor area; and an assembly wiring layer including multiple pairs of assembly wires arranged between the substrate and the pixel area layer, wherein each of the pixel areas may include a light emitting area in which a light emitting device is mounted, and a pixel transistor area, which is positioned in a first direction with respect to the light emitting area and in which a thin film transistor for lighting the light emitting device is disposed, and the assembly wires may be arranged in a second direction different from the first direction. | 2022-09-01 |
20220278261 | Method For Making Electronic Device Arrays Using A Temporary Substrate And A Carrier Substrate - A method for making light emitting device LED arrays includes the steps of providing a plurality of LEDs having a desired configuration (e.g., VLED, FCLED, PLED); attaching the LEDs to a carrier substrate and to a temporary substrate; forming one or more metal layers and one or more insulator layers configured to electrically connect the LEDs to form a desired circuitry; and separating the LEDs along with the layered metal layers and insulator layers that form the desired circuitry from the carrier substrate and the temporary substrate. | 2022-09-01 |
20220278262 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND DISPLAY DEVICE INCLUDING THE SAME - A semiconductor device includes a substrate including a first region and a second region that are arranged in a first direction that is parallel to an upper surface of the substrate; a separation layer provided on the first region of the substrate; a high electron mobility transistor (HEMT) device overlapping the separation layer in a second direction that is perpendicular to the upper surface of the substrate; a light-emitting device provided on the second region of the substrate; and a first insulating pattern covering a side surface of the HEMT device, wherein the first insulating pattern overlaps the separation layer in the second direction. | 2022-09-01 |
20220278263 | THERMOELECTRIC CONVERSION MATERIAL, THERMOELECTRIC CONVERSION ELEMENT, THERMOELECTRIC CONVERSION MODULE, AND OPTICAL SENSOR - A thermoelectric conversion material is represented by a composition formula Ag | 2022-09-01 |
20220278264 | Thermal Radiation Sensor Comprising an Ionic Conductor - One or more devices, systems, apparatuses, methods of manufacture and/or methods of use to facilitate thermal sensing in a field related to thermal radiation are envisioned. In one embodiment, an ionic thermoelectric thermal radiation sensor, comprises a substrate, an ionic thermoelectric sensing unit arranged on the substrate and comprising ionically conductive and electrically insulating material, wherein the ionic thermoelectric sensing unit is a voltage-producing unit having first and second surfaces spaced apart from and disposed opposite to one other, wherein the ionic thermoelectric sensing unit produces voltage via thermal diffusion of ions or via the Soret effect under a temperature difference between the first and second surfaces, a thermal radiation absorber that generates heat when exposed to thermal radiation, and one or more electrical connectors that connect the first and second surface. | 2022-09-01 |
20220278265 | GRAPHENE/DOPED 2D LAYERED MATERIAL VAN DER WAALS HETEROJUNCTION SUPERCONDUCTING COMPOSITE STRUCTURE, SUPERCONDUCTING DEVICE, AND MANUFACTURING METHOD THEREFOR - A graphene/doped 2D layered material Van der Waals heterojunction superconducting composite structure, a superconducting device and a manufacturing method therefor, which relate to the technical field of superconducting materials. Said structure includes: a (2n+1)-layered structure formed by graphene layers and doped 2D layered materials which are alternately provided. An outer layer of the layered structure is the graphene layer, n is an integer between 1 to 50, a superconducting region is formed by a region in which the graphene perpendicularly overlaps the doped 2D layered material, and the graphene layers and the doped two-dimensional layered materials are self-assembled into one piece by means of a Van der Waals force. | 2022-09-01 |
20220278266 | LAMINATED PIEZOELECTRIC ELEMENT - A laminated piezoelectric element has excellent suppression effect on characteristics deterioration caused by a pyroelectric effect. Inside an element main body are a first internal electrode, a piezoelectric layer, and a second internal electrode that has different polarity from the first internal electrode, which are repeatedly layered a plurality of times along the lamination direction. A first external electrode is formed on a first side surface of the element main body. A second external electrode is formed on a second side surface of the element main body. A resistance layer connected to the internal electrodes is formed in at least part of a third side surface of the element main body in which the internal electrodes are exposed. An insulating layer is formed on a third side of the element main body so as to cover the resistance layer. | 2022-09-01 |
20220278267 | SOUND PRESSURE-ELECTRICAL SIGNAL CONVERSION DEVICE AND CONVERSION METHOD FOR SAME - Provided is a sheet-shape electrostatic sound pressure-electrical signal conversion device that is three-dimensionally deformable and has a low drive voltage. | 2022-09-01 |
20220278268 | PIEZOELECTRIC VIBRATION ELEMENT, PIEZOELECTRIC RESONATOR UNIT, AND ELECTRONIC DEVICE - A piezoelectric vibration element includes a piezoelectric piece having a main surface; an excitation electrode disposed on the main surface of the piezoelectric piece; and a connection electrode disposed on the main surface of the piezoelectric piece and electrically connected to the excitation electrode, wherein when the main surface of the piezoelectric piece is viewed in a plan, the piezoelectric piece has a through-hole in an area between the excitation electrode and the connection electrode, and wherein an internal wall of the through-hole located closer to the excitation electrode has at least four slopes. | 2022-09-01 |
20220278269 | METHOD FOR MANUFACTURING A HYBRID STRUCTURE - A method for manufacturing a hybrid structure comprising an effective layer of piezoelectric material having an effective thickness and disposed on a supporting substrate having a substrate thickness and a thermal expansion coefficient lower than that of the effective layer includes: a) a step of providing a bonded structure comprising a piezoelectric material donor substrate and the supporting substrate, b) a first step of thinning the donor substrate to form a thinned layer having an intermediate thickness and disposed on the supporting substrate, the assembly forming a thinned structure; c) a step of heat treating the thinned structure at an annealing temperature; and d) a second step, after step c), of thinning the thinned layer to form the effective layer. The method also comprises, prior to step b), a step a′) of determining a range of intermediate thicknesses that prevent the thinned structure from being damaged during step c). | 2022-09-01 |
20220278270 | MAGNETORESISTIVE ELEMENT HAVING AN ADJACENT-BIAS LAYER AND A TOGGLE WRITING SCHEME - A magnetoresistive element using combined spin-transfer-torque controlled magnetic bias and VCMA effects comprising a free layer and an adjacent-bias layer separated by a nonmagnetic spacing layer, wherein the free layer has an interfacial perpendicular magnetic anisotropy and a variable magnetization direction substantially perpendicular to a film surface, the adjacent-bias layer has a perpendicular magnetic anisotropy and a variable magnetization direction substantially perpendicular to a film surface, and the perpendicular anisotropy of the free layer is sufficiently higher than that of the adjacent-bias layer such that the critical switching current to reverse the free layer magnetization direction is at least 3 times as high as the critical switching current to reverse the adjacent-bias layer magnetization direction. Further, there is provided a toggle writing method of the perpendicular magnetoresistive element comprises: applying a first write pulse having a first voltage magnitude and a first pulse width to reverse the adjacent-bias layer magnetization direction to be anti-parallel to the free layer magnetization direction by spin-transfer-torque effect, and applying a second write pulse having a second voltage magnitude and a second pulse width to reverse the free layer magnetization direction to be parallel to the adjacent-bias layer magnetization direction by voltage-controlled magnetic anisotropy effect under the magnetic dipole bias field from the adjacent-bias layer. | 2022-09-01 |
20220278271 | MAGNETORESISTANCE EFFECT ELEMENT - In the magnetoresistance effect element according to one aspect, the metal oxide constituting the metal oxide layer has the ratio of oxygen higher than the total ratio of metal when the composition is expressed in the stoichiometric composition; and the resistivity of the metal oxide layer is higher than that of the tunnel barrier layer. | 2022-09-01 |
20220278272 | MAGNETORESISTANCE EFFECT ELEMENT - A magnetoresistance effect element includes a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer that is interposed between the first ferromagnetic layer and the second ferromagnetic layer. The tunnel barrier layer is a stacked body including one or more first oxide layers having a spinel structure and one or more second oxide layers having a spinel structure with a composition which is different from a composition of the first oxide layer. | 2022-09-01 |
20220278273 | VERTICAL VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF OPERATION IN THE SAME - A vertical variable resistance memory device includes gate electrodes and a pillar structure. The gate electrodes are spaced apart from one another on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate. The pillar structure extends in the vertical direction through the gate electrodes on the substrate. The pillar structure includes a vertical gate electrode extending in the vertical direction, a variable resistance pattern disposed on a sidewall of the vertical gate electrode, and a channel disposed on an outer sidewall of the variable resistance pattern. The channel and the vertical gate electrode contact each other. | 2022-09-01 |
20220278274 | ELECTRICAL MEMRISTIVE DEVICES BASED ON BILAYER ARRANGEMENTS OF HFOy AND WOx - An electrical memristive device has a layer structure. The later structure comprises two electrodes and a bilayer material arrangement that connects the two electrodes. The bilayer material arrangement may, for example, be sandwiched by the two electrodes, in direct contact therewith. The bilayer material arrangement includes an HfO | 2022-09-01 |
20220278275 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device includes a semiconductor memory. A method for fabricating the electronic device includes forming a first memory cell extending vertically from a surface of substrate and having a first upper portion that protrudes laterally, forming a second memory cell extending vertically from the surface of the substrate and having a second upper portion that protrudes laterally towards the first upper portion, and forming a liner layer over the first and second memory cells, the liner layer having a first portion disposed over the first upper portion and a second portion disposed over the second upper portion, the first and second portions of the liner layer contacting each other. | 2022-09-01 |
20220278276 | A Resistive Memory Device Structure Based on Stacked Layers Of Nanocrystalline TMDCs - Herein provided is a multilayered structure including one or more nanocrystalline layers each comprising a transition metal dichalcogenide, one or more substantially amorphous electrically insulating layers each comprising a transition metal oxide, wherein the transition metal oxide comprises a transition metal which is identical to the transition metal of the transition metal dichalcogenide, wherein the one or more nanocrystalline layers and the one or more substantially amorphous electrically insulating layers are formed in an alternating manner, and wherein each of the one or more nanocrystalline layers is formed adjacent to the substantially amorphous insulating layer. A resistive memory device comprising the multilayered structure and a process of fabricating the multilayered structure are also disclosed herein. | 2022-09-01 |
20220278277 | PREPARATION METHODS FOR ORGANIC FUNCTIONAL LAYERS OF LIGHT-EMITTING DEVICE AND PREPARATION METHODS FOR DISPLAY PANEL - A method of preparing organic functional layers of light-emitting device including: forming a plurality of holding portions in a pixel definition layer on a substrate; forming a plurality of ink droplets in the holding portions, the ink droplets including a first solvent, a second solvent and one or more solutes, a first saturated vapor pressure of the first solvent being higher than a second saturated vapor pressure of the second solvent, a solubility of the solutes in the first solvent being less than a solubility of the solutes in the second solvent, and a first affinity of lower parts of side walls of the holding portions for the first solvent is greater than a second affinity of the lower parts of the side walls of the holding portions for the second solvent; adjusting a vacuum degree of vacuum drying equipment to a first vacuum degree below the first saturated vapor pressure and above the second saturated vapor pressure to completely remove the first solvent; and adjusting the vacuum degree of the vacuum drying equipment to a second vacuum degree below the saturated vapor pressure of the second solvent to completely remove the second solvent. | 2022-09-01 |
20220278278 | ORGANIC MOLECULES FOR OPTOELECTRONIC DEVICES - The invention relates to an organic molecule, in particular for the application in optoelectronic devices. According to the invention, the organic molecule has a structure of formula I: | 2022-09-01 |
20220278279 | LIGHT-EMITTING DEVICE INCLUDING HETEROCYCLIC COMPOUND AND ELECTRONIC APPARATUS INCLUDING THE LIGHT-EMITTING DEVICE - An electronic device that includes a light-emitting device includes: a first electrode; a second electrode facing the first electrode; an interlayer between the first electrode and the second electrode and including an emission layer; and a heterocyclic compound of Formula 1: | 2022-09-01 |
20220278280 | Peel-off Patterning Method for Fabrication of Organic Optoelectronic Devices - A method of fabricating an organic optoelectronic device comprises positioning a patterning layer over a substrate, etching the patterning layer using a photolithographic process to create an etched patterning layer, positioning a layer of an organic material over the etched patterning layer, and removing at least a portion of the etched patterning layer and at least a portion of the layer of the organic material to create a patterned organic layer over the substrate. | 2022-09-01 |
20220278281 | METHOD FOR PRODUCING CHARGE TRANSPORTING THIN FILM - This method for producing a charge transporting thin film, wherein a charge transporting varnish containing a charge transporting substance, an electron accepting dopant substance containing at least one substance selected from among naphthalene sulfonates and benzene sulfonates, and an organic solvent is applied onto a substrate and is subsequently heated at 100-180° C. so that the organic solvent is evaporated therefrom, is capable of efficiently producing a charge transporting thin film which is able to be used as a hole collecting layer that enables the achievement of an organic photoelectric conversion element having high photoelectric conversion efficiency. | 2022-09-01 |
20220278282 | ORGANIC LIGHT EMITTING DIODE AND ORGANIC LIGHT EMITTING DEVICE INCLUDING THE SAME - The present disclosure relates to an OLED that includes a first electrode; a second electrode facing the first electrode; a first emitting material layer including a first host being an anthracene derivative and a first dopant being a pyrene derivative and positioned between the first and second electrodes; and a first electron blocking layer including an electron blocking material of an amine derivative including a polycyclic aryl group and positioned between the first electrode and the first emitting material layer, wherein at least one of hydrogen atoms in the anthracene derivative and the pyrene derivative is deuterated. | 2022-09-01 |
20220278283 | ORGANIC ELECTROLUMINESCENT ELEMENT AND ELECTRONIC DEVICE - The compound represented by formula (1): | 2022-09-01 |
20220278284 | COMPOUND FOR ORGANIC ELECTRONIC ELEMENT, ORGANIC ELECTRONIC ELEMENT USING THE SAME, AND AN ELECTRONIC DEVICE THEREOF - Provided herein are an organic electronic compound capable of improving luminous efficiency, stability and lifespan of an electronic device, an organic electronic element employing the same, and an electronic device thereof. | 2022-09-01 |
20220278285 | COMPOUND FOR ORGANIC ELECTRIC ELEMENT, ORGANIC ELECTRIC ELEMENT COMPRISING THE SAME, AND ELECTRONIC DEVICE THEREOF - Provided are a compound represented by Formula 24, an organic electric element comprising a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode and comprising the compound of Formula 24, and an electronic device thereof, the element and device having improved driving voltage, luminous efficiency and life time from the employment of the compound. | 2022-09-01 |
20220278286 | COMPOUND, MATERIAL FOR ORGANIC ELECTROLUMINESCENT DEVICES, ORGANIC ELECTROLUMINESCENT DEVICE, AND ELECTRONIC APPARATUS - Provided are: a compound capable of further improving the performance of organic EL devices, an organic electroluminescent device having more improved device performance, and an electronic apparatus including such an organic electroluminescent device. Precisely provided are: a compound represented by the following formula (1): | 2022-09-01 |
20220278287 | ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES - Novel iridium complexes containing phenylpyridine and pyridyl aza-benzo fused ligands are described. These complexes are useful as light emitters when incorporated into OLEDs. | 2022-09-01 |
20220278288 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE DISPLAY DEVICE - A method of manufacturing a display device includes providing an inorganic layer on a carrier substrate, providing a first flexible substrate on the inorganic layer, providing a first shielding layer including a metal on the first flexible substrate, providing a first barrier layer on the first shielding layer, and providing a thin film transistor layer on the first barrier layer. The inorganic layer includes at least one material selected from silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiOxNy), and a thickness of the inorganic layer is in a range from about 10 Å to about 6000 Å. | 2022-09-01 |
20220278289 | Flexible Substrate, Manufacturing Method for Flexible Substrate and Display Device - The present disclosure provides a flexible substrate, the flexible substrate is divided into a display region, a binding region on a side of the display region, a to-be-bent region between the display region and the binding region, two transition regions between the to-be-bent region and the display region and between the to-be-bent region and the binding region respectively; the transition regions comprise a plurality of transition sub-regions arranged in a first direction, the first direction is a direction from the display region to the binding region; the flexible substrate comprises a flexible base and a back film disposed on the flexible base, a portion of the back film is located in the transition regions; in any one of the transition regions, the amount of distribution per unit area of the back film in each of the transition sub-regions gradually decreases in a direction gradually approaching the to-be-bent region. | 2022-09-01 |
20220278290 | MULTI-JUNCTION PHOTOVOLTAIC DEVICE - A multi-junction photovoltaic device comprises a first sub-cell and a second sub-cell, the second sub-cell overlying the first sub-cell such that incident light passes through the second sub-cell before the first sub-cell. The light-receiving surface of the second sub-cell comprises a layer of a transparent conductive material and one or more metal tracks extending in a first direction and in contact with the layer of transparent conductive material. A layer of electrically insulating material is provided on the light receiving surface of the second sub-cell located under one end of the one or more metal tracks at an edge of the device, and an electrically conductive pad is provided over the layer of electrical insulator and in electrical contact with the one or more metal tracks to provide electrical contact to an external circuit. | 2022-09-01 |
20220278291 | DISPLAY PANEL AND MANUFACTURING METHOD THEREFOR, AND DISPLAY APPARATUS - Provided are a display panel and a manufacturing method therefor, and a display apparatus. The display panel includes a plurality of sub-pixels of at least two colors and further comprises: a base substrate; a first electrode on the base substrate; an electron transport layer at the side of the first electrode facing away from the base substrate; a quantum dot light-emitting layer at the side of the electron transport layer facing away from the base substrate; and a second electrode at the side of the quantum dot light-emitting layer facing away from the base substrate. Materials of the quantum dot light-emitting layer of the sub-pixels of different colors are different. The electron transport layer is of an alloy heterostructure at least composed of a metal oxide and a metal chalcogenide. Contents of the metal chalcogenide in the alloy heterostructure at positions of the sub-pixels of different colors are different. | 2022-09-01 |
20220278292 | LIGHT-EMITTING DEVICE, DISPLAY DEVICE, LIGHT-EMITTING APPARATUS, ELECTRONIC DEVICE, AND LIGHTING DEVICE - A light-emitting device with high emission efficiency is provided. The light-emitting device includes a first electrode, a second electrode, and an EL layer positioned between the first electrode and the second electrode. The EL layer includes at least a light-emitting layer, a first layer, a second layer, and a third layer. The first layer is positioned between the first electrode and the light-emitting layer. The third layer is positioned between the first layer and the light-emitting layer. The second layer is positioned between the first layer and the third layer. The first layer includes a first organic compound. The second layer includes a second organic compound. The third layer includes a third organic compound. The ordinary refractive index of the second organic compound is higher than the ordinary refractive indices of the first organic compound and the third organic compound. | 2022-09-01 |
20220278293 | ORGANIC ELECTROLUMINESCENT DEVICE AND ARRAY SUBSTRATE - An organic electroluminescent device comprises an anode, a first organic light emitting layer, an exciton control layer, a second organic light emitting layer, and a cathode that are successively stacked, wherein the first organic light emitting layer comprises a hole transport type host material and a first doped material; the exciton control layer is provided on the surface of the first organic light emitting layer away from the anode; the exciton control layer comprises a first hole transport material and a first electron transport material; the second organic light emitting layer comprises an electron transport type host material and a second doped material; the cathode is provided on the side of the second organic light emitting layer away from the anode; and one of the first doped material and the second doped material is a fluorescence-doped material, and the other is a phosphorescence-doped material. | 2022-09-01 |
20220278294 | LIGHT-EMITTING DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME - Provided are a light-emitting device and an electron apparatus including the same. The light-emitting device includes a first electrode, a second electrode facing the first electrode, and an interlayer disposed between the first electrode and the second electrode. The interlayer includes an emission layer and an electron transport region, the emission layer includes a host and a dopant, the electron transport region is disposed between the emission layer and the second electrode and includes a first electron transport layer and a second electron transport layer, the first electron transport layer includes a first electron-transporting material, a lowest excitation triplet (T | 2022-09-01 |
20220278295 | LIGHT-EMITTING DEVICE INCLUDING FUSED CYCLIC COMPOUND, ELECTRONIC APPARATUS INCLUDING THE LIGHT-EMITTING DEVICE, AND THE FUSED CYCLIC COMPOUND - A light-emitting device having a fused cyclic compound includes: a first electrode; a second electrode facing the first electrode; an interlayer between the first electrode and the second electrode and including an emission layer; and a fused cyclic compound of Formula 1: | 2022-09-01 |