37th week of 2015 patent applcation highlights part 54 |
Patent application number | Title | Published |
20150255396 | SEMICONDUCTOR DEVICE AND FORMATION THEREOF - A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate. The metal plug has a contact bottom surface that is substantially convex. The substantially convex contact bottom surface has an increased contact area as compared to a contact bottom surface of a metal plug that is not substantially convex. The increased contact area decreases a resistance of the metal plug. The increased contact area requires a smaller deposition amount to form a metal plug seed layer of the metal plug than a semiconductor device with a smaller contact area. A smaller deposition amount reduces an overhang of the deposited metal plug seed layer material. A reduced overhang of the deposited metal plug seed layer material reduces pitting in a metal plug formed from the deposited metal plug seed layer material. | 2015-09-10 |
20150255397 | DOPING OF COPPER WIRING STRUCTURES IN BACK END OF LINE PROCESSING - A method of forming a metal interconnect structure includes forming a copper line within an interlevel dielectric (ILD) layer; directly doping a top surface of the copper line with a copper alloy material; and forming a dielectric layer over the ILD layer and the copper alloy material; wherein the copper alloy material serves an adhesion interface layer between the copper line and the dielectric layer. | 2015-09-10 |
20150255398 | SELECTIVE LOCAL METAL CAP LAYER FORMATION FOR IMPROVED ELECTROMIGRATION BEHAVIOR - A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines. | 2015-09-10 |
20150255399 | WIRE AND SEMICONDUCTOR DEVICE - A wire of an embodiment includes: a substrate; a metal film provided on the substrate; a metal part provided on the metal film; and graphene wires formed on the metal part, wherein the graphene wire is electrically connected to the metal film, and the metal film and the metal part are formed using different metals or alloys from each other. | 2015-09-10 |
20150255400 | Method for Forming Alignment Marks and Structure of Same - A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks. | 2015-09-10 |
20150255401 | ELECTRONIC COMPONENT MODULE - An electronic component module according to the present invention is provided with an electronic component, a sealing resin that seals the electronic component, and a metal film that covers a surface of the sealing resin. The sealing resin contains filler of oxide particles. Part of the filler in the sealing resin is exposed to the surface of the sealing resin. At least the part of the filler exposed to the surface of the sealing resin includes a crack that extends from an exposed surface of the filler into an inner portion. The crack is filled with at least one metal that constitutes the metal film. | 2015-09-10 |
20150255402 | PACKAGED RADIO-FREQUENCY MODULE HAVING WIREBOND SHIELDING - According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds. The wirebond cage forms an EMI shield around the component. According to this exemplary embodiment, the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component. | 2015-09-10 |
20150255403 | METHODS RELATED TO FABRICATION OF SHIELDED RADIO-FREQUENCY MODULE - According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds. The wirebond cage forms an EMI shield around the component. According to this exemplary embodiment, the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component. | 2015-09-10 |
20150255404 | TSV WAFER FRACTURE STRENGTH - A method including forming a through-substrate via through a thickness of a substrate, the thickness of the substrate is measured from a front side of the substrate to a back side of the substrate, removing a first portion of the substrate to form an opening in the back side of the substrate such that a second portion of the substrate remains in direct contact surrounding a vertical sidewall of the through-substrate via, and filling the opening with an alternate material having a lower modulus of elasticity than the substrate. | 2015-09-10 |
20150255405 | CHAMFERED CORNER CRACKSTOP FOR AN INTEGRATED CIRCUIT CHIP - A corner crackstop is formed in each of the four corners of an integrated circuit (IC) chip, in which the corner crackstop differs structurally from a portion of the crackstop disposed along the sides of the IC chip. Each corner crackstop includes a plurality of layers, formed on a top surface of a silicon layer of the IC chip, within a perimeter boundary region that comprises a triangular area, in which a right angle is disposed on a bisector of the corner, equilateral sides of the triangle are parallel to sides of the IC chip, and the right angle is proximate to the corner relative to a hypotenuse of the triangle. The plurality of layers of the corner crackstop include crackstop elements, each comprising a metal cap centered over a via bar, in which the plurality of layers of the corner crackstop is chamfered to deflect crack ingress forces by each corner crackstop. | 2015-09-10 |
20150255406 | SOLDER BALL PROTECTION IN PACKAGES - An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material. | 2015-09-10 |
20150255407 | System and Method for a Microfabricated Fracture Test Structure - According to an embodiment, a micro-fabricated test structure includes a structure mechanically coupled between two rigid anchors and disposed above a substrate. The structure is released from the substrate and includes a test layer mechanically coupled between the two rigid anchors. The test layer includes a first region having a first cross-sectional area and a constricted region having a second cross-sectional area smaller than the first cross-sectional area. The structure also includes a first tensile stressed layer disposed on a surface of the test layer adjacent the first region. | 2015-09-10 |
20150255408 | SUBSTRATE CAPABLE OF ELECTROSTATIC SELF-PROTECTION AND MANUFACTURING METHOD THEREOF - A substrate capable of electrostatic self-protection and a manufacturing method thereof, and the substrate ( | 2015-09-10 |
20150255409 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME - A thin film transistor substrate includes pixels disposed in a display area and connected to gate lines and data lines crossing the gate lines, a gate driver disposed in a non-display area adjacent to the display area and connected to the gate lines, signal pad parts disposed in the non-display area and connected to the gate driver and the data lines, test pad parts disposed in a cutting area adjacent to the non-display area and connected to the signal pad parts, static electricity dispersion parts disposed in the cutting area and connected to the plurality of test pad parts, and a guard line disposed in the cutting area and connected to the static electricity dispersion parts. The static electricity dispersion parts disperse a static electricity inflowing from the signal pad parts and the plurality of test pad parts to the guard line. | 2015-09-10 |
20150255410 | MECHANICALLY ANCHORED BACKSIDE C4 PAD - The present invention relates generally to flip chip technology and more particularly, to a method and structure for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure. In an embodiment, a method is disclosed that may include forming a bonding pad having one or more anchor regions that extend into a semiconductor structure and may inhibit the bonding pad from physically separating from the TSV during temperature fluctuations. | 2015-09-10 |
20150255411 | DIE-TO-DIE BONDING AND ASSOCIATED PACKAGE CONFIGURATIONS - Embodiments of the present disclosure are directed towards die-to-die bonding and associated integrated circuit (IC) package configurations. In one embodiment, a package assembly includes a package substrate having a solder resist layer disposed on a first side and a second side disposed opposite to the first side, a first die mounted on the first side and having an active side that is electrically coupled with the package substrate by one or more first die-level interconnects and a second die bonded with the active side of the first die using one or more second die-level interconnects, wherein at least a portion of the second die is disposed in a cavity that extends into the solder resist layer. Other embodiments may be described and/or claimed. | 2015-09-10 |
20150255412 | EMBEDDED DIE FLIP-CHIP PACKAGE ASSEMBLY - Embodiments of the present disclosure describe integrated circuit (IC) package assemblies and methods of fabricating IC package assemblies. These embodiments include dies embedded in embedding substrates to provide larger pitch interconnects to facilitate coupling to substrates or circuit boards through flip chip techniques. The embedding substrates may contain conductive pathways for coupling die contacts to larger pitch contacts located on the embedding substrate. By embedding the dies in the embedding substrates, dies having smaller pitch contacts can be used in package assemblies with larger pitch components without the need for silicon interposers and without having to utilize more stringent pick and place operations. Other embodiments may be described and/or claimed. | 2015-09-10 |
20150255413 | ENHANCED BOARD LEVEL RELIABILITY FOR WAFER LEVEL PACKAGES - A wafer level package device, electronic device, and fabrication methods for fabrication of the wafer level package device are described that include forming an exposed lead tip on the wafer level package for providing a solder buttress structure when coupling the wafer level package device to another electrical component. In implementations, the wafer level package device includes at least one integrated circuit die, a metal pad, a first dielectric layer, a redistribution layer, a second dielectric layer, a pillar structure, a molding layer, a pillar layer, and a plating layer, where the pillar layer is sawn to form pad contacts on at least two sides of the wafer level package device. The exposed pad contact facilitate a solder fillet and buttress structure resulting in improved board level reliability. | 2015-09-10 |
20150255414 | SOLDER ALLOY TO ENHANCE RELIABILITY OF SOLDER INTERCONNECTS WITH NIPDAU OR NIAU SURFACE FINISHES DURING HIGH TEMPERATURE EXPOSURE - Embodiments of the present disclosure describe solder compounds for electrically coupling integrated circuit (IC) substrates as well as methods for using the solder compounds to couple IC subtrates. The solder compounds are formulated with lower Copper (Cu) percentages to prevent the formation of Cu rich intermettalic compounds (IMCs) which may undergo transitions at elevated temperatures resulting in void formation when NiPdAu or NiAu surface finishes are used on both sides of the solder interconnect. Additionally, nickel (Ni), may be included in the solder compounds to improve fatigue and/or creep properties. Other embodiments may be described and/or claimed. | 2015-09-10 |
20150255415 | Package Structure To Enhance Yield of TMI Interconnections - An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound. | 2015-09-10 |
20150255416 | INTEGRATED DEVICE COMPRISING HIGH DENSITY INTERCONNECTS AND REDISTRIBUTION LAYERS - Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die coupled to a first surface of the base portion, and an underfill between the first die and the base portion. The base portion includes a dielectric layer, and a set of redistribution metal layers. In some implementations, the integrated device further includes an encapsulation material that encapsulates the first die. In some implementations, the integrated device further includes a second die coupled to the first surface of the base portion. In some implementations, the integrated device further includes a set of interconnects on the base portion, the set of interconnects electrically coupling the first die and the second die. In some implementations, the first die includes a first set of interconnect pillars and the second die includes a second set of interconnect pillars. | 2015-09-10 |
20150255417 | FACILITATING CHIP DICING FOR METAL-METAL BONDING AND HYBRID WAFER BONDING - A method of forming a stacked assembly of semiconductor chips can include juxtaposing and metallurgically joining kerf metal elements exposed in kerf regions of a first wafer with corresponding kerf metal elements exposed in kerf regions of a second wafer, and affixing undiced semiconductor chips of the first wafer with corresponding undiced semiconductor chips of the second wafer. The assembled wafers are then cut along the dicing lanes thereof into a plurality of individual assemblies of stacked semiconductor chips, each assembly including an undiced semiconductor chip of the first wafer and an undiced semiconductor chip of the second wafer affixed therewith. | 2015-09-10 |
20150255418 | ULTRA-THIN EMBEDDED SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THEREOF - A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit. | 2015-09-10 |
20150255419 | SEMICONDUCTOR DEVICE AND CERAMIC CIRCUIT SUBSTRATE, AND PRODUCING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device comprises a circuit layer composed of a conductive material, and a semiconductor element mounted on the circuit layer, wherein an underlayer having a porosity in the range of 5 to 55% is formed on one surface of the circuit layer, a bonding layer composed of a sintered body of a bonding material including an organic substance and at least one of metal particles and metal oxide particles is formed on the underlayer, and the circuit layer and the semiconductor element are bonded together via the underlayer and the bonding layer. | 2015-09-10 |
20150255420 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In order to improve the reliability of a semiconductor device, dummy wiring includes: a first dummy part provided to be spaced apart from and to be parallel to, of a plurality of sides that form a pad, a first side nearest to a corner; and a second dummy part provided to be spaced apart from and to be parallel to, of the sides that form the pad, a second side nearest to an edge side of a semiconductor chip. That is, the dummy wiring is formed by: a first dummy part extending along the first side of the pad; and a second dummy part extending along the second side of the pad. | 2015-09-10 |
20150255421 | SEMICONDUCTOR MANUFACTURING DEVICE AND SEMICONDUCTOR MANUFACTURING METHOD - According to one embodiment, a semiconductor manufacturing device includes a first stage, a second stage, a transfer unit, and a detector. The first stage corrects a position of the semiconductor chip. The second stage supports an object into which the semiconductor chip is to be installed. The transfer unit transfers the semiconductor chip picked up from the first stage to the second stage. The detector detects an elastic wave from the semiconductor chip. The detector is attached to at least one of the first stage and the second stage. | 2015-09-10 |
20150255422 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer. | 2015-09-10 |
20150255423 | COPPER CLAD LAMINATE HAVING BARRIER STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A copper clad laminate is disclosed to include a substrate defining a plurality of carrier zones for attachment of chips and having a plurality of barrier portions each arranged around at least one of the carrier zones for isolating the carrier zones. Thus, when tin sheets mounted between the chips and the carrier zones of the substrate become liquids in a thermal reflow process, the barrier portions of the substrate will stop an overflow of molten tin to prevent the chips from damage caused by a solder bridge problem. | 2015-09-10 |
20150255424 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. | 2015-09-10 |
20150255425 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element, a lead, and a wire including a first bonding portion bonded to the semiconductor element and a second bonding portion bonded to the lead. The semiconductor element includes a first bonding surface which faces to a first side in a first direction and to which the first bonding portion is bonded. The lead includes a second bonding surface and a third bonding surface both facing to the first side in the first direction and forming an angle larger than 180° on the first side in the first direction. The semiconductor device further includes a ball bump extending onto both the second bonding surface and the third bonding surface. The second bonding portion is bonded to the lead via the ball bump. | 2015-09-10 |
20150255426 | SEMICONDUCTOR DEVICE WITH REDUCED WARPAGE - A semiconductor device with reduced warpage is disclosed and may, for example, include bonding at least two semiconductor die to a substrate, forming underfill material between the at least two semiconductor die and the substrate and between the at least two semiconductor die, and removing a portion of the underfill material between the at least two semiconductor die, thereby forming a groove. The at least two semiconductor die and the underfill material may, for example, be encapsulating utilizing an encapsulant. The groove may, for example, be filled using the encapsulant. The underfill material between the at least two semiconductor die may, for example, be removed utilizing laser etching. The underfill material between the at least two semiconductor die may, for example, be removed to a depth of 60-70% of a thickness of the at least two semiconductor die. | 2015-09-10 |
20150255427 | CHIP STACK EMBEDDED PACKAGES - A chip stack embedded package includes a first dielectric layer having a multistep cavity therein, a first plurality of semiconductor chips disposed in a first level of the multistep cavity, a second plurality of semiconductor chips disposed in a second level of the multistep cavity, and a second dielectric layer filling the multistep cavity to cover the first and second pluralities of semiconductor chips. | 2015-09-10 |
20150255428 | CHIP ARRANGEMENT - A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip carrier top side; and electrically insulating material configured to at least partially surround the first chip carrier and the second chip carrier; at least one electrical interconnect configured to electrically contact the first chip to the second chip through the electrically insulating material; one or more first electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier top side and second chip carrier top side, and one or more second electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier bottom side and second chip carrier bottom side. | 2015-09-10 |
20150255429 | Thermal Vias Disposed in a Substrate Proximate to a Well Thereof - An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at least a first die and a second die interconnected to one another using die-to-die interconnects. A substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate. A first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom. The substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate. A second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity. | 2015-09-10 |
20150255430 | PACKAGE STRUCTURE - A package structure is disclosed. The package structure includes a first die, a second die on the first die, and a substrate disposed corresponding to the first die. The first die includes a first die identification (ID) region defined thereon and a plurality of first through silicon vias (TSVs) in the first die ID region. The second die includes another first die identification (ID) region and a second die ID region defined thereon and a plurality of second TSVs in the another first die ID region and a plurality of third TSVs in the second die ID region, in which the second TSVs are electrically connected to the first TSVs in the first die. | 2015-09-10 |
20150255431 | Semiconductor Package and Method - A first package is bonded to a second package with a structural member located between the first package and the second package for structural support. In an embodiment the structural member is a plate or one or more conductive balls. Once the structural member is in place, the first package is bonded to the second package. | 2015-09-10 |
20150255432 | SOLUTION FOR REDUCING POOR CONTACT IN INFO PACKAGES - A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding compound, and a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs on opposite sides of the molding compound. The through-via electrically couples one of the first plurality of RDLs to one of the second plurality of RDLs. The package further includes a second package bonded to the first package, a spacer disposed in a gap between the first package and the second package, and a first electrical connector and a second electrical connector on opposite sides of the spacer. The first electrical connector and the second electrically couple the first package to the second package. The spacer is spaced apart from the first electrical connector and the second electrical connector. | 2015-09-10 |
20150255433 | COMBINED SUBSTRATE - A combined substrate includes a first substrate having multiple first metal posts, a second substrate having multiple second metal posts such that the second metal posts are positioned to oppose the first metal posts, respectively, and multiple solder structures interposed between the first metal posts and the second metal posts, respectively. The first metal posts and/or the second metal posts have recessed surfaces formed such that the solder structures are formed on the recessed surfaces, respectively. | 2015-09-10 |
20150255434 | SEMICONDUCTOR INTERPOSER INTEGRATION - Integrated circuits are described which directly connect a semiconductor interposer to a motherboard or printed circuit board by way of large pitch connections. A stack of semiconductor interposers may be connected directly to one another by a variety of means and connected to a printed circuit board through only a ball grid array of solder bumps. The stack of semiconductor interposers may include one or more semiconductor interposers which are shifted laterally to enable directly electrical connections to intermediate semiconductor interposers. The top semiconductor interposer may have no electrical connections on the top to increase security by making electrical “taps” much more difficult. An electrically insulating layer may be incorporated between adjacent semiconductor interposers and cavities or air gaps may also be included within one or more semiconductor interposers. | 2015-09-10 |
20150255435 | Single Mask Package Apparatus - Disclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the land and a protective layer disposed over the first surface of the first substrate and around the stud. The protective layer may optionally have a thickness of at least 3 μm. A PPI may be disposed over the protective layer and in electrical contact with the stud, with a first portion of the PPI extending laterally from the stud. An interconnect may be disposed on and in electrical contact with the first portion of the PPI, and a second substrate mounted on the interconnect. A molding compound may be disposed over the PPI and around the interconnect. The stud may be a substantially solid material having a cylindrical cross section and may optionally be wirebonded to the land. | 2015-09-10 |
20150255436 | SUBSTRATE FOR MOUNTING LED ELEMENT, LED LIGHT SOURCE AND LED DISPLAY - Provided is a substrate for mounting an LED element in which a stable light-emitting surface is obtained, as well as a light source and an LED display using this substrate, so that the axis at which light is emitted by a chip LED does not vary. The substrate for mounting an LED element ( | 2015-09-10 |
20150255437 | Optoelectronic Component - An optoelectronic component includes a carrier, a first optoelectronic semiconductor chip arranged on the carrier, a first conversion element arranged on the first semiconductor chip, a second optoelectronic semiconductor chip arranged on the carrier and a second conversion element arranged on the second semiconductor chip. The optoelectronic component also includes an insulation material arranged on the carrier. The insulation material surrounds the first and second semiconductor chips and the first and second conversion element. The first conversion element is embodied in a stepped fashion and has a first and a second section wherein the first section projects laterally beyond the second section. | 2015-09-10 |
20150255438 | MULTI-LAYER CONDUCTIVE BACKPLANE FOR LED LIGHT SHEET SEGMENTS - Relatively small, electrically isolated segments of LED light sheets are fabricated having an anode terminal and a cathode terminal. The segments contain microscopic printed LEDs that are connected in parallel by two conductive layers sandwiching the LEDs. The top conductive layer is transparent. Separately formed from the light sheet segments is a flexible, large area conductor backplane having a single layer or multiple layers of solid metal strips (traces). The segments are laminated over the backplane's metal pattern to supply power to the segment terminals. An adhesive layer secures the segments to the backplane. The metal pattern may connect the segments in series, or parallel, or form an addressable circuit for a display. The segments may be on a common substrate or physically separated from each other prior to the lamination. | 2015-09-10 |
20150255439 | DISPLAY DEVICE USING SEMICONDUCTOR LIGHT EMITTING DEVICE - Discussed is a display device including a wiring substrate having a first electrode and a second electrode formed on different surfaces, a conductive adhesive layer configured to cover the wiring substrate, and a sub-pixel portion coupled to the conductive adhesive layer to have a plurality of light emitting portions that emit different color lights, wherein the sub-pixel portion has a plurality of first conductive electrodes corresponding to the plurality of light emitting portions, and a second conductive electrode as a common electrode for the plurality of light emitting portions, and wherein an electrode hole is formed on the wiring substrate to electrically connect the second electrode to the second conductive electrode. | 2015-09-10 |
20150255440 | LIGHT-EMITTING DEVICE - This disclosure discloses a light-emitting device. The light-emitting device is configured to electrically connect to an external circuit and comprises: a first light-emitting structure; a second light-emitting structure; a first conductive structure comprising a first connecting pad having a side surface and a top surface connected to the first light-emitting structure, and a first connecting portion extending from the side surface and connected to the external circuit; and a second conductive structure electrically connecting the first light-emitting structure with the second light-emitting structure. | 2015-09-10 |
20150255441 | THERMALLY ENHANCED THREE-DIMENSIONAL INTEGRATED CIRCUIT PACKAGE - Embodiments of the present invention disclose a semiconductor structure and method for increasing thermal dissipation in a three-dimensional integrated circuit package. In certain embodiments, the semiconductor structure comprises a logic die or a processor die attached to a substrate; a memory die stack attached to the logic die or the processor die; and a first lid attached to a first side of the logic or the processor die. The semiconductor structure further comprises a second lid attached to a second side of the memory die stack; a first heat sink attached to the first lid; and a second heat sink attached to the second lid. | 2015-09-10 |
20150255442 | POWER SEMICONDUCTOR MODULE - According to one embodiment, a power semiconductor module includes a substrate, a first interconnection layer, semiconductor elements, and a rectifier element. The first interconnection layer is provided on the substrate. The semiconductor elements are provided on the first interconnection layer. Each of the semiconductor elements includes first, second, and third electrodes. The second electrode is electrically connected to the first interconnection layer. The rectifier element is provided on the first interconnection layer, and includes a fifth electrode electrically connected to the first interconnection layer and a fourth electrode electrically connected to the first electrode. The semiconductor elements and the rectifier elements are radially disposed on the first interconnection layer. Arbitrary points fallen in respective regions of the semiconductor elements and an arbitrary point fallen in a region of the rectifier element are disposed in point symmetry or line symmetry based on the first point. | 2015-09-10 |
20150255443 | EXPOSED DIE POWER SEMICONDUCTOR DEVICE - A semiconductor package has a lead frame and a power die. The lead frame has a first die paddle with a cavity formed entirely therethrough. The power die, which has a lower surface, is mounted on the first die paddle such that a first portion of the lower surface is attached to the first die paddle using a solderless die-attach adhesive, and a second portion of the lower surface, is not attached to the first die paddle and abuts the cavity formed in the first die paddle such that the second portion is exposed. | 2015-09-10 |
20150255444 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, AND POSITIONING JIG - A semiconductor device has a plurality of small-sized semiconductor chips disposed between an insulated circuit board having a conductive pattern and a terminal. The semiconductor device exhibits a high accuracy in positioning the semiconductor chips. The semiconductor device includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected to the conductive pattern through a first joining material, a second semiconductor chip with a rectangular shape, disposed on the conductive pattern separated from the first semiconductor chip and connected to the conductive pattern through a second joining material, and a terminal disposed above the first semiconductor chip and the second semiconductor chip, connected to the first semiconductor chip through a third joining material, and connected to the second semiconductor chip through a fourth joining material. The terminal has a through-hole above a place between the first semiconductor chip and the second semiconductor chip. | 2015-09-10 |
20150255445 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - An organic light emitting diode (OLED) display includes: a substrate including a plurality of organic light emitting elements; an adhesive member on at least a portion of an upper surface of the substrate; a flexible circuit board adhered to the upper surface of the adhesive member and having a portion bent to be mounted to a lower surface of the substrate; and a light blocking member at the upper surface of the substrate, wherein the light blocking member is laterally offset from the adhesive member. | 2015-09-10 |
20150255446 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFORE - Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized. | 2015-09-10 |
20150255447 | Interconnect Structure for Package-on-Package Devices - An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package. | 2015-09-10 |
20150255448 | MOLD CHASE FOR INTEGRATED CIRCUIT PACKAGE ASSEMBLY AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure are directed towards a mold chase for integrated circuit package assembly and associated techniques and configurations. In one embodiment, a method includes receiving a package substrate, the package substrate including a first die mounted on the package substrate by a plurality of first interconnect structures, and a plurality of second interconnect structures disposed on the package substrate and to route electrical signals of a second die, protecting a top surface of individual interconnect structures of the plurality of second interconnect structures from deposition of a mold material, and depositing the mold material on the package substrate between the individual interconnect structures of the plurality of second interconnect structures. Other embodiments may be described and/or claimed. | 2015-09-10 |
20150255449 | Electrostatic Discharge Circuit and Liquid Crystal Display Device Including the Same - Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a transistor structure having at least five thin film transistors (TFTs), said transistor structure configured in view of changes in operating characteristics that depend on a channel length of a back channel etched (BCE) type oxide transistor. | 2015-09-10 |
20150255450 | Field-Effect Device and Manufacturing Method Thereof - Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region, and a pocket implant region adjacent to the first source/drain region, the pocket implant region being of a second conductivity type, wherein the second conductivity type is different from the first conductivity type. The body region physically contacts the pocket implant region. | 2015-09-10 |
20150255451 | SEMICONDUCTOR DEVICE - A semiconductor device includes a heat source and a heat detection element which are formed on a semiconductor substrate; and a heat conductive member formed across both of the heat source and the heat detection element, a thermal conductivity of the heat conductive member being higher than a thermal conductivity of the semiconductor substrate, and wherein the heat source, the heat detection element and the heat conductive member are integrated on the semiconductor substrate. | 2015-09-10 |
20150255452 | SEMICONDUCTOR DEVICE - To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged. | 2015-09-10 |
20150255453 | SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment is provided with a first metal substrate, a second metal substrate separated from the first metal substrate, a normally-off transistor of a silicon semiconductor provided on the first metal substrate, and a normally-on transistor of a nitride semiconductor provided on the second metal substrate. | 2015-09-10 |
20150255454 | SEMICONDUCTOR DEVICE | 2015-09-10 |
20150255455 | SEMICONDUCTOR DEVICE AND SYSTEM USING THE SAME - There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set to an OFF state. | 2015-09-10 |
20150255456 | REPLACEMENT FIN INSOLATION IN A SEMICONDUCTOR DEVICE - Embodiments herein provide approaches for forming a set of replacement fins in a semiconductor device. Specifically, a device is formed having a set of replacement fins over a substrate, each of the set of replacement fins comprising a first section separated from a second section by a liner layer, the first section having a lower dopant centration than a dopant concentration of the second section. In one embodiment, sequential epitaxial deposition with insitu doping is used to form the second section, the liner layer, and then the first section of each of the set of replacement fins. In another embodiment, the second section is formed over the substrate, and the liner layer is formed through a carbon implant. The first section is then epitaxially formed over the liner layer, and serves as the fin channel. As provided, upward dopant diffusion is suppressed, resulting in the first section of each fin being maintained with low doping so that the fin channel is fully depleted channel during device operation. | 2015-09-10 |
20150255457 | METHODS AND APPARATUS TO FORM FIN STRUCTURES OF DIFFERENT COMPOSITIONS ON A SAME WAFER VIA MANDREL AND DIFFUSION - Methods and structures for forming finFETs of different semiconductor composition and of different conductivity type on a same wafer are described. Some finFET structures may include strained channel regions. FinFETs of a first semiconductor composition may be grown in trenches formed in a second semiconductor composition. Material of the second semiconductor composition may be removed from around some of the fins at first regions of the wafer, and may remain around fins at second regions of the wafer. A chemical component from the second semiconductor composition may be driven into the fins by diffusion at the second regions to form finFETs of a different chemical composition from those of the first regions. The converted fins at the second regions may include strain. | 2015-09-10 |
20150255458 | REPLACEMENT METAL GATE STACK FOR DIFFUSION PREVENTION - A method of forming a semiconductor structure includes depositing a gate dielectric layer lining a recess of a gate structure formed on a substrate with a first portion of the gate dielectric layer covering sidewalls of the recess and a second portion of the gate dielectric layer covering a bottom of the recess. A protective layer is deposited above the gate dielectric layer and then recessed selectively to the gate dielectric layer so that a top surface of the protective layer is below of the recess. The first portion of the gate dielectric layer is recessed until a top of the first portion of the gate dielectric layer is approximately coplanar with the top surface of the protective layer. The protective layer is removed and a conductive barrier is deposited above the recessed first portion of the gate dielectric layer to cut a diffusion path to the gate dielectric layer. | 2015-09-10 |
20150255459 | CMOS TRANSISTORS WITH IDENTICAL ACTIVE SEMICONDUCTOR REGION SHAPES - A disposable semiconductor material is deposited to form disposable semiconductor material portions on semiconductor fins. A first dielectric liner is deposited and patterned to form openings above a first set of disposable semiconductor material portions on a first semiconductor fin. The first set of disposable semiconductor material portions is replaced with a first set of active semiconductor regions by a combination of an etch and a selective epitaxy process that deposits a first semiconductor material. A second dielectric liner is deposited and patterned to form openings above the second set of disposable semiconductor material portions. The second set of disposable semiconductor material portions is replaced with a second set of active semiconductor regions employing another epitaxy process that deposits a second semiconductor material. The active semiconductor regions can have the same faceting profile irrespective of the semiconductor materials therein. | 2015-09-10 |
20150255460 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR STRUCTURE WITH III-V AND SILICON GERMANIUM TRANSISTORS ON INSULATOR - Embodiments for the present invention provide a CMOS structure and methods for fabrication. In an embodiment of the present invention, a CMOS structure comprises a NFET, formed on a wafer, having a gate stack and a channel. A PFET having a gate stack and a channel is also formed on the wafer. The channel of the PFET and the channel of the NFET include semiconductor material formed on III-V semiconductor material, such that the III-V semiconductor material acts like a buried oxide because of a valence band offset between the semiconductor material and the III-V material. There is a height difference between a terminal of the NFET and a terminal of the PFET. In addition, the gate stack NFET is the same height as the gate stack PFET. | 2015-09-10 |
20150255461 | STACKED COMMON GATE FINFET DEVICES FOR AREA OPTIMIZATION - A MOS device includes a first FinFET having a first transistor source, drain, gate, and set of fins, and includes a second FinFET having a second transistor source, drain, gate, and set of fins. The MOS device further includes a gate interconnect extending linearly to form and to connect together the first and second transistor gates. The MOS device further includes a first interconnect on a first side of the gate interconnect that connects together the set of first transistor fins at the first transistor drain and the set of second transistor fins at the second transistor source, a second interconnect on a second side of the gate interconnect that connects together the set of first transistor fins at the first transistor source, and a third interconnect on the second side of the gate interconnect that connects together the set of second transistor fins at the second transistor drain. | 2015-09-10 |
20150255462 | Structure for FinFETs - A FinFET device comprises a well over a substrate, an isolation region over the well and a fin line over the well and surrounded by the isolation region, wherein the fin line is wrapped by a first gate electrode structure to form a first transistor and an end of the fin line is of a tapered shape. | 2015-09-10 |
20150255463 | METHODS AND STRUCTURE TO FORM HIGH K METAL GATE STACK WITH SINGLE WORK-FUNCTION METAL - A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate. | 2015-09-10 |
20150255464 | SEMICONDUCTOR DEVICE HAVING BURIED GATE AND MANUFACTURING METHOD THEREOF - A dummy active region is formed in a region in which a gate contact for supplying operation power to the buried gate is formed, and a PN junction diode connected to the gate contact in a reverse bias direction is formed in the dummy active region. Current leakage, in which current flows out toward a substrate, is prevented even when misalignment of the gate contact occurs. | 2015-09-10 |
20150255465 | SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD FOR SAME - This method for manufacturing a semiconductor device comprises: a step for forming a first groove ( | 2015-09-10 |
20150255466 | SEMICONDUCTOR DEVICE WITH LINE-TYPE AIR GAPS AND METHOD FOR FABRICATING THE SAME - A method includes: forming a first contact hole by etching a first inter-layer dielectric layer; forming a preliminary first conductive plug that fills the first contact hole; forming a bit line structure over the preliminary first conductive plug; forming a first conductive plug by etching the preliminary first conductive plug so that a gap is formed between a sidewall of the first contact hole and the first conductive plug; forming an insulating plug in the gap; forming a multi-layer spacer including a sacrificial spacer; forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer and the insulating plug therebetween; and forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer. | 2015-09-10 |
20150255467 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a retention section that retains data by using a pair of first conductivity-type load transistors and a pair of second conductivity-type drive transistors, and a transfer section with transistors that operate to transfer data to and from the retention section and has a gate length shorter than the gate length of at least one of the drive transistors and the load transistors. | 2015-09-10 |
20150255468 | CONTACT STRUCTURE AND FORMING METHOD - Vias are formed within a stack of alternating active and insulating layers by forming a first sub stack, a second sub stack over the first sub stack, a first buffer layer therebetween and a second buffer layer under the first sub stack. An upper layer of the first sub stack is exposed through a set of vias by first and second etching processes. The first etching process forms a first set of etch vias through the second sub stack and stops at or in the first buffer layer. The second etching process etches through the first buffer layer to the upper layer of the first sub stack. A third etching process etches through the first set of etch vias, through the first sub stack and stops at or in the second buffer layer. A fourth etching process and etches through the second buffer layer. | 2015-09-10 |
20150255469 | FUSE STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A fuse structure includes a first fin pattern disposed in a field insulating layer that includes an upper surface that projects above an upper surface of the field insulating layer, a conductive pattern on the field insulating layer that crosses the first fin pattern, a first semiconductor region positioned on at least one side of the conductive pattern, and first and second contacts disposed on the conductive pattern on each side of the first fin pattern. The fuse structure may be included in a semiconductor device. | 2015-09-10 |
20150255470 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - In accordance with an embodiment, a semiconductor memory device includes a substrate and memory transistors on the substrate. The substrate has a semiconductor layer having impurity diffusion regions which become sources or drains. The memory transistors share the impurity diffusion regions. | 2015-09-10 |
20150255471 | SPLIT-GATE FLASH MEMORY EXHIBITING REDUCED INTERFERENCE - A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack. | 2015-09-10 |
20150255472 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a floating gate formed over a substrate; a contact plug formed on a first side of the floating gate and disposed parallel to the floating gate with a gap defined therebetween; and a spacer formed on a sidewall of the floating gate and filling the gap, wherein the contact plug and the floating gate have a sufficiently large overlapping area to enable the contact plug to operate as a control gate for the floating gate. | 2015-09-10 |
20150255473 | FLASH MEMORY AND FABRICATION METHOD THEREOF - A flash memory fabrication method includes: providing a substrate having a plurality of floating gate structures separated by trenches, which includes at least a source trench and a drain trench, and source/drain regions; forming a metal film on the substrate and on the floating gate structures; performing a thermal annealing process on the metal film to form a first silicide layer on the source regions and a second silicide layer on the drain regions; removing portions of the metal film to form a metal layer on the bottom and lower sidewalls of the source trench and contacting with the first silicide layer, and forming a dielectric layer on the substrate and the floating gate structures, covering the source trench and the drain trench. Further, the method includes forming a first conducting structure and one or more second conducting structures in the dielectric layer. The first conducting structure is on the metal layer in the source trench, the second conducting structures are on the second silicide layer, and adjacent first conducting structure and second conducting structure have a predetermined distance. | 2015-09-10 |
20150255474 | SEMICONDUCTOR DEVICE AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A semiconductor device includes a semiconductor substrate, a first insulating film on the semiconductor substrate, a first electrode film on the first insulating film, a second insulating film on the first electrode film, a second electrode film on the second insulating film, an opening extending through the second electrode film and the second insulating film and into the first electrode film, a barrier film over the surfaces of the opening and a portion of the first electrode film exposed within the opening, and a metal film disposed on the barrier film disposed over the surfaces of the opening. The barrier film directly contacts at least a portion of the second insulating film exposed in the opening and the metal film overlies the location where the barrier film directly contacts the second insulating film exposed in the opening. | 2015-09-10 |
20150255475 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF p-CHANNEL MOS TRANSISTOR - A non-volatile semiconductor memory device includes a memory cell transistor having a memory cell capable of writing and erasing data, and a peripheral circuit that drives the memory cell which includes a first p-channel MOS transistor including a gate electrode that is formed on a semiconductor layer with a first gate insulation film therebetween, a channel region that is formed on a surface of the semiconductor layer and has a first peak dopant concentration, a source region and a drain region that have a second peak dopant concentration higher than the first peak dopant concentration, and overlap regions that extend between the channel region and the source region and the drain region, and also below a portion of the gate electrode, that have a third peak dopant concentration higher than the first peak dopant concentration and lower than the second peak dopant concentration by one order of magnitude or more. | 2015-09-10 |
20150255476 | EEPROM DEVICE AND FORMING METHOD AND ERASING METHOD THEREOF - An EEPROM device, a forming method thereof, and a method for implementing an erase operation to the device are provided. The EEPROM device includes: a semiconductor substrate having active regions therein; a word line disposed on a first active region; float gate dielectric layers disposed on second active regions; float gates disposed on the float gate dielectric layers, wherein each of the float gates has a width larger than that of the second active region; control gates disposed on control gate dielectric layers which are disposed on the float gates; an isolation oxide layer disposed between the word line and the float gates along with the control gates; and bit line doping regions disposed on third active regions. Accordingly, an erase operation can be implemented from a bit line, and coupling ratios of a float gate to a control gate and to a bit line doping region can be improved. | 2015-09-10 |
20150255477 | CHIP AND AN ELECTRONIC DEVICE - A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material. | 2015-09-10 |
20150255478 | APPARATUSES INCLUDING MEMORY ARRAYS WITH SOURCE CONTACTS ADJACENT EDGES OF SOURCES - Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device can include at least two sources; at least two memory arrays respectively formed over and coupled to the at least two sources; and a source conductor electrically respectively coupled to the at least two sources using source contacts adjacent one or more edges of the source. Each of the at least two memory arrays can include memory cells, control gates, and data lines. There is no data line between an edge of a source and the source contacts adjacent the edge. | 2015-09-10 |
20150255479 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first stacked layer structure including first to n | 2015-09-10 |
20150255480 | Method to Improve Charge Trap Flash Memory Top Oxide Quality - A semiconductor processing method to provide a high quality top oxide layer in charged-trapping NAND and NOR flash memory. The top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method described overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride. | 2015-09-10 |
20150255481 | Metal Replacement Process For Low Resistance Source Contacts In 3D NAND - A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to memory holes at a bottom of a stack. The stack includes alternating control gate layers and dielectric layers on a substrate, and memory holes are etched through the stack. The process avoids the need to etch through films at the bottom of the memory hole. Instead, a path is formed from the bottom of the memory hole to the top of the stack. The path includes a horizontal portion using a voided trench in a substrate dielectric, and a passageway etched in the stack. The memory films, a channel material and a dielectric material are deposited throughout the interior surfaces of the void and the memory holes concurrently. The path is filled with metal to form a continuous, low resistance conductive path. | 2015-09-10 |
20150255482 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device according to an embodiment includes a semiconductor layer. A tunnel dielectric film is formed on the semiconductor layer. A charge accumulation layer is formed on the tunnel dielectric film. A block film is formed on the charge accumulation layer. A control gate is formed on the block film. The block film includes a metal oxide film containing nitrogen in a concentration range equal to or lower than | 2015-09-10 |
20150255483 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - An integrated circuit device according to an embodiment includes a stacked structural body, a stopper film selectively provided in the stacked structural body, a first vertical member and a second vertical member provided in the stacked structural body. The first vertical member extends in a stacking direction of the stacked structural body and has a bottom end entering into the stopper film. The second vertical member extends in the stacking direction and passes a side of the stopper film. The stopper film has an upper film and a lower film. The upper film has a composition that differs from a composition of each portion of the stacked structural body. The lower film has a composition that differs from the composition of the upper film. The lower film has a maximum width less than the maximum width of the upper film. | 2015-09-10 |
20150255484 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a stacked body, a second insulating film, a third insulating film and a plurality of contacts. The stacked body includes alternatively stacked electrode films and first insulating films, and has an end portion in which a terrace is formed for each pair of the electrode film and the first insulating film. The second insulating film covers the upper faces and the lower faces of the electrode films in the end portion of the stacked body. The second insulating film has a composition different from the composition of the first insulating film. The third insulating film is provided on the end portion of the stacked body. The third insulating film has a composition different from the composition of the second insulating film. The contact passes through the third insulating film and the second insulating film, and contacts the electrode film. | 2015-09-10 |
20150255485 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device includes a semiconductor substrate; a stack structure disposed above the substrate and including insulation layers and conductive layers stacked alternatively; and a select gate electrode layer disposed above the stack structure; holes extending through the stack structure and the electrode layer; a connecting portion connecting lower portions of adjacent holes; and a pillar insulating film and semiconductor pillars disposed in the connected holes and in the connecting portion. A back gate is disposed between a portion above the connecting portion and the stack structure. An isolation trench is disposed between the adjacent and connected pillars to isolate the stack structure and the electrode layer. The trench has a bottom portion contacting the back gate. A bottom surface of the trench is lower than an upper surface of the back gate. A metal silicide is disposed in a portion where the back gate contacts the trench. | 2015-09-10 |
20150255486 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device including a semiconductor substrate; a stack structure disposed above the substrate and including insulation layers and conductive layers stacked alternatively above one another; a select gate electrode layer disposed above the stack structure; at least one hole extending through the stack structure and the select gate electrode layer; at least one semiconductor pillar disposed along an inner side of the at least one hole; storage layers disposed between the at least one semiconductor pillar and the conductive layers; a gate insulating film disposed between the at least one semiconductor pillar and the select gate electrode layer; an isolation trench disposed so as to isolate the select gate electrode layer, the trench having a bottom portion being lower than an upper surface of an uppermost conductive layer; and a metal silicide disposed in a portion of the conductive layer in the uppermost layer contacting the trench. | 2015-09-10 |
20150255487 | ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE USING SAME - An active matrix substrate ( | 2015-09-10 |
20150255488 | Semiconductor Device, Display Device, And Electronic Device - A pixel includes a load, a transistor which controls a current supplied to the load, a storage capacitor, and first to fourth switches. By inputting a potential in accordance with a video signal into the pixel after the threshold voltage of the transistor is held in the storage capacitor, and holding a voltage of the sum of the threshold voltage and the potential, variations of a current value caused by variations of threshold voltage of a transistor can be suppressed. Consequently, a predetermined current can be supplied to the load such as a light-emitting element. Further, by changing the potential of a power supply line, a display device with a high duty ratio can be provided. | 2015-09-10 |
20150255489 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of selectively forming a depression in an upper surface of a substrate or forming an opening which penetrates the upper surface through a back surface; forming an element group having a transistor so as to cover the upper surface of the substrate and the depression, or the opening; and exposing the element group formed in the depression or the opening by thinning the substrate from the back surface. A means for thinning the substrate can be performed by partially removing the substrate by performing grinding treatment, polishing treatment, etching by chemical treatment, or the like from the back surface of the substrate. | 2015-09-10 |
20150255490 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device suitable for miniaturization and higher density. The semiconductor device includes a first transistor, a second transistor overlapping with the first transistor, a capacitor overlapping with the second transistor, and a first wiring electrically connected to the capacitor. The first wiring includes a region overlapping with an electrode of the second transistor. The first transistor, the second transistor, and the capacitor are electrically connected to one another. A channel of the first transistor includes a single crystal semiconductor. A channel of the second transistor includes an oxide semiconductor. | 2015-09-10 |
20150255491 | ACTIVE-MATRIX SUBSTRATE AND LIQUID-CRYSTAL DISPLAY DEVICE - An active matrix substrate ( | 2015-09-10 |
20150255492 | SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE - To provide a semiconductor device including a small-area circuit with high withstand voltage, an oxide semiconductor (OS) transistor is used as some of transistors included in a circuit handling an analog signal in a circuit to which high voltage is applied. The use of an OS transistor with high withstand voltage as a transistor requiring resistance to high voltage enables the circuit area to be reduced without lowering the performance, as compared to the case using a Si transistor. Furthermore, an OS transistor can be provided over a Si transistor, so that transistors using different semiconductor layers can be stacked, resulting in a much smaller circuit area. | 2015-09-10 |
20150255493 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes a substrate comprising a display area and a non-display area. A gate line and a data line are disposed on the substrate. A thin film transistor is disposed on the display area and coupled to the gate line and the data line. A pad is disposed in the non-display area. A passivation layer is disposed on the thin film transistor and the pad. A pixel electrode is coupled to the thin film transistor. The passivation layer has a thickness that is smaller in the non-display area than in the display area, and the passivation layer has a thickness of about 0.1 μm to about 1 μm in the non-display area. | 2015-09-10 |
20150255494 | ETCH CHEMISTRIES FOR METALLIZATION IN ELECTRONIC DEVICES - In various embodiments, etchants featuring (i) mixtures of hydrochloric acid, methanesulfonic acid, and nitric acid, or (ii) mixtures of phosphoric acid, methanesulfonic acid, and nitric acid, are utilized to etch metallic bilayers while minimizing resulting etch discontinuities between the layers of the bilayer. | 2015-09-10 |
20150255495 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - Image sensor and method of manufacturing the same are provided. The image sensor includes a semiconductor substrate including a pixel area, a voltage connection area, and a pad area, a plurality of photoelectric conversion devices in the pixel area, an anti-reflective layer on a back side of the semiconductor substrate and on the plurality of photoelectric conversion devices, a device isolation structure between the plurality of photoelectric conversion devices, at least one voltage connection structure in the voltage connection area, and electrically connected to the device isolation structure, at least one voltage applying device electrically connected to the at least one voltage connection structure, an internal circuit including at least one conductive inner wire and at least one conductive inner via in an insulating layer, and a through via structure in the pad area. | 2015-09-10 |