37th week of 2014 patent applcation highlights part 20 |
Patent application number | Title | Published |
20140252459 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Provided is a method for fabricating a semiconductor device, which includes the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar, and a doped region is disposed at a bottom of each pillar. An insulation layer is formed below each doped region. | 2014-09-11 |
20140252460 | High Density MOSFET Array with Self-Aligned Contacts Delimited by Nitride-Capped Trench Gate Stacks and Method - A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations. | 2014-09-11 |
20140252461 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a fabricating method thereof are provided. The semiconductor device include: a trench disposed within a substrate, the trench comprising an upper trench part that is wider than a lower trench part in width; a gate disposed in the trench; an interlayer insulating layer pattern disposed above the gate in the trench; a source region disposed within the substrate and contacting a sidewall of the upper trench part; a body region disposed below the source region in the substrate; and a contact trench disposed above the body region and filled with a conductive material. | 2014-09-11 |
20140252462 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes: a trench disposed within a substrate, the trench comprising an upper trench part that is wider than a lower trench part in width; a gate disposed in the trench; an interlayer insulating layer pattern disposed above the gate in the upper trench part; a source region disposed within the substrate and contacting a sidewall of the upper trench part; a body region disposed below the source region in the substrate; and a contact trench disposed above the body region and filled with a conductive material. | 2014-09-11 |
20140252463 | SCHOTTKY AND MOSFET+SCHOTTKY STRUCTURES, DEVICES, AND METHODS - Power devices which include trench Schottky barrier diodes and also (preferably) trench-gate transistors. Isolation trenches flank both the gate regions and the diode mesas, and have an additional diffusion below the bottom of the isolation trenches. The additional diffusion helps to reduce the electric field (and leakage), when the device is in the OFF state, at both the Schottky barrier and at the body diode. | 2014-09-11 |
20140252464 | METHOD OF FORMING STACKED TRENCH CONTACTS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate. | 2014-09-11 |
20140252465 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A semiconductor device has a semiconductor substrate including a body region, a drift region, a trench that extends from a surface of the semiconductor substrate into the drift region through the body region, and a source region located adjacent to the trench in a range exposed to the surface of the semiconductor substrate, the source region being isolated from the drift region by the body region. A specific layer is disposed on a bottom of the trench, and it has a characteristic of forming a depletion layer at a junction between the specific layer and the drift region. An insulating layer covers an upper surface of the specific layer and a sidewall of the trench. A conductive portion is formed on a part of the side wall of the trench. The conductive portion is joined to the specific layer, and reaches the surface of the semiconductor substrate. | 2014-09-11 |
20140252466 | Electronic Device Including a Conductive Electrode and a Process of Forming the Same - An electronic device can include a semiconductor layer, an insulating layer overlying the semiconductor layer, and a conductive electrode. In an embodiment, a first conductive electrode member overlies the insulating layer, and a second conductive electrode member overlies and is spaced apart from the semiconductor layer. The second conductive electrode member has a first end and a second end opposite the first end, wherein each of the semiconductor layer and the first conductive electrode member are closer to the first end of the second conductive electrode member than to the second end of the second conductive electrode member. In another embodiment, the conductive electrode can be substantially L-shaped. In a further embodiment, a process can include forming the first and second conductive electrode members such that they abut each other. The second conductive electrode member can have the shape of a sidewall spacer. | 2014-09-11 |
20140252467 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTORS FOR RADIO FREQUENCY POWER AMPLIFIERS - Embodiments of laterally diffused metal oxide semiconductor (LDMOS) transistors are provided. An LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth. | 2014-09-11 |
20140252468 | Engineered Source/Drain Region for N-Type MOSFET - Integrated circuit devices with field effect transistors have source and drain regions that include a first and a second layer. The first layer is formed below the plane of the channel region. The first layer includes doped silicon and carbon that has a crystal lattice structure that is smaller than that of silicon. The second layer is formed over the first layer and rises above the plane of the channel region. The second layer is formed by a material that includes doped epitaxially grown silicon. The second layer has an atomic fraction of carbon less than half that of the first layer. The first layer is formed to a depth at least 10 nm below the surface of the channel region. This structure facilitates the formation of source and drain extension areas that form very shallow junctions. The devices provide sources and drains that have low resistance while being comparatively resistant to short channel effects. | 2014-09-11 |
20140252469 | FinFETs with Strained Well Regions - A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band. | 2014-09-11 |
20140252470 | Semiconductor Device with Integrated Electrostatic Discharge (ESD) Clamp - A device includes a substrate, a body region in the substrate and having a first conductivity type, source and drain regions in the substrate, having a second conductivity type, and spaced from one another to define a conduction path that passes through the body region, a doped isolating region in the substrate, having the second conductivity type, and configured to surround a device area in which the conduction path is disposed, an isolation contact region in the substrate, having the second conductivity type, and electrically coupled to the doped isolating region to define a collector region of a bipolar transistor, and first and second contact regions within the body region, having the first and second conductivity types, respectively, and configured to define a base contact region and an emitter region of the bipolar transistor, respectively. | 2014-09-11 |
20140252471 | Shared contacts for mosfet devices - In one aspect, the present invention provides electronic devices that comprise a doped semiconductor shared contact between (a) a gate conductor region of at least one transistor and (b) a source/drain diffusion region of at least one transistor. One specific example of such as shared contact, among many others, is a doped SiGe shared contact between (a) a gate conductor region shared by an N-channel MOSFET and a P-channel MOSFET and (b) a drain diffusion region of an N-channel MOSFET or of a P-channel MOSFET. | 2014-09-11 |
20140252472 | SEMICONDUCTOR DEVICE WITH INCREASED SAFE OPERATING AREA - A semiconductor device includes a substrate having a surface, a composite body region disposed in the substrate, having a first conductivity type, and comprising a body contact region at the surface of the substrate and a well in which a channel is formed during operation, a source region disposed in the semiconductor substrate adjacent the composite body region and having a second conductivity type, and an isolation region disposed between the body contact region and the source region. The composite body region further includes a body conduction path region contiguous with and under the source region, and the body conduction path region has a higher dopant concentration level than the well. | 2014-09-11 |
20140252473 | Electronic Device Including a Vertical Conductive Structure and a Process of Forming the Same - An electronic device can include a buried conductive region and a semiconductor layer over the buried conductive region. The electronic device can further include a horizontally-oriented doped region and a vertical conductive region, wherein the vertical conductive region is electrically connected to the horizontally-oriented doped region and the buried conductive region. The electronic device can still further include an insulating layer overlying the horizontally-oriented doped region, and a first conductive electrode overlying the insulating layer and the horizontally-oriented doped region, wherein a portion of the vertical conductive region does not underlie the first conductive electrode. The electronic device can include a Schottky contact that allows for a Schottky diode to be connected in parallel with a transistor. Processes of forming an electronic device allow a vertical conductive region to be formed after a conductive electrode, a gate electrode, a source region, or both. | 2014-09-11 |
20140252474 | METHOD OF FORMING FINFET HAVING FINS OF DIFFERENT HEIGHT - A method is performed on a silicon-on-insulator (SOI) wafer formed of a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer. The method includes forming a first mask over the surface at a first portion of the wafer and leaving a second portion of the wafer unmasked, etching the wafer at the unmasked second portion of the wafer to form a depression in the active silicon layer, the depression having a bottom, forming a thermal oxide layer substantially filling the depression, removing the first mask, and forming fins at the first and second portions of the wafer. | 2014-09-11 |
20140252475 | FinFETs and Methods for Forming the Same - A FinFET includes a semiconductor fin including an inner region, and a germanium-doped layer on a top surface and sidewall surfaces of the inner region. The germanium-doped layer has a higher germanium concentration than the inner region. The FinFET further includes a gate dielectric over the germanium-doped layer, a gate electrode over the gate dielectric, a source region connected to a first end of the semiconductor fin, and a drain region connected to a second end of the semiconductor fin opposite the first end. Through the doping of germanium in the semiconductor fin, the threshold voltage may be tuned. | 2014-09-11 |
20140252476 | Rotated STI Diode on FinFET Technology - A diode includes a first plurality of combo fins having lengthwise directions parallel to a first direction, wherein the first plurality of combo fins comprises portions of a first conductivity type. The diodes further includes a second plurality of combo fins having lengthwise directions parallel to the first direction, wherein the second plurality of combo fins includes portions of a second conductivity type opposite the first conductivity type. An isolation region is located between the first plurality of combo fins and the second plurality of combo fins. The first and the second plurality of combo fins form a cathode and an anode of the diode. The diode is configured to have a current flowing in a second direction perpendicular to the first direction, with the current flowing between the anode and the cathode. | 2014-09-11 |
20140252477 | FinFET with an Asymmetric Source/Drain Structure and Method of Making Same - Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width. | 2014-09-11 |
20140252478 | FinFET with Channel Backside Passivation Layer Device and Method - A FinFET with backside passivation layer comprises a template layer disposed on a substrate, a buffer layer disposed over the template layer, a channel backside passivation layer disposed over the buffer layer and a channel layer disposed over the channel backside passivation layer. A gate insulator layer is disposed over and in contact with the channel layer and the channel backside passivation layer. The buffer layer optionally comprises aluminum and the channel layer may optionally comprise a III-V semiconductor compound. STIs may be disposed on opposite sides of the channel backside passivation layer, and the channel backside passivation layer may have a top surface disposed above the top surface of the STIs and a bottom surface disposed below the top surface of the STIs. | 2014-09-11 |
20140252479 | SEMICONDUCTOR FIN ISOLATION BY A WELL TRAPPING FIN PORTION - A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer. | 2014-09-11 |
20140252480 | COMBINATION FINFET AND PLANAR FET SEMICONDUCTOR DEVICE AND METHODS OF MAKING SUCH A DEVICE - A device includes a plurality of trenches and fins defined in a substantially un-doped layer of semiconducting material, a gate insulation layer positioned on the fins and on the bottom of the trenches, a gate electrode and a device isolation structure. One method disclosed herein involves identifying a top width of each of a plurality of fins and a depth of a plurality of trenches to be formed in a substantially un-doped layer of semiconducting material, wherein, during operation, the device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to the device, performing at least one process operation to define the trenches and fins in the layer of semiconducting material, forming a gate insulation layer on the fins and on a bottom of the trenches and forming a gate electrode above the gate insulation layer. | 2014-09-11 |
20140252481 | TRANSISTOR INCLUDING A GATE ELECTRODE EXTENDING ALL AROUND ONE OR MORE CHANNEL REGIONS - A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode. | 2014-09-11 |
20140252482 | FINFET TRANSISTOR STRUCTURE AND METHOD FOR MAKING THE SAME - A FINFET transistor structure includes a substrate including a fin structure. Two combined recesses embedded within the substrate, wherein each of the combined recesses includes a first recess extending in a vertical direction and a second recess extending in a lateral direction, the second recess has a protruding side extending to and under the fin structure. Two filling layers respectively fill in the combined recesses. A gate structure crosses the fin structure. | 2014-09-11 |
20140252483 | SEMICONDUCTOR DEVICE HAVING FINFET STRUCTURES AND METHOD OF MAKING SAME - A semiconductor device and method making it comprises pFETs with an SiGe channel and nFETs with an Si channel, formed on an SOI substrate. Improved uniformity of fin height and width is attained by forming the fins additively by depositing an SiGe layer on the SOI substrate and forming first fins from the superposed SiGe layer and underlying thin Si film of the SOI substrate. Second fins of Si can then be formed by replacing the upper SiGe portions of selected first fins with Si. | 2014-09-11 |
20140252484 | Electronic Device Including a Schottky Contact - An electronic device can include a semiconductor layer having a primary surface, and a Schottky contact comprising a metal-containing member in contact with a horizontally-oriented lightly doped region within the semiconductor layer and lying adjacent to the primary surface. In an embodiment, the metal-containing member lies within a recess in the semiconductor layer and contacts the horizontally-oriented lightly doped region along a sidewall of the recess. In other embodiment, the Schottky contact may not be formed within a recess, and a doped region may be formed within the semiconductor layer under the horizontally-oriented lightly doped region and have a conductivity type opposite the horizontally-oriented lightly doped region. The Schottky contacts can be used in conjunction with power transistors in a switching circuit, such as a high-frequency voltage regulator. | 2014-09-11 |
20140252485 | Low-Cost CMOS Structure with Dual Gate Dielectrics and Method of Forming the CMOS Structure - Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor. | 2014-09-11 |
20140252486 | Fin Shape For Fin Field-Effect Transistors And Method Of Forming - A fin field-effect transistor (finFET) and a method of forming are provided. A gate electrode is formed over one or more fins. Notches are formed in the ends of the gate electrode along a base of the gate electrode. Optionally, an underlying dielectric layer, such as a shallow trench isolation, may be recessed under the notch, thereby reducing gap fill issues. | 2014-09-11 |
20140252487 | Gate Security Feature - An anti-counterfeiting security circuit is incorporated into an authentic integrated circuit device to induce failure in a counterfeited integrated circuit device by forming the security circuit (e.g., | 2014-09-11 |
20140252488 | Channel Epitaxial Regrowth Flow (CRF) - A Fin-FET fabrication approach and structure are provided using channel epitaxial regrowth flow (CRF). The method includes forming a Fin-FET structure including a Si line on a substrate, shallow trench isolation (STI) oxide on both sides of the Si line on the substrate, and a poly wall on top of and across the STI oxide and the Si line, wherein the Si line is higher than the STI oxide from the substrate. The method further includes thinning the STI oxide and the Si line while maintaining about the same height ratio of the Si line and the STI oxide, and forming a spacer wall adjacent to both sides of the poly wall and further adjacent to Si and STI oxide side walls under the poly wall uncovered due thinning the STI oxide and the Si line. | 2014-09-11 |
20140252489 | FinFET with Rounded Source/Drain Profile - A method of forming a FinFET with a rounded source/drain profile comprises forming a fin in a substrate, etching a source/drain recess in the fin, forming a plurality of source/drain layers in the source/drain recess; and etching at least one of the plurality of source/drain layers. The source/drain layers may be a silicon germanium compound. Etching at the source/drain layers may comprises partially etching each of the plurality of source/drain layers prior to forming subsequent layers of the plurality of source/drain layers. The source/drain layers may be formed with a thickness at a top corner of about 15 nm, and the source/drain layers may each be etched back by about 3 nm prior to forming subsequent layers of the plurality of source/drain layers. Forming the plurality of source/drain layers optionally comprises forming at least five source/drain layers. | 2014-09-11 |
20140252490 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device including a semiconductor device including a substrate, a nitride semiconductor layer formed over the substrate and including an active region and an element isolation region, inert atoms being introduced into the element isolation region, a source electrode formed over the nitride semiconductor layer in the active region, a gate electrode formed over the nitride semiconductor layer in the active region away from the source electrode, and a drain electrode formed over the nitride semiconductor layer in the active region away from the gate electrode, the drain electrode including an end portion provided away from a boundary between the element isolation region and the active region by a first distance, wherein the first distance is greater than a second distance, the second distance being a distance where a concentration of the inert atoms diffused from the element isolation region into the active region becomes a first concentration, and an electron density in the active region at a position where the concentration of the inert atoms is higher than the first concentration is lower than an electron density in a center portion of the active region. | 2014-09-11 |
20140252491 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a semiconductor device includes a first epitaxial layer of a first material, a second epitaxial layer of a second material, a conductive material, a third epitaxial layer of the first material and a fourth epitaxial layer of the second material. The first epitaxial layer is formed in the source region and the drain region of a P-MOS transistor. The second epitaxial layer is formed in the source region and the drain region of an n-MOS transistor. The conductive material includes a gate electrode structure. The third epitaxial layer and the fourth epitaxial layer are laminated around the polysilicon. | 2014-09-11 |
20140252492 | GATE STACK INCLUDING A HIGH-K GATE DIELECTRIC THAT IS OPTIMIZED FOR LOW VOLTAGE APPLICATIONS - A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure. | 2014-09-11 |
20140252493 | GATE STACK INCLUDING A HIGH-K GATE DIELECTRIC THAT IS OPTIMIZED FOR LOW VOLTAGE APPLICATIONS - A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure. | 2014-09-11 |
20140252494 | INTEGRATED SNUBBER IN A SINGLE POLY MOSFET - Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2014-09-11 |
20140252495 | METHOD OF FORMING A CMOS STRUCTURE HAVING GATE INSULATION FILMS OF DIFFERENT THICKNESSES - The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units. | 2014-09-11 |
20140252496 | Gate Contact Structure for FinFET - An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions of sidewalls of the fin, a gate electrode over the gate dielectric, and a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width. | 2014-09-11 |
20140252497 | Isolation Region Gap Fill Method - An isolation region gap fill method comprises depositing a first dielectric material over a semiconductor device through a flowable deposition process or other gap fill deposition processes, wherein the semiconductor device includes a first FinFET comprising a plurality of first fins and a second FinFET comprising a plurality of second fins. The method further comprises removing the first dielectric material between the first FinFET and the second FinFET to form an inter-device gap, depositing a second dielectric material into the inter-device gap and applying an annealing process to the semiconductor device. | 2014-09-11 |
20140252498 | METHOD FOR FABRICATING A FIELD EFFECT TRANSISTOR, AND FIELD EFFECT TRANSISTOR - In a method for fabricating a field effect transistor, a first source/drain region and a second source/drain region are formed in a substrate. A channel region is formed between the first source/drain region and the second source/drain region. A gate region is formed on the channel region. Micro-cavities are formed in the substrate at least below the channel region, and the micro-cavities are oxidized. | 2014-09-11 |
20140252499 | Metal-Oxide-Semiconductor Field-Effect Transistor with Extended Gate Dielectric Layer - A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain, and a gate dielectric layer disposed between the substrate and the gate electrode. At least a portion of the gate dielectric layer is extended beyond the gate electrode toward at least one of the source or the drain. | 2014-09-11 |
20140252500 | SACRIFICIAL REPLACEMENT EXTENSION LAYER TO OBTAIN ABRUPT DOPING PROFILE - At least one gate structure having a first spacer located on a vertical sidewall thereof is provided on an uppermost surface of a semiconductor substrate. Exposed portions of the semiconductor substrate are then removed utilizing the at least one gate structure and first spacer as an etch mask. A sacrificial replacement material is formed on each recessed surface of the semiconductor substrate. Next, a second spacer is formed contacting the first spacer. Source/drain trenches are then provided by removing exposed portions of the sacrificial replacement material and an underlying portion of the semiconductor substrate. Remaining sacrificial replacement material located beneath the second spacer is removed providing an opening beneath the second spacer. A doped semiconductor material is formed within the source/drain trenches and the opening. | 2014-09-11 |
20140252501 | SACRIFICIAL REPLACEMENT EXTENSION LAYER TO OBTAIN ABRUPT DOPING PROFILE - At least one gate structure having a first spacer located on a vertical sidewall thereof is provided on an uppermost surface of a semiconductor substrate. Exposed portions of the semiconductor substrate are then removed utilizing the at least one gate structure and first spacer as an etch mask. A sacrificial replacement material is formed on each recessed surface of the semiconductor substrate. Next, a second spacer is formed contacting the first spacer. Source/drain trenches are then provided by removing exposed portions of the sacrificial replacement material and an underlying portion of the semiconductor substrate. Remaining sacrificial replacement material located beneath the second spacer is removed providing an opening beneath the second spacer. A doped semiconductor material is formed within the source/drain trenches and the opening. | 2014-09-11 |
20140252502 | MULTILAYER DIELECTRIC STRUCTURES FOR SEMICONDUCTOR NANO-DEVICES - Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers. | 2014-09-11 |
20140252503 | MULTI-PLASMA NITRIDATION PROCESS FOR A GATE DIELECTRIC - A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric. | 2014-09-11 |
20140252504 | Method for Fabricating a Semiconductor Device - A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well. | 2014-09-11 |
20140252505 | SEMICONDUCTOR ANALYSIS MICROCHIP AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor analysis microchip configured to detect a fine particle in a sample liquid, including a semiconductor substrate, a first flow channel provided in the semiconductor substrate, to which the sample liquid is introduced, and a pore provided in the first flow channel and configured to pass the fine particle in the sample liquid. | 2014-09-11 |
20140252506 | SEMI-CONDUCTOR SENSOR FABRICATION - Methods of fabricating semiconductor sensor devices include steps of fabricating a hermetically sealed MEMS cavity enclosing a MEMS sensor, while forming conductive vias through the device. The devices include a first semi-conductor layer defining at least one conductive via lined with an insulator and having a lower insulating surface; a central dielectric layer above the first semiconductor layer; a second semiconductor layer in contact with the at least one conductive via, and which defines a MEMS cavity; a third semiconductor layer disposed above the second semiconductor layer, and which includes a sensor element aligned with the MEMS cavity; a cap bonded to the third semiconductor to enclose and hermetically seal the MEMS cavity; wherein the third semiconductor layer separates the cap and the second semiconductor layer. | 2014-09-11 |
20140252507 | SELF-SEALING MEMBRANE FOR MEMS DEVICES - Embodiments of the present disclosure are related to MEMS devices having a suspended membrane that are secured to and spaced apart from a substrate with a sealed cavity therebetween. The membrane includes openings with sidewalls that are closed by a dielectric material. In various embodiments, the cavity between the membrane and the substrate is formed by removing a sacrificial layer through the openings. In one or more embodiments, the openings in the membrane are closed by depositing the dielectric material on the sidewalls of the openings and the upper surface of the membrane. | 2014-09-11 |
20140252508 | MEMS Device with a Capping Substrate - An integrated circuit device includes a dielectric layer disposed onto a first substrate, the dielectric layer having a sacrificial cavity formed therein. The circuit also includes a membrane layer formed onto the dielectric layer and suspended over the sacrificial cavity, and a capping substrate bonded to the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity though a via formed into the membrane layer. | 2014-09-11 |
20140252509 | MEMS DEVICE AND CORRESPONDING MICROMECHANICAL STRUCTURE WITH INTEGRATED COMPENSATION OF THERMO-MECHANICAL STRESS - A micromechanical structure of a MEMS device, integrated in a die of semiconductor material provided with a substrate and having at least a first axis of symmetry lying in a horizontal plane, has a stator structure, which is fixed with respect to the substrate, and a rotor structure, having a suspended mass, mobile with respect to the substrate and to the stator structure as a result of an external action, the stator structure having fixed sensing electrodes capacitively coupled to the rotor structure; a compensation structure is integrated in the die for compensation of thermo-mechanical strains. The compensation structure has stator compensation electrodes, which are fixed with respect to the substrate, are capacitively coupled to the rotor structure, and are arranged symmetrically to the fixed sensing electrodes with respect to the first axis of symmetry. | 2014-09-11 |
20140252510 | SIGNAL BOOSTING APPARATUS AND METHOD OF BOOSTING SIGNALS - A signal boosting apparatus and a method of boosting signals applied in the MEMS are disclosed. The signal boosting apparatus includes a substrate, an oxide layer, and a signal transmission layer. The substrate has a doped region. The doped region has a plurality of conductive carriers. These conductive carriers have the same polarity as an electronic signal. The oxide layer is located on the substrate, and the signal transmission layer is located on the oxide layer. The signal transmission layer can receive and boost the electronic signal. | 2014-09-11 |
20140252511 | MEMS APPARATUS - A MEMS apparatus includes a pillar, a supporter, and a solder. The pillar has a first side and a second side opposite to the first side. The supporter supports the pillar. The supporter is adjacent to the pillar, but the supporter is not connected to the pillar. The supporter has a third side and a fourth side opposite to the third side. The supporter includes a plurality of first confined layers and a plurality of second confined layers. These first confined layers and these second confined layers are overlapped with each other. The second side and the third side are adjacent to each other. The solder is located between the second side and the third side. The solder is also located at the first side and the fourth side. The solder is utilized to combine the pillar and the supporter. The solder also isolates the pillar and the supporter. | 2014-09-11 |
20140252512 | Methods And Apparatus For MEMS Structure Release - Methods and apparatus for MEMS release are disclosed. A method is described including providing a substrate including at least one MEMS device supported by a sacrificial layer; performing an etch in solution to remove the sacrificial layer from at least one MEMS device; immersing the substrate including the at least one MEMS device in an organic solvent; and while the substrate is immersed in the organic solvent, removing water from the organic solvent until the water remaining in the organic solvent is less than a predetermined threshold. An apparatus is disclosed for performing the methods. Additional alternative methods are disclosed. | 2014-09-11 |
20140252513 | Elongated Magnetoresistive Tunnel Junction Structure - A Magnetoresistive Tunnel Junction (MTJ) device includes an elongated MTJ structure formed onto a substrate, the MTJ structure including a magnetic reference layer and a tunnel barrier layer. The MTJ device also includes a number of discrete free magnetic regions disposed onto the tunnel barrier layer. The ratio of length to width of the elongated MTJ structure is such that the magnetic field of the magnetic reference layer is pinned in a single direction. | 2014-09-11 |
20140252514 | MAGNETIC SENSOR AND METHOD OF FABRICATING THE SAME - Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface. | 2014-09-11 |
20140252515 | MAGNETIC ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF - A magnetic electronic device comprises a substrate, a buffer layer, a first CoFeB layer, a first metal oxidation layer and a capping layer. The buffer layer is disposed above the substrate. The first CoFeB layer is disposed above the buffer layer. The first metal oxidation layer is disposed above the first CoFeB layer. The capping layer is disposed above the first metal oxidation layer and covers the first metal oxidation layer. A manufacturing method of the magnetic electronic device is also disclosed. | 2014-09-11 |
20140252516 | Magnetic Random Access Memory Cells with Isolating Liners - A manufacturing method to form a memory device includes forming a hard mask on a magnetic stack. A first magnetic stack etch is performed to form exposed magnetic layers. A liner is applied to the exposed magnetic layers to form protected magnetic layers. A second magnetic stack etch forms a magnetic random access memory (MRAM) cell, where the liner prevents shunting between the protected magnetic layers. | 2014-09-11 |
20140252517 | Thin Seeded Antiferromagnetic Coupled Side Shield for Sensor Biasing Applications - A composite side shield structure is disclosed for providing biasing to a free layer in a sensor structure. The sensor is formed between a bottom shield and top shield each having a magnetization in a first direction that is parallel to an ABS. The side shield is stabilized by an antiferromagnetic (AFM) coupling scheme wherein a bottom (first) magnetic layer is AFM coupled to a second magnetic layer which in turn is AFM coupled to an uppermost (third) magnetic layer. First and third magnetic layers each have a magnetization aligned in the first direction and are coupled to bottom and top shields, respectively, for additional stabilization. The top shield may be modified to include an AFM scheme for providing additional stabilization and guidance to magnetic moments within AFM coupled magnetic layers in the top shield, and to the third magnetic layer in the side shield. | 2014-09-11 |
20140252518 | High Moment Wrap-Around Shields for Magnetic Read Head Improvements - A wrap around shield structure is disclosed for biasing a free layer in a sensor and includes a bottom shield, side shields, and top shield in which each shield element comprises a high moment layer with a magnetization saturation greater than that of Ni | 2014-09-11 |
20140252519 | MAGNETORESISTIVE STRUCTURES, MAGNETIC RANDOM-ACCESS MEMORY DEVICES INCLUDING THE SAME AND METHODS OF MANUFACTURING THE MAGNETORESISTIVE STRUCTURE - Magnetoresistive structures, magnetic random-access memory devices including the same, and methods of manufacturing the magnetoresistive structure, include a first magnetic layer having a magnetization direction that is fixed, a second magnetic layer corresponding to the first magnetic layer, wherein a magnetization direction of the second magnetic layer is changeable, and a magnetoresistance (MR) enhancing layer and an intermediate layer both between the first magnetic layer and the second magnetic layer. | 2014-09-11 |
20140252520 | NEUTRON-DETECTING APPARATUSES AND METHODS OF FABRICATION - Neutron-detecting structures and methods of fabrication are provided which include: a substrate with a plurality of cavities extending into the substrate from a surface; a p-n junction within the substrate and extending, at least in part, in spaced opposing relation to inner cavity walls of the substrate defining the plurality of cavities; and a neutron-responsive material disposed within the plurality of cavities. The neutron-responsive material is responsive to neutrons absorbed for releasing ionization radiation products, and the p-n junction within the substrate spaced in opposing relation to and extending, at least in part, along the inner cavity walls of the substrate reduces leakage current of the neutron-detecting structure. | 2014-09-11 |
20140252521 | Image Sensor with Improved Dark Current Performance - Provided is a semiconductor image sensor device. The image sensor device includes a semiconductor substrate having a first side and a second side opposite the first side. The semiconductor substrate contains a radiation-sensing region configured to sense radiation projected toward the substrate from the second side. A first layer is disposed over the second side of the semiconductor substrate. The first layer has a first energy band gap. A second layer is disposed over the first layer. The second layer has a second energy band gap. A third layer is disposed over the second layer. The third layer has a third energy band gap. The second energy band gap is smaller than the first energy band gap and the third energy band gap. | 2014-09-11 |
20140252522 | CAMERA MODULE - In a camera module, a planar part, which is for mitigating deformation of the surface of a second insulating portion on which an imaging device is mounted, is embedded in the second insulating portion of a substrate so as to face the imaging device mounted on the surface (top surface) of the second insulating portion. | 2014-09-11 |
20140252523 | Backside Structure and Methods for BSI Image Sensors - A back side image sensor and method of manufacture are provided. In an embodiment a bottom anti-reflective coating is formed over a substrate, and a metal shield layer is formed over the bottom anti-reflective coating. The metal shield layer is patterned to form a grid pattern over a sensor array region of the substrate, and a first dielectric layer and a second dielectric layer are formed to at least partially fill in openings within the grid pattern. | 2014-09-11 |
20140252524 | ARRAY OF MUTUALLY ISOLATED, GEIGER-MODE, AVALANCHE PHOTODIODES AND MANUFACTURING METHOD THEREOF - An embodiment of array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type and housing an anode region, of a second conductivity type, facing a top surface of the body, a cathode-contact region, having the first conductivity type and a higher doping level than the body, facing a bottom surface of the body, an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the anode region and the cathode-contact region. The insulation region is formed by a first mirror region of polycrystalline silicon, a second mirror region of metal material, and a channel-stopper region of dielectric material, surrounding the first and second mirror regions. | 2014-09-11 |
20140252525 | METHOD FOR FORMING STRUCTURE FOR REDUCING NOISE IN CMOS IMAGE SENSORS - A method and device is disclosed for reducing noise in CMOS image sensors. An improved CMOS image sensor includes a light sensing structure surrounded by a support feature section. An active section of the light sensing structure is covered by no more than optically transparent materials. A light blocking portion includes an opaque layer or a black light filter layer in conjunction with an opaque layer, covering the support feature section. The light blocking portion may also cover a peripheral portion of the light sensing structure. The method for forming the CMOS image sensors includes using film patterning and etching processes to selectively form the opaque layer and the black light filter layer where the light blocking portion is desired, but not over the active section. The method also provides for forming microlenses over the photosensors in the active section. | 2014-09-11 |
20140252526 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, AND ELECTRONIC APPARATUS - A method of manufacturing a semiconductor device includes: forming, on a cover glass, a film having a predetermined specific gravity and configured to shield an alpha ray that arises from the cover glass; and bonding the cover glass on which the film is formed and an image pickup device, by filling a transparent resin between the cover glass and the image pickup device. | 2014-09-11 |
20140252527 | SOLID-STATE IMAGING ELEMENT, METHOD FOR MANUFACTURING SOLID-STATE IMAGING ELEMENT, AND ELECTRONIC DEVICE - A solid-state imaging element including: a sensor substrate in which a photoelectric conversion section is arranged and formed; a circuit substrate in which a circuit for driving the photoelectric conversion section is formed, the circuit substrate being laminated to the sensor substrate; a sensor side electrode drawn out to a surface of the sensor substrate on a side of the circuit substrate and formed as one of a projection electrode and a depression electrode; and a circuit side electrode drawn out to a surface of the circuit substrate on a side of the sensor substrate, formed as one of the depression electrode and the projection electrode, and joined to the sensor side electrode in a state of the circuit side electrode and the sensor side electrode being fitted together. | 2014-09-11 |
20140252528 | SEMICONDUCTOR PHOTODETECTOR AND METHOD FOR MANUFACTURING THE SAME - In order to improve reliability by preventing an edge breakdown in a semiconductor photodetector having a mesa structure such as a mesa APD, the semiconductor photodetector comprises a mesa structure formed on a first semiconductor layer of the first conduction type formed on a semiconductor substrate, the mesa structure including a light absorbing layer for absorbing light, an electric field buffer layer for dropping an electric field intensity, an avalanche multiplication layer for causing avalanche multiplication to occur, and a second semiconductor layer of the second conduction type, wherein the thickness of the avalanche multiplication layer at the portion in the vicinity of the side face of the mesa structure is made thinner than the thickness at the central portion of the mesa structure. | 2014-09-11 |
20140252529 | Pb-salt Mid-infrared Detectors and Method for Making Same - The disclosure describes methods for preparing lead salt materials which are sensitive to the mid-infrared spectrum which can be used to manufacture high-uniformity, high-detectivity, polycrystalline lead salt photoconductive and photovoltaic photodetectors. | 2014-09-11 |
20140252530 | Structure and Method of Fabricating a CZTS Photovoltaic Device by Electrodeposition - Techniques for using electrodeposition to form absorber layers in diodes (e.g., solar cells) are provided. In one aspect, a method for fabricating a diode is provided. The method includes the following steps. A substrate is provided. A backside electrode is formed on the substrate. One or more layers are electrodeposited on the backside electrode, wherein at least one of the layers comprises copper, at least one of the layers comprises zinc and at least one of the layers comprises tin. The layers are annealed in an environment containing a sulfur source to form a p-type CZTS absorber layer on the backside electrode. An n-type semiconductor layer is formed on the CZTS absorber layer. A transparent conductive layer is formed on the n-type semiconductor layer. A diode is also provided. | 2014-09-11 |
20140252531 | SYSTEMS AND METHODS FOR HARVESTING DISSIPATED HEAT FROM INTEGRATED CIRCUITS (ICS) IN ELECTRONIC DEVICES INTO ELECTRICAL ENERGY FOR PROVIDING POWER FOR THE ELECTRONIC DEVICES - Systems and methods for harvesting dissipated heat from integrated circuits (ICs) in electronic devices into electrical energy for providing power for the electronic devices are disclosed. In one embodiment, energy transferred from one or more ICs in the form of dissipated heat is harvested to convert at least a portion of this dissipated heat into electricity. This power can be used to provide power to the ICs to reduce overall power consumption by the electronic device. The harvested dissipated heat can be supplied to ICs in the electronic device to provide power to the ICs. Alternatively, or in addition, the harvested dissipated heat can be stored in an energy storage device to provide power to the ICs at a later time. | 2014-09-11 |
20140252532 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening. | 2014-09-11 |
20140252533 | INSULATING STRUCTURE, A METHOD OF FORMING AN INSULATING STRUCTURE, AND A CHIP SCALE ISOLATOR INCLUDING SUCH AN INSULATING STRUCTURE - A method of forming an insulating structure, comprising forming an insulating region comprising at least one electrical or electronic component or part thereof embedded within the insulating region, and forming a surface structure in a surface of the insulating region. | 2014-09-11 |
20140252534 | METHOD OF MAKING DEEP TRENCH, AND DEVICES FORMED BY THE METHOD - A method for forming a semiconductor device includes providing a semiconductor-on-insulator (SOI) structure, and forming at least one hard mask (HM) layer over the SOI structure. The SOI structure includes an insulator layer and a semiconductor layer over the insulator layer. The method further comprises forming a trench inside the at least one HM layer and the semiconductor layer, and depositing a spacer layer in the trench. The spacer layer comprises a bottom surface portion over the bottom surface of the trench, and a side wall portion along the side wall of the trench. The method further comprises etching the bottom surface portion of the spacer layer while the side wall portion of the spacer layer remains, and etching the insulator layer to extend the trench into the insulator layer. | 2014-09-11 |
20140252535 | Integrated Passive Device Having Improved Linearity and Isolation - Disclosed is a structure for improved electrical signal isolation in a semiconductor substrate between integrated passive devices (IPDs) and an associated method for the structure's fabrication. The structure includes an amorphized region in the semiconductor substrate, a dielectric layer formed over the amorphized region, and IPDs formed over the dielectric layer. The amorphized region is not recrystallized and may be formed by utilizing an inert implant that does not charge-dope the amorphized region, while forming a plurality of charge carrier traps at an interface between the amorphized region and the dielectric layer to prevent a parasitic conduction layer from forming at the interface. The inert implant may include one of Argon, Xenon and Germanium. In many implementations, the structure does not include an active device. | 2014-09-11 |
20140252536 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes line patterns disposed on a substrate, the line patterns extending in a first direction and being parallel to one another. The semiconductor device includes conductive patterns spaced apart from each other in the first direction between an adjacent pair of the line patterns. The semiconductor device includes insulating fences electrically isolating the conductive patterns from each other and having chamfered corners. The semiconductor device includes insulating patterns filling gaps between side surfaces of the line patterns and the chamfered corners of the insulating fences. | 2014-09-11 |
20140252537 | PACKAGE ARRANGEMENT AND A METHOD OF MANUFACTURING A PACKAGE ARRANGEMENT - In various embodiments, a package arrangement is provided. The package arrangement may include a first package. The package arrangement may further include a through hole package including at least one contact terminal. The first package may include at least one hole in an encapsulant to receive the at least one contact terminal of the through hole package. The received at least one contact terminal may provide a solder contact. | 2014-09-11 |
20140252538 | ELECTRONIC FUSE WITH RESISTIVE HEATER - A method of forming an electronic fuse including forming an M | 2014-09-11 |
20140252539 | PLANAR POLYSILICON REGIONS FOR PRECISION RESISTORS AND ELECTRICAL FUSES AND METHOD OF FABRICATION - A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections. | 2014-09-11 |
20140252540 | Semiconductor Device and Method of Manufacturing Thereof - A semiconductor device includes a semiconductor substrate having a first main surface in which a recess is formed. Further, the semiconductor device includes an electrical interconnect structure which is arranged at a bottom of the recess. A semiconductor chip is located in the recess. The semiconductor chip includes a plurality of chip electrodes facing the electrical interconnect structure. Further, a plurality of electrically conducting elements is arranged in the electrical interconnect structure and electrically connected to the plurality of chip electrodes. | 2014-09-11 |
20140252541 | SYSTEMS AND METHODS FOR POWER TRAIN ASSEMBLIES - A power train assembly is provided. The power train assembly includes a component package including a first transistor having a first gate, a first drain, and a first source, a second transistor having a second gate, a second drain, and a second source, and a thermal pad configured to dissipate heat generated in the component package, wherein the thermal pad is electrically coupled to the first source and the second drain. The power train assembly further includes a printed circuit board (PCB) electrically coupled to the component package, and an electrical component electrically coupled directly to the thermal pad, wherein the electrical component is external to the component package. | 2014-09-11 |
20140252542 | Structure and Method for an Inductor With Metal Dummy Features - The present disclosure provides a semiconductor device. The semiconductor device includes an inductor formed on a substrate and configured to be operable with a current of a frequency; and dummy metal features configured between the inductor and the substrate, the dummy metal features having a first width less than 2 times of a skin depth associated with the frequency. | 2014-09-11 |
20140252543 | METAL-OXIDE-METAL (MOM) CAPACITOR WITH ENHANCED CAPACITANCE - A particular metal-oxide-metal (MOM) capacitor device includes a conductive gate material coupled to a substrate. The MOM capacitor device further includes a first metal structure coupled to the conductive gate material. The MOM capacitor device further includes a second metal structure coupled to the substrate and proximate to the first metal structure. | 2014-09-11 |
20140252544 | DC/ AC DUAL FUNCTION POWER DELIVERY NETWORK (PDN) DECOUPLING CAPACITOR - Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate. | 2014-09-11 |
20140252545 | CONTACT STRUCTURE AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A semiconductor memory device includes a substrate having thereon a memory array region and a periphery circuit region. A first dielectric layer covers the memory array region and the periphery circuit region on the substrate. A second dielectric layer covers the memory array region and the periphery circuit region on the first dielectric layer. At least a capacitor structure is provided in the memory array region. The capacitor structure includes an electrode material layer embedded in the second dielectric layer. The semiconductor memory device further includes a contact structure comprising the electrode material layer. | 2014-09-11 |
20140252546 | SWITCHED CAPACITOR STRUCTURE - A capacitor structure comprising semiconductor substrate and a matrix of capacitor units formed over the semiconductor substrate each capacitor unit. The matrix includes an interior structure comprised of one or more vertical plates, each vertical plate of the interior structure formed from a plurality of conductive portions connected vertically to each other, an exterior structure comprised of one or more vertical plates, each vertical plate of the exterior structure formed from a plurality of conductive portions connected vertically to each other, the exterior structure substantially encompassing the interior structure, and insulative material separating the interior and exterior structures. The structure also comprises a switching mechanism included in the capacitor structure to switch between ones of the plural capacitor units. | 2014-09-11 |
20140252547 | SEMICONDUCTOR DEVICE HAVING INTEGRATED PASSIVE DEVICE AND PROCESS FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device and a process for fabricating the same. In one embodiment, the semiconductor device includes a substrate and a plurality of integrated passive devices. The integrated passive devices are disposed on the substrate and include at least two capacitors which have different capacitance values. | 2014-09-11 |
20140252548 | Filter and Capacitor Using Redistribution Layer and Micro Bump Layer - An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer. | 2014-09-11 |
20140252549 | Metal-Insulator-Metal Capacitor - An embodiment metal-insulator-metal (MiM) capacitor includes a gate stack disposed upon an insulation layer, the gate stack including a gate metal, the gate metal serving as a bottom electrode, a dielectric layer disposed upon the gate stack, and a top metal layer disposed upon the dielectric layer, the top metal serving as a top electrode. | 2014-09-11 |
20140252550 | STACK CAPACITOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention provides a stack capacitor structure and a manufacturing method thereof, adapted for a random access memory. The stack capacitor structure is formed on a semiconductor substrate. The stack capacitor structure includes an oxide layer and a circular-shaped stopping layer. The oxide layer is disposed on the semiconductor substrate. The oxide layer has a capacitor trench therein. The circular-shaped stopping layer surrounds an edge of an opening of the capacitor trench. The disclosed stack capacitor structure and the manufacturing method thereof may thereby prevent the occurrence of the stack capacitor structure from having CD variation and belly region causing cell to cell leakage as result of manufacturing process limitation. | 2014-09-11 |
20140252551 | Method and Apparatus for Constructing an Isolation Capacitor in an Integrated Circuit - At least one high voltage rated isolation capacitor is formed on a face of a primary integrated circuit die. The isolation capacitor AC couples the primary integrated circuit in a first voltage domain to a second integrated circuit in a second voltage domain. The isolation capacitor DC isolates the primary integrated circuit from the second integrated circuit die. | 2014-09-11 |
20140252552 | SEMICONDUCTOR DIES HAVING SUBSTRATE SHUNTS AND RELATED FABRICATION METHODS - Die structures for electronic device packages and related fabrication methods are provided. An exemplary die structure includes a substrate having a first layer of semiconductor material including a semiconductor device formed thereon, a handle layer of semiconductor material, and a buried layer of dielectric material between the handle layer and the first layer. The die structure also includes a plurality of shunting regions in the first layer of semiconductor material, wherein each shunting region includes a doped region in the first layer that is electrically connected to the handle layer of semiconductor material, and a body region underlying the doped region that is contiguous with at least a portion of the first layer underlying a semiconductor device. | 2014-09-11 |
20140252553 | WAFER STRUCTURE AND POWER DEVICE USING THE SAME - In one embodiment, a method of making a super-junction MOS transistor in a wafer can include: (i) forming a first doping layer having a high doping concentration; (ii) forming a second doping layer on the first doping layer, wherein a doping concentration of the second doping layer is less than a doping concentration of the first doping layer; (iii) forming a third doping layer on the second doping layer, wherein the third doping layer comprises an intrinsic layer; (iv) etching through the third doping layer and partially through the second doping layer to form trenches; and (v) filling the trenches to form pillar structures. | 2014-09-11 |
20140252554 | WAFER STRUCTURE AND POWER DEVICE USING THE SAME - In one embodiment, a wafer structure configured for a power device can include: (i) a first doping layer having a high doping concentration; (ii) a second doping layer on the first doping layer, where a doping concentration of the second doping layer is less than the high doping concentration; and (iii) a third doping layer on the second doping layer, where a doping concentration of the third doping layer is greater than the doping concentration of the second doping layer. For example, the power device can be part of a switching voltage regulator. | 2014-09-11 |
20140252555 | SUBSTRATE FOR FORMING ELEMENTS, AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a substrate for forming elements includes a substrate; an insulating film provided on the substrate; and a Ge layer or an SiGe layer bonded to the substrate via the insulating film. The insulating film is a laminated structure comprising a plurality of films including an oxide film, a high-dielectric constant insulating film, and a compound insulating film including a metal element and Ge. | 2014-09-11 |
20140252556 | SINGLE-MASK SPACER TECHNIQUE FOR SEMICONDUCTOR DEVICE FEATURES - A method for fabricating semiconductor features. The method includes forming a first layer over a substrate. Forming a plurality of first holes in the first layer. The first layer includes sidewalls separating at least a portion of each first hole. The first holes include overlapping holes that are not separated by the sidewalls. Forming a plurality of spacers on the substrate and first layer. The spacers include spacer sidewalls separating adjacent overlapping holes. Etching exposed portions of the substrate to form a plurality of second holes. | 2014-09-11 |
20140252557 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE STRUCTURES - Semiconductor device structures and methods for forming a semiconductor device are provided. In embodiments, one or more fins are provided, each of the one or more fins having a lower portion and an upper portion disposed on the lower portion. The lower portion is embedded in a first insulating material. The shape of the upper portion is at least one of a substantially triangular shape and a substantially rounded shape and a substantially trapezoidal shape. Furthermore, a layer of a second insulating material different from the first insulating material is formed on the upper portion. | 2014-09-11 |
20140252558 | Methods and Apparatus for Wafer Level Packaging - A semiconductor device comprises a substrate, a bond pad above the substrate, a guard ring above the substrate, and an alignment mark above the substrate, between the bond pad and the guard ring. The device may comprise a passivation layer on the substrate, a polymer layer, a post-passivation interconnect (PPI) layer in contact with the bond pad, and a connector on the PPI layer, wherein the connector is between the bond pad and the guard ring, and the alignment mark is between the connector and the guard ring. The alignment mark may be at the PPI layer. There may be multiple alignment marks at different layers. There may be multiple alignment marks for the device around the corners or at the edges of an area surrounded by the guard ring. | 2014-09-11 |