37th week of 2014 patent applcation highlights part 38 |
Patent application number | Title | Published |
20140254260 | REDUCING COUPLING NOISE DURING READ OPERATION - A method is provided for sensing data in a memory device. The memory device includes a block of memory cells coupled to a plurality of bit lines. The method includes precharging the plurality of bit lines to a first level V | 2014-09-11 |
20140254261 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND READ METHOD THEREOF - A nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array comprises a plurality of memory cells and stores initial setting data in the plurality of memory cells. The control circuit is configured to apply a first voltage to gates of the plurality of memory cells to read the initial setting data and, depending on that read result, apply a second voltage different from the first voltage to the gates of the plurality of memory cells to read the initial setting data. | 2014-09-11 |
20140254262 | INTERNAL DATA LOAD FOR NON-VOLATILE STORAGE - Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells. | 2014-09-11 |
20140254263 | Write Sequence Providing Write Abort Protection - In a multi-level cell (MLC) nonvolatile memory array, data is assigned sequentially to the lower and upper page of a word line, then both lower and upper pages are programmed together before programming a subsequent word line. Word lines of multiple planes are programmed together using latches to hold data until all data is transferred. Tail-ends of data of write commands are stored separately. | 2014-09-11 |
20140254264 | Defect Or Program Disturb Detection With Full Data Recovery Capability - A programming operation for a set of non-volatile storage elements determines whether the storage elements have been programmed properly after a program-verify test is passed and a program status=pass is issued. Write data is reconstructed from sets of latches associated with the storage elements using logical operations optionally one or more reconstruction read operations. Normal read operations are also performed to obtain read data. A number of mismatches between the read data and the reconstructed write data is determined, and determination is made as to whether re-writing of the write data is required based on the number of the mismatches. | 2014-09-11 |
20140254265 | Flash Memory Cells, NAND Cell Units, Methods of Forming NAND Cell Units, and Methods of Programming NAND Cell Unit Strings - Some embodiments include utilization of alternating first and second gate types along NAND strings, with the second gate types having floating gates thicker than floating gates of the first gate types, and capacitively coupled with control gates of the first gate types. The second gate types may be multilevel cell (MLC) devices, and pass voltage applied to the control gates of the first gate types may be utilized to reduce programming voltages utilized to reach memory states of the MLC devices. Some embodiments include NAND cell units, and some embodiments include methods of forming NAND cell units. Also, some embodiments include methods of programming NAND cell unit string gates in which programming voltage applied to a first string gate is held below a threshold, and pass voltage applied to an adjacent string gate is increased and utilized to program the first string gate. | 2014-09-11 |
20140254266 | DIRECT MULTI-LEVEL CELL PROGRAMMING - A data storage device includes a controller coupled to a non-volatile memory having a three-dimensional (3D) configuration. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage. | 2014-09-11 |
20140254267 | MEMORY DEVICES WITH DIFFERENT SIZED BLOCKS OF MEMORY CELLS AND METHODS - In an embodiment, each block of a plurality of blocks includes a respective plurality of strings of memory cells, where each of the plurality of strings of a block is coupled to a respective select transistor, and wherein each of the select transistors coupled to the plurality of strings of the block is coupled to a common first select line. The plurality of blocks includes N block sizes, where N may be an integer greater than or equal to three. N−1 blocks of one block size of the N block sizes collectively include a first number of second select lines. A group of blocks consisting of a respective block of each remaining block size of the N block sizes collectively include a second number of second select lines that is equal to the first number of select lines or that is less than the first number of second select lines. | 2014-09-11 |
20140254268 | HYBRID NON-VOLATILE MEMORY CELLS FOR SHARED BIT LINE - A non-volatile storage system includes a plurality of groups of connected non-volatile storage elements. Each group comprises multiple connected data non-volatile storage elements and multiple select gates on a common side of the data non-volatile storage elements. The multiple select gates comprise a first select gate and a second select gate. The first select gate has a first threshold voltage for a first subset of the groups and a second threshold voltage for a second subset of the groups due to active area implantation for the second subset of groups that causes the second threshold voltage to be lower than the first threshold voltage. The second select gate of each group has a programmable threshold voltage. Each of the plurality of bit lines are connected to multiple groups of connected non-volatile storage elements. | 2014-09-11 |
20140254269 | NON-VOLATILE STORAGE WITH SHARED BIT LINES AND FLAT MEMORY CELLS - A non-volatile storage system is disclosed that includes pairs (or another number) of NAND strings (or other groupings of memory cells) in the same block being connected to and sharing a common bit line. By sharing bit lines, less bit lines are needed in the storage system. Using less bit lines reduces the space needed to implement the storage system. Each NAND string will have two drain side select gates. The non-volatile storage system will have two drain side selection lines each connected to one of the two drain side select gates so that the NAND strings sharing a bit line can be individually selected. To allow proper selection of a NAND string using the select gates, the select gates will be subjected to non-volatile programming in order to set the threshold voltage of the select gates to an appropriate level. | 2014-09-11 |
20140254270 | SEMICONDUCTOR MEMORY DEVICE AND DATA WRITING METHOD OF THE SAME - A semiconductor memory device includes memory cells which are laminated on a semiconductor substrate and include charge storage layers and control gates, a plurality of word lines each of which is commonly connected to the control gates of a plurality of the memory cells, and a control unit which performs programming and verification of data in units of a page of memory cells. The control unit consecutively performs programming of data in two or more pages of memory cells connected to the same word line, and then consecutively performs verification of the data programmed in the two or more pages of memory cells connected to the same word line. | 2014-09-11 |
20140254271 | Nonvolatile Memory Device and Read Method Thereof - A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed. | 2014-09-11 |
20140254272 | SIMULTANEOUS SENSING OF MULTIPLE WORDLINES AND DETECTION OF NAND FAILURES - Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed. | 2014-09-11 |
20140254273 | METHOD AND SYSTEM FOR MINIMIZING NUMBER OF PROGRAMMING PULSES USED TO PROGRAM ROWS OF NON-VOLATILE MEMORY CELLS - A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of subsets of data that has been programmed in the row. The size of each subset corresponds to the number of read data bits coupled from the memory device, which are simultaneously applied to error checking and correcting circuitry. During iterative programming of a row of cells, the pseudo pass circuit indicates a pseudo pass condition to terminate further programming of the row if none of the subsets of data have a number of data errors that exceeds the number of data errors that can be corrected by the error checking and correcting circuitry. | 2014-09-11 |
20140254274 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell and a control circuit. The memory cell is such that a ferroelectric film is provided as a gate dielectric film. When data is stored in the memory cell, the control circuit applies a first voltage to the gate dielectric film and thereafter applies a second voltage, whose amplitude is smaller than that of the first voltage and whose polarity is opposite to that of the first voltage. | 2014-09-11 |
20140254275 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a memory cell, a word line, and a peripheral circuit are provided. In the memory cell, a ferroelectric film is provided for a gate insulating film. The word line is connected to a control gate electrode of the memory cell. In the peripheral circuit, ferroelectric films are provided for gate insulating films and the peripheral circuit is provided near the memory cell. Here, between the same conductive type transistors of the peripheral circuit, a channel impurity concentration of a transistor to which a driving voltage which drives the word line is applied is different from a channel impurity concentration of a transistor to which a voltage which is lower than the driving voltage is applied. | 2014-09-11 |
20140254276 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device comprises memory cells each which stores data with two or more levels. Each of the memory cells includes a semiconductor layer, a first insulating layer on the semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer, and the second insulating layer includes a ferroelectric layer. | 2014-09-11 |
20140254277 | Method And Apparatus For Program And Erase Of Select Gate Transistors - Techniques are provided for programming and erasing of select gate transistors in connection with the programming or erasing of a set of memory cells. In response to a program command to program memory cells, the select gate transistors are read to determine whether their Vth is below an acceptable range, in which case the select gate transistors are programmed before the memory cells. Or, a decision can be made to program the select gate transistors based on a count of program-erase cycles, whether a specified time period has elapsed and/or a temperature history of the non-volatile storage device. When an erase command is made to erase memory cells, the select gate transistors are read to determine whether their Vth is above an acceptable range. If their Vth is above the acceptable range, the select gate transistors can be erased concurrently with the erasing of the memory cells. | 2014-09-11 |
20140254278 | Writing Data To A Thermally Sensitive Memory Device - Writing data to a thermally sensitive memory device, including: receiving a physical layout of the thermally sensitive memory device; receiving the direction of airflow across the thermally sensitive memory device; selecting an address for writing data to the thermally sensitive memory device in dependence upon the physical layout of the thermally sensitive memory device and the direction of airflow across the thermally sensitive memory device; and writing data to the selected address of the thermally sensitive memory device. | 2014-09-11 |
20140254279 | Writing Data To A Thermally Sensitive Memory Device - Writing data to a thermally sensitive memory device, including: receiving a physical layout of the thermally sensitive memory device; receiving the direction of airflow across the thermally sensitive memory device; selecting an address for writing data to the thermally sensitive memory device in dependence upon the physical layout of the thermally sensitive memory device and the direction of airflow across the thermally sensitive memory device; and writing data to the selected address of the thermally sensitive memory device. | 2014-09-11 |
20140254280 | Programming Method For Memory Cell - A method for programming memory cells includes applying a programming voltage to a selected memory cell in a memory cell array and a neighboring passing voltage to a neighboring memory cell next to the selected memory cell, increasing the programming voltage for programming the selected memory cell, and increasing the neighboring passing voltage for programming the selected memory cell. | 2014-09-11 |
20140254281 | 3D NON-VOLATILE MEMORY DEVICE AND METHOD FOR OPERATING AND FABRICATING THE SAME - A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line. | 2014-09-11 |
20140254282 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage. | 2014-09-11 |
20140254283 | Programming Select Gate Transistors And Memory Cells Using Dynamic Verify Level - Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration. | 2014-09-11 |
20140254284 | WORD LINE DRIVER CIRCUIT FOR SELECTING AND DESELECTING WORD LINES - A memory circuit includes word lines coupled to a memory array, including a first set of one or more word lines deselected in an erase operation, and a second set of one or more word lines selected in the erase operation. Control circuitry couples the first set of one or more word lines deselected in the erase operation to a reference voltage, responsive to receiving an erase command for the erase operation. Some examples further include a first transistor that switchably couples a word line to a global word line, and a second transistor that switchably couples the word line to a ground voltage. The control circuitry is coupled to the first transistor and the second transistor, wherein the control circuitry has a plurality of modes including at least an erase operation. In a first mode, the first transistor couples the word line to the global word line, and the second transistor decouples the word line from the ground voltage. In a second mode, the first transistor decouples the word line from the global word line, and the second transistor couples the word line to the ground voltage. | 2014-09-11 |
20140254285 | Temperature-Based Adaptive Erase or Program Parallelism - A method includes, in one implementation, performing a memory operation to place memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the operation is performed on the memory cells using the voltage of the charge pump. A temperature of the memory array is compared to a threshold. If the temperature is above a reference level, a load on the charge pump is reduced by providing the voltage to only a reduced number of memory cells. | 2014-09-11 |
20140254286 | THERMAL ANNEAL USING WORD-LINE HEATING ELEMENT - In response to detecting an event during operation of an integrated-circuit memory device containing charge-storing memory cells, an electric current is enabled to flow through a word line coupled to the charge-storing memory cells for a brief interval to heat the charge-storing memory cells to an annealing temperature range. | 2014-09-11 |
20140254287 | SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF CONTROLLING READ COMMAND - The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode. | 2014-09-11 |
20140254288 | Pipelining in a Memory - A system including a memory cell array including a plurality of memory cells, and a writing device to generate multiple back-to-back write pulses to write to target memory cells from among the plurality of memory cells, the multiple back-to-back write pulses overlapping during an overlap duration, the overlap duration being adjustable based on a performance parameter of the memory cell array. | 2014-09-11 |
20140254289 | DATA CIRCUIT - A circuit includes a first plurality of memory cells coupled with a first data line and a first data transfer circuit coupled with the first data line and a second data line. In a first operation mode of the circuit, the first data line is left floating and is caused to have a first logical value by a current in at least one memory cell of the first plurality of memory cells. In a second operation mode of the circuit, the first data line is configured to reflect data stored in a memory cell of the plurality of memory cells, and the second data line is configured to reflect the data on the first data line through the first data transfer circuit. | 2014-09-11 |
20140254290 | Local Evaluation Circuit for Static Random-Access Memory - A local evaluation circuit for a memory array includes first and second NAND gates and first, second, third, and fourth switches. The first switch is configured to couple a first node of the second NAND gate to a first power supply node in response to a first read signal. The second switch is configured to couple a first node of the first NAND gate to the first power supply node in response to a second read signal. The third switch is configured to couple a second node of the first NAND gate to a second power supply node in response to the first read signal. The fourth switch is configured to couple a second node of the second NAND gate to the second power supply node in response to the second read signal. | 2014-09-11 |
20140254291 | MEMORY STATE SENSING BASED ON CELL CAPACITANCE - A memory cell and method for operating a memory cell including a bidirectional access device and memory element electrically coupled in series. The bidirectional access device includes a tunneling capacitance. The memory element programmable to a first and second state by application of a first and second write voltage opposite in polarity to one another. The memory element has a lower capacitance in the first state than the second state. A read unit senses a transient read current due to a voltage drop upon application of a read voltage. Determining if the memory element is the first or second state is based on whether the read current is greater or less than a sense threshold. The sense threshold is based on a capacitance ratio between the first and second state. | 2014-09-11 |
20140254292 | OVERLAPPING INTERCONNECT SIGNAL LINES FOR REDUCING CAPACITIVE COUPLING EFFECTS - Described herein are various principles for designing, manufacturing, and operating integrated circuits having functional components and one or more metal interconnect layers, where the dimensions of signal lines of the metal interconnect layers are larger than dimensions of the functional components. In some embodiments, a signal line may have a width greater than a width of a terminal of a functional component to which the signal line is connected. In some embodiments, two functional components formed in a same functional layer of the integrated circuit may be connected to metal signal lines in different metal interconnect layers. Further, the metal signal lines of the different metal interconnect layers may overlap some distance. | 2014-09-11 |
20140254293 | HIGH-SPEED MEMORY WRITE DRIVER CIRCUIT WITH VOLTAGE LEVEL SHIFTING FEATURES - Various aspects of a fast, energy efficient write driver capable of efficient operation in a dual-voltage domain memory architecture are provided herein. Specifically, various aspects of the write driver described herein combine a high speed driver with voltage level shifting capabilities that may be implemented efficiently in reducing use of silicon area while using lower power. The write driver circuit shifts or adjusts voltage levels between a first voltage domain to a second voltage domain. In one example, the write driver circuit is coupled to a global write bitline and a local write bitline that is coupled to one or more bitcells (of SRAM memory). The write driver circuit converts a first voltage level at the global write bitline to a second voltage level at the local write bitline during a write operation. | 2014-09-11 |
20140254294 | MEMORY CONTROLLER FOR STROBE-BASED MEMORY SYSTEMS - An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal. | 2014-09-11 |
20140254295 | MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A memory device is provided. The memory device includes programming first bit data into a plurality of memory cells; identifying target memory cells which are in a first state and whose threshold voltages are equal to or greater than a first voltage from the memory cells programmed with the first bit data; receiving second bit data which is to be programmed into the memory cells; calculating a plurality of third bit data by performing a first process on the second bit data; selecting third bit data which changes a largest number of target memory cells from the first state to a second state in response to the memory cells being programmed with each of the plurality of third bit data from the plurality of third bit data; and programming the selected third bit data into the memory cells. | 2014-09-11 |
20140254296 | Bit Based Fuse Repair - In accordance with some embodiments, instead of providing replacement rows, an area within a fuse array may be reserved for storing addresses of bits that are defective. Then these bits can be readily repaired by simply reading the stored state of identified defective bit, and inverting the stored state of the identified defective bit to get the correct output. | 2014-09-11 |
20140254297 | METHOD AND APPARATUS FOR MEMORY REPAIR - An integrated circuit includes an array of memory cells that is arranged into rows, main columns, and redundant columns that perform repairs in the array. The main columns and the redundant columns are divided into row blocks. Bit lines couple the main columns to status memory indicating repair statuses of the repairs by the redundant columns. The integrated circuit receives a command, and performs an update on the status memory with the repair statuses specific to particular ones of the row blocks in a portion of the memory accessed by the command. Alternatively or in combination, the status memory has insufficient size to store the repair statuses of multiple ones of the row blocks of the main columns. | 2014-09-11 |
20140254298 | VARIABLE DYNAMIC MEMORY REFRESH - A system and method are provided for refreshing a dynamic memory. A first region of a memory is refreshed at a first refresh rate and a second region of the memory is refreshed at a second refresh rate that is different than the first refresh rate. A memory controller is configured to refresh the first region of a memory at the first refresh rate and refresh the second region of the memory at the second refresh rate. | 2014-09-11 |
20140254299 | ROBUST MEMORY START-UP USING CLOCK COUNTER - In accordance with at least one embodiment, a clock counter on a system (for example, a system-on-a-chip (SOC) or other system) is utilized to count a number of a clock edges of a memory clock within a predefined time based on a predetermined system clock frequency and, therefore, to determine whether the memory clock for a memory array (for example, a non-volatile memory (NVM) array or other memory array) is correct or not. The system is directed to wait until the count is within an expected range before moving to the next step in a start-up procedure. If the maximum allowed start-up time is exceeded, an error signal is sent to the system such that the application can react to it. | 2014-09-11 |
20140254300 | DEVICES AND SYSTEM PROVIDING REDUCED QUANTITY OF INTERCONNECTIONS - Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections. | 2014-09-11 |
20140254301 | Shearing Paddles in a Drum Mixer for Low Slump Concrete - A batch mixer for mixing concrete materials into a mixed concrete includes a mixing drum having a plurality of paddles fixed to the drum for rotation with the mixing drum about the longitudinal axis of the mixing drum. The paddles include mixing paddles oriented to urge the concrete materials away from the outlet opening at the second end of the drum when the mixing drum is rotated in the mixing direction, and at least one shearing paddle which is oriented at less than 25 degrees from the longitudinal direction of the mixing drum. The shearing paddles has a main body portion interrupted by shearing apertures through which concrete material are directed and an inner edge which is discontinuous and interrupted by longitudinally spaced teeth. | 2014-09-11 |
20140254302 | STRUCTURE OF PRESS-TO-OPERATE STIRRING CONTAINER - A press-to-operate stirring container includes a container, a fixing base, a rotating device, an actuation member, and an elastic body. The rotating device is mounted in the fixing base and includes a rotor having a unidirectional rotation driving member coupled to the container so that the container is driven by the rotor to rotate unidirectionally. The actuation member is arranged vertical in the fixing base and is depressible for driving the rotating device. The elastic body helps position returning of the actuation member. As such, a user is allowed to easily control the container to rotate through a pressing-down operation so as to apply effects of stirring and reducing temperature of the substance (such as liquid) received and held in the container. Further, the actuation member can readily keep the container continuously rotating thereby achieving convenient and effective control of stirring speed of the container. | 2014-09-11 |
20140254303 | MIXING SYRINGE - A movable mixing disc may be utilized in connection with a syringe. The mixing disc may comprise a hole which may be covered by a fine screen or coupled to a porous member, allowing only certain elements of a solution to pass through the mixing disc. Actuation of a plunger of the syringe may cause liquid to emerge from the mixing disc hole as a high velocity jet or other turbulent flow, stirring up any settled particles on a distal side of the mixing disc. As the ejection continues, the mixing disc may be pushed forward by the plunger in order to eliminate any unused volume. Also, the mixing disc may be moved forward by virtue of a pressure difference created by a pressure drop across the mixing disc, such as a pressure drop created as the plunger is displaced to induce fluid flow across the mixing disc. | 2014-09-11 |
20140254304 | DISPOSABLE BEVERAGE CUP - A disposable beverage cup, comprising: a wall, in a form of a rolled foil; a bottom; and a mixing device made of substantially the same material as the wall, the mixing device comprising: an adherent strip adhered at a relatively low portion of the wall; a movable flap, extending from the adherent strip, for mixing a beverage; and a tab, extending from the flap substantially to a top of the cup, for moving said flap, wherein a mixing capability of the movable flap disposed at a low portion of the cup is significantly larger than a mixing capability other portions of said mixing device, thereby without tearing the mixing device, mixing substantially the bottom only of the beverage, thereby not splashing thereof. | 2014-09-11 |
20140254305 | AUTO-CONTROLLED AIR-OXYGEN BLENDER - A gas mixing apparatus comprising an oxygen input-source, the oxygen input-source further comprising an oxygen sensor, a gas input-source, the gas input further comprises a first gas flow sensor and a combined gas output-source. The gas output source further comprises a second gas flow sensor. The gas mixing apparatus further comprise an electronic mixing-valve, the electronic mixing valve adapted to be controlled by an input-knob or by a CPU. Wherein, the electronic mixing valve, responds to a CPU, the CPU adapted to receive signals from an accelerometer, an oxygen sensor, a gas flow sensor, an input-knob, a digital input source, and a wireless transceiver; wherein said CPU controls said electronic mixing valve by comparing stored preset values and adjusting said electronic mixing valve through a feedback loop. The method of precisely mixing gas and oxygen comprising the steps of using an electronic mixing valve; said electronic mixing valve adapted to receive processed signals from a CPU. Wherein said CPU creates a feedback loop by receiving signals from an accelerometer, an oxygen sensor, a gas flow sensor, a pulse oximeter, an input-knob, a digital input source, and a wireless transceiver. | 2014-09-11 |
20140254306 | Device For Enhancing the Mobility of a Standard Mixer - A device for enhancing the mobility of a standard mixer, the device including a housing attached to a mixer, the housing having at least one shoulder attached thereto, the at least one shoulder having at least one nodule jutting out therefrom, a lever pivotally connected to the housing, a rod pivotally connected to the lever, a plate mounted to the rod, the plate having at least one finger that protrudes therefrom and a retractable member having at least one transfer ball attached thereto for rolling on a surface, the retractable member slidably engaged to the at least one finger, the retractable member having at least one groove thereon for fitting the at least one finger therein, the at least one groove having at least one bar fitted therein for permitting the first side of the at least one finger to slide over the at least one bar. | 2014-09-11 |
20140254307 | ULTRASOUND FUSION HARMONIC IMAGING SYSTEMS AND METHODS - An ultrasound imaging system includes: a harmonic filter coupled to an ultrasound transmitter to reduce transmitted harmonic components; a fundamental filter coupled with an ultrasound receiver to reduce received fundamental components; and a fusion processor configured to generate multiple frames of fusion images for two subsequent frames of ultrasound transmissions to improve frame rate. The ultrasound receiver may optionally perform signal alignment and matching to improve image quality. To improve image quality, the ultrasound system may optionally use multiple amplitude-modulated transmit pulses with different delays, or multiple transmit pulses with different amplitudes to extract harmonic signals. | 2014-09-11 |
20140254308 | IDENTIFYING REFLECTION ACOUSTIC SIGNALS - Various implementations described herein are directed to identifying reflected acoustic signals. In one implementation, a method may include receiving initial positions of an acoustic positioning source and an acoustic positioning receiver of an acoustic positioning system in a seismic spread. The method may also include calculating an expected travel difference between the acoustic positioning source and the acoustic positioning receiver. The method may further include receiving an acoustic positioning signal from the acoustic positioning receiver. The method may additionally include calculating an actual travel difference between the acoustic positioning source and the acoustic positioning receiver based on the acoustic positioning signal. The method may further include comparing the actual travel difference to the expected travel difference. The method may also include identifying whether the acoustic positioning signal is a reflected positioning signal based on the comparison. | 2014-09-11 |
20140254309 | DIGITAL SEISMIC RECORDER INCLUDING WIRED, WIRELESS AND CABLE-LESS TELEMETRY - A digital seismic recorder including wired, wireless and cable-less telemetry, which is optimized and combined from three types of instrument: a wired telemetry digital seismic recorder, a wireless telemetry digital seismic recorder and a cable-less digital seismic recorder, is divided into four main parts: a central control operating system (CCOS), a wired telemetering Acquisition Station (AS), a Wireless telemetering Acquisition Station (WAS) and a Cable-less Acquisition Station (CAS). The CCOS is respectively connected to a wired communication Root Unit (RU), a Wireless communication Root Unit (WRU) and a Cable-less Data Unit (CDU), and controls and connects the AS via the RU, controls and connects the WAS via the WRU, and retrieves the data of the CAS via the CDU. The digital seismic recorder including wired, wireless and cable-less telemetry makes the best advantages of wired telemetry, wireless telemetry and cable-less operation, and can be applied to various complex earth surfaces and landforms, providing an optimal solution for seismic exploration and reducing cost of operation. | 2014-09-11 |
20140254310 | Marine Streamer Having Variable Stiffness - Disclosed are methods and systems for performing marine geophysical surveys that utilize a streamer having variable stiffness. An embodiment discloses a sensor streamer comprising: an outer surface; tension members within the outer surface extending along a length of the sensor streamer; spacers disposed within the outer surface along the length of the sensor streamer; a geophysical sensor disposed in an interior of one of the spacers; and an actuator assembly configured to apply tension to the tension members. | 2014-09-11 |
20140254311 | AUTONOMOUS CLEANING DEVICE FOR SEISMIC STREAMERS AND METHOD - A cleaning device for cleaning a marine element towed in water and related methods are provided. The cleaning device includes a body configured to enclose the marine element; at least one wing attached to the body and configured to impart translational and rotational motion to the body when interacting with the water; a switching and locking mechanism configured to change an orientation of the at least one wing between a first orientation and a second orientation when contacting a stopper and also to lock the selected orientation; rotating means attached to an internal surface of the body and configured to contact the marine element, the rotating means having axles that make a fix angle with a longitudinal axis of the body; and a cleaning tool attached to the body and configured to clean the marine element. | 2014-09-11 |
20140254312 | METHOD AND SYSTEM FOR AUGMENTING FREQUENCY RANGE OF CONVENTIONAL MARINE SEISMIC SOURCE WITH LOW-FREQUENCY - A resonant source element is configured to generate seismic waves in water. The resonant source element includes a housing having two openings covered by first and second pistons, wherein the first and second pistons are configured to freely translate relative to the housing to generate the seismic waves; and a high-pressure system configured to discharge inside the housing and to actuate the first and second pistons. The first and second pistons are configured to oscillate after the high-pressure system is fired to generate low-frequency seismic waves. | 2014-09-11 |
20140254313 | METHOD AND SYSTEM FOR AUGMENTING FREQUENCY RANGE OF CONVENTIONAL MARINE SEISMIC SOURCE WITH LOW-FREQUENCY - A resonant source element configured to generate seismic waves. The resonant source element includes a housing; a high-pressure system configured to be discharged inside the housing; and a first conduit attached to an opening of the housing, wherein a distal end of the first conduit freely communicates with an ambient. | 2014-09-11 |
20140254314 | STREAMER DESIGN FOR GEOPHYSICAL PROSPECTING - An apparatus is disclosed that includes a solid-core streamer with particle motion sensors disposed within the solid core. Some embodiments may additionally include one or more pressure sensors that are disposed outside of the solid core. In some embodiments, the apparatus may also include one or more electromagnetic sensors. Also disclosed are various methods of operating an apparatus that includes a streamer with particle motion sensors disposed within the solid core of the streamer. | 2014-09-11 |
20140254315 | POWER SAVINGS MODE FOR OCEAN BOTTOM SEISMIC DATA ACQUISITION SYSTEMS - Embodiments of the invention provide methods, systems, and apparatus for conserving power while conducting an ocean bottom seismic survey. Sensor nodes placed on an ocean floor may be configured to operate in at least an idle mode and an active mode. When a seismic source boat approached the sensor node, the node may adjust its mode of operation from an idle mode to an active mode. After the seismic source boat is no longer near the sensor node, the idle mode may be entered again to conserve power. | 2014-09-11 |
20140254316 | System and Method for Seismic Surveying Using Distributed Sources - Disclosed are methods and systems for marine surveying that use electrically powered seismic sources that are distributed at spaced apart locations. In one example, a marine seismic survey system comprises: a survey vessel; a plurality of seismic sources configured to be towed by the survey vessel, wherein the seismic sources are electrically powered and are distributed behind the survey vessel at spaced apart locations with a spacing of about 50 meters or more; and a plurality of sensor streamers configured to be towed. | 2014-09-11 |
20140254317 | Correlation Techniques for Passive Electroseismic and Seismoelectric Surveying - A method for surveying, may include receiving, by a processor, first survey data from a first source, the first source comprising a first signal generated by a subsurface earth formation in response to a passive-source electromagnetic signal, wherein the electromagnetic signal is generated by an electroseismic or seismoelectric conversion of the passive-source electromagnetic signal. The method may also include receiving, by the processor, second survey data from a second source and processing the first survey data and the second survey data to determine one or more properties of a subsurface earth formation. | 2014-09-11 |
20140254318 | BURIED HYDROPHONE WITH SOLID OR SEMI-RIGID COUPLING - According to an embodiment, a seismic receiver device is described for use in a borehole surrounded by an ambient material, e.g., rock, mud, etc. The seismic receiver device includes a pressure wave measuring device which is configured to sense pressure changes associated with received seismic waves, a coating layer disposed on the pressure wave measuring device, and an outer layer disposed on the coating layer which is made of a material that is selected to have a bulk modulus number that is substantially similar to a bulk modulus number of the ambient medium. In this way, the acoustic impedance of the device is better matched to the ambient material so that more accurate seismic acquisition may be performed. | 2014-09-11 |
20140254319 | LOW FREQUENCY PASSIVE SEISMIC DATA ACQUISITION AND PROCESSING - Low sensitivity, single vertical axis or uniaxial transducer sensors are deployed along receiver lines across an area of interest to acquire low frequency passive seismic data from the earth. Recordings formed of the acquired low frequency passive seismic data are decomposed in the frequency-wavenumber (F-K) domain according to wavefront dipping angles into mono-dominant velocity seismic records. Resulting seismic waves of different types are identifiable based on the different dipping angles. Wavefields can then be analyzed separately in either time or frequency domains and analyzed or integrated with other data. | 2014-09-11 |
20140254320 | VERTICAL SEISMIC PROFILING-COMMON MIDPOINT GATHERS (VSP-CMP) BY WAVEFIELD EXTRAPOLATION - Direct arrivals from walkaway vertical seismic profiling or VSP survey data are used to derive Green's functions representing the seismic wave amplitude and travel time information required to extrapolate the vertical seismic profiling survey data from individual wellbore receivers to the individual source locations. The derived Green's functions are employed in a convolution process with upcoming primary wavefields from the VSP survey data for other surface locations. The derived Green's functions are also used in a correlation process with downgoing wavefields from the VSP survey data to extend lateral coverage of the VSP image. The sets of VSP-CMP gathers so formed are then processed to obtain information about the subsurface formations. | 2014-09-11 |
20140254321 | METHODS AND SYSTEMS FOR DETERMINING CLATHRATE PRESENCE AND SATURATION USING SIMULATED WELL LOGS - Methods and systems for determining a presence and saturation of clathrates are provided. One method includes identifying a potential zone of clathrates based on observed seismic data, the observed seismic data including an observed signal amplitude at the potential zone of clathrates, and assigning subsurface sediment types within and around the potential zone of clathrates. The method includes creating one or more lithologic type logs based on the interpreted subsurface sediment types, and creating from each of the one or more lithologic type logs a plurality of synthetic logs including compressional velocity at a plurality of possible clathrate saturation levels. The method includes matching expected signals from one of the plurality of synthetic logs to the observed signals in the observed seismic data to determine a best-fit match synthetic log to the observed seismic data, thereby determining a clathrate saturation level from among the plurality of possible clathrate saturation levels. | 2014-09-11 |
20140254322 | Telemetry Coding and Surface Detection for a Mud Pulser - A method for receiving an encoded integer includes acquiring a digitized waveform including a first plurality of pulses distributed among a second plurality of time slots, locating each of the pulses in the digitized waveform, computing a confidence value for each of the pulses, selecting a subset of the plurality of pulses, the subset including pulses having low confidence values computed, generating a set of unique waveforms corresponding to various combinations of the subset of pulses selected, computing a cross-correlation between each of the waveforms generated and the digitized waveform acquired, and selecting the waveform having the highest cross-correlation computed. | 2014-09-11 |
20140254323 | METHOD AND APPARATUS FOR DETERMINING BIOFOULING OF A MEMBRANE - A method of determining a state of biofouling of a membrane is provided. The membrane is contained within a flow cell and the flow cell has an outer surface coupled to a tranducer, The method comprises introducing inorganic particles into the flow cell such that the inorganic particles form a part of a top surface of a foulant layer on the membrane. The transducer then emits acoustic waves towards the membrane and an acoustic signature of reflected sound waves are detected. A state of biofouling of the membrane is determined based on the detected acoustic signature. A method and an apparatus are also provided for determining a state of biofouling in commercial membrane modules such as spiral wounded membrane modules. | 2014-09-11 |
20140254324 | SYSTEM AND METHOD FOR CLASSIFICATION OF OBJECTS FROM 3D RECONSTRUCTION - System and method for detecting and classifying man-made objects on the seafloor using 3D reconstruction techniques. Enhanced sea floor object detection with classification is provided that is as good as provided by short range optical imagery. This approach eliminates the step of passing off identification to humans, and enhances the speed, accuracy, and safety of present operations in mine detection and neutralization. | 2014-09-11 |
20140254325 | COMPOSITE TRANSDUCER APPARATUS AND SYSTEM FOR PROCESSING A SUBSTRATE AND METHOD OF CONSTRUCTING THE SAME - An apparatus and method for processing articles utilizing acoustic energy. In one embodiment, the invention is an apparatus comprising a support; a conduit for applying a fluid to a surface of the article; and a transducer assembly comprising: a transmitting structure having a concave inner surface and a convex outer surface; a first acoustic transducer having a convex bottom surface bonded to the concave inner surface of the transmitting structure, wherein the first acoustic transducer is configured to create a first acoustically active area on the convex outer surface of the transmitting structure when the first acoustic transducer is energized; and a second acoustic transducer having a convex bottom surface bonded to the concave inner surface of the transmitting structure, wherein the second acoustic transducer is configured to create a second acoustically active area on the convex outer surface of the transmitting structure when the second acoustic transducer is energized. | 2014-09-11 |
20140254326 | LOW-POWER AND BATTERY-FREE TRANSMITTER FOR REMOTE CONTROL - A transmitter for remote control, the transmitter includes a first analog-to-digital converter (ADC) configured to receive a first audio signal from a electronic device and convert the first audio signal to a first direct-current (DC) signal, a first boost circuit electrically connected to the first ADC to receive and amplify the first DC signal, and a transmission module electrically connected to the first boost circuit to receive the amplified first DC signal, wherein the amplified first DC signal is configured to modulate a carrier signal generated by the transmission module and the first audio signal is one of a left channel audio signal and a right channel audio signal output from the electronic device through an audio connector. | 2014-09-11 |
20140254327 | RFID TRANSMITTER FOR REMOTE CONTROL - A transmitter for remote control, the transmitter includes an amplifier configured to receive a first audio signal from an electronic device and amplify the first audio signal, a transmission module electrically connected to the amplifier to receive the amplified first audio signal and generating a carrier signal, a power supply connected to the transmission module, and an attenuation circuit electrically connected to the transmission module to receive the carrier signal, wherein the amplified first audio signal is configured to modulate the carrier signal and the first audio signal is one of a left channel audio signal and a right channel audio signal output from the electronic device via an audio connector. | 2014-09-11 |
20140254328 | PIEZOELECTRIC VIBRATING PIECE, PIEZOELECTRIC VIBRATOR, OSCILLATOR, ELECTRONIC APPARATUS AND RADIO CONTROLLED TIMEPIECE - A piezoelectric vibrating piece includes: a pair of vibrating arm sections which are disposed at a distance away from each other in a width direction of a base section; the base section to which each base end of the pair of vibrating arm sections is connected; and a support arm section that is connected to the base section between the pair of vibrating arm sections and extends from the base section to the same side as the pair of vibrating arm sections, in which convex sections are formed continuous with side surfaces of roots of the vibrating arm sections and side surfaces of the base section. | 2014-09-11 |
20140254329 | PIEZOELECTRIC VIBRATING PIECE, PIEZOELECTRIC VIBRATOR, OSCILLATOR, ELECTRONIC APPARATUS AND RADIO CONTROLLED TIMEPIECE - A piezoelectric vibrating piece is provided including: a pair of vibrating arm sections; a base section which is provided between the pair of vibrating arm sections; and connecting sections which connect base end sections of the pair of vibrating arm sections and a base end section of the base section, in which the vibrating arm sections have bending points and the vibrating arm sections extend in a direction away from the base section from the base end sections of the vibrating arm sections to the bending points, and the vibrating arm sections extend along the base section from the bending points to leading end sections of the vibrating arm sections. | 2014-09-11 |
20140254330 | SPIRAL SPRING - A spiral spring ( | 2014-09-11 |
20140254331 | SPIRAL SPRING - A spiral spring ( | 2014-09-11 |
20140254332 | BEARING INCLUDING FIRST AND SECOND FUNCTIONAL ELEMENTS ON TWO DISTINCT FACES - The invention relates to a bearing comprising a sintered ceramic body traversed by a hole. According to the invention, the body includes a top surface and a bottom surface each of which includes a functional element communicating with said hole. | 2014-09-11 |
20140254333 | POLARIZATION CONVERTER INCLUDING A JAGGED DIAGONAL LINE IN PLANE ORTHOGONAL TO PROPAGATION DIRECTION OF ELECTROMAGNETIC WAVE - A polarization converter of the invention includes a core part that wave-guides an electromagnetic wave and a cladding part that is provided around the core part. The core part includes a conversion part converting a polarization state of the electromagnetic wave. A cross-sectional shape of the conversion part in a plane orthogonal to a propagation direction of the electromagnetic wave is a shape formed by cutting off a portion of a rectangular or square shape along a jagged diagonal line. | 2014-09-11 |
20140254334 | ENCAPSULATED LASER DIODE FOR HEAT-ASSISTED MAGNETIC RECORDING - A magnetic write head is disclosed that includes a slider that includes a laser diode having a light-emitting edge or surface of a laser diode and an optical waveguide. The disclosed magnetic write head also includes a dielectric layer disposed in a gap between the laser diode and an input to the optical waveguide. The dielectric layer fills the gap completely and provides a low-loss optical pathway for the laser diode to the input of the optical waveguide. Also disclosed is a method that includes spinning on a dielectric in a gap between the light-emitting surface and the optical waveguide coupler, wherein after the spinning on, the laser diode is optically coupled to the optical waveguide coupler through the dielectric. | 2014-09-11 |
20140254335 | WAVEGUIDE WITH PHASE SHIFTING PORTIONS - An apparatus includes a plasmonic transducer with first and second oppositely disposed outer edges. A waveguide is configured to receive light from a light source, the waveguide have first and second portions that deliver first and second portions of the light to the first and second edges of the plasmonic transducer. The first and second portions are different by at least one of a geometry and a construction to cause a relative phase shift between the first and second portions of the light. | 2014-09-11 |
20140254336 | NEAR-FIELD TRANSDUCER WITH FLARE PEG - Disclosed are plasmonic near-field transducers that are useful in heat-assisted magnetic recording. The disclosed plasmonic near-field transducers have an enlarged region and a flared region. In some embodiments the disclosed plasmonic near-field transducer can also include a peg region. The flared region can act as a heat sink and can lower the thermal resistance of the peg region of the near-field transducer, thus reducing its temperature. Also disclosed are methods that include delivering light to a magnetic transducer region via a waveguide, receiving the light at a plasmonic near-field transducer having an output end and disposed in proximity to the magnetic transducer region, and delivering a surface plasmon-enhanced near-field radiation pattern proximate the output end of the plasmonic transducer in response to receiving the light, | 2014-09-11 |
20140254337 | GENERATING SURFACE PLASMONS USING ELECTRICAL CURRENT - A device comprises a near field transducer (NFT) and electrodes configured to at least one of generate or enhance surface plasmons in the NFT by passing electrical current through a portion of the NFT. | 2014-09-11 |
20140254338 | NANOIMPRINT LITHOGRAPHY FOR THIN FILM HEADS - Nanoimprint lithography can be used in a variety of ways to improve resolution, pattern fidelity and symmetry of microelectronic structures for thin film head manufacturing. For example, write poles, readers, and near-field transducers can be manufactured with tighter tolerances that improve the performance of the microelectronic structures. Further, entire bars of thin film heads can be manufactured simultaneously using nanoimprint lithography, which reduces or eliminated alignment errors between neighboring thin film heads in a bar of thin film heads. | 2014-09-11 |
20140254339 | ETCH STOP CONFIGURATION - A method of making a transducer head disclosed herein includes depositing a spacer layer on an NFT layer of the transducer head, forming an etch stop layer on a spacer layer of a transducer, depositing a cladding layer on the etch stop layer, and milling the cladding layer at a sloped angle such that the milling stops at the etch stop layer. | 2014-09-11 |
20140254340 | TOPOGRAPHIC FEEDFORWARD SYSTEM - A control mechanism may control the height and/or position of a read/write head configured to interact with a rotating information storage surface. A computation unit may compute a detected topography from gap measurements using a dynamic filter including a model of read/write head dynamics. A sensor may detect gap measurements of a side read/write track while the read/write head is interacting with a current read/write track. A memory may store the detected topography. The control mechanism may adjust the height of the read/write head based on the detected and/or stored topography. The control mechanism may be a reactionless control mechanism configured to apply a counterforce to offset movements of the read/write head and/or a slider. | 2014-09-11 |
20140254341 | Friction Force Measurement Assembly and Method - The application discloses a sensor device to measure friction force at a head-media interface. As disclosed, the sensor device has a transducer element oriented to provide an electrical output responsive to force or strain imparted to the transducer element along an in-plane axis. Sensor circuitry is coupled to the transducer element to process the electrical output to provide an output measure of friction force. In illustrated embodiments, the head includes an actuator element which is powered on/off at an on/off frequency to cyclically protrude a localized portion of the head. The on/off frequency of the actuator is used by the sensor circuitry to detect excitation of the sensor device due to friction force at the head-media interface. | 2014-09-11 |
20140254342 | SPINSTAND WITH MOTOR HAVING FLUID DYNAMIC BEARING - Provided herein is an apparatus, including a spinstand configured to position a disk in a testing orientation and a motor coupled to the spinstand, configured to rotate the disk. The motor comprises a fluid dynamic bearing. | 2014-09-11 |
20140254343 | PEER TO PEER VIBRATION MITIGATION - A system for peer-to-peer vibration mitigation in a distributing computing system includes a secondary communication interface over which chassis management electronics (e.g., a chassis-level controller) and/or system storage nodes may initiate communications to in order to affect system changes that may decrease vibration-related performance degradation in the system. | 2014-09-11 |
20140254344 | Contact Detection - A method of detecting a contact between a transducing head and a storage medium is provided. The method applies an input signal, having a select power level and known frequency, to an actuator for actuating the head. An output signal is obtained in response to the input signal. At least one signal component is extracted from the output signal at the same or a harmonic of the same known frequency as the input signal applied to the actuator. Whether the at least one extracted signal component indicates a contact between the head and the medium is determined. The power level of the applied wave pattern is increased incrementally until the extracted signal component indicates a contact between the head and the storage medium. | 2014-09-11 |
20140254345 | OBJECTIVE LENS, OPTICAL HEAD, OPTICAL DISK DEVICE, AND INFORMATION PROCESSING DEVICE - Assuming that third-order coma aberration per unit angle generated by tilt of BD ( | 2014-09-11 |
20140254346 | ENHANCED RADAR DETECTION FOR COMMUNICATION NETWORKS - Radar signals can be detected by a Wireless Local Area Network (WLAN) receiver by modifying one or more pattern matching attributes. In one embodiment, the pattern matching attributes are modified when signal pulses received by the WLAN receiver are determined to have an increased likelihood of being radar signals. In one embodiment, a frequency variance of received signal pulses is used to determine the likelihood of received signal pulses being radar signals. The frequency variance is based, at least in part, on frequencies of Fast Fourier Transforms of the received signal pulses. | 2014-09-11 |
20140254347 | Ethernet Ring Protection Switching Method, Node, and System - Embodiments of the present invention disclose an Ethernet ring protection switching method, node, and system. In an Ethernet ring protection switching method is disclosed, it is determined whether the current link is a lower-bandwidth link according to bandwidth information of a current link and bandwidth information of another link on a ring. If the current link is a lower-bandwidth link, a port corresponding to the current link is blocked. | 2014-09-11 |
20140254348 | METHODS AND SYSTEMS FOR AUTOMATICALLY REROUTING LOGICAL CIRCUIT DATA - An example involves when a first logical circuit identifier of the dedicated logical circuit that is to communicate data only between a host device and a remote device does not match a second logical circuit identifier of a logical failover circuit comprising an alternate communication path for communicating the data, and when the dedicated logical circuit has failed: the second logical circuit identifier is renamed to identify the logical failover circuit using the first logical circuit identifier when the logical failover circuit is a dedicated logical failover circuit to communicate only when the dedicated logical circuit fails, and the dedicated logical circuit is renamed to identify the dedicated logical circuit using the second logical circuit identifier when the logical failover circuit is to communicate regardless of failure of the dedicated logical circuit. | 2014-09-11 |
20140254349 | SYSTEMS AND METHODS FOR SEAMLESS DATA STREAM TRANSFER DURING BAND SWITCH BETWEEN WIRELESS STATIONS - One innovation includes an apparatus, for wirelessly communicating with a communication system via a first wireless channel and a second wireless channel, including a memory unit that is configured to store a first data packet and a second data packet, the first data packet and the second data packet have consecutive sequence numbers. The apparatus further includes a processor configured to retrieve the first data packet and the second data packet from the memory unit, a transceiver that is configured to transmit the first data packet to the communication system via the first channel, to receive a first acknowledgement from the communication system and to transmit the second data packet to the communication system via the second channel after the processor detects that the first acknowledgement comprises a positive acknowledgement of the first reception information. | 2014-09-11 |
20140254350 | Reconnection in a Transmission Tree - The invention refers to operating a first node of a communication network comprising a plurality of nodes which are interconnected by communication links and wherein data traffic is provided over the communication links to provide a data stream to the nodes, wherein the first node ( | 2014-09-11 |
20140254351 | ENHANCED ACKNOWLEDGEMENT AND RETRANSMISSION MECHANISM - Protocol data units (PDUs) associated with a packet stream are transmitted with sequence numbers to support reordering and selective acknowledgement. A selective acknowledgement (SACK) message may be used to indicate at least one sequence number of a lost or corrupted PDU which was not properly received by the receiving device. Responsive to the SACK message, the lost or corrupted PDU is retransmitted via a different path of the network, different from the path used to transmit the original PDU. Lost or corrupted PDUs may not be retransmitted if the estimated retransmission delay is greater than a delay tolerance associated with the quality of service requirements of the application. Instead, a control message (i.e. “cut losses” message) may be transmitted to indicate that PDUs earlier than a particular sequence number will not be transmitted. | 2014-09-11 |
20140254352 | SYSTEM AND METHOD FOR RAPID VLT CONNECTION FAILURE HANDLING - A system and method for rapid virtual link trunk connection failure handling includes receiving a packet at a first network switching unit where the packet is to be forwarded to a second network switching unit, detecting a failure in a network connection between the first network switching unit and the second network switching unit and associated with a first LAG of the first network switching unit, determining a second LAG associated with an inter-chassis link (ICL) as a failover LAG for the first LAG, redirecting the packet to the second LAG, altering the packet to set a redirection status bit to a logic value, and forwarding the altered packet using the ICL. | 2014-09-11 |
20140254353 | NOTIFYING OF A LSP FAILURE - According to an example, in a method and apparatus for notifying a LSP, the downstream LSR detecting the link failure on the work LSP sends a SF message on the direction of the work LSP, so that the upstream LSR detecting the link failure on the work LSP receives the SF message and sends the packet via the protection LSP according to the SF message. | 2014-09-11 |
20140254354 | RESILIENT DATA COMMUNICATIONS WITH PHYSICAL LAYER LINK AGGREGATION, EXTENDED FAILURE DETECTION AND LOAD BALANCING - Rapid channel failure detection and recovery in wireless communication networks is needed in order to meet, among other things, carrier class Ethernet channel standards. Thus, resilient wireless packet communications is provided using a physical layer link aggregation protocol with a hardware-assisted rapid channel failure detection algorithm and load balancing, preferably in combination. This functionality may be implemented in a Gigabit Ethernet data access card with an engine configured accordingly. In networks with various topologies, these features may be provided in combination with their existing protocols. | 2014-09-11 |
20140254355 | APPARATUS, METHOD, AND SYSTEM FOR INCENTIVIZING OPEN ACCESS TO CLOSED SUBSCRIBER GROUP LOW-POWER BASE STATIONS - Apparatus and methods are disclosed that provide various incentive schemes for owners of low-power base stations to allow others nearby to use their base station, enabling offloading of some users from a nearby macrocell, thus helping improve overall network performance. For example, a “win-win” scenario might exist when a sharing opportunity at a low-power base station overlaps with a sharing opportunity at the neighboring macrocell. During this overlap, when the low-power base station provides access to its air interface to one or more UEs outside of a set of UEs associated with the low-power base station, an incentive credit may be received. Incentive credits can take various forms, and in some examples, may be in an amount that is a function of an amount of contribution to the network resulting from the provision of access to the air interface. | 2014-09-11 |
20140254356 | METHOD AND APPARATUS FOR CONTROLLING TRAFFIC OF RADIO ACCESS NETWORK IN A WIRELESS COMMUNICATION SYSTEM - Provided is a method for controlling traffic of a Radio Access Network (RAN) in a wireless communication system. The method includes acquiring at least one of subscription class information of a User Equipment (UE) user and type information of an application or content; determining whether a congestion situation has occurred in the RAN; and controlling traffic for the UE based on the acquired information, if the congestion situation has occurred in the RAN. | 2014-09-11 |
20140254357 | FACILITATING NETWORK FLOWS - Disclosed are various embodiments for facilitating network flows in a networked environment. In various embodiments, a switch transmits data using an egress port that comprises an egress queue. The switch sets a congestion notification threshold for the egress queue. The switch generates a drain rate metric based at least in part on a drain rate for the egress queue, and the congestion notification threshold is adjusted based at least in part on the drain rate metric. | 2014-09-11 |
20140254358 | Method for Providing Bearer Specific Information for Wireless Networks - The Packet Control Function (PCF) has limited knowledge about the nature of the packet data arriving on a bearer path connected via the Packet Data Serving Node (PDSN), and cannot make an intelligent decision on its own as to how best to handle the packet data. Thus, the PDSN provides bearer-specific information by classifying the priority of received packet data; encapsulating the packet data within the payload of a Generic Routing Encapsulation (GRE) frame; and for high priority packet data i) setting a protocol type field in the header of the GRE frame indicating said packet includes an attribute field; and ii) adding an attribute field to the payload of the GRE packet which provides an indication of said high priority data. Furthermore, the PCF can send an A-11 request to the PDSN indicating the features that the PCF is requesting the PDSN enable. For example, for a short data indication, the PCF would request the PDSN enable adding the attribute field to the GRE frame when an Short Data Burst (SDB) is suitable. | 2014-09-11 |
20140254359 | MOBILE NETWORK CONGESTION RECOGNITION FOR OPTIMIZATION OF MOBILE TRAFFIC - Systems and methods for mobile network congestion recognition for optimization of mobile traffic are disclosed. A mobile device having a local proxy equipped with congestion recognition capabilities can sample time consumed to establish data connection between the mobile device and the mobile network, collect data including at least one of signal strength data, cell identifier, and location area code associated with the data connection between the mobile device and the mobile network, and anticipate network congestion, based at least on the time consumed and the collected data. On detecting mobile network congestion, the local proxy can apply a blocking policy to block all or low priority traffic from signaling the congested mobile network to ease the congestion. | 2014-09-11 |