37th week of 2014 patent applcation highlights part 56 |
Patent application number | Title | Published |
20140256066 | Radiofrequency Adjustment for Instability Management in Semiconductor Processing - Methods, systems, and computer programs are presented for reducing chamber instability while processing a semiconductor substrate. One method includes an operation for identifying a first recipe with steps having an operating frequency equal to the nominal frequency of a radiofrequency (RF) power supply. Each step is analyzed with the nominal frequency, and the analysis determines if any step produces instability at the nominal frequency. The operating frequency is adjusted, for one or more of the steps, when the instability in the one or more steps exceeds a threshold. The adjustment acts to find an approximate minimum level of instability. A second recipe is constructed after the adjustment, such that at least one of the steps includes a respective operating frequency different from the nominal frequency. The second recipe is used to etch the one or more layers disposed over the substrate in the semiconductor processing chamber. | 2014-09-11 |
20140256067 | Structure and Method for E-Beam In-Chip Overlay Mark - The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction. | 2014-09-11 |
20140256068 | ADJUSTABLE LASER PATTERNING PROCESS TO FORM THROUGH-HOLES IN A PASSIVATION LAYER FOR SOLAR CELL FABRICATION - Embodiments of the invention contemplate formation of a high efficiency solar cell utilizing an adjustable or optimized laser patterning process to form openings with different geometry in a passivation layer disposed on a substrate based on different film properties in the passivation layer and the substrate. In one embodiment, a method of forming a solar cell includes transferring a substrate having a passivation layer formed on a back surface of a substrate into a laser patterning apparatus, performing a substrate inspection process by a detector disposed in the laser patterning apparatus, determining a laser patterning recipe configured to form openings in the passivation layer based on information obtained from the substrate inspection process, and performing a laser patterning process on the passivation layer using the determined laser patterning recipe. | 2014-09-11 |
20140256069 | METHOD FOR MANUFACTURING LIQUID DISCHARGE HEAD - A method for manufacturing a liquid discharge includes a process of forming a plurality of blind holes extending from a first surface of the silicon substrate toward a second surface which is a surface opposite to the first surface in the silicon substrate and a process of subjecting the silicon substrate in which the plurality of blind holes are formed to anisotropic etching from the first surface to form a liquid supply port in the silicon substrate, in which, in the process of forming the liquid supply port, the silicon in a region sandwiched by the plurality of blind holes when the silicon substrate is seen from the second surface side is left without being removed by the anisotropic etching to use the left silicon as a beam. | 2014-09-11 |
20140256070 | PLASMA CURING OF PECVD HMDSO FILM FOR OLED APPLICATIONS - Methods for forming an OLED device are described. An encapsulation layer having a buffer layer sandwiched between barrier layers is deposited over an OLED structure. The buffer layer is deposited on the first barrier layer and is cured with a fluorine-containing plasma at a temperature less than 100 degrees Celsius. The second barrier layer is then deposited on the buffer layer. | 2014-09-11 |
20140256071 | METHOD OF MANUFACTURING LIGHT-EMITTING DIODE PACKAGE - A method of manufacturing a light-emitting diode package is illustrated. A light-emitting diode chip is manufactured. A material layer is formed on side surfaces and a rear surface of the light-emitting diode chip. The material layer is then oxidized to convert the material layer into an oxidized layer to form a reflective layer on the side surfaces and the rear surface of the light-emitting diode chip. The light-emitting diode chip is packaged. | 2014-09-11 |
20140256072 | Semiconductor Light Emitting Device Packages and Methods - A submount for a light emitting device package includes a substrate with a first bond pad and a second bond pad on a first surface. The first bond pad includes a die attach region offset toward a first end of the substrate and configured to receive a light emitting diode. The second bond pad includes a bonding region between the first bond pad and the second end of the substrate and a second bond pad extension that extends from the bonding region along a side of the substrate toward a corner of the substrate at the first end of the substrate. First and second solder pads are on the second surface of the substrate. The first solder pad is adjacent the first end of the substrate and contacts the second bond pad. The second solder pad is adjacent the second end of the substrate and contacts the first bond pad. | 2014-09-11 |
20140256073 | Simultaneous Modulation of Quantum Dot Photoluminescence using Orthogonal Fluorescence Resonance Energy Transfer (FRET) and Charge Transfer Quenching (CTQ) - Quantum dots are modified with varying amounts of (a) a redox-active moiety effective to perform charge transfer quenching, and (b) a fluorescent dye effective to perform fluorescence resonance energy transfer (FRET), so that the modified quantum dots have a plurality of photophysical properties. The FRET and charge transfer pathways operate independently, providing for two channels of control for varying luminescence of quantum dots having the same innate properties. | 2014-09-11 |
20140256074 | LIQUID CRYSTAL DISPLAY DEVICE HAVING TOUCH SENSOR EMBEDDED THEREIN, METHOD FOR DRIVING THE SAME, AND METHOD FOR FABRICATING THE SAME - Disclosed is a liquid crystal display device having touch sensors embedded therein. The liquid crystal display device includes a liquid crystal layer interposed between upper and lower substrates, pixels, each of which includes pixel and common electrodes applying a horizontal electric field to the liquid crystal layer, a pixel thin film transistor to drive the pixel electrode, and a common thin film transistor to drive the common electrode, touch sensors, each of which forms a sensing capacitor between an object and the common electrode, sensor power lines, readout lines, and sensor gate lines. Each touch sensor includes the common electrode, a first sensor thin film transistor charging the common electrode with the sensing driving voltage in response to control of the previous sensor gate line, and a second sensor thin film transistor outputting the sensing signal to the readout line in response to control of the current sensor gate line. | 2014-09-11 |
20140256075 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR MANUFACTURING LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device includes a pair of substrates of which one substrate is provided with a plurality of scanning lines and a plurality of common wirings, a first insulation film covering the scanning lines, the common wirings, and the one substrate, a plurality of signal lines provided on the first insulation film, a thin film transistor provided near an intersection part of the scanning lines and the signal lines, a lower electrode formed below the first insulation film and connected to the common wirings, a second insulation film formed on surfaces of the thin film transistor, the signal lines, and the first insulation film, and an upper electrode formed on the second insulation film and having a slit, a display region in which the liquid crystal layer is driven by an electric field, and a non-display region that is formed outside the display region. | 2014-09-11 |
20140256076 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A display device includes a substrate; a gate wire including a gate electrode and a first capacitor electrode formed on the substrate; a gate insulating layer formed on the gate wire; a semiconductor layer pattern formed on the gate insulating layer, and including an active region overlapping at least a part of the gate electrode and a capacitor region overlapping at least a part of the first capacitor electrode; an etching preventing layer formed on a part of the active region of the semiconductor layer pattern; and a data wire including a source electrode and a drain electrode formed over the active region of the semiconductor layer from over the etching preventing layer, and separated with the etching preventing layer therebetween, and a second capacitor electrode formed on the capacitor region of the semiconductor layer. | 2014-09-11 |
20140256077 | Method for preparation of micro electro-mechanical structure - The present invention discloses an adhesive-free method for preparation of micro electro-mechanical structure, comprising forming a micro electro-mechanical structure on a first substrate, forming an enclosing space for immersing liquid on the first or second substrate, and applying pressure to fix the first and second substrate. Before applying the pressure, the assembly including the two substrates is flipped, to make the contact surface immersed by the immersing liquid. | 2014-09-11 |
20140256078 | SEMICONDUCTOR PROCESSING BY MAGNETIC FIELD GUIDED ETCHING - Methods, systems, and devices are described for slicing and shaping materials using magnetically guided chemical etching. In one aspect, a method includes forming a pattern on a substrate by a mask, depositing a catalytic etcher layer on the patterned substrate, a magnetic guide layer on the etcher layer, and a protection layer on the guide layer, etching the substrate by applying an etching solution to the substrate that chemically reacts with the etcher layer and etches material from the substrate at exposed regions not covered by the mask, steering the composite etching structure into the substrate during the etching by an applied magnetic field that creates a force on the guide layer to direct the etching, in which the steering defines the shape of the sliced regions of the etched substrate, and removing the etched material, the mask, and the composite etching structure to produce a sliced material structure. | 2014-09-11 |
20140256079 | PRODUCTION METHOD FOR SPECTROSCOPIC SENSOR - A method for manufacturing a spectroscopic sensor | 2014-09-11 |
20140256080 | SEMICONDUCTOR DEVICE PN JUNCTION FABRICATION USING OPTICAL PROCESSING OF AMORPHOUS SEMICONDUCTOR MATERIAL - Systems and methods for semiconductor device PN junction fabrication are provided. In one embodiment, a method for fabricating an electrical device having a P-N junction comprises: depositing a layer of amorphous semiconductor material onto a crystalline semiconductor base, wherein the crystalline semiconductor base comprises a crystalline phase of a same semiconductor as the amorphous layer; and growing the layer of amorphous semiconductor material into a layer of crystalline semiconductor material that is epitaxially matched to the lattice structure of the crystalline semiconductor base by applying an optical energy that penetrates at least the amorphous semiconductor material. | 2014-09-11 |
20140256081 | Methods For Producing Thin Film Charge Selective Transport Layers - Methods for producing thin film charge selective transport layers are provided. In one embodiment, a method for forming a thin film charge selective transport layer comprises: providing a precursor solution comprising a metal containing reactive precursor material dissolved into a complexing solvent; depositing the precursor solution onto a surface of a substrate to form a film; and forming a charge selective transport layer on the substrate by annealing the film. | 2014-09-11 |
20140256082 | METHOD AND APPARATUS FOR THE FORMATION OF COPPER-INDIUMGALLIUM SELENIDE THIN FILMS USING THREE DIMENSIONAL SELECTIVE RF AND MICROWAVE RAPID THERMAL PROCESSING - A method of depositing CIGS thin films for solar panel construction comprising: providing a chamber; providing a substrate and placing said substrate inside said chamber; providing a material source; placing said material source inside said chamber; reducing pressure within said chamber; heating said substrate and said material source using electromagnetic heating (RF and Microwaves) source; perform deposition of said material source oto said substrate. | 2014-09-11 |
20140256083 | High Speed Copper Plating Process - A copper electrolyte comprising a copper nitrate salt is described. The electrolyte is suitable for use in a light induced plating process for metallizing contacts in a photovoltaic solar cell. A method of metallizing an electrical contact in a photovoltaic solar cell using the copper electrolyte is also described. | 2014-09-11 |
20140256084 | SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a solar cell is discussed. The method may include injecting first impurity ions at a first surface of a substrate by using a first ion implantation method to form a first impurity region, the substrate having a first conductivity type and the first impurity ions having a second conductivity type, and the first impurity region having the second conductivity type; heating the substrate with the first impurity region to activate the first impurity region to form an emitter region from the first impurity region; etching the emitter region from a surface of the emitter region to a predetermined depth to form an emitter part from the emitter region; and forming a first electrode on the emitter part to connect to the emitter part and a second electrode on a second surface of the substrate to connect to the second surface of the substrate. | 2014-09-11 |
20140256085 | METHOD OF MANUFACTURING AN ORGANIC SEMICONDUCTOR THIN FILM - A method of manufacturing an organic semiconductor thin film includes coating an organic semiconductor solution on a substrate, and shearing the organic semiconductor solution in a direction that results in a shearing stress being applied to the organic semiconductor solution to form the organic semiconductor thin film, wherein a speed of the shearing is controlled such that an intermolecular distance of the organic semiconductor solution is adjusted. | 2014-09-11 |
20140256086 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A transistor with superior electric characteristics is manufactured. An oxide insulating film is formed over a substrate, an oxide semiconductor film is formed over the oxide insulating film, heat treatment is then conducted at a temperature at which hydrogen contained in the oxide semiconductor film is desorbed and part of oxygen contained in the oxide insulating film is desorbed, then the heated oxide semiconductor film is etched into a predetermined shape to form an island-shaped oxide semiconductor film, a pair of electrodes is formed over the island-shaped oxide semiconductor film, a gate insulating film is formed over the pair of electrodes and the island-shaped oxide semiconductor film, and a gate electrode is formed over the gate insulating film. | 2014-09-11 |
20140256087 | Hybrid Bonding and Apparatus for Performing the Same - A method includes performing a hybrid bonding to bond a first package component to a second package component, so that a bonded pair is formed. In the bonded pair, first metal pads in the first package component are bonded to second metal pads in the second package component, and a first surface dielectric layer at a surface of the first package component is bonded to a second surface dielectric layer at a surface of the second package component. After the hybrid bonding, a thermal compressive annealing is performed on the bonded pair. | 2014-09-11 |
20140256088 | SEMICONDUCTOR DEVICE HAVING CHIP MOUNTED ON AN INTERPOSER - A semiconductor device | 2014-09-11 |
20140256089 | STACKED SEMICONDUCTOR PACKAGES - Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device. | 2014-09-11 |
20140256090 | SELECTIVE AREA HEATING FOR 3D CHIP STACK - A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively. | 2014-09-11 |
20140256091 | METHODS FOR BONDING A DIE AND A SUBSTRATE - Embodiments of methods for forming a semiconductor device that includes a die and a substrate include pressing together the die and the substrate such that a first gold layer and one or more additional material layers are between the die and the substrate, and performing a bonding operation to form a die attach layer between the die and the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon. | 2014-09-11 |
20140256092 | Interconnect Structures and Methods of Forming Same - Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface. | 2014-09-11 |
20140256093 | FinFET Device Structure and Methods of Making Same - Embodiments of the present disclosure are a method of forming a semiconductor device and a method of forming a FinFET device. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first hardmask layer on the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further includes forming a second dielectric layer on the first dielectric layer and the first hardmask portion, forming a third dielectric layer on the second dielectric layer, and etching the third dielectric layer and a portion of the second dielectric layer to form a first and second spacer on opposite sides of the first hardmask portion. | 2014-09-11 |
20140256094 | FinFETs and Methods for Forming the Same - Methods for forming a semiconductor device and a FinFET device are disclosed. A method comprises forming a dummy gate electrode layer over a substrate, the dummy gate electrode layer having a first height, forming a first etch stop layer on the dummy gate electrode layer, forming a first hard mask layer on the first etch stop layer, and patterning the first hard mask layer. The method further comprises patterning the first etch stop layer to align with the patterned first hard mask layer, and patterning the gate electrode layer to form a dummy gate electrode, the dummy gate electrode aligning with the patterned first etch stop layer, wherein after the patterning the gate electrode layer the first hard mask layer has a vertical sidewall of a second height, the second height being less than the first height, and the first hard mask layer having a rounded top surface. | 2014-09-11 |
20140256095 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide a manufacturing method of a highly reliable TFT, by which a more refined pattern can be formed through a process using four or three masks, and a semiconductor device. A channel-etched bottom gate TFT structure is adopted in which a photoresist is selectively exposed to light by rear surface exposure utilizing a gate wiring to form a desirably patterned photoresist, and further, a halftone mask or a gray-tone mask is used as a multi-tone mask. Further, a step of lifting off using a halftone mask or a gray-tone mask and a step of reflowing a photoresist are used. | 2014-09-11 |
20140256096 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device is provided, which includes a single crystal semiconductor layer formed over an insulating surface and having a source region, a drain region, and a channel formation region, a gate insulating film covering the single crystal semiconductor layer and a gate electrode overlapping with the channel formation region with the gate insulating film interposed therebetween. In the semiconductor device, at least the drain region of the source and drain regions includes a first impurity region adjacent to the channel formation region and a second impurity region adjacent to the first impurity region. A maximum of an impurity concentration distribution in the first impurity region in a depth direction is closer to the insulating surface than a maximum of an impurity concentration distribution in the second impurity region in a depth direction. | 2014-09-11 |
20140256097 | METHODS FOR FORMING INTEGRATED CIRCUIT SYSTEMS EMPLOYING FLUORINE DOPING - A method for forming a semiconductor device is provided which includes providing a gate structure in an active region of a semiconductor substrate, wherein the gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to the gate structure and, thereafter, performing a fluorine implantation process. Also a method for forming a CMOS integrated circuit structure is provided which includes providing a semiconductor substrate with a first active region and a second active region, forming a first gate structure in the first active region and a second gate structure in the second active region, wherein each gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to each of the first and second gate structures and, thereafter, performing a fluorine implantation process. | 2014-09-11 |
20140256098 | MEMORIES WITH MEMORY ARRAYS EXTENDING IN OPPOSITE DIRECTIONS FROM A SEMICONDUCTOR AND THEIR FORMATION - Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array. | 2014-09-11 |
20140256099 | METHOD OF CONVERTING BETWEEN NON-VOLATILE MEMORY TECHNOLOGIES AND SYSTEM FOR IMPLEMENTING THE METHOD - A method of designing a charge trapping memory array including designing a floating gate memory array layout. The floating gate memory layout includes a first type of transistors, electrical connections between memory cells of the floating gate memory array layout, a first input/output (I/O) interface, a first type of charge pump, and an I/O block. The method further includes modifying the floating gate memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes determining an operating voltage difference between the I/O block and the second type of transistors. The method further includes modifying the floating gate memory array layout, using the processor, to modify the first charge pump based on the determined operating voltage difference. | 2014-09-11 |
20140256100 | ELECTRICAL COUPLING OF MEMORY CELL ACCESS DEVICES TO A WORD LINE - A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory cell access devices. The memory array also includes a first set of at least two vertical pillars positioned above and electrically coupled to the source line. A second set of vertical pillars electrically isolated from the source line and positioned such that the source line does not extend below the second set of vertical pillars is also included. Furthermore, gate terminals of the memory cell access devices laterally surround the first set of vertical pillars and the second set of vertical pillars. Finally, a first word line contact is positioned between two of the second set of vertical pillars. The first word line contact is electrically coupled to the gate terminals. | 2014-09-11 |
20140256101 | METHODS OF FABRICATING THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES - A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates. | 2014-09-11 |
20140256102 | Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same - A method of making a tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A source region is formed as a top portion of the frustoconical protrusion structure. A series connection and a parallel connection are made among TFET devices units. | 2014-09-11 |
20140256103 | METHOD FOR FABRICATING ELECTRONIC DEVICES HAVING SEMICONDUCTOR MEMORY UNIT - Devices and methods based on disclosed technology include, among others, an electronic device including silicide layers capable of effectively reducing contact resistance in the electronic device including buried gates and a method for fabricating the electronic device. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate and silicide layers formed over the substrate between the buried gates and protruding upwardly from the buried gates. | 2014-09-11 |
20140256104 | MANUFACTURING METHOD OF VERTICAL CHANNEL TRANSISTOR ARRAY - A manufacturing method of a vertical channel transistor array is provided. The method includes following steps. A plurality of embedded word lines are formed at bottoms of trenches, and each of the embedded word lines is located at a first side wall of one of the trenches and connected to first sides of the semiconductor pillars in the same row. Each of the embedded word lines is not connected to second sides of the semiconductor pillars in the same row, and the first sides are opposite to the second sides. Only one embedded word line is correspondingly connected to the semiconductor pillars arranged in one row. An isolation structure is formed between a second side wall of each of the trenches and each of the embedded word lines. The first side wall is opposite to the second side wall. | 2014-09-11 |
20140256105 | Self-Aligned Passivation of Active Regions - A method includes forming a semiconductor fin, performing a first passivation step on a top surface of the semiconductor fin using a first passivation species, and performing a second passivation step on sidewalls of the semiconductor fin using a second passivation species different from the first passivation species. A gate stack is formed on a middle portion of the semiconductor fin. A source or a drain region is formed on a side of the gate stack, wherein the source or drain region and the gate stack form a Fin Field-Effect Transistor (FinFET). | 2014-09-11 |
20140256106 | PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES - A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment. | 2014-09-11 |
20140256107 | High Gate Density Devices and Methods - A method of forming a semiconductor device includes providing a semiconductor substrate and forming a plurality of dummy gate structures in the substrate. The method further includes forming sidewall spacers on sidewalls of the dummy gate structures and forming a plurality of epitaxial growth regions between the dummy gate structures. After forming the plurality of epitaxial growth regions, one of the dummy gate structures is removed to form an isolation trench, which is filled with a dielectric layer to form an isolation feature. The remaining dummy gate structures are removed to form gate trenches, and gate structures are formed in the gate trenches. | 2014-09-11 |
20140256108 | HYBRID ACTIVE-FIELD GAP EXTENDED DRAIN MOS TRANSISTOR - An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions. | 2014-09-11 |
20140256109 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is disclosed. In one aspect the method includes forming a gate stack over a substrate. The method also includes forming a dummy sidewall spacer around the gate stack. The method also includes depositing a stress liner of diamond-like amorphous carbon (DLC) on the substrate, the gate stack and the dummy sidewall spacer. The method also includes annealing, so that a channel region in the substrate below the gate stack and the gate stack memorize stress in the stress liner. The method also includes removing the dummy sidewall spacer. The method also includes forming a sidewall spacer around the gate stack. In the method according to the disclosed technology, large stress in the liner of DLC is memorized and applied to the dummy gate stack and the channel region to increase carrier mobility and improve performances of the device. | 2014-09-11 |
20140256110 | SELF ALIGNED FIN-TYPE PROGRAMMABLE MEMORY CELL - A fin-type programmable memory cell includes a bottom electrode electrically coupled to an access device, a top electrode, and an L-shaped memory material element electrically coupled to the bottom and top electrodes. A memory array includes an array of such memory cells, electrically coupled to an array of access devices. Method for making a memory cell, includes: forming a dielectric support layer over a bottom electrode, the dielectric support layer having an upper surface; forming a cavity through the dielectric support layer, exposing a surface of the bottom electrode and defining a dielectric support structure having a sidewall; forming a film of memory material over the dielectric support structure and in the cavity; depositing a dielectric spacer layer over the memory material film; forming a dielectric sidewall spacer from the dielectric spacer layer and a memory material structure having a generally horizontal portion underlying the dielectric sidewall spacer and a generally vertical portion between the dielectric sidewall spacer and the sidewall of the dielectric support structure; forming a dielectric fill; planarizing the dielectric fill to expose upper ends of the vertical portion of the memory material structure; depositing a top electrode material over the planarized dielectric fill; and forming a top electrode from the top electrode material and a memory material element from the memory material structure. | 2014-09-11 |
20140256111 | Nonvolatile Memory Elements - Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer. | 2014-09-11 |
20140256112 | Semiconductor Devices and Methods of Fabricating the Same - Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers. | 2014-09-11 |
20140256113 | Semiconductor Device and Method for Forming the Same - A method includes forming a recess in a substrate and filling a dielectric layer in the recess. The method further includes forming a capping layer over the substrate and the dielectric layer. A top portion of the capping layer is then removed, while leaving a bottom portion of the capping layer over the dielectric layer. A gate structure is then formed over the remaining capping layer. | 2014-09-11 |
20140256114 | SILICON-ON-INSULATOR CHANNELS - Novel methods to fabricate biological sensors and electronics are disclosed. A silicon-on-insulator wafer can be employed by etching a pattern of holes in the silicon layer, then a pattern of cavities in the insulating layer, and then sealing the top of the cavities. Further, n or p doped regions and metallic regions can be defined in the processed wafer, thereby enabling integration of biological sensing and electronic capabilities in the same wafer. | 2014-09-11 |
20140256115 | SEMICONDUCTOR PROCESS - A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided. | 2014-09-11 |
20140256116 | Semiconductor Device and Manufacturing Method Thereof - There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 μm or more. | 2014-09-11 |
20140256117 | METHODS OF FORMING EPITAXIAL LAYERS - A method of forming an epitaxial layer includes forming a plurality of first insulation patterns in a substrate, the plurality of first insulation patterns spaced apart from each other, forming first epitaxial patterns on the plurality of first insulation patterns, forming second insulation patterns between the plurality of first insulation patterns to contact the plurality of first insulation patterns, and forming second epitaxial patterns on the second insulation patterns and between the first epitaxial patterns to contact the first epitaxial patterns, the first epitaxial patterns and the second epitaxial patterns forming a single epitaxial layer. | 2014-09-11 |
20140256118 | METHOD FOR FORMING POLYSILICON USING HIGH ENERGY RADIATION SOURCE - A method for forming polysilicon using high energy sources of radiation includes the steps of providing a laser system which has at least two laser sources with different wavelengths, a dichroic mirror, a reflecting mirror and a substrate; generating a laser beam by the laser sources to irradiate towards the substrate perpendicularly by the dichroic mirror and the reflecting mirror which are faced to the laser source and meet the laser sources at a certain angle; placing the reflecting mirror above the dichroic mirror; placing the a semiconductor thin-film material on the substrate. The advantages of the above technical solution are that as follows: the crystallization rate of poly-silicon is effectively increased; the usage frequency of the excimer laser is reduced; the cost thereof is reduced; the throughput of annealing is affectively improved. | 2014-09-11 |
20140256119 | CYCLIC EPITAXIAL DEPOSITION AND ETCH PROCESSES - A cyclic deposition and etch method is provided. The method includes depositing an epitaxial layer over a substrate at a first temperature and etching a portion of the deposited epitaxial layer at a variable temperature higher than the first temperature. The step of etching is performed while varying the temperature. | 2014-09-11 |
20140256120 | Process for Preparing Graphene Based on Metal Film-Assisted Annealing and the Reaction with Cl2 - A method for preparing graphene by reaction with Cl | 2014-09-11 |
20140256121 | TECHNIQUES AND APPARATUS FOR HIGH RATE HYDROGEN IMPLANTATION AND CO-IMPLANTION - An apparatus for hydrogen and helium implantation is disclosed. The apparatus includes a plasma source system to generate helium ions and hydrogen molecular ions comprising H | 2014-09-11 |
20140256122 | Methods And Apparatus For Carbon Ion Source Head - Methods and apparatus for a carbon ion source head. An ionization chamber is configured to receive a process gas containing carbon and a noble carrier gas; a cathode is disposed in the ionization chamber and configured to emit electrons in thermionic emission; a graphite coating is provided on at least a portion of the cathode; and an outlet on the ionization chamber is configured to output carbon ions. A method for ion implantation of carbon is disclosed. Additional alternative embodiments are disclosed. | 2014-09-11 |
20140256123 | ELECTRICALLY ACTUATED DEVICE AND METHOD OF CONTROLLING THE FORMATION OF DOPANTS THEREIN - In an example of a method for controlling the formation of dopants in an electrically actuated device, a predetermined concentration of a dopant initiator is selected. The predetermined amount of the dopant is localized, via diffusion, at an interface between an electrode and an active region adjacent to the electrode. The dopant initiator reacts with a portion of the active region to form the dopants. | 2014-09-11 |
20140256124 | IN-SITU METAL GATE RECESS PROCESS FOR SELF-ALIGNED CONTACT APPLICATION - A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (CMP) processes to planarize the formed gate structure using a CMP tool. An in situ gate etching process is performed in a CMP cleaner of the CMP tool to form a gate recess. A contact etch stop layer (CESL) can then be deposited in the formed gate recess and one or more CMP processes performed to planarize the CESL. | 2014-09-11 |
20140256125 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate including a trench, a buried gate filling a part of the trench, an inter-layer dielectric layer formed on the buried gate to gap-fill the rest of the trench, and a protection layer covering substantially an entire surface of the substrate including the inter-layer dielectric layer. | 2014-09-11 |
20140256126 | Electrical Connectors and Methods for Forming the Same - A method includes coating a photo resist over an Under-Bump Metallurgy (UBM) layer and exposing the photo resist. In the step of exposing, a light amount reaching a bottom of the photo resist is less than about 5 percent of a light amount reaching a top surface of the photo resist. The method further includes developing the photo resist to form an opening in the photo resist. A portion of the UBM layer is exposed through the opening. The opening has a bottom lateral dimension greater than a top lateral dimension. An electrical connector is formed in the opening, wherein the electrical connector is non-reflowable. | 2014-09-11 |
20140256127 | METHODS FOR REDUCING METAL OXIDE SURFACES TO MODIFIED METAL SURFACES USING A GASEOUS REDUCING ENVIRONMENT - Method and apparatus for reducing metal oxide surfaces to modified metal surfaces are disclosed. Metal oxide surfaces are reduced to form a film integrated with a metal seed layer on a substrate by exposing the metal oxide surfaces to a reducing gas atmosphere comprising radicals of a reducing gas species. The radicals of the reducing gas species can form from exposing the reducing gas species to ultraviolet radiation and/or a plasma. The substrate is maintained at a temperature below a temperature that produces agglomeration of the metal seed layer during exposure to the reducing gas atmosphere, such as below 150° C. for copper. In some embodiments, the reducing gas species can include at least one of hydrogen, ammonia, carbon monoxide, diborane, sulfite compounds, carbon and/or hydrocarbons, phosphites, and hydrazine. | 2014-09-11 |
20140256128 | METHOD AND APPARATUS FOR REMOTE PLASMA TREATMENT FOR REDUCING METAL OXIDES ON A METAL SEED LAYER - Method and apparatus for reducing metal oxide surfaces to modified metal surfaces are disclosed. By exposing a metal oxide surface to a remote plasma, the metal oxide surface on a substrate can be reduced to pure metal and the metal reflowed. A remote plasma apparatus can treat the metal oxide surface as well as cool, load/unload, and move the substrate within a single standalone apparatus. The remote plasma apparatus includes a processing chamber and a controller configured to provide a substrate having a metal seed layer in a processing chamber, form a remote plasma of a reducing gas species where the remote plasma includes radicals, ions, and/or ultraviolet (UV) radiation from the reducing gas species, and expose a metal seed layer of the substrate to the remote plasma to reduce oxide of the metal seed layer to metal and to reflow the metal. | 2014-09-11 |
20140256129 | SEMICONDUCTOR FILM DEPOSITION APPARATUS AND METHOD WITH IMPROVED HEATER COOLING EFFICIENCY - Provided is a physical vapor deposition apparatus with one or multiple deposition chambers for depositing films on substrates. The deposition chambers includes a heater and various cooling features to cool the chamber, the heater and the substrate. The sidewalls and top of the chamber are cooled by a cooling feature. The heater includes a cooling plate. A fitted heated cover is disposed between the heater and the substrate. A cooling pipe delivers a coolant throughout the cooling plate and extends in a high spatial density throughout the surface of the cooling plate. The cooling pipe occupies an area of about 14-20% of the area of the cooling plate and no location on the cooling plate surface is greater than about 15-20 mm from the cooling pipe. The cooling pipe cools the heater rapidly and enables deposition operations of long duration and using high power to be carried out. | 2014-09-11 |
20140256130 | FRONT SIDE WAFER ID PROCESSING - A method for printing a wafer ID on a wafer, the method comprises identifying a wafer ID on a back side of the wafer. Subsequently, etching a plurality of recesses, consistent in size with chip features of the wafer, into the front side of the wafer, such that the plurality of recesses depicts the wafer ID. The method further comprises filling the recesses with a metal. | 2014-09-11 |
20140256131 | SELECTIVE TITANIUM NITRIDE REMOVAL - Methods are described herein for selectively etching titanium nitride relative to dielectric films, which may include, for example, alternative metals and metal oxides lacking in titanium and/or silicon-containing films (e.g. silicon oxide, silicon carbon nitride and low-K dielectric films). The methods include a remote plasma etch formed from a chlorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the titanium nitride. The plasma effluents react with exposed surfaces and selectively remove titanium nitride while very slowly removing the other exposed materials. The substrate processing region may also contain a plasma to facilitate breaking through any titanium oxide layer present on the titanium nitride. The plasma in the substrate processing region may be gently biased relative to the substrate to enhance removal rate of the titanium oxide layer. | 2014-09-11 |
20140256132 | METHOD FOR PATTERNING SEMICONDUCTOR STRUCTURE - A method for patterning a semiconductor structure is provided. The method comprises following steps. A first mask defining a first pattern in a first region and a second pattern in a second region adjacent to the first region is provided. The first pattern defined by the first mask is transferred to a first film structure in the first region, and the second pattern defined by the first mask is transferred to the first film structure in the second region. A second film structure is formed on the first film structure. A second mask defining a third pattern in the first region is provided. At least 50% of a part of the first region occupied by the first pattern defined by the first mask is identical with a part of the first region occupied by the third pattern defined by the second mask. | 2014-09-11 |
20140256133 | POST METAL CHEMICAL-MECHANICAL PLANARIZATION CLEANING PROCESS - A post metal chemical-mechanical planarization (CMP) cleaning process for advanced interconnect technology is provided. The process, which follows CMP, combines an acidic clean and a basic clean in sequence. The process can achieve a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic clean process. The process also eliminates the circular ring defects that occur intermittently during roller brush cleans within a roller brush clean module. | 2014-09-11 |
20140256134 | METHOD AND APPARATUS FOR IMPROVING CMP PLANARITY - Provided is a method of planarizing a semiconductor device. A dielectric layer is formed over a substrate. A plurality of openings is formed in the dielectric layer. The openings have varying distribution densities. The openings are filled with a metal material. A first chemical-mechanical-polishing (CMP) process is performed to remove portions of the metal material over the dielectric layer. Thereafter, a sacrificial layer is formed over the dielectric layer and the metal material. The sacrificial layer has a planar surface. The sacrificial layer is formed through one of: a spin-on process or a flowable chemical vapor deposition (FCVD) process. A second CMP process is then performed to remove the sacrificial layer and portions of the dielectric layer and the metal material therebelow. The second CMP process uses a slurry configured to have a substantially similar polishing selectivity between the sacrificial layer, the dielectric layer, and the metal material. | 2014-09-11 |
20140256135 | METHODS OF REMOVING GATE CAP LAYERS IN CMOS APPLICATIONS - One illustrative method disclosed herein includes the steps of forming a masking layer that covers a P-type transistor and exposes at least a gate cap layer of an N-type transistor, performing a first etching process through the masking layer to remove a portion of the gate cap of the N-type transistor so as to thereby define a reduced thickness gate cap layer for the N-type transistor, removing the masking layer, and performing a common second etching process on the P-type transistor and the N-type transistor that removes a gate cap layer of the P-type transistor and the reduced thickness gate cap of the N-type transistor. | 2014-09-11 |
20140256136 | METHOD FOR FORMING FIN-SHAPED STRUCTURES - The present invention provides a method for forming a fin structure comprising the following steps: first, a multiple-layer structure is formed on a substrate; then, a sacrificial pattern is formed on the multiple-layer structure, a spacer is formed on the sidewall of the sacrificial pattern and disposed on the multiple-layer structure, the sacrificial pattern is removed, the spacer is used as a cap layer to etch parts of the multiple-layer structure, and then the multiple-layer structure is used as a cap layer to etch the substrate and to form at least one fin structure in the substrate. | 2014-09-11 |
20140256137 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING AN IMPLANTATION OF IONS INTO A LAYER OF SPACER MATERIAL - A method includes providing a semiconductor structure including a substrate and a transistor element. A layer of a spacer material is deposited over the substrate and the gate structure, wherein the deposited layer of spacer material has an intrinsic stress. Ions are implanted into the layer of spacer material. After the deposition of the layer of spacer material and the implantation of ions into the layer of spacer material, a sidewall spacer is formed at sidewalls of the gate structure from the layer of spacer material. | 2014-09-11 |
20140256138 | METHOD AND EQUIPMENT FOR REMOVING PHOTORESIST RESIDUE AFTER DRY ETCH - A method for removing photoresist residue includes etching a photoresist layer disposed over a front side of a semiconductor substrate during fabrication of a semiconductor device, and exposing at least one of the front side and the back side of the semiconductor substrate to an atmosphere comprising active oxygen. The method further includes cleaning at least one of the front side and the back side of the semiconductor substrate with a cleaning fluid. | 2014-09-11 |
20140256139 | SELF-ALIGNED TRENCH OVER FIN - A stack of a first hard mask portion and a second hard mask portion is formed over a semiconductor material layer by anisotropically etching a stack, from bottom to top, of a first hard mask layer and a second hard mask layer. The first hard mask portion is laterally recessed by an isotropic etch. A dielectric material layer is conformally deposited and planarized. The dielectric material layer is etched employing an anisotropic etch that is selective to the first hard mask portion to form a dielectric material portion that laterally surrounds the first hard mask portion. After removal of the second and first hard mask portions, the semiconductor material layer is etched employing the dielectric material portion as an etch mask. Optionally, portions of the semiconductor material layer underneath the first and second hard mask portions can be undercut at a periphery. | 2014-09-11 |
20140256140 | Methods Of Forming A Pattern On A Substrate - A method of forming a pattern on a substrate includes forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Photoresist is formed elevationally over and laterally inward of the cylinder-like structures. The photoresist is patterned to form interstitial spaces into the photoresist laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by at least three of the cylinder-like structures. The patterned photoresist is used as an etch mask while etching interstitial openings into the base and while the photoresist is laterally inward of the cylinder-like structures. Other aspects are disclosed. | 2014-09-11 |
20140256141 | METHODS FOR FABRICATING INTEGRATED CIRCUITS UTILIZING SILICON NITRIDE LAYERS - A method of fabricating an integrated circuit includes the steps of providing a semiconductor substrate comprising a semiconductor device disposed thereon and depositing a first silicon nitride layer over the semiconductor substrate and over the semiconductor device using a first deposition process. The first deposition process is a plasma-enhanced chemical vapor deposition (PECVD) process that operates over a plurality of cycles, each cycle having a first time interval and a second time interval. The PECVD process includes the steps of generating a plasma with a power source during the first time interval, the plasma comprising reactive ionic and radical species of a silicon-providing gas and a nitrogen-providing gas, and discontinuing generating the plasma during the second time interval immediately subsequent to the first time interval. The method further includes depositing a second silicon nitride layer over the first silicon nitride layer after the plurality of cycles. | 2014-09-11 |
20140256142 | METHOD OF ETCHING AN ETCH LAYER - A method for etching an etch layer is provided. A glue layer having metallizable terminations is formed over the etch layer. The glue layer is exposed to a patterned light, wherein the metallizable terminations of the glue layer illuminated by the patterned light become unmetallizable. A metal deposition layer is formed on the glue layer, wherein the metal deposition layer only deposits on areas of the glue layer with metallizable terminations of the glue layer. The etch layer is etched through portions of the glue layer without the metal deposition layer. | 2014-09-11 |
20140256143 | Method for Hard Mask Loop with Defect Reduction - The present disclosure provides one embodiment of a method of fabricating an integrated circuit. The method includes forming a patterned hard mask on a substrate; performing a fabrication process to the substrate through openings of the patterned hard mask; performing a first etch process to remove the patterned hard mask; and applying an NHD solution to the substrate, wherein the NHD solution includes ammonium hydroxide, hydrogen peroxide and deionized water with ratios tuned such that the NHD solution is weak basic. | 2014-09-11 |
20140256144 | SEMICONDUCTOR FIN FORMATION METHOD AND MASK SET - A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks. | 2014-09-11 |
20140256145 | DSA GRAPHO-EPITAXY PROCESS WITH ETCH STOP MATERIAL - A method for defining a template for directed self-assembly (DSA) materials includes forming an etch stop layer on a neutral material, forming a mask layer on the etch stop layer and forming an anti-reflection coating (ARC) on the mask layer. A resist layer is patterned on the ARC using optical lithography to form a template pattern. The ARC and the mask layer are reactive ion etched down to the etch stop layer in accordance with the template pattern to form a template structure. The ARC is removed from the mask layer and the template structure is trimmed to reduce a width of the template structure. A wet etch is performed to remove the etch stop layer to permit the neutral material to form an undamaged DSA template for DSA materials. | 2014-09-11 |
20140256146 | Method and Structure to Improve Process Window for Lithography - The present disclosure provides a method for forming resist patterns. The method includes providing a substrate; forming a material layer including a plurality of quenchers on the substrate; forming a resist layer on the material layer; exposing the resist layer; and developing the resist layer to form a structure featuring resist remaining layer on an upper surface of the material layer, and a plurality of resist features on the resist remaining layer to improve the yield of lithography process | 2014-09-11 |
20140256147 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - Advantages of a conventional upper electrode DC power applying manner can be maintained and disadvantages of the upper electrode DC power applying manner can be removed. In a capacitively coupled plasma processing apparatus, a first high frequency power RF | 2014-09-11 |
20140256148 | METHOD AND APPARATUS FOR HIGH EFFICIENCY GAS DISSOCIATION IN INDUCTIVE COUPLED PLASMA REACTOR - Embodiments of the present disclosure relate to method and apparatus for providing processing gases to a process chamber with improved plasma dissociation efficiency. One embodiment of the present disclosure provides a baffle nozzle assembly comprising an outer body defining an extension volume connected to a processing chamber. A processing gas is flown to the processing chamber through the extension volume which is exposed to power source for plasma generation. | 2014-09-11 |
20140256149 | METHOD FOR ETCHING HIGH-K DIELECTRIC USING PULSED BIAS POWER - A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm). | 2014-09-11 |
20140256150 | WAFER PROCESSING METHOD - A wafer processing method for forming a via hole in a wafer. The wafer processing method includes a filament forming step of applying a pulsed laser beam to the wafer, the pulsed laser beam having a transmission wavelength to the wafer, in the condition where the focal point of the pulsed laser beam is set inside the wafer in a subject area where the via hole is to be formed, thereby forming an amorphous filament inside the wafer in the subject area, and an etching step of etching the amorphous filament formed inside the wafer by using an etching agent to thereby form the via hole inside the wafer. | 2014-09-11 |
20140256151 | METHOD FOR REMOVING NITRIDE MATERIAL - A method for removing silicon nitride material includes following steps. A substrate having at least a gate structure formed thereon is provided, and at least a silicon nitride hard mask is formed on top of the gate structure. A first removal is performed to remove a portion of the silicon nitride hard mask with a first phosphoric acid (H | 2014-09-11 |
20140256152 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND RECORDING MEDIUM - A substrate processing apparatus comprising: a processing chamber that can accommodate a plurality of substrates, the interior of which is divided into a plurality of zones; a gas supply system that supplies a first reactive gas, a second reactive gas, and an inert gas to each of the plurality of zones; and an exhaust system for removing the gas from the zones. A thin film is formed on the substrates in the zones by repeatedly executing a plurality of steps in relation to the zones, these steps include the following: a first reactive gas supply step; a first purge step; a second reactive gas supply step; and a second purge step. While the film is being formed, a control unit controls the gas supply system and the gas exhaust system so that the steps performed in the plurality of zones at the same time are different from one another. | 2014-09-11 |
20140256153 | MULTILAYER DIELECTRIC STRUCTURES FOR SEMICONDUCTOR NANO-DEVICES - Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers. | 2014-09-11 |
20140256154 | INTERLEVEL DIELECTRIC STACK FOR INTERCONNECT STRUCTURES - A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity. | 2014-09-11 |
20140256155 | Cleaning Solution for Preventing Pattern Collapse - A chemical solution for use in cleaning a patterned substrate includes water, from approximate 0.01 to 99.98 percent by weight; hydrogen peroxide, from 0 to 30 percent by weight; a pH buffering agent, from approximate 0.01 to 50 percent by weight; a metal chelating agent, from approximate 0 to 10 percent by weight; and a compound for lowering a surface tension of the combination of water, hydrogen peroxide, pH buffering agent, and metal chelating agent. Examples of the compound include an organic solvent, from approximate 0 to 95 percent by weight, or a non-ionic surfactant agent, from approximate 0 to 2 percent by weight. | 2014-09-11 |
20140256156 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device, includes treating a surface of an insulating film formed on a substrate by supplying a first precursor including a predetermined element and a halogen group to the substrate; and forming a thin film including the predetermined element on the treated surface of the insulating film by performing a cycle a predetermined number of times, the cycle comprising: supplying a second precursor including the predetermined element and the halogen group to the substrate; and supplying a third precursor to the substrate. | 2014-09-11 |
20140256157 | VAPORIZING UNIT, FILM FORMING APPARATUS, FILM FORMING METHOD, COMPUTER PROGRAM AND STORAGE MEDIUM - A vaporizing unit, in supplying a gas material produced by vaporizing a liquid material onto a substrate to conduct a film forming process, can vaporize the liquid material with high efficiency to suppress generation of particles. With the vaporizing unit, positively or negatively charged bubbles, which have a diameter of 1000 nm or less, are produced in the liquid material, and the liquid material is atomized to form a mist of the liquid material. Further, the mist of the liquid material is heated and vaporized. The fine bubbles are uniformly dispersed in advance in the liquid material, so that very fine and uniform mist particles of the liquid material are produced when the liquid material is atomized, which makes heat exchange readily conducted. By vaporizing the mist of the liquid material, vaporization efficiency is enhanced, and generation of particles can be suppressed. | 2014-09-11 |
20140256158 | IMPRINT MASK, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, an imprint mask includes a quartz plate. The quartz plate has a plurality of concave sections formed in part of an upper surface on the quartz plate, and impurities are contained in a portion between the concave sections in the quartz plate. | 2014-09-11 |
20140256159 | CVD PRECURSORS - A method of producing silicon containing thin films by the thermal polymerization of a reactive gas mixture bisaminosilacyclobutane and source gas selected from a nitrogen providing gas, an oxygen providing gas and mixtures thereof. The films deposited may be silicon nitride, silicon carbonitride, silicon dioxide or carbon doped silicon dioxide. These films are useful as dielectrics, passivation coatings, barrier coatings, spacers, liners and/or stressors in semiconductor devices. | 2014-09-11 |
20140256160 | Apparatus for Manufacturing Semiconductor Device, Method of Manufacturing Semiconductor Device, and Recording Medium - An apparatus for manufacturing semiconductor devices is provided with a processing liquid supply part for supplying processing liquid into a processing chamber which houses a substrate, a heater part for heating the processing liquid in the processing chamber, and a substrate support part which is provided in the processing chamber and supports the substrate. | 2014-09-11 |
20140256161 | PROCESS SHEET RESISTANCE UNIFORMITY IMPROVEMENT USING MULTIPLE MELT LASER EXPOSURES - Embodiments described herein relate to apparatus and methods of thermal processing. More specifically, apparatus and methods described herein relate to laser thermal treatment of semiconductor substrates by increasing the uniformity of energy distribution in an image at a surface of a substrate. | 2014-09-11 |
20140256162 | MAGNETIC POWER CONNECTOR AND AN ELECTRONIC SYSTEM USING THE MAGNETIC POWER CONNECTOR ASSEMBLY - A magnetic power connector and an electronic system using a magnetic power connector assembly are disclosed, wherein a magnetic element of the magnetic power connector is magnetically attracted to a matching magnetic connector to ensure a stable contact. In addition, the electrical conductive path created between the contact elements does not pass through any elastic elements, thereby avoiding heating and improving the lifespan of the elements. Furthermore, sealing member can be disposed in the gaps between the connector elements to make the connector waterproof. In addition, a trigger signal can be generated by establishing an electrical connection between a signal contact element and the conductive element in the magnetic power connector so as to achieve the purpose of identification or control, thereby avoiding the functional failure caused by the damage of the contact element of the matching magnetic connector. | 2014-09-11 |
20140256163 | MAGNETIC POWER CONNECTOR AND AN ELECTRONIC SYSTEM USING THE MAGNETIC POWER CONNECTOR ASSEMBLY - A magnetic power connector and an electronic system using a magnetic power connector are disclosed, wherein a magnetic element of the magnetic power connector is magnetically attracted to a matching magnetic connector to ensure a stable contact. In addition, the electrical conductive path created between the contact elements does not pass through any elastic elements, thereby avoiding heating and improving the lifespan of the elements. Furthermore, sealing can be disposed in the gaps between the connector elements to make the connector waterproof. In addition, a trigger signal can be generated by establishing an electrical connection between a signal contact element and the conductive element in the magnetic power connector so as to achieve the purpose of identification or control, thereby avoiding the functional failure caused by the damage of the contact element of the matching magnetic connector. | 2014-09-11 |
20140256164 | STORAGE INTERFACE MODULE - A storage interface module including a substrate and a connecting member is provided. The substrate has a first surface, a second surface and a plurality of first openings. The first surface and the second surface are back to each other. Each of the first openings is connected through the first surface and the second surface. The connecting member is disposed on the first surface of the substrate. The connecting member has a first terminal set and a second terminal set, in which a first end of each of the terminals is connected to the first surface, and a second end of each of the terminals passes through the corresponding first opening and protrudes out of the second surface, and a third end of each of the terminals in the second terminal set is connected to the first surface. | 2014-09-11 |
20140256165 | CONNECTOR - A connector includes a lower casing, a circuit board, a connecting head, multiple puncturing terminals, an upper casing and an upper lid. The lower casing includes a base and at least one support pole provided on the base. The base has an accommodating slot. The circuit board disposed in the accommodating slot. The connecting head is disposed on the base, and is electrically connected to the circuit board. The puncturing terminals are disposed on the circuit board. The upper casing includes a casing body, a cantilever structure extending from one side of the casing body and a cable holder located on the cantilever structure. The upper lid is disposed on the upper casing body. The upper lid has a release position and an open position relative to the casing body. | 2014-09-11 |