37th week of 2014 patent applcation highlights part 82 |
Patent application number | Title | Published |
20140258674 | SYSTEM-ON-CHIP AND METHOD OF OPERATING THE SAME - A system on chip (SoC) includes a central processing unit (CPU), an intellectual property (IP) block, and a memory management unit (MMU). The CPU is configured to set a prefetch direction corresponding to a working set of data. The IP block is configured to process the working set of data. The MMU is configured to prefetch a next page table entry from a page table based on the prefetch direction during address translation between a virtual address of the working set of data and a physical address. | 2014-09-11 |
20140258675 | MEMORY CONTROLLER AND MEMORY SYSTEM - A memory controller according to the embodiment includes a front-end unit that issues an invalidation command in response to a command from outside of the memory controller, the command including a logical address, an address translation unit that stores a correspondence relationship between the logical and a physical address, an invalidation command processing unit that, when the invalidation command is received, registers the logical address associated with the invalidation command as an invalidation registration region in an invalidation registration unit and issues a notification to the front-end unit, and an internal processing unit that dissolves a correspondence relationship between the logical address registered in the invalidation registration unit and the physical address in the address translation unit in a predetermined order by referencing the logical address registered in the invalidation registration unit. The front-end unit transmits completion command which indicates the completion of the command in response to the notification. | 2014-09-11 |
20140258676 | APPARATUSES AND METHODS FOR PROVIDING DATA FROM MULTIPLE MEMORIES - Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories provide data to the data bus responsive, at least in part, to a first address. The plurality of memories further provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories provide N bits of data to the data bus at different times. | 2014-09-11 |
20140258677 | ANALYZING POTENTIAL BENEFITS OF VECTORIZATION - Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media (transitory and non-transitory) are described herein for analyzing execution of a plurality of executable instructions and, based on the analysis, providing an indication of a benefit to be obtained by vectorization of at least a subset of the plurality of executable instructions. In various embodiments, the analysis may include identification of the subset of the plurality of executable instructions suitable for conversion to one or more single-instruction multiple-data (“SIMD”) instructions. | 2014-09-11 |
20140258678 | Parallel Configuration of a Reconfigurable Instruction Cell Array - A reconfigurable instruction cell array (RICA) includes a plurality of switch boxes. Each switch box includes an instruction cell and a switch fabric configurable according to a configuration word stored in a latch array for the switch box. The switch boxes are arranged into broadcast sets such that the latch arrays in each broadcast set receive a configuration word in parallel. | 2014-09-11 |
20140258679 | Reconfigurable Protocol Tables Within An ASIC - A high performance computing system is provided with an ASIC that communicates with another device in the system according to a protocol defined by the other device. The ASIC is coupled to a reconfigurable protocol table, in the form of a high speed content-addressable memory (“CAM”). The CAM includes instructions to control the execution of the protocol by the ASIC. The CAM may include instructions to control the ASIC in the event that unanticipated signals or other errors are encountered while executing the protocol. Internal ASIC state data may be routed to the CAM to permit the ASIC to generate a reasonable response to errors either in the design or fabrication of the ASIC or the device with which it is communicating. | 2014-09-11 |
20140258680 | PARALLEL DISPATCH OF COPROCESSOR INSTRUCTIONS IN A MULTI-THREAD PROCESSOR - Techniques are addressed for parallel dispatch of coprocessor and thread instructions to a coprocessor coupled to a threaded processor. A first packet of threaded processor instructions is accessed from an instruction fetch queue (IFQ) and a second packet of coprocessor instructions is accessed from the IFQ. The IFQ includes a plurality of thread queues that are each configured to store instructions associated with a specific thread of instructions. A dispatch circuit is configured to select the first packet of thread instructions from the IFQ and the second packet of coprocessor instructions from the IFQ and send the first packet to a threaded processor and the second packet to the coprocessor in parallel. A data port is configured to share data between the coprocessor and a register file in the threaded processor. Data port operations are accomplished without affecting operations on any thread executing on the threaded processor. | 2014-09-11 |
20140258681 | ANTICIPATED PREFETCHING FOR A PARENT CORE IN A MULTI-CORE CHIP - Embodiments relate to prefetching data on a chip having a scout core and a parent core coupled to the scout core. The method includes determining that a program executed by the parent core requires content stored in a location remote from the parent core. The method includes sending a fetch table address determined by the parent core to the scout core. The method includes accessing a fetch table that is indicated by the fetch table address by the scout core. The fetch table indicates how many of pieces of content are to be fetched by the scout core and a location of the pieces of content. The method includes based on the fetch table indicating, fetching the pieces of content by the scout core. The method includes returning the fetched pieces of content to the parent core. | 2014-09-11 |
20140258682 | PIPELINED PROCESSOR - Provided is a processor with a multi-pipeline fetch structure or a multi-cycle cache structure, including: an integer core which reads instruction transmitted from a lower block, executes an operation corresponding to the instruction, and transmits an instruction address to the lower block; an instruction buffer which stores instruction data which are requested by the integer core by using the instruction address and transmits the instruction data in response to the request of the integer core; and an instruction cache which stores a portion of data of a program memory and transmit the data to the instruction buffer in response to the request of the instruction buffer. | 2014-09-11 |
20140258683 | INSTRUCTION AND LOGIC TO PROVIDE VECTOR HORIZONTAL COMPARE FUNCTIONALITY - Instructions and logic provide vector horizontal compare functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read values from data fields of the specified size in the source operand, corresponding to the mask and compare the values for equality. In some embodiments, responsive to a detection of inequality, a trap may be taken. In some alternative embodiments, a flag may be set. In other alternative embodiments, a mask field may be set to a masked state for the corresponding unequal value(s). In some embodiments, responsive to all unmasked data fields of the source operand being equal to a particular value, that value may be broadcast to all data fields of the specified size in the destination operand. | 2014-09-11 |
20140258684 | System and Method to Increase Lockstep Core Availability - A system and method for increasing lockstep core availability provides for writing a state of a main CPU core to a state buffer, executing one or more instructions of a task by the main CPU core to generate a first output for each executed instruction, and executing the one or more instructions of the task by a checker CPU core to generate a second output for each executed instruction. The method further includes comparing the first output with the second output, and if the first output does not match the second output, generating one or more control signals, and based upon the generation of the one or more control signals, loading the state of the main CPU core from the state buffer to the main CPU core and the checker CPU core. | 2014-09-11 |
20140258685 | Using Reduced Instruction Set Cores - A processor may be built with cores that only execute some partial set of the instructions needed to be fully backwards compliant. Thus, in some embodiments power consumption may be reduced by providing partial cores that only execute certain instructions and not other instructions. The instructions not supported may be handled in other, more energy efficient ways, so that, the overall processor, including the partial core, may be fully backwards compliant. | 2014-09-11 |
20140258686 | INTEGRATED CIRCUIT, ELECTRONIC DEVICE AND INSTRUCTION SCHEDULING METHOD - An integrated circuit comprising a set of data processing units including a first data processing unit and at least one second data processing unit operable at variable frequencies is disclosed. The integrated circuit further includes an instruction scheduler adapted to evaluate data dependencies between individual instructions in a received plurality of instructions and assign the instructions to the first data processing unit and the at least one second data processing unit for parallel execution in accordance with said data dependencies. The integrated circuit is operable in a first power mode and a second power mode. The second power mode is a reduced power mode compared to the first power mode and is adapted to adjust the operating frequency of the first data processing unit and the at least one second data processing unit in the second power mode as a function of the evaluated data dependencies. | 2014-09-11 |
20140258687 | MICRO-OPS INCLUDING PACKED SOURCE AND DESTINATION FIELDS - A method and apparatus for register packing prior to register renaming in a microprocessor are provided. The method includes: receiving a plurality of micro operations (micro-ops) decoded from one or more instructions; packing a plurality of registers which are included in the micro-ops into a packed register structure including a plurality of packed registers based on a preset number of rename ports of a renamer through which the packed registers are read or written for register renaming; and sending the packed registers for register renaming. | 2014-09-11 |
20140258688 | BENCHMARK GENERATION USING INSTRUCTION EXECUTION INFORMATION - Methods and systems are provided for generating a benchmark representative of a reference process. One method involves obtaining execution information for a subset of the plurality of instructions of the reference process from a pipeline of a processing module during execution of those instructions by the processing module, determining performance characteristics quantifying the execution behavior of the reference process based on the execution information, and generating the benchmark process that mimics the quantified execution behavior of the reference process based on the performance characteristics. | 2014-09-11 |
20140258689 | PROCESSOR FOR LARGE GRAPH ALGORITHM COMPUTATIONS AND MATRIX OPERATIONS - A node processor and method for performing matrix operations includes storing, in memory, non-zero matrix elements of a first sparse matrix, non-zero matrix elements of a second sparse matrix, and matrix elements of a sparse results matrix mapped to the node processor. A matrix communications module exchanges with other node processors, non-zero matrix elements of one or more of the first sparse matrix, second sparse matrix, and sparse results matrix. An arithmetic logic unit generates partial results based on the non-zero matrix elements of the first sparse matrix and on the non-zero matrix elements of the second sparse matrix stored in memory. The arithmetic logic unit further generates a final value for each matrix element of the sparse results matrix mapped to the node processor based on the partial results generated by the arithmetic logic unit and on partial results received from the other node processors. | 2014-09-11 |
20140258690 | APPARATUS AND METHOD FOR NON-BLOCKING EXECUTION OF STATIC SCHEDULED PROCESSOR - An apparatus and method for non-blocking execution of a static scheduled processor, the apparatus including a processor to process at least one operation using transferred input data, and an input buffer used to transfer the input data to the processor, and store a result of processing the at least one operation, wherein the processor may include at least one functional unit (FU) to execute the at least one operation, and the at least one FU may process the transferred input data using at least one of a regular latency operation and an irregular latency operation. | 2014-09-11 |
20140258691 | THREAD TRANSITION MANAGEMENT - Various systems, processes, products, and techniques may be used to manage thread transitions. In particular implementations, a system and process for managing thread transitions may include the ability to determine that a transition is to be made regarding the relative use of two data register sets and determine, based on the transition determination, whether to move thread data in at least one of the data register sets to second-level registers. The system and process may also include the ability to move the thread data from at least one data register set to second-level registers based on the move determination. | 2014-09-11 |
20140258692 | DATA PROCESSOR - A RISC data processor in which the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. An instruction for generating flags according to operands' data sizes is defined, and an instruction set handled by the RISC data processor includes an instruction capable of executing an operation on operands in more than one data size. An identical operation process is conducted on the small-size operand and on low-order bits of the large-size operand, and flags are generated capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation. Thus, a reduction in instruction code space of the RISC data processor can be achieved. | 2014-09-11 |
20140258693 | SYSTEM AND METHOD FOR HARDWARE SCHEDULING OF CONDITIONAL BARRIERS AND IMPATIENT BARRIERS - A method and a system are provided for hardware scheduling of barrier instructions. Execution of a plurality of threads to process instructions of a program that includes a barrier instruction is initiated, and when each thread reaches the barrier instruction during execution of program, it is determined whether the thread participates in the barrier instruction. The threads that participate in the barrier instruction are then serially executed to process one or more instructions of the program that follow the barrier instruction. A method and system are also provided for impatient scheduling of barrier instructions. When a portion of the threads that is greater than a minimum number of threads and less than all of the threads in the plurality of threads reaches the barrier instruction each of the threads in the portion is serially executed to process one or more instructions of the program that follow the barrier instruction. | 2014-09-11 |
20140258694 | Apparatus and Method for Branch Instruction Bonding - A processor is configured to identify a branch instruction immediately followed by an architectural delay slot. A single bonded instruction comprising the branch instruction immediately followed by the architectural delay slot is created. The single bonded instruction is loaded into an instruction buffer. | 2014-09-11 |
20140258695 | Last Branch Record Indicators For Transactional Memory - In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed. | 2014-09-11 |
20140258696 | STRIDED TARGET ADDRESS PREDICTOR (STAP) FOR INDIRECT BRANCHES - Systems and methods for predicting an indirect branch target address. A strided target address predictor (STAP) system can observe a striding pattern from a previous indirect branch target. The system can predict a target address based on the observed striding pattern. The system can initialize a confidence counter. The system can determine a previous indirect branch target address. The system can determine a predicted target address. The system can determine an actual target address, determine if the predicted target has the same address as the actual target, determine if a confidence counter is less than a prediction threshold if the predicted target has the same address as the actual target, and if the confidence counter is less than a prediction threshold, increase the value of the confidence counter, reinitialize the confidence counter, assign the value of the difference between the actual target and the previous indirect branch target to the stride length, and assign the address of the actual target to the previous indirect branch target value. | 2014-09-11 |
20140258697 | Apparatus and Method for Transitive Instruction Scheduling - A processor includes a multiple stage pipeline with a scheduler with a wakeup block and select logic. The wakeup block is configured to wake, in a first cycle, all instructions dependent upon a first selected instruction to form a wake instruction set. In a second cycle, the wakeup block wakes instructions dependent upon the wake instruction set to augment the wake instruction set. The select logic selects instructions from the wake instruction set based upon program order. | 2014-09-11 |
20140258698 | INDICATING CRITICAL BATTERY STATUS IN MOBILE DEVICES - An integrated circuit such as a SoC may indicate the critical battery status without powering-on a substantial portion including the host processing cores. The SoC may include a microcontroller, which may cause the critical battery status data to be stored in a static memory and the display unit may retrieve such data from the static memory to display a visual symbol on the screen. The other portions of the SoC such as the dynamic memory, system agent, media processors, and memory controller hubs may be powered-down while the critical battery status is displayed in the visual form on the screen. | 2014-09-11 |
20140258699 | BOOT FAULT TOLERANT DEVICE AND METHOD THEREOF - An auto firmware update device and method for fault-tolerance is provided. According to an embodiment of the invention, the auto firmware update device includes a serial port, a processor, a timer, a memory and a control unit. The serial port is used for coupling to an external device and updating firmware. The processor fetches instructions to boot. The timer is configured to start counting when the processor boots or restart each time, wherein the timer generates an alarm signal if the timer expires before the processor successfully boots. The memory stores a copy of firmware for booting. The control unit receives the alarm signal to stop the processor, downloads another copy of firmware for booting through the serial port to write to the memory, and restarts the processor. | 2014-09-11 |
20140258700 | DYNAMICALLY LOADED MEASURED ENVIRONMENT FOR SECURE CODE LAUNCH - A “Secure Code Launcher” establishes platform trustworthiness, i.e., a trusted computing base (TCB), and uses hardware or firmware based components to securely launch one or more software components. The Secure Code Launcher measures and loads software components by interfacing with security extension functionality integral to one or more hardware or firmware-based components in the computing device. For example, various embodiments of the Secure Code Launcher include firmware-based components that interface with security extension functionality integral to the computing device to measure and load boot managers, operating system (OS) loaders, or other OS components including OS kernels. Similarly, the Secure Code Launcher is capable of measuring and loading software components responsible for installing an instance of an OS. In addition, various embodiments of the Secure Code Launcher provide a hypervisor loader that measures and loads a hypervisor which in turn measures and loads operating system components including virtual machines. | 2014-09-11 |
20140258701 | COMPUTING PLATFORM PERFORMANCE MANAGEMENT WITH RAS SERVICES - In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS RAS services for one or more hardware components, regardless of a particular platform hardware configuration, as long as the platform hardware and OS are in conformance with the PPM interface. | 2014-09-11 |
20140258702 | OPERATING METHODS FOR A COMPUTER SYSTEM AND COMPUTER SYSTEM - An operating method for a computer system having system firmware and an operating element to switch on the computer system includes monitoring the operating element for an actuation, immediately after starting actuation of the operating element, performing a first part of a boot sequence, determining a time period for which the operating element is actuated, executing a remaining part of full boot sequence with the system firmware if the determined time period exceeds a predetermined time period, where the full boot sequence includes activation of a keyboard and mouse through the firmware, and executing a remaining part of limited boot sequence with the system firmware if the determined time period does not exceed the predetermined time period, wherein the limited boot sequence does not include at least one of activation of a keyboard and mouse through the firmware. | 2014-09-11 |
20140258703 | ADAPTIVE DATA SYNCHRONIZATION - In one embodiment, an application module | 2014-09-11 |
20140258704 | CHANGING THE PERSONALITY OF A DEVICE BY INTERCEPTING REQUESTS FOR PERSONALITY INFORMATION - A method and system for a target to adopt the personality of a source without loading the personality information of the source onto the target is provided. The personality system extracts personality information from the source and stores the personality information on a removable storage medium. The storage medium is then connected to the target. The personality system intercepts requests of the target to retrieve personality information, which but for the interception would be serviced based on personality information of the target. When a request is intercepted, the personality system retrieves the personality information from the connected storage medium, rather than from the personality information of the target. The personality system then replies to the request with the retrieved personality information. | 2014-09-11 |
20140258705 | LOW LATENCY SERVER-SIDE REDIRECTION OF UDP-BASED TRANSPORT PROTOCOLS TRAVERSING A CLIENT-SIDE NAT FIREWALL - Systems, methods, and machine-readable media for low latency server-side redirection of User Datagram Protocol (UDP)-based transport protocols traversing a client-side Network Address Translation (NAT) are provided. At a first server, a request for directing a data resource to a client may be received. The request may be received from the client or a back-end server trying to push the data resource to the client. The first server may lack the data resource or the resources to provide the data resource to the client. A second server may be determined for responding to the request. The request may be redirected to the second server. The first server may provide for the second server to connect to the client and directly respond to the request. The second server may have not been previously connected to the client. | 2014-09-11 |
20140258706 | GESTURE-INITIATED ENCRYPTION USING ERROR CORRECTION CODING - Methods and systems for providing gesture-based security are disclosed. For example, a method for establishing secure communications can include receiving one or more human gestures using a sensor on a first device, quantizing the one or more human gestures so as to create a metric of the one or more human gestures, performing an error correction operation on the metric using error correction information derived from a template of the metric to create a corrected metric, performing a hashing operation on the corrected metric to create a metric hash, and comparing the metric hash to a hash of the template to verify that the one or more human gestures sufficiently conform to the template. | 2014-09-11 |
20140258707 | SECURE COMMUNICATIONS SYSTEM FOR DIRECT TRANSFER BETWEEN MOBILE DEVICE - Apparatus and associated methods relate to securely transmitting, directly between two mobile devices, AES-256 encrypted file attachments which are decrypted within an application program (APP) using a decryption key that is available only to the APP. In an illustrative embodiment, the encrypted file may be attached to an e-mail. The e-mail may be transmitted directly to another mobile device via direct Wi-Fi, for example. The e-mail may be transmitted directly to another mobile device using Bluetooth, for example. In encrypted attachment may be deciphered only within the APP running on the receiving mobile device using a private key accessible to only the APP. | 2014-09-11 |
20140258708 | SECURING VARIABLE LENGTH KEYLADDER KEY - A system for securing a variable length keyladder key includes a keyladder decryptor configured to alter a first layer key and to execute a keyladder algorithm to generate a content key, the keyladder algorithm to generate the content key by decrypting an encrypted second layer key with the altered first layer key. The alteration mirrors the alteration applied to encrypt the second layer key by a content server providing content data to be decrypted. The system may further include a cryptographic direct memory access controller (DMAC) coupled with the keyladder decryptor and to decrypt encrypted content data using the generated content key. The keyladder decryptor may be further configured to send the content key to be stored in the DMAC without information regarding how the first layer key was altered. The alteration may include a permutation function or other change or modification. | 2014-09-11 |
20140258709 | INFORMATION PROCESSING APPARATUS, SERVER, METHOD FOR CONTROLLING THE SAME AND STORAGE MEDIUM - An information processing apparatus for accessing a server via a network transmits an issuance request of a certificate including information unique to the information processing apparatus to a certificate authority, and receives the certificate transmitted by the certificate authority in response to the issuance request. The apparatus determines whether or not it is possible to access the server by comparing information unique to the information processing apparatus with the unique information included in the received certificate, and restricts, if it is determined that it is not possible to access the server, issuance of a connection request to the server. | 2014-09-11 |
20140258710 | Mobile Handset Identification and Communication Authentication - Disclosed is a system and method for authenticating a communications channel between a mobile handset associated with a user and an application server for uniquely identifying the mobile handset and for encrypting communications between the mobile handset and the application server over the communication channel is provided. The system includes a certificate authority configured to issue digital certificates to the handset and the application server, as well as software applications operating on both the handset and application server. The digital certificates may be used by the handset and application server to uniquely identify one another as well as to exchange encryption keys by means of which further communication between them may be encrypted. | 2014-09-11 |
20140258711 | Application Specific Certificate Management - Application specific certificate deployment may be provided. An application may generate a security certificate comprising a public key and a first private key. The public key may be stored in a shared segment of a memory store, from where it may be retrieved and signed. The signed public key may be re-deployed and/or used to transmit securely encrypted resources. | 2014-09-11 |
20140258712 | Secure Socket Layer Keystore and Truststore Generation - A method for managing keystore information on a computing device may include requesting a keystore from a distribution system, receiving the keystore from the distribution system, and populating a runtime environment with keystore information contained within the keystore. A method for generating a keystore may include receiving, by a distribution system, a request for a keystore from a computing device, generating a key pair including a public key and a private key, generating a certificate signing request, digitally signing the public key with the private key, generating the keystore, combining the signed public key with the private key in the keystore, and providing the keystore to the computing device. A method for generating a truststore may include receiving, by a distribution system, a request for a truststore from a computing device, generating the truststore, adding a certificate to the truststore, and providing the truststore to the computing device. | 2014-09-11 |
20140258713 | SYSTEMS AND METHODS FOR SECURELY STREAMING MEDIA CONTENT - Systems and methods securely provide media content from a media server to a media client via a network. The media content is segmented to create multiple media segments that are each identified in a playlist, and at least one of the media segments is encrypted using a cryptographic key. The cryptographic key is also identified in the playlist, and the playlist is provided from the media server to the media client via the network. The various media segments and cryptographic keys may then be requested from and provided by the media server using hypertext transport protocol (HTTP) or similar constructs to allow the media client to receive and decrypt the various segments of the media content. | 2014-09-11 |
20140258714 | Federated Digital Rights Management Scheme Including Trusted Systems - Federated systems for issuing playback certifications granting access to technically protected content are described. One embodiment of the system includes a registration server connected to a network, a content server connected to the network and to a trusted system, a first device including a non-volatile memory that is connected to the network and a second device including a non-volatile memory that is connected to the network. In addition, the registration server is configured to provide the first device with a first set of activation information in a first format, the first device is configured to store the first set of activation information in non-volatile memory, the registration server is configured to provide the second device with a second set of activation information in a second format, and the second device is configured to store the second set of activation information in non-volatile memory. | 2014-09-11 |
20140258715 | Session Attribute Propagation through Secure Database Server Tiers - Mechanisms are provided for handling a database client request. An encrypted database client request (DCR) is received, by an unsecure access local agent, from a client computing device as part of a session between the client computing device and a database data processing system. The unsecure access local agent retrieves a database session information (DSI) address corresponding to the session and generates a first unique identifiable key (UIK) based on a portion of the encrypted DCR. The unsecure access local agent generates a DSI mapping data structure that maps the first UIK to the DSI address. A secure access local agent of the database data processing system processes the encrypted DCR using the DSI mapping data structure. | 2014-09-11 |
20140258716 | TOTAL HYPERVISOR ENCRYPTOR - Embodiments are directed towards providing cryptographic services to protect guest operating system (OS) images in virtualized computing environments. A hypervisor may trap privileged operations initiated by guest OS images. These trapped operations may be intercepted by a cryptographic module. A hypervisor may trap a write operation made by a guest OS image, and cryptographic module may encrypt the write buffer and return it the hypervisor. A hypervisor may trap a read operation made by a guest OS image, and provide the encrypted data to the cryptographic module for decrypting. If the data is decrypted, the cryptographic module may provide the decrypted data to the hypervisor which provides the decrypted data to the guest OS image. Also, guest OS image context information may be decrypted and encrypted as the guest OS image is scheduled and de-scheduled on physical CPU(s). Further, if necessary entire guest OS images may be encrypted. | 2014-09-11 |
20140258717 | CLOUD APPLICATION INSTALLED IN CLIENT TERMINAL CONNECTED TO CLOUD SERVER - A cloud application system installed in a client terminal that is connected to a cloud server via a network, the cloud application system comprising: a first driver controlling module configured to display a list of folders of a relevant user in the cloud server by communicating with the cloud server; a second cloud driver controlling module configured to encrypt a file of the cloud server to store it as the encrypted security file when the file is stored in the client terminal. | 2014-09-11 |
20140258718 | METHOD AND SYSTEM FOR SECURE TRANSMISSION OF BIOMETRIC DATA - The invention relates to a system ( | 2014-09-11 |
20140258719 | DISTRIBUTED ENCRYPTION AND ACCESS CONTROL SCHEME IN A CLOUD ENVIRONMENT - System, computer readable medium and method for decryption. The method may include receiving, by a third computerized system and from a fourth computerized system, a first encrypted file entity key and signed access metadata. The first encrypted file entity key is created by encrypting a file entity key by a first computerized system using an encryption key of a second computerized system. The signed access metadata is signed by the file entity key. The encrypted file entity is created by encrypting a file entity by the first computerized system using the file entity key. Sending, by the third computerized system, the signed access metadata and the first encrypted file entity key to the second computerized system. Receiving a response from the second computerized system. Determining, based on the response from the second computerized system, whether to facilitate a decryption of the encrypted file entity by the fourth computerized entity. | 2014-09-11 |
20140258720 | SYSTEMS AND METHODS FOR TRANSPARENT PER-FILE ENCRYPTION AND DECRYPTION VIA METADATA IDENTIFICATION - A new approach is proposed that contemplates systems and methods to support encryption and decryption of files including data and source code associated with a software application running in a virtual environment on a per-file basis outside of a kernel of an operating system. The proposed approach utilizes metadata of the files associated with the software application to determine the files to be encrypted and decrypted and to monitor various properties of the files including the sizes of the unencrypted files for accurate reporting of information about the files. Under such an approach, the source code of the applications are encrypted and decrypted transparently at the file level without modifying or altering any of the source code of the application, the kernel and libraries of the operating system, and/or any components which are proprietary to the virtual environment. | 2014-09-11 |
20140258721 | LINEAR FEEDBACK SHIFT REGISTER (LFSR) - A wireless communication device is described. The wireless communication device includes a linear feedback shift register. The linear feedback shift register is initialized. The linear feedback shift register is a word based odd characteristic linear feedback shift register. The linear feedback shift register includes multiple 64-bit registers. A feedback function output is generated using the 64-bit registers. The feedback function output is placed into a highest register of the linear feedback shift register. | 2014-09-11 |
20140258722 | Forwarding E-Mail From A Wireless Device - A system and method of sending an e-mail message associated with a wireless device is provided. A request to forward or reply to an original e-mail message is sent from the wireless device to a server. The request contains one or more recipients and includes a message identifier of an original e-mail message. A portion indicator is provided for retrieving portions of the original e-mail message identified by the message identifier. An e-mail message is sent to the one or more recipients comprising any added user text and the one or more retrieved portions of the original e-mail message such that text of the original message that the user may not be aware is not forwarded to new recipients. | 2014-09-11 |
20140258723 | METHOD AND A DEVICE OF AUTHENTICATION IN THE CONVERGED WIRELESS NETWORK - In the existing WLAN network, the authentication method using the pre-shared cipher key has low safety, and is not applicable for large scale deployment; while the authentication method based on 802.1x is very complex and needs to introduce EAP/RADIUS servers. The invention provides an authentication method and device in a converged wireless access network, wherein, the wireless access network and the UE all maintain a cipher key of a UE for accessing the first wireless access network, when the UE accessing the second wireless access network, the wireless access network and the UE implements the authentication based on the cipher key. In the invention, the UE key for accessing the first wireless access network, which has been obtained safely, is used in the authentication for the access of the UE in the second wireless access network. Compared to the traditional solution of the shared cipher key, the proposed solution ensures safety; and compared to the traditional 802.1x solution, it saves the operation of obtaining the cipher key via negotiating, and does not need to involve the network element such as key servers etc. | 2014-09-11 |
20140258724 | SECURE SIMPLE ENROLLMENT - Methods, systems, and apparatus are disclosed for generating one or more device identifiers based on a public key associated with a respective device. Various embodiments include condensing and/or hashing a device public key to generate the corresponding device identifier. By using the relationship between a device public key and its device identifier, public key exchanges are implemented to verify this relationship and facilitate device enrollment into one or more networks. The embodiments further describe enrolling one or more devices into networks and/or authorizing devices to enroll one more devices into networks based on public key exchanges and verification that the one or more device identifiers match the respective public keys. Embodiments for authorizing other devices describe a first device enrolling a second device in a first network and authorizing a third device to enroll the second device in a second network using an exchange of public keys and/or messages. | 2014-09-11 |
20140258725 | SYSTEMS AND METHODS FOR IMPLEMENTING TRANSPARENT ENCRYPTION - A method of providing transparent encryption for a web resource includes a key manager receiving an encryption key policy; receiving user identifiers and resource locators; defining an access control list based the user identifiers; generating an encryption key and a key identifier for a first resource locator; and establishing a secure communication channel between first and second watchdog modules. The method also includes the watchdog sending encryption information using the secure communication channel. The method also includes a transparent encryption module storing the encryption key and the access control list in protected memory; receiving an input comprising a request to access the first resource stored in the web resource; determining that the user identifier is included in the access control list; encrypting data using the encryption key; and decrypting data using the encryption key. | 2014-09-11 |
20140258726 | SMART CARD, ELECTRONIC DEVICE, AND PORTABLE ELECTRONIC DEVICE - According to an embodiment, a smart card includes a communication section, a generation part, a first record section and an erasure section. The communication section transmits and receives data with the external device. The generation section generates a session key according to the command which is received by the communication section and requires generation of a session key. The first record section stores the session key generated by the generation section. The erasure section erases the session key when a holding period of the session key stored in the first record section exceeds a threshold. | 2014-09-11 |
20140258727 | System and Method of Using a Signed GUID - A method and apparatus wherein the method includes the steps of generating a globally unique identifier (GUID) for a security system appliance, saving a public key and private key of the security system appliance in a memory of the security system appliance, a manufacturer of the security system appliance generating a signed version of the GUID and the public key, saving the signed version of the GUID and public key in the memory of the security system appliance, the security system appliance sending a registration message including the signed version of the GUID and public key to a security system server and the security system server authenticating the security system appliance using the signed version of the GUID and public key of the security system appliance and a public key of the manufacturer. | 2014-09-11 |
20140258728 | SECURE PASSWORD GENERATION - A secure password generation method and system is provided. The method includes enabling by a processor of a computing system, password translation software. The computer processor generates and stores the random translation key. A first password is received and a second associated password is generated. The computer processor associates the second password with a secure application. The computer processor stores the random translation key within an external memory device and disables a connection between the computing system and the external memory device. | 2014-09-11 |
20140258729 | Stored Authorization Status for Cryptographic Operations - A hardware authentication device is disclosed that uses a cryptographic signature verification operation to authorize a subsequent cryptographic operation to be performed using the same or different keys and stores that authorization status in protected memory. The cryptographic algorithm may be an ECDSA signature, SHA-based Message Authentication Code (MAC) or any other cryptographic algorithm. The authorization status may be stored for a number of uses for a period of time or until a certain event occurs. In some implementations, the authorization status and the key that was authorized are stored in the same protected location in memory to preserve their relation to each other and prevent modification of either of them. Depending on system policy, the authorization mechanism might be a static stored external token that authorizes key use or an authorization process that is regenerated using a random (e.g., unique) number. | 2014-09-11 |
20140258730 | DATA PROTECTION USING PROGRAMMATICALLY GENERATED KEY PAIRS FROM A MASTER KEY AND A DESCRIPTOR - Systems and methods are disclosed for allowing an authority to monitor a computer user's information in a most palatable manner for the computer user. The authority is provided access to information with encrypted user identification information and the user is notified if decryption is facilitated. The systems and methods also include a novel key production system whereby large numbers of deterministic key pairs may be created for use in the monitoring system. | 2014-09-11 |
20140258731 | DATA ENCRYPTION SYSTEM AND METHOD - A data encryption method is implemented by a data encryption system including a processing unit and a plurality of operating units which are electrically connected to the processing unit. Each operating unit includes an encryption element and a memory element storing a plurality of encryption programs. Each encryption program has a different combination of encryption algorithm and encryption mode. The data encryption method includes steps of: selecting one of the encryption programs randomly by each encryption element; receiving, by each encryption element, one of a plurality of keys randomly generated; inputting an unencrypted data; dividing the unencrypted data into a plurality of unencrypted data blocks by the processing unit; and encrypting the unencrypted data blocks according to the selected encryption programs and received keys by the encryption elements, respectively, to generate an encrypted data. A data encryption system is also disclosed. | 2014-09-11 |
20140258732 | SOURCE IDENTIFICATION FOR UNAUTHORIZED COPIES OF CONTENT - Systems and methods for authentication generate keys from secret credentials shared between authenticating parties and authenticators. Generation of the keys may involve utilizing specialized information in the form of parameters that are used to specialize keys. Keys and/or information derived from keys held by multiple authorities may be used to generate other keys such that signatures requiring such keys and/or information can be verified without access to the keys. Keys may also be derived to form a hierarchy of keys that are distributed such that a key holder's ability to decrypt data depends on the key's position in the hierarchy relative to the position of a key used to encrypt the data. Key hierarchies may also be used to distribute key sets to content processing devices to enable the devices to decrypt content such that sources or potential sources of unauthorized content are identifiable from the decrypted content. | 2014-09-11 |
20140258733 | ROOTS-OF-TRUST FOR MEASUREMENT OF VIRTUAL MACHINES - Embodiments of techniques and systems associated with roots-of-trust (RTMs) for measurement of virtual machines (VMs) are disclosed. In some embodiments, a computing platform may provide a virtual machine RTM (vRTM) in a first secure enclave of the computing platform. The computing platform may be configured to perform an integrity measurement of the first secure enclave. The computing platform may provide a virtual machine trusted platform module (vTPM), for a guest VM, outside the first secure enclave of the computing platform. The computing platform may initiate a chain of integrity measurements between the vRTM and a resource of the guest VM. Other embodiments may be described and/or claimed. | 2014-09-11 |
20140258734 | DATA SECURITY METHOD AND ELECTRONIC DEVICE IMPLEMENTING THE SAME - A method and an apparatus that may safely secure data in an electronic device including a computing resource, that is, software (for example, an operating system) and hardware (for example, a memory and a Central Processing Unit (CPU)) for operating the electronic device are provided. The method includes receiving a request for an application key from a data generation application or a proxy application that executes encryption of data in place of the data generation application, generating an application key using an application Identification (ID) corresponding to the data generation application and a security key stored in a secure area of the electronic device, in response to the request, and encrypting data using the generated application key. | 2014-09-11 |
20140258735 | PORTABLE RECORDING MEDIUM, SYSTEM INCLUDING THE PORTABLE RECORDING MEDIUM, AND DATA RECOVERY METHOD OF THE PORTABLE RECORDING MEDIUM - A technique of the present invention includes a storage section for storing contents data and an encryption flag indicating that any one of an encryption recording mode and a non-encryption recording mode is set, an encrypting engine for encrypting contents data using an encryption key when the encryption recording mode is set, and a control section for controlling a storage section so that the encryption key and the encrypted contents data are stored when the encryption recording mode is set. Further, when the setting is changed from the encryption recording mode into the non-encryption recording mode, the control section controls the storage section so that the encryption flag is changed to indicate the setting of the non-encryption recording mode with the continuous storage of the encryption key. | 2014-09-11 |
20140258736 | Systems and Methods for Maintaining Integrity and Secrecy in Untrusted Computing Platforms - A method for operating a computing system with a trusted processor include generating a secret cryptographic key based on a physically unclonable function in at least one hardware component in the trusted processor, generating a first public key and first private key using first secret cryptographic key, and executing instruction code corresponding to a first software program. The method further includes generating output data with the trusted processor during execution of the first software program, generating encrypted data corresponding to the output data using the first public key for at least a portion of the encryption, generating a signature of the encrypted data, and transmitting with an input/output (I/O) interface operatively connected to the trusted processor the encrypted data and the signature for storage in an untrusted memory. | 2014-09-11 |
20140258737 | IMAGE FORMING APPARATUS AND CONTROL METHOD THEREOF - An image forming apparatus including an image forming unit to form an image, a user switch unit to output a user operation signal to switch between a power-on state and a power-off state of the image forming apparatus, a main controller to control the image forming unit and to output a power control signal based on the user operation signal, a power switching unit to selectively supply operation power to the main controller based on the user operation signal and the power control signal, and an auxiliary controller to control the power switching unit such that the operation power is not supplied to the main controller when the power control signal is changed in a power-off state. | 2014-09-11 |
20140258738 | EMPLOYING POWER OVER ETHERNET FOR AUXILIARY POWER IN COMPUTER SYSTEMS - Methods and apparatus for implementing Power over Ethernet (PoE) for auxiliary power in computer systems. Under aspects of the methods, one or more voltage inputs comprising standard power input is employed by a power control component in a network interface in an apparatus such as a network adaptor board, a System on a Chip (SoC), computer server or server blade to supply power to a network controller on the apparatus when the apparatus is operating at a normal power state. To enable the apparatus to maintain network communication when operating at a reduced power state, a PoE power input derived from at least one PoE signal received at at least one Ethernet jack of the apparatus is employed to provide power to the network controller absent use or availability of the standard power input. Accordingly, the PoE power input facilitates an auxiliary power function that may be used alone or in combination with existing (as applicable) auxiliary power input when apparatus are operated in reduced power states. | 2014-09-11 |
20140258739 | ADAPTIVE POWER CONTROL IN A NETWORK - A power manager in a network monitors a set of multiple interconnected network elements for failures. During non-failing operation, the multiple interconnected network elements cooperatively communicate amongst each other to provide one or more computer devices connectivity to a core network. In response to detecting a failing network element in the set, the network power manager adaptively controls power settings of at least one non-failing network element in the set of multiple interconnected network elements. Via power control notifications, power settings of the non-failing network elements that depend on the particular failing network element can be reduced to save power in the network. Subsequent to correcting the failure, when the particular network element is functioning properly again, the network power manager notifies the non-failing network elements in the reduced power mode to switch back to a standard power mode and standard operational mode again. | 2014-09-11 |
20140258740 | INTERNAL COMMUNICATION INTERCONNECT SCALABILITY - Interconnect frequency control technologies of adjusting an operating frequency of a communication interconnect between an integrated circuit comprising multiple functional hardware units are described. A power management unit (PMU) is configured to collect workload data from the functional hardware units and determine a workload metric from the workload data. The PMU adjusts an operating frequency of the communication interconnect in view of the workload metric. | 2014-09-11 |
20140258741 | PROTECTIVE DEVICE AND METHOD FOR PREVENTING SUPPLY VOLTAGE SAG OF MICROCONTROLLER FROM SAGIN ELECTRONIC CIGARETTE - A protective device and method for preventing supply voltage of microcontroller from sag in electronic cigarette is provided, comprising a microcontroller, a power supply module, a field effect transistor, an energy storage circuit, wherein, the energy storage circuit is connected between the microcontroller and the power supply module, the energy storage circuit supplies electric power to the microcontroller when an over current or short circuit occurs, and maintains the supply voltage of the microcontroller not being less than its minimal operating voltage in a certain period of time; the microcontroller processes the over current or short circuit signal and turns off the MOSFET to cut off the current flow in a load circuit. The unstable or uncontrollable phenomena of the microcontroller in the existing technology are resolved. The circuit of the present invention is simple and low cost. | 2014-09-11 |
20140258742 | HYBRID FIBER OPTIC AND POWER OVER ETHERNET - Connectors for connecting between devices using optical communication where at least one of the devices is configured to receive power from the connector by one or more power over Ethernet (PoE) contacts in the plug. In some variations, described herein are hybrid fiber optic power over Ethernet (PoE) cables that provide power and optically transmit information between and/or to Ethernet devices. Also described herein are extenders configured to provide optical communication between two (or more) devices where at least one of the devices is configured to receive power from the extender by power over Ethernet. | 2014-09-11 |
20140258743 | MEDICAL COMMUNICATION HUB AND ASSOCIATED METHODS - A powered medical communication hub including a housing and a rear interface assembly. The rear interface assembly includes a first data link configured to transmit first medical data to a processing system and a power link configured to receive a first amount of power. The hub also includes a power distribution module disposed within the housing, electrically coupled to the power link, and configured to convert the first amount of power into a plurality of power levels, and a forward interface assembly including a first connector communicatively coupled to the first data link and electrically coupled to the power distribution module, the first connector being configured to provide a first medical sensing device coupled thereto with a second amount of power equal to one of the plurality of power levels and receive the first medical data from the first medical sensing device. | 2014-09-11 |
20140258744 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR CONTROLLING PROCESSOR CARD POWER CONSUMPTION IN A NETWORK TEST EQUIPMENT CHASSIS THAT INCLUDES A PLURALITY OF PROCESSOR CARDS - Methods, systems, and computer readable media for controlling processor card power consumption are disclosed. In one example, the method is conducted in a network test equipment chassis that includes a plurality of processor cards that implements network testing functions. The method includes detecting an event or status associated with one of the plurality of processor cards and determining whether the event or status satisfies a condition of at least one power management rule. In response to determining that the event or status satisfies a condition of the at least one power management rule, the method further includes adjusting power consumption of the processor card in the network test equipment in accordance with the at least one power management rule. | 2014-09-11 |
20140258745 | POWER STATE CHANGE IN DISK DRIVE BASED ON DISK ACCESS HISTORY - A data storage device that includes a magnetic storage device selects one or more power states of the magnetic storage device based on a time interval since a most recent time data has been read from or written to the magnetic storage device. The power state of the magnetic storage device can be changed from a higher power consumption state to a lower power consumption state when the time interval exceeds a predetermined value. The power consumption state may be changed from an active servo state to an intermediate power consumption state, a park state, and/or a standby state, depending on the time elapsed since the most recent time data has been read from or written to the magnetic storage device. | 2014-09-11 |
20140258746 | Collective Operation Management In A Parallel Computer - Methods, apparatuses, and computer program products for collective operation management in a parallel computer are provided. Embodiments include a parallel computer having a first compute node operatively coupled for data communications over a tree data communications network with a plurality of child compute nodes. Embodiments also include each child compute node performing a first collective operation. The first compute rode, for each child compute node, receives from the child compute node, a result of the first collective operation performed by the child compute node. In response to receiving at least one result, the first compute node reduces a power consumption level of the child compute node. | 2014-09-11 |
20140258747 | TECHNIQUES FOR MULTIMEDIA PLAYBACK - Various embodiments are generally directed to an apparatus, method and other techniques for receiving multimedia information at a computing device and receiving one or more of power information and bandwidth information for the computing device. In various embodiments, video processing may be disabled for the computing device when the power information is below a power threshold or bandwidth information is below a bandwidth threshold and an audio only portion of multimedia information may be sent to one or more output devices coupled to the computing device. Other embodiments are described and claimed. | 2014-09-11 |
20140258748 | Collective Operation Management In A Parallel Computer - Methods, apparatuses, and computer program products for collective operation management in a parallel computer are provided. Embodiments include a parallel computer having a first compute node operatively coupled for data communications over a tree data communications network with a plurality of child compute nodes. Embodiments also include each child compute node performing a first collective operation. The first compute rode, for each child compute node, receives from the child compute node, a result of the first collective operation performed by the child compute node. In response to receiving at least one result, the first compute node reduces a power consumption level of the child compute node. | 2014-09-11 |
20140258749 | DYNAMICALLY ENTERING LOW POWER STATES DURING ACTIVE WORKLOADS - Systems and methods may provide for identifying runtime information associated with an active workload of a platform, and making an active idle state determination for the platform based on at least in part the runtime information. In addition, a low power state of a shared resource on the platform may be controlled concurrently with an execution of the active workload based on at least in part the active idle state determination. | 2014-09-11 |
20140258750 | CONTROL SYSTEM AND METHOD FOR SERVER - A control system for a server includes a control chip, a switch module, a hardware power module, a software power module, a power chip, and a basement management controller (BMC) chip. The hardware power module and the software power module output first and second power signals, respectively. The control chip outputs corresponding state signals according to a control signal outputted by the BMC chip. The switch module selectively outputs the first or the second power signals to the power supply chip, to control the power supply chip to perform corresponding power operations. | 2014-09-11 |
20140258751 | MOBILE SYSTEM OPTIMIZATION METHOD - Provided is a method of a mobile system, comprising executing an application at the mobile system, determining an execution condition of the application, and controlling a performance of the mobile system in response to a result of the determined execution condition before the application performs an actual workload. The mobile system optimization method enhances the performance of the mobile system by utilizing the same resources. | 2014-09-11 |
20140258752 | POWER MANAGEMENT FOR PROCESSOR - Techniques are generally described related to management of power consumption for a processor. One example method may include identifying a target operating constraint and a first operating parameter; determining a second operating parameter based on the target operating constraint and the first operating parameter; estimating an actual operating constraint; comparing the target operating constraint and the actual operating constraint; and setting up the first operating parameter and the second operating parameter of the processor based on a comparison of the target operating constraint and the actual operating constraint, wherein the target operating constraint is not a worst-case operating constraint. Other examples of methods, systems, and computer programs related to managing power consumption for a processor are also contemplated. | 2014-09-11 |
20140258753 | INFORMATION PROCESSING APPARATUS, METHOD FOR CONTROLLING INFORMATION PROCESSING APPARATUS, AND STORAGE MEDIUM - An information processing apparatus includes a selection unit configured to select a mode of processing to be executed when a power supply state of the information processing apparatus is shifted from a first power supply state to a second power supply state, a determination unit configured to determine time necessary for executing the processing based on the mode selected by the selection unit, an execution unit configured to execute the processing in the mode selected by the selection unit, and a control unit configured to control the execution unit to execute the processing again when the processing has not been completed within the time determined by the determination unit. | 2014-09-11 |
20140258754 | Reducing Power Consumption During Graphics Rendering - In accordance with some embodiments, the knowledge that a capped frame time is used can be exploited to reduce power consumption. Generally a capped frame time is a pre-allocated amount of time to apply power for rendering in graphics processing. Generally the frame time involves the application of power and some down time in which only idle power is applied pending the next frame time. By making better use of that down time, power consumption reductions can be achieved in some embodiments. | 2014-09-11 |
20140258755 | STORAGE DEVICE POWER FAILURE INFRASTRUCTURE - A power fail protection system wherein pluralities of individual energy storage components are electrically connected to one or more SSD drives during a power failure though a power switch matrix. Typically an individual high-energy supply will be connected to one SSD drive during a power failure. The power fail protection system may also test the transient energy response of individual energy storage components, or include an imminent power fail warning connected directly to an SSD drive interface. Some embodiments further provide for identifying, reporting, and replacing weak energy storage components. High-energy supplies may be modular, or hot swappable. | 2014-09-11 |
20140258756 | METHOD AND APPARATUS FOR OPERATING POWER SAVING MODE OF TERMINAL - Disclosed is a method of operating a power saving mode of a terminal, the method including setting at least one power saving display object to be displayed in the power saving mode; configuring a power saving display object DataBase (DB) including information corresponding to the at least one power saving display object, and updating the information corresponding to the at least one power saving display object; beginning an operation of the power saving mode; and displaying the at least one power saving display object in response to a request for a display operation of the at least one power saving display object. | 2014-09-11 |
20140258757 | Methods And Apparatuses For Reducing Power Consumption Of Processor Switch Operations - Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions. | 2014-09-11 |
20140258758 | IMAGE FORMING APPARATUS AND CONTROL METHOD THEREOF - An image forming apparatus and a control method thereof includes an image forming unit to form images, a main control unit to control operations of the image forming unit; a switching unit to selectively supply an operating voltage to the main control unit according to a level of the voltage control, a power mode selecting unit to convert an on state or an off state according to a user's operation, a first voltage determining unit to determine a level of the control voltage according to the state of the power mode selecting unit, and a second voltage determining unit to determine the level of the control voltage in parallel with the first voltage determining unit, according to the control signal output from the main control unit. | 2014-09-11 |
20140258759 | SYSTEM AND METHOD FOR DE-QUEUING AN ACTIVE QUEUE - Aspects of the disclosure pertain to a system and method for de-queuing an active queue. The system promotes power efficiency by providing a mechanism for allowing some of its active queues to be de-queued and one or more of its processors associated with those active queues to be powered off during low traffic periods. Using fewer than all of its queues and processors, the system can handle incoming traffic during these low traffic periods without packet loss and without ordering issues. | 2014-09-11 |
20140258760 | Controlling Operating Voltage Of A Processor - In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed. | 2014-09-11 |
20140258761 | ASYNCHRONOUS MANAGEMENT OF ACCESS REQUESTS TO CONTROL POWER CONSUMPTION - Systems and methods are disclosed for asynchronous management of access requests to control power consumption. In some cases, by asynchronously managing power within a system, multiple dies of a NVM can simultaneously draw current in order to match the power demand. In particular, an arbiter of the system can receive multiple requests to draw current, where each request may be associated with a different die of the NVM. In some embodiments, the arbiter can determine the servicing order using the time of arrival of the request (e.g., a first-in, first-out scheme). In other embodiments, the arbiter can simultaneously service multiple requests so long as the servicing of the multiple requests does not exceed a power budget. | 2014-09-11 |
20140258762 | SERVER AND POWER MANAGEMENT METHOD - A server and a power management method for the server are provided. The server is connected to other servers. The server includes a power source and a battery. The battery and batteries of other servers are in parallel. The server monitors power supplying of the server in real time. When the power source does not provide enough power for the server, the server sends a trigger signal to control the battery and the batteries of other servers to provide power for the server. | 2014-09-11 |
20140258763 | SERVER - The server includes a power supply apparatus; a power receipt terminal connected to a network and supplied with electric power fed to over the network; and a controller configured to perform state monitoring of the server by being supplied with electric power from the power supply apparatus, or electric power from the power supply apparatus and electric power from the power receipt terminal, and when supply of electric power from the power supply apparatus is quitted, the controller changes an electric power supply route so as to be supplied the electric power only from the power receipt terminal. | 2014-09-11 |
20140258764 | TIMING SYNCHRONIZATION CIRCUIT WITH LOOP COUNTER - An apparatus for synchronizing an output dock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback dock signal representative of the output clock signal responsive a strobe signal. The control logic is operable to generate an enable signal based on the reference clock signal and generate the strobe signal based on the feedback clock signal. The counter is operable to count cycles of the reference clock signal occurring between the enable signal and the strobe signal to generate a loop count for the first timing synchronization circuit. | 2014-09-11 |
20140258765 | CPU Current Ripple and OCV Effect Mitigation - High frequency current transients, due to logic switching inside the CPU, are reduced by applying clock signals having different relative phases to different parts of the CPU. This reduces the amplitude of current variations, and hence noise induced onto the power supply voltage. In some embodiments, different CPU cores within multi-core CPUs are clocked with a different clock phases. Additionally a method and circuit for low-latency communication in the presence of large OCV effects is provided. The low-latency communication may be based on a FIFO. Strobes are used to indicate safe points in time to update and read signals between transmitter and receiver. The strobes are generated in a central clock generation module. The strobe mechanism is used to transfer the read and write pointers between the transmitter and receiver, while the payload data is transferred using a FIFO data array that allows data writes to be asynchronous to corresponding data reads. | 2014-09-11 |
20140258766 | Technique For Sub-Microsecond Latency Measurement Across A Bus - Methods and systems for determining latency across a bus, such as a PCIe bus, coupling a field programmable gate array (FPGA) and a processor having different time incrementation rates. Both the FPGA and the processor count clock ticks independently, and using a calibration offset and the two incrementation rates, the processor converts the FPGA clock ticks into processor clock ticks in order to determine latency across the bus. | 2014-09-11 |
20140258767 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to input/output a normal data synchronized with a center of a source clock, in response to data input/output commands; and a data recovery information signal input/output block configured to receive and store a data recovery information signal synchronized with an edge of the source clock and having a predetermined pattern, in response to either a command of the data input/output commands or the predetermined command upon entry to a data recovery operating mode, and to output the data recovery information signal after the passage of a predetermined time period. | 2014-09-11 |
20140258768 | CHANGING SETTINGS FOR A TRANSIENT PERIOD ASSOCIATED WITH A DETERMINISTIC EVENT - Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances. | 2014-09-11 |
20140258769 | PARTIAL R-BLOCK RECYCLING - An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of R-blocks. The controller is coupled to the non-volatile memory. The controller is configured to (i) write data using the R-blocks as a unit of allocation and (ii) perform recycling operations selectively on either an entire one of the R-blocks or a portion less than all of one of the R-blocks. | 2014-09-11 |
20140258770 | INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS, AND COMPUTER PROGRAM PRODUCT - The system includes: an extracting part extracting one or more devices where the same phenomenon as occurred in a target device had occurred; an index-value calculating part acquiring device information of the target device and calculating an index value thereof, and acquiring pieces of device information of the devices and calculating index values thereof; a first-similarity calculating part calculating a first similarity between the index values of the target device and each of the devices; a second-similarity calculating part acquiring environment information of the target device and pieces of environment information of the devices, and calculating a second similarity between the environment informations of the target device and each of the devices; and a presuming part determining one or more reference devices based on the similarities, and presuming a replacement part of the target device based on replacement parts that the reference devices used for elimination of the phenomenon. | 2014-09-11 |
20140258771 | HIGH-AVAILABILITY CLUSTER ARCHITECTURE AND PROTOCOL - Methods and systems are provided for an improved cluster-based network architecture. According to one embodiment, an active connection is established between a first interface of a network device and an enabled interface of a first cluster unit of a high availability (HA) cluster. The HA cluster is configured to provide connectivity between network devices of an internal and external network. A backup connection is established between a second interface of the network device and a disabled interface of a second cluster unit. While the first cluster unit is operational and has connectivity, it receives and processes all traffic originated by the network device that is destined for the external network. Upon determining the first cluster unit has failed or has lost connectivity, then all subsequent traffic originated by the network device that is destined for the external network is directed to the second cluster unit. | 2014-09-11 |
20140258772 | UTILIZING BACKWARD DEFECT INDICATIONS IN Y-CABLE PROTECTION SWITCHING - In accordance with teachings of the present disclosure, a method includes—at a network element communicatively coupled to a y-cable through two transmitters of the network element—transmitting data from a transmitter through the y-cable to a client and withholding transmission from the other transmitter, and determining whether receivers have received a backward defect indicator from the client. The method further includes determining that an interruption has occurred within a transmission media between the network element and the client, based on the determinations of whether the receivers have received the backward defect indicator from the client. The method also includes, based on the determination of the interruption, transmitting data from the other transmitter through the y-cable to the client and withholding transmission from the transmitter. | 2014-09-11 |
20140258773 | Match Server for a Financial Exchange Having Fault Tolerant Operation - Fault tolerant operation is disclosed for a primary match server of a financial exchange using an active copy-cat instance, a.k.a. backup match server, that mirrors operations in the primary match server, but only after those operations have successfully completed in the primary match server. Fault tolerant logic monitors inputs and outputs of the primary match server and gates those inputs to the backup match server once a given input has been processed. The outputs of the backup match server are then compared with the outputs of the primary match server to ensure correct operation. The disclosed embodiments further relate to fault tolerant failover mechanism allowing the backup match server to take over for the primary match server in a fault situation wherein the primary and backup match servers are loosely coupled, i.e. they need not be aware that they are operating in a fault tolerant environment. | 2014-09-11 |