37th week of 2013 patent applcation highlights part 17 |
Patent application number | Title | Published |
20130234253 | SELF-ALIGNED CONTACT FOR REPLACEMENT METAL GATE AND SILICIDE LAST PROCESSES - A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches. | 2013-09-12 |
20130234254 | METHOD OF HYBRID HIGH-K/METAL-GATE STACK FABRICATION - A process fabricating a semiconductor device with a hybrid HK/metal gate stack fabrication is disclosed. The process includes providing a semiconductor substrate having a plurality of isolation features between a PFET region and a NFET region, and forming gate stacks on the semiconductor substrate. In the PFET region, the gate stack is formed as a HK/metal gate. In the NFET region, the gate stack is formed as a polysilicon gate. A high-resistor is also formed on the semiconductor substrate by utilizing another polysilicon gate. | 2013-09-12 |
20130234255 | Spacer Elements for Semiconductor Device - The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. In an embodiment, the first spacer element includes silicon nitride. A second spacer element is adjacent the first spacer element. In an embodiment, the second spacer element includes silicon oxide. A raised source and a first raised drain is provided laterally contacting sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element. | 2013-09-12 |
20130234256 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element | 2013-09-12 |
20130234257 | PACKAGE CONFIGURATIONS FOR LOW EMI CIRCUITS - An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion. | 2013-09-12 |
20130234258 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - Provided are a semiconductor device having a high breakdown voltage and attaining the restraint of the action of a parasite bipolar transistor, and a method for producing the device. A high-breakdown-voltage p-channel-type transistor included in the semiconductor device has a first n-type semiconductor layer arranged in a semiconductor substrate and at a main-surface-side (upside) of a p-type region in the semiconductor substrate, and a local n-type buried region arranged just below a first p-type dopant region to contact the first n-type semiconductor layer. | 2013-09-12 |
20130234259 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and method where a side wall insulating layer, extending perpendicular from a top surface of a semiconductor substrate, is prevented from contacting the semiconductor substrate by a barrier layer formed at an interface between the semiconductor substrate and the insulating layer. | 2013-09-12 |
20130234260 | INTERCONNECT STRUCTURE FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN - The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask. | 2013-09-12 |
20130234261 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain. | 2013-09-12 |
20130234262 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate. The method also includes performing a thermal annealing process on the semiconductor substrate using an inert gas as a thermal annealing protective gas after removing the oxide layer, and forming an insulating layer on the semiconductor substrate after performing the thermal annealing process. Further, the method includes forming a high-K gate dielectric layer on a surface of the insulating layer, and forming a protective layer on a surface of the high-K gate dielectric layer. | 2013-09-12 |
20130234263 | MEMS ELEMENT - According to one embodiment, a MEMS element comprises a first electrode that is fixed on a substrate and has plate shape, a second electrode that is disposed above the first electrode while facing the first electrode, the second electrode being movable in a vertical direction and having plate shape, and a first film that includes a first cavity in which the second electrode is accommodated on the substrate. The second electrode is connected to an anchor portion connected to the substrate via a spring portion. An upper surface of the second electrode is connected to the first film. | 2013-09-12 |
20130234264 | SEMICONDUCTOR SENSOR DEVICE AND ELECTRONIC APPARATUS - Disclosed is a semiconductor sensor device, including a substrate, a sensor element mounted on the substrate, a hollow member configured to surround a periphery of the sensor element, a sealing material configured to fill in the hollow member and cover the sensor element, and a recess formed on the substrate, the recess being configured to position the hollow member. | 2013-09-12 |
20130234265 | PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes patterning a wiring layer to form at least one fixed plate and forming a sacrificial material on the wiring layer. The method further includes forming an insulator layer of one or more films over the at least one fixed plate and exposed portions of an underlying substrate to prevent formation of a reaction product between the wiring layer and a sacrificial material. The method further includes forming at least one MEMS beam that is moveable over the at least one fixed plate. The method further includes venting or stripping of the sacrificial material to form at least a first cavity. | 2013-09-12 |
20130234266 | MAGNETIC TUNNEL JUNCTION WITH AN IMPROVED TUNNEL BARRIER - The present disclosure concerns a method of fabricating a magnetic tunnel junction suitable for a magnetic random access memory (MRAM) cell and comprising a first ferromagnetic layer, a tunnel barrier layer, and a second ferromagnetic layer, comprising: forming the first ferromagnetic layer; forming the tunnel barrier layer; and forming the second ferromagnetic layer; wherein said forming the tunnel barrier layer comprises depositing a layer of metallic Mg; and oxidizing the deposited layer of metallic Mg such as to transform the metallic Mg into MgO; the step of forming the tunnel barrier layer being performed at least twice such that the tunnel barrier layer comprises at least two layers of MgO. | 2013-09-12 |
20130234267 | MAGNETIC DEVICE - A magnetic body structure including: a magnetic layer pattern; and a conductive pattern including a metallic glass alloy and covering at least a portion of the magnetic body structure. | 2013-09-12 |
20130234268 | MAGNETIC MEMORY CELL AND METHOD OF MANUFACTURING THE SAME - The present invention suppresses short circuits of a magnetic memory cell and a deterioration of the characteristics of a magnetic layer. A magnetic memory cell includes: a data storage layer; a tunnel barrier layer formed on the data storage layer; a reference layer formed on the tunnel barrier layer so as to cover a part of the tunnel barrier layer; and a metallic oxide layer formed on the tunnel barrier layer without covering the reference layer. The metallic oxide layer contains an oxide of a material of a contact part of the reference layer with the tunnel barrier layer. | 2013-09-12 |
20130234269 | MAGNETIC MEMORY DEVICES INCLUDING MAGNETIC LAYERS SEPARATED BY TUNNEL BARRIERS - A magnetic memory device may include a first vertical magnetic layer, a non-magnetic layer on the first vertical magnetic layer, and a first junction magnetic layer on the non-magnetic layer, with the non-magnetic layer being between the first vertical magnetic layer and the first junction magnetic layer. A tunnel barrier may be on the first junction magnetic layer, with the first junction magnetic layer being between the non-magnetic layer and the tunnel barrier. A second junction magnetic layer may be on the tunnel barrier with the tunnel barrier being between the first and second junction magnetic layers, and a second vertical magnetic layer may be on the second junction magnetic layer with the second junction magnetic layer being between the tunnel barrier and the second vertical magnetic layer. | 2013-09-12 |
20130234270 | Atomic Layer Deposition Strengthening Members and Method of Manufacture - In one embodiment, a method of forming a semiconductor device includes providing a substrate, forming a sacrificial layer above the substrate layer, forming a first trench in the sacrificial layer, forming a first sidewall layer with a thickness of less than about 50 nm on a first sidewall of the first trench using atomic layer deposition (ALD), and removing the sacrificial layer. | 2013-09-12 |
20130234271 | CONDUCTIVE COMPOSITIONS AND PROCESSES FOR USE IN THE MANUFACTURE OF SEMICONDUCTOR DEVICES - The present invention is directed to a thick film conductive composition comprising: (a) electrically conductive silver powder; (b) zinc-containing additive; (c) glass frit wherein said glass frit is lead-free; dispersed in (d) organic medium. The present invention is further directed to an electrode formed from the composition above wherein said composition has been fired to remove the organic vehicle and sinter said glass particles. Still further, the invention is directed to a method of manufacturing a semiconductor device from a structural element composed of a semiconductor having a p-n junction and an insulating film formed on a main surface of the semiconductor comprising the steps of (a) applying onto said insulating film the thick film composition detailed above; and (b) firing said semiconductor, insulating film and thick film composition to form an electrode. Additionally, the present invention is directed to a semiconductor device formed by the method detailed above and a semiconductor device formed from the thick film conductive composition detailed above. | 2013-09-12 |
20130234272 | IMAGE-SENSING MODULE - An image-sensing module includes a substrate unit, a light-transmitting unit, an image-sensing unit and a lens unit. The substrate unit includes at least one flexible substrate having at least one through opening. The light-transmitting unit includes at least one light-transmitting element disposed on the top surface of the flexible substrate and corresponding to the through opening. The image-sensing unit includes at least one image-sensing element disposed on the bottom surface of the light-transmitting element and embedded in the through opening, and the image-sensing element is electrically connected to the flexible substrate. The lens unit includes an opaque frame disposed on the top surface of the flexible substrate to surround the light-transmitting element and a lens positioned on the opaque frame to correspond to the light-transmitting element. | 2013-09-12 |
20130234273 | IMAGE SENSORS AND METHODS OF FORMING THE SAME - The inventive concept provides image sensors and methods of forming the same. In the image sensor, a surface trap region may be disposed to be adjacent to a surface of a substrate lens component. Thus, a dark current characteristic may be improved. | 2013-09-12 |
20130234274 | LIGHT EMITTING APPARATUS - There is provided a light emitting apparatus including: at least one pair of lead frames; a light emitting device electrically connected to the lead frames to emit ultraviolet rays; a body including a side wall surrounding the light emitting device, and a groove portion formed in an upper surface of the side wall to receive an adhesive; and a lens part disposed above the light emitting device and fixed to the upper surface of the side wall of the body by the adhesive. | 2013-09-12 |
20130234275 | METHODS OF FABRICATION OF PACKAGE ASSEMBLIES FOR OPTICALLY INTERACTIVE ELECTRONIC DEVICES AND PACKAGE ASSEMBLIES THEREFOR - Packaging assemblies for optically interactive devices and methods of forming the packaging assemblies in an efficient manner that eliminates or reduces the occurrence of process contaminants. In a first embodiment, a transparent cover is attached to a wafer of semiconductor material containing a plurality of optically interactive devices. The wafer is singulated, and the optically interactive devices are mounted on an interposer and electrically connected with wire bonds. In a second embodiment, the optically interactive devices are electrically connected to the interposer with back side conductive elements. In a third embodiment, the optically interactive devices are mounted to the interposer prior to attaching a transparent cover. A layer of encapsulant material is formed over the interposer, and the interposer and encapsulant material are cut to provide individual packaging assemblies. In a fourth embodiment, the optically interactive devices are mounted in a preformed leadless chip carrier. | 2013-09-12 |
20130234276 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC EQUIPMENT - A solid state imaging device including a semiconductor layer comprising a plurality of photodiodes, a first antireflection film located over a first surface of the semiconductor layer, a second antireflection film located over the first antireflection film, a light shielding layer having side surfaces which are adjacent to at least one of first and the second antireflection film. | 2013-09-12 |
20130234277 | SEMICONDUCTOR DEVICE AND IMAGING APPARATUS - The invention relates to a semiconductor device having a vertical transistor bipolar structure of emitter, base, and collector formed in this order from a semiconductor substrate surface in a depth direction. The semiconductor device includes an electrode embedded from the semiconductor substrate surface into the inside and insulated by an oxide film. In the surface of the substrate, a first-conductivity-type first semiconductor region, a second-conductivity-type second semiconductor region, and a first-conductivity-type third semiconductor region are arranged, from the surface side, inside a semiconductor device region surrounded by the electrode and along the electrode with the oxide film interposed therebetween, the second semiconductor region located below the first semiconductor region, the third semiconductor region located below the second semiconductor region. The electrode is insulated from the first to third semiconductor regions, and current gain is variable through application of voltage to the electrode. | 2013-09-12 |
20130234278 | SCHOTTKY CONTACT - The present disclosure relates to a Schottky contact for a semiconductor device. The semiconductor device has a body formed from one or more epitaxial layers, which reside over a substrate. The Schottky contact may include a Schottky layer, a first diffusion barrier layer, and a third layer. The Schottky layer is formed of a first metal and is provided over at least a portion of a first surface of the body. The first diffusion barrier layer is formed of a silicide of the first metal and is provided over the Schottky layer. The third layer is formed of a second metal and is provided over the first diffusion barrier layer. In one embodiment, the first metal is nickel, and as such, the silicide is nickel silicide. Various other layers may be provided between or above the Schottky layer, the first diffusion barrier layer, and the third layer. | 2013-09-12 |
20130234279 | SEMICONDUCTOR DEVICE WITH BURIED WORD LINE STRUCTURES AND METHOD OF MANUFACTURING THE SAME - A semiconductor device with buried word line structures and methods of forming the semiconductor device are provided. The semiconductor device includes a plurality of insulating line patterns extending in a direction in a substrate, a plurality of word lines alternately with ones of the plurality of insulating line patterns, the plurality of word lines extending in the direction and comprising a metal, a plurality of first doped regions on respective ones of the plurality of the word lines and between two adjacent ones of the plurality of insulating line patterns, an interlayer insulating film on the plurality of insulating line patterns and the plurality of first doped regions, the interlayer insulating film including a plurality of openings exposing upper surfaces of ones of the plurality of first doped regions and a plurality of second doped regions contacting respective ones of the plurality of first doped regions within the openings. | 2013-09-12 |
20130234280 | SHALLOW TRENCH ISOLATION IN DYNAMIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method of STI in DRAM includes the following steps. Step 1 is providing a substrate and step 2 is forming at least one trench in the substrate. Step 3 is doping at least one of side portions and bottom portions of the trench with a dopant. Step 4 is forming an oxidation inside the trench and step 5 is providing a planarization step to remove the oxidation. The stress of the corners of STI is reduced so as to modify the defect of the substrate and improve the DRAM variability in retention time. | 2013-09-12 |
20130234281 | Wafer with Spacer including Horizontal Member - A method of forming an insulating spacer is disclosed that includes providing a base layer, providing an intermediate layer above an upper surface of the base layer, etching a first trench in the intermediate layer, depositing a first insulating material portion within the first trench, depositing a second insulating material portion above an upper surface of the intermediate layer, forming an upper layer above an upper surface of the second insulating material portion, etching a second trench in the upper layer, and depositing a third insulating material portion within the second trench and on the upper surface of the second insulating material portion. A wafer is also disclosed. | 2013-09-12 |
20130234282 | SEMICONDUCTOR DEVICE WITH VERTICAL CELLS AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor substrate includes defining an active region by forming a device isolation layer over the substrate, forming a first trench dividing the active region into a first active region and a second active region, forming a buried bit line filling a portion of the first trench, forming a gap-filling layer gap-filling an upper portion of the first trench over the buried bit line, forming second trenches by etching the gap-filling layer and the device isolation layer in a direction crossing the buried bit line, and forming a first buried word line and a second buried word line filling the second trenches, wherein the first buried word line and the second buried word line are shaped around sidewalls of the first active region and the second active region, respectively. | 2013-09-12 |
20130234283 | Semiconductor Packages and Methods of Forming The Same - In one embodiment, a method of fabricating a semiconductor package includes forming a first plurality of die openings on a laminate substrate. The laminate substrate has a front side and an opposite back side. A plurality of first dies is placed within the first plurality of die openings. An integrated spacer is formed around each die of the plurality of first dies. The integrated spacer is disposed in gaps between the laminate substrate and an outer sidewall of each die of the plurality of first dies. The integrated spacer holds the die within the laminate substrate by partially extending over a portion of a top surface of each die of the plurality of first dies. Front side contacts are formed over the front side of the laminate substrate. | 2013-09-12 |
20130234284 | Fuse and Integrated Conductor - A fuse structure includes within an aperture within a dielectric layer located over a substrate that exposes a conductor contact layer within the substrate a seed layer interposed between the conductor contact layer and another conductor layer. The seed layer includes a doped copper material that includes a dopant immobilized predominantly within the seed layer. The fuse structure may be severed while not severing a conductor interconnect structure also located over the substrate that exposes a second conductor contact layer within a second aperture. In contrast with the fuse structure that includes the doped seed layer having the immobilized dopant, the interconnect structure includes a doped seed layer having a mobile dopant. | 2013-09-12 |
20130234285 | INDUCTOR ELEMENT, INDUCTOR ELEMENT MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE WITH INDUCTOR ELEMENT MOUNTED THEREON - An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer. | 2013-09-12 |
20130234286 | SEMICONDUCTOR DEVICE HAVING HIGH-FREQUENCY INTERCONNECT - Provided is a semiconductor device including high-frequency interconnect and dummy conductor patterns (second dummy conductor patterns). The dummy conductor patterns are disposed in a interconnect layer different from a interconnect layer in which the high-frequency interconnect is disposed. The dummy conductor patterns are disposed so as to keep away from a region overlapping the high-frequency interconnect in plan view. The semiconductor device further includes dummy conductor patterns (first dummy conductor patterns) in the interconnect layer in which the high-frequency interconnect is disposed. | 2013-09-12 |
20130234287 | HIGH PRECISION CAPACITOR WITH LOW VOLTAGE COEFFICIENT OF CAPACITANCE AND METHOD FOR MANUFACTURING THE SAME - A high-precision capacitor includes a first degenerately doped polysilicon plate, a second degenerately doped polysilicon plate, and a dielectric material disposed between the first and the second degenerately doped polysilicon plates. The first degenerately doped polysilicon plate may be formed by performing POCL (phosphorus oxychloride) diffusion, and performing ion implantation through the POCL oxide to replenish the loss of dopants. The second degenerately doped polysilicon plate may be formed by performing POCL doping. The high-precision capacitor may exhibit a voltage coefficient of capacitance (VCC) comparable to a Metal-Insulator-Metal capacitor, however, with a dielectric of higher quality. | 2013-09-12 |
20130234288 | Trench Structure for an MIM Capacitor and Method for Manufacturing the Same - A method for manufacturing a MIM capacitor trench structure includes forming a lower metal film on an inter-metal dielectric; forming a first inter-metal dielectric on the lower metal film; forming a first trench; sequentially forming a dielectric film and a first barrier metal film along the bottom surface and sidewalls of the first trench; and filling the first trench with a conductive material to form a first upper metal film. Further, the method includes forming a second inter-metal dielectric on the first upper metal film; forming a second trench; forming a via hole in a via hole region of the second inter-metal dielectric; forming a second barrier metal film along the bottom surface and sidewalls of the second trench; and filling the via hole and the second trench with the conductive material to form a via contact and a second upper metal film. | 2013-09-12 |
20130234289 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode. | 2013-09-12 |
20130234290 | METHOD OF PATTERNING A METAL ON A VERTICAL SIDEWALL OF AN EXCAVATED FEATURE, METHOD OF FORMING AN EMBEDDED MIM CAPACITOR USING SAME, AND EMBEDDED MEMORY DEVICE PRODUCED THEREBY - A method of patterning a metal ( | 2013-09-12 |
20130234291 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first electrode electrically connected to an upper surface of a semiconductor element, a first internal electrode electrically connected to a lower surface of the semiconductor element and having a plurality of first comb finger portions and a first connection portion connecting the plurality of first comb finger portions together, a second electrode electrically connected to the first internal electrode, a second internal electrode electrically connected to a lower surface of the first electrode and having a plurality of second comb finger portions and a second connection portion connecting the plurality of second comb finger portions together, the plurality of second comb finger portions being interdigitated with but not in contact with the plurality of first comb finger portions, and a lower dielectric filling the space between the plurality of first comb finger portions and the plurality of second comb finger portions. | 2013-09-12 |
20130234292 | THIN FILM RESISTOR STRUCTURE - A thin film resistor structure includes a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, and each top surface of the first contacts is on the same level as a top surface of the bottom ILD; a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, and each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD. | 2013-09-12 |
20130234293 | SEMICONDUCTOR CERAMIC AND METHOD FOR MANUFACTURING THE SAME, AND LAMINATED SEMICONDUCTOR CERAMIC CAPACITOR WITH VARISTOR FUNCTION AND METHOD FOR MANUFACTURING THE SAME - A semiconductor ceramic contains a donor element solid-solved in crystal grains of a SrTiO | 2013-09-12 |
20130234294 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD - A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A negative photoresist layer is formed on a positive photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist layer and to form a second exposure region in the negative photoresist layer in response to a first and a second intensity thresholds of the exposure energy. A negative-tone development process is performed to remove portions of the negative photoresist layer to form first opening(s). The positive photoresist layer is then etched along the first opening(s) to form second opening(s) therein. A positive-tone development process is performed to remove the first exposure region therefrom to form a double patterned positive photoresist layer. | 2013-09-12 |
20130234295 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME, WIRING BOARD AND METHOD OF MANUFACTURING SAME, SEMICONDUCTOR PACKAGE, AND ELECTRONIC DEVICE - Passivation films | 2013-09-12 |
20130234296 | INTERCONNECT STRUCTURES FOR STACKED DIES, INCLUDING PENETRATING STRUCTURES FOR THROUGH-SILICON VIAS, AND ASSOCIATED SYSTEMS AND METHODS - Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate. | 2013-09-12 |
20130234297 | SEMICONDUCTOR DEVICE, WAFER ASSEMBLY AND METHODS OF MANUFACTURING WAFER ASSEMBLIES AND SEMICONDUCTOR DEVICES - A cavity is formed in a working surface of a substrate in which a semiconductor element is formed. A glass piece formed from a glass material is bonded to the substrate, and the cavity is filled with the glass material. For example, a pre-patterned glass piece is used which includes a protrusion fitting into the cavity. Cavities with widths of more than 10 micrometers are filled fast and reliably. The cavities may have inclined sidewalls. | 2013-09-12 |
20130234298 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a method for manufacturing a semiconductor device includes a placement step and a bonding step. The placement step faces a semiconductor active portion toward a support substrate portion via a bonding portion disposed between the semiconductor active portion and the support substrate portion. The bonding portion includes a bonding layer and a light absorption layer, absorptance of the light absorption layer for laser light being higher than or equal to absorptance of the bonding layer for the laser light. The bonding step bonds the semiconductor active portion and the support substrate portion by irradiating the light absorption layer with the laser light through the support substrate portion and melting the bonding layer by thermal conduction from the light absorption layer heated by the laser light. | 2013-09-12 |
20130234299 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a_semiconductor device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked. The semiconductor device includes a mark and a supporting unit. The mark is opened onto a surface of the stacked body. The supporting unit is provided around the mark. The supporting unit extends in a stacked direction of the stacked body. The supporting unit is in contact with at least a plurality of conductive layers. | 2013-09-12 |
20130234300 | SEMICONDUCTOR DEVICE INCLUDING A STRESS BUFFER MATERIAL FORMED ABOVE A LOW-K METALLIZATION SYSTEM - A bump structure or pillar structure formed above a metallization system of a complex semiconductor device may include a stress buffer layer, which may efficiently distribute the resulting mechanical stress which may typically occur during the chip package interaction due to a thermal mismatch of these components. The stress buffer layer comprises copper-based buffer regions that cover a significant portion of the overall surface, wherein a thickness of approximately 3-10 μm may also be used. Moreover, the buffer regions may efficiently replace aluminum as a terminal metal active region. | 2013-09-12 |
20130234301 | PATTERNED STRUCTURE OF SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A method for fabricating a patterned structure in a semiconductor device is provided. First, a substrate with a first region and a second region is provided. Then, a plurality of sacrificial patterns is respectively formed within the first region and the second region. A first spacer is then formed on the sidewalls of each of the sacrificial patterns followed by forming a mask layer to cover the sacrificial patterns located within the first region. Finally, the first spacer exposed from the mask layer is trimmed to be a second spacer and the mask layer is then removed. | 2013-09-12 |
20130234302 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD - A semiconductor structure including a double patterned structure and a method for forming the semiconductor structure are provided. A positive photoresist layer is formed on a negative photoresist layer, which is formed over a substrate. An exposure process is performed to form a first exposure region in the positive photoresist layer and to form a second exposure region in the negative photoresist layer in response to a first and a second intensity thresholds of the exposure energy. A positive-tone development process is performed to remove the first exposure region from the positive photoresist layer to form first opening(s). The second exposure region in the negative photoresist layer is then etched along the first opening(s) to form second opening(s) therein. A negative-tone development process is performed to remove portions of the negative photoresist layer outside of remaining second exposure region to form a double patterned negative photoresist layer. | 2013-09-12 |
20130234303 | METAL SHIELD FOR INTEGRATED CIRCUITS - A metal shield structure is provided for an integrated circuit (IC) having at least a first metal contact coupled to a fixed potential and a second metal contact. A first passivation layer is located between the first and second metal contacts and on a first portion of the first metal contact and a first portion of the second metal contact, leaving a second portion of the first metal contact and a second portion of the second metal contact uncovered by the first passivation layer. A metal shield layer is provided on the second portion of the first metal contact and on the first passivation layer, and a second passivation layer is formed on the metal shield layer. | 2013-09-12 |
20130234304 | SEMICONDUCTOR DEVICE - When a material of an organic substrate is glass epoxy and a material of a semiconductor chip is silicon or gallium arsenide, a substrate warp sometimes occurs because of a difference between thermal expansion coefficients of the materials. The shape of the antenna formed on the organic substrate due to such a substrate warp, so that the characteristics of the antenna are sometimes shifted from desired values. An antenna is provided on the substrate on which a semiconductor chip is mounted, and is covered with a resin. The resin has enough hardness to suppress the warp caused by joining the semiconductor chip and the substrate and a transformation of the antenna. By changing a connection relation of adjustment vias after the manufacture of the semiconductor device, the characteristic of the antenna can be changed. | 2013-09-12 |
20130234305 | 3D TRANSMISSION LINES FOR SEMICONDUCTORS - A transmission line structure for semiconductor RF and wireless circuits, and method for forming the same. The transmission line structure includes embodiments having a first die including a first substrate, a first insulating layer, and a ground plane, and a second die including a second substrate, a second insulating layer, and a signal transmission line. The second die may be positioned above and spaced apart from the first die. An underfill is disposed between the ground plane of the first die and the signal transmission line of the second die. Collectively, the ground plane and transmission line of the first and second die and underfill forms a compact transmission line structure. In some embodiments, the transmission line structure may be used for microwave applications. | 2013-09-12 |
20130234306 | LEAD FRAME FOR ASSEMBLING SEMICONDUCTOR DEVICE - A lead frame has a flag, a peripheral frame, and main tie bars coupling the flag to the peripheral frame. At least one cross tie bar extends between two of the main tie bars and an inner row of external connector pads extending from an inner side of the cross tie bar and an outer row of external connector pads extending from an outer side of the cross tie bar. Both an inner non-electrically conductive support bar and an outer non-electrically conductive support bar are attached across the two of the main tie bars. The inner non-electrically conductive support bar is attached to upper surfaces of the two of the main tie bars and to upper surfaces of the inner row of the external connector pads. | 2013-09-12 |
20130234307 | LEAD FRAME LAND GRID ARRAY - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 2013-09-12 |
20130234308 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED DEVICE AND METHOD OF MANUFACTURING THE SAME - A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip. | 2013-09-12 |
20130234309 | SEMICONDUCTOR DEVICE - Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads. | 2013-09-12 |
20130234310 | FLIP CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A flip chip package may include package substrate, a semiconductor chip, conductive bumps, a molding member and a heat sink. The semiconductor chip may be arranged over an upper surface of the package substrate. The conductive bumps may be interposed between a lower surface of the semiconductor chip and the upper surface of the package substrate to electrically connect the semiconductor chip and the package substrate with each other. The molding member may be formed on the upper surface of the package substrate to cover the semiconductor chip. The heat sink may make contact with the semiconductor chip to dissipate a heat in the semiconductor chip. An ultrasonic wave may pass through only one interface between the semiconductor chip and the molding member, so that scattering of the ultrasonic wave may be suppressed. | 2013-09-12 |
20130234311 | Semiconductor component that includes a protective structure - In accordance with an embodiment a semiconductor component includes an electrically conductive structure formed over a portion of a semiconductor material. An electrical interconnect having a top surface and opposing edges contacts the electrically conductive structure. A protective structure is formed on the top surface and the opposing edges of the electrical interconnect and over a portion of the electrically conductive structure, wherein the protective structure forms a seal that protects the electrical interconnect. | 2013-09-12 |
20130234312 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Terminal assembly portions, lying on a front surface side of a case, are aligned in a left-right direction in a portion raised from a bottom of the case so that opening faces of the terminal assembly portions are positioned above circuit formation regions. Wiring terminal plates are led out into the terminal assembly portions, and disposed adjacent to each other. After each wiring terminal plate is connected by a laser welding to one end of one external connection terminal plate formed integrally with a cover, these welded portions are sealed with a second mold resin portion made of gel or an insulating resin such as epoxy. By so doing, even when the terminal junction area and distance between terminal junctions in the terminal assembly portions are small, it is possible to increase the joint strength of the terminals, and also secure withstand voltage. | 2013-09-12 |
20130234313 | GROWN CARBON NANOTUBE DIE ATTACH STRUCTURES, ARTICLES, DEVICES, AND PROCESSES FOR MAKING THEM - An article of manufacture includes a semiconductor die ( | 2013-09-12 |
20130234314 | FLEXIBLE MICRO-SYSTEM AND FABRICATION METHOD THEREOF - A fabrication method for integrating chip(s) onto a flexible substrate in forming a flexible micro-system. The method includes a low-temperature flip-chip and a wafer-level fabrication process. Using the low-temperature flip-chip technique, the chip is bonded metallically onto the flexible substrate. To separate the flexible substrate from the substrate, etching is used to remove the sacrificial layer underneath the flexible substrate. The instant disclosure applies standardized micro-fabrication process for integrating chip(s) onto the flexible substrate. Without using special materials or fabrication procedures, the instant disclosure offers a cost-effective fabrication method for flexible micro-systems. | 2013-09-12 |
20130234315 | STRUCTURES AND METHODS FOR DETECTING SOLDER WETTING OF PEDESTAL SIDEWALLS - Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances. | 2013-09-12 |
20130234316 | SELF-ALIGNED POLYMER PASSIVATION/ALUMINUM PAD - The invention provides a semiconductor chip structure having at least one aluminum pad structure and a polyimide buffering layer under the aluminum pad structure, wherein the polyimide buffering layer is self-aligned to the aluminum pad structure, and a method of forming the same. The method includes forming a polyimide buffering layer on a substrate, forming an aluminum pad structure on the buffering layer, and, using the aluminum pad structure as a mask, etching the substrate to remove the polyimide buffering layer from the substrate everywhere except under the aluminum pad structure. | 2013-09-12 |
20130234317 | Packaging Methods and Packaged Semiconductor Devices - Packaging methods and packaged semiconductor devices are disclosed. In one embodiment, a packaging method includes providing a first die, partially packaging the first die, and forming a plurality of solder balls on a surface of the partially packaged first die. An epoxy flux is disposed over the plurality of solder balls. A second die is provided, and the second die is partially packaged. The plurality of solder balls is coupled to the partially packaged second die. | 2013-09-12 |
20130234318 | Semiconductor Device and Method of Forming Non-Linear Interconnect Layer with Extended Length for Joint Reliability - A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate. | 2013-09-12 |
20130234319 | SEMICONDUCTOR CONSTRUCTIONS - Some embodiments include a planarization method. A liner is formed across a semiconductor substrate and along posts that extending upwardly from the substrate. Organic fill material is formed over the liner and between the posts. A planarized surface is formed which extends across the posts and across one or both of the liner and the fill material. Some embodiments include a semiconductor construction containing a semiconductor die. Electrically conductive posts extend through the die. The posts have upper surfaces above a backside surface of the die, and have sidewall surfaces extending between the backside surface and the upper surfaces. A liner is across the backside surface of the die and along the sidewall surfaces of the posts. Electrically conductive caps are over the upper surfaces of the posts, and have rims along the liner adjacent the sidewall surfaces of the posts. | 2013-09-12 |
20130234320 | CHIP STACK STRUCTURE AND METHOD FOR FABRICATING THE SAME - A chip stack structure taking a wafer as a stacking base and stacking chips thereon is provided. The chip stack structure is capable of achieving high density electrode bonding and breaking the bottleneck of requiring interposer to serve as a transferring interface in three dimensional chip package. The chip stack structure is easily fabricated and compatible with wafer level process, so as to reduce processing time and manufacturing cost. A method for fabricating the chip stack structure is also provided. | 2013-09-12 |
20130234321 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device includes a plurality of pillar patterns formed over a semiconductor substrate. Each pillar pattern includes a silicon layer; a bit line junction region formed at the bottom of one side of the pillar pattern, and configured to be in contact the silicon layer; a bit line provided between the pillar patterns, coupled to the bit line junction region, and extending along a first direction; and a gate spaced apart from an upper part of the bit line, extending along a second direction perpendicular to the bit line, and formed at a sidewall of the pillar pattern. | 2013-09-12 |
20130234322 | Thin 3D Fan-Out Embedded Wafer Level Package (EWLB) for Application Processor and Memory Integration - A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die. | 2013-09-12 |
20130234323 | SEMICONDUCTOR CHIP AND MANUFACTURING METHOD THEREOF - A semiconductor device comprising stacked substrates through a bump, the bump comprising a solder bump formed on a copper bump wherein the solder bump includes Zn. | 2013-09-12 |
20130234324 | Semiconductor Device and Method of Forming Vertically Offset Conductive Pillars Over First Substrate Aligned to Vertically Offset BOT Interconnect Sites Formed Over Second Substrate - A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device. | 2013-09-12 |
20130234325 | FILLED THROUGH-SILICON VIA AND THE FABRICATION METHOD THEREOF - By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased. | 2013-09-12 |
20130234326 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor apparatus comprises of a first semiconductor chip having a through silicon via (TSV) and a second semiconductor chip also having a TSV, wherein the respective semiconductor chips are stacked vertically and are connected through a conductive connection member without the assistance of an additional bump between the conductive connection member and the second semiconductor chip. | 2013-09-12 |
20130234327 | SEMICONDUCTOR DEVICE BONDING WITH STRESS RELIEF CONNECTION PADS - An inventive semiconductor device includes: a semiconductor chip; an internal pad provided on a surface of the semiconductor chip for electrical connection; a surface protective film covering the surface of the semiconductor chip and having a pad opening from which the internal pad is exposed; a stress relief layer provided on the surface protective film and having an opening portion through which the internal pad exposed from the pad opening is exposed; a connection pad including an anchor buried in the pad opening and the opening portion and connected to the internal pad, and a projection provided integrally with the anchor as projecting on the stress relief layer, the projection having a width greater than an opening width of the opening portion; and a metal ball provided for external electrical connection as covering the projection of the connection pad. | 2013-09-12 |
20130234328 | METHODS OF FLUXLESS MICRO-PIERCING OF SOLDER BALLS, AND RESULTING DEVICES - A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. The method also includes performing a heating process to heat at least the solder balls and applying a force causing each of a plurality of piercing bond structures on a substrate to pierce one of the solder balls and its associated oxide layer to thereby establish a conductive connection between the solder ball and the piercing bond structure. | 2013-09-12 |
20130234329 | STRUCTURES AND METHODS TO REDUCE MAXIMUM CURRENT DENSITY IN A SOLDER BALL - Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance. | 2013-09-12 |
20130234330 | Semiconductor Packages and Methods of Formation Thereof - In one embodiment, a method of forming a semiconductor package includes applying a film layer having through openings over a carrier and attaching a back side of a semiconductor chip to the film layer. The semiconductor chip has contacts on a front side. The method includes using a first common deposition and patterning step to form a conductive material within the openings. The conductive material contacts the contacts of the semiconductor chip. A reconfigured wafer is formed by encapsulating the semiconductor chip, the film layer, and the conductive material in an encapsulant using a second common deposition and patterning step. The reconfigured wafer is singulated to form a plurality of packages. | 2013-09-12 |
20130234331 | WIRING STRUCTURE, THIN FILM TRANSISTOR ARRAY SUBSTRATE INCLUDING THE SAME, AND DISPLAY DEVICE - In a wiring conversion part which connects a lower conductive film to a first conductive film each functioning as a wiring, a first transparent conductive film is formed into a pattern in which it covers an end surface of the first conductive film, and an angle formed at a corner part in a portion of the first transparent conductive film making contact with a lower first insulating film (outside a width of the first conductive film) is larger than 90 degrees and smaller than 270 degrees or the corner part has an arc shape. A second transparent conductive film is connected to the lower conductive film and the first transparent conductive film, and the first transparent conductive film is connected to the first conductive film, so that the lower conductive film and the first conductive film are electrically connected to each other. | 2013-09-12 |
20130234332 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked. The semiconductor device includes a plurality of contact electrodes, a plurality of first insulating portions, and a plurality of second insulating portions. The plurality of contact electrodes extends in a stacking direction of the stacked body. Each of the contact electrodes reaches corresponding one of the conductive layers. The plurality of first insulating portions respectively is provided between the plurality of contact electrodes and the stacked body. The plurality of second insulating portions respectively is provided between the plurality of first insulating portions and the stacked body. | 2013-09-12 |
20130234333 | COPPER INTERCONNECTS HAVING A TITANIUM-TITANIUM NITRIDE ASSEMBLY BETWEEN COPPER AND COMPOUND SEMICONDUCTOR - Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a first titanium (Ti) layer disposed over a compound semiconductor, a first titanium nitride (TiN) layer disposed over the first Ti layer, and a copper (Cu) layer disposed over the first TiN layer. The first Ti layer and the first TiN layer can be configured as a barrier between the Cu layer and the compound semiconductor. The metalized structure can further include a second TiN layer disposed over the Cu layer and a first platinum (Pt) layer disposed over the second TiN layer. | 2013-09-12 |
20130234334 | SEMICONDUCTOR DEVICE WITH A LINE AND METHOD OF FABRICATION THEREOF - A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole.. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained. | 2013-09-12 |
20130234335 | HNO3 SINGLE WAFER CLEAN PROCESS TO STRIP NICKEL AND FOR MOL POST ETCH - Ni and Pt residuals are eliminated by replacing an SPM cleaning process with application of HNO | 2013-09-12 |
20130234336 | PROCESSES FOR FORMING INTEGRATED CIRCUITS AND INTEGRATED CIRCUITS FORMED THEREBY - Processes for forming integrated circuits and integrated circuits formed thereby are provided in which a first dielectric layer including a first dielectric material is formed on an underlying substrate. A first etch mask having at least two patterned recesses is patterned over the first dielectric layer. At least one first-level via is etched in the first dielectric layer through one patterned recess in the first etch mask with a first etchant, and the first-level via is filled with electrically-conductive material. A second dielectric layer including a second dielectric material is formed over the first dielectric layer. A second etch mask having patterned recesses corresponding to the patterned recesses of the first etch mask is patterned over the second dielectric layer. Second-level vias are etched in the second dielectric layer through the patterned recesses in the second etch mask with a second etchant and exposed to the first etchant. | 2013-09-12 |
20130234337 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes a substrate having opposite first and second surfaces and a ground layer therein. Further, the second surface has at least a recessed portion for exposing portions of the ground layer. The semiconductor package further includes a semiconductor chip disposed on the first surface of the substrate; an encapsulant formed on the first surface of the substrate for encapsulating the semiconductor chip; and a metal layer covering the encapsulant and the substrate and extending to the recessed portion for electrically connecting the ground layer. As such, the space for circuit layout is increased and the circuit layout flexibility is improved. | 2013-09-12 |
20130234338 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a plurality of contact electrodes that reach corresponding conductive layers. Each of the contact electrodes includes a columnar portion, a stopper, and a first connection portion. The columnar portion extends in a stacked direction of the stacked body. The stopper covers the side of the columnar portion. The first connection portion is provided at a lower edge of the columnar portion. The first connection portion is in contact with the corresponding conductive layer. A cross-section dimension of the first connection portion in a direction orthogonal to the stacked direction is larger than a cross-section of the lower edge of the columnar portion. An etching rate of a material for the stopper is lower than an etching rate of a material for the first insulating layer. | 2013-09-12 |
20130234339 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME, AND MANAGEMENT SYSTEM OF SEMICONDUCTOR DEVICE - After stacking m wafers in each of which a plurality of semiconductor chips are formed, the m wafers are diced to semiconductor chips to form a first chip stack having m of the semiconductor chips stacked, and, after stacking n wafers, the n wafers are diced to semiconductor chips to form a second chip stack having n of the semiconductor chips stacked. Next, the first chip stack is sorted according to the number of defective semiconductor chips included in the first chip stack, and the second chip stack is sorted according to the number of defective semiconductor chips included in the second chip stack. Furthermore, the first chip stack or the second chip stack after sorting are combined to form a third chip stack. | 2013-09-12 |
20130234340 | VERTICALLY STACKABLE DIES HAVING CHIP IDENTIFIER STRUCTURES - A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through silicon via to communicate a chip identifier and other data. The semiconductor device also includes a chip identifier structure that comprises at least two through silicon vias that are each hard wired to an external electrical contact. | 2013-09-12 |
20130234341 | INTERPOSER SUBSTRATE MANUFACTURING METHOD AND INTERPOSER SUBSTRATE - A method for manufacturing an interposer substrate includes: forming a conductive portion on a first surface of a semiconductor substrate via a first insulating layer, the conductive portion being formed of a first metal; forming a through hole at a second surface side of the semiconductor substrate located on an opposite side to the first surface so as to expose the first insulating layer; forming a second insulating layer on at least an inner wall surface and a bottom surface of the through hole; exposing the conductive portion by removing portions of the first and second insulating layers using a dry etching method that uses an etching gas containing a fluorine gas, the portions of the first and second insulating layers being located on the bottom surface of the through hole; and forming a conductive layer on the second insulating layer and electrically connecting the conductive layer to the conductive portion, wherein when exposing the conductive portion, forming a tapered portion is performed. | 2013-09-12 |
20130234342 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip including a plurality of driver circuits and an output switching circuit coupled to the plurality of driver circuits. The device also includes a second semiconductor chip and a plurality of through silicon vias provided on at least one of the first and second semiconductor chips. The output switching circuit is coupled between the plurality of driver circuits and the plurality of the through silicon vias, and outputs each of signals from the plurality of driver circuits to corresponding one of the plurality of through silicon vias. | 2013-09-12 |
20130234343 | THROUGH-HOLE SUBSTRATE AND METHOD OF PRODUCING THE SAME - A substrate ( | 2013-09-12 |
20130234344 | FLIP-CHIP PACKAGING TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed. | 2013-09-12 |
20130234345 | FUEL METERING DIAPHRAGM WITH BACKING PLATE - In at least some implementations, a carburetor having a fuel metering system including a diaphragm assembly that moves in response to pressure changes in a metering chamber to actuate a metering valve may include a flexible diaphragm adapted to carried by a body of the carburetor at a periphery to define part of the metering chamber. The portion of the diaphragm that defines part of the metering chamber defines a chamber projected area of the diaphragm. A backing plate is attached to the flexible diaphragm and arranged to be located outside the metering chamber. The backing plate having an outer perimeter defining a plate projected area, wherein an area ratio of the plate projected area to the chamber projected area is greater than about 0.1. | 2013-09-12 |
20130234346 | HUMIDIFYING APPARATUS - Humidifying apparatus includes a base housing a motor and impeller unit for generating a first air flow. A nozzle includes an interior passage for receiving the first air flow and an air outlet for emitting the first air flow. The nozzle defines an opening through which air from outside the apparatus is drawn by air emitted from the air outlet. The apparatus is configured to humidify a second air flow, which is emitted from a plurality of second air outlets. The second air flow is humidified with water supplied from a water tank mounted on the base. The water tank surrounds at least an upper section of the motor and impeller unit. | 2013-09-12 |
20130234347 | HUMIDIFYING APPARATUS - Humidifying apparatus includes a base housing a motor and impeller unit for generating a first air flow. A removable nozzle includes an interior passage for receiving the first air flow and an air outlet for emitting the first air flow. The nozzle defines an opening through which air from outside the apparatus is drawn by air emitted from the air outlet. The apparatus is configured to humidify a second air flow, which is emitted from a plurality of second air outlets. The second air flow is humidified with water supplied from a water tank mounted on the base. The water tank has a handle which is moveable between a stowed position and a deployed position, and which is biased towards the deployed position. The nozzle is configured to urge the handle towards the stowed position. | 2013-09-12 |
20130234348 | CROSS FLOW TRAY AND SUPPORT SYSTEM FOR USE IN A MASS TRANSFER COLUMN - Cross flow trays are provided with a support system. The support system interconnects the upper cross flow tray to a downcomer of the lower cross flow tray to provide support for the upper tray. In some aspects, the support system may also interconnect the downcomer of the lower cross flow tray to an upper tray of an underlying pair, providing additional support for the assembly. Such tray assemblies may facilitate easier installation without impeding the performance of the column. | 2013-09-12 |
20130234349 | Optical Film, Process of Producing the Same, and Polarizing Plate and Image Displaying Device Employing the Same - An optical film comprising a first domain of a polymer composition and a second domain disposed inside the first domain, wherein the second domain is a bubble having a morphology anisotropy, and the mean alignment direction of the main chain of the polymer molecule in the first domain differs from the mean direction of the major axis of the second domain, is capable of contributing toward display performance unification and body thickness reduction of an image display device. | 2013-09-12 |
20130234350 | Method And Apparatus For Micropelletization - In a method and apparatus for micropelletization of a polymeric material, a melt thread of the polymeric material is formed by an extruder. A flowing gas is directed to the melt thread to form Rayleigh disturbances in the melt thread and break up the melt thread into discrete microdroplets. The discrete microdroplets are then solidified to form micropellets. | 2013-09-12 |
20130234351 | Makeup Restoring Kit and Method - An economical makeup restoring kit and method that allows the individual consumer to re-solidify the fragments of a broken powder cake within the powder tray of the original compact case is provided. The makeup restoring kit includes an alcohol dispenser, a mixing/smoothing implement, and a cleaning implement. Variations of the implements are presented. The makeup restoring kit is preferably provided in a kit receptacle suitable for transporting and storing the kit contents. | 2013-09-12 |
20130234352 | METHOD OF MANUFACTURING A PART MADE OF COMPOSITE MATERIAL AND TOOL FOR THE IMPLEMENTATION THEREOF - A method and apparatus for manufacturing a composite material part from a preform of fibers pre-impregnated with resin. The method includes laying the preform on a laying surface of a tool with a peripheral shoulder, covering the preform with a conforming plate delimited by a peripheral edge which extends beyond the peripheral flank of the preform over the entire periphery of the preform, using shims calibrated to position the conforming plate, the shims being arranged between the support surface of the peripheral shoulder and the peripheral edge of the conforming plate, removing the calibrated shims, arranging a seal connecting the conforming plate and the tool all around the preform, and polymerizing the preform. | 2013-09-12 |