37th week of 2012 patent applcation highlights part 45 |
Patent application number | Title | Published |
20120231556 | ETCH TOOL PROCESS INDICATOR METHOD AND APPARATUS - A method for providing a process indicator for an etching chamber is provided. A wafer with a blanket etch layer is provided into the etching chamber. A blanket etch is performed on the blanket etch layer. A blanket deposition layer is deposited over the blanket etch layer after performing the blanket etch has been completed. A thickness of the blanket etch layer and a thickness of the blanket deposition layer is measured. The measured thicknesses are used to determine a process indicator. | 2012-09-13 |
20120231557 | METHOD OF MANUFACTURING FILM FOR SEMICONDUCTOR DEVICE - The present invention aims to provides a method of manufacturing a film for a semiconductor device in which a dicing film, a die bond film, and a protecting film are laminated in this order, including the steps of: irradiating the die bond film with a light ray having a wavelength of 400 to 800 nm to detect the position of the die bond film based on the obtained light transmittance and punching the dicing film out based on the detected position of the die bond film, and in which T | 2012-09-13 |
20120231558 | METHOD AND SYSTEM FOR DETERMINING OPTICAL PROPERTIES OF SEMICONDUCTOR WAFERS - A method and system are disclosed for determining at least one optical characteristic of a substrate, such as a semiconductor wafer. Once the optical characteristic is determined, at least one parameter in a processing chamber may be controlled for improving the process. For example, in one embodiment, the reflectivity of one surface of the substrate may first be determined at or near ambient temperature. From this information, the reflectance and/or emittance of the wafer during high temperature processing may be accurately estimated. The emittance can be used to correct temperature measurements using a pyrometer during wafer processing. In addition to making more accurate temperature measurements, the optical characteristics of the substrate can also be used to better optimize the heating cycle. | 2012-09-13 |
20120231559 | METHOD OF FORMING SEMICONDUCTOR THIN FILM AND SEMICONDUCTOR THIN FILM INSPECTION APPARATUS - A method of forming a semiconductor thin film includes the steps of: forming an amorphous semiconductor thin film on a substrate; forming a crystalline semiconductor thin film partially in each element region by applying laser light to the amorphous semiconductor thin film to selectively perform a heating process on the amorphous semiconductor thin film, thereby crystallizing the amorphous semiconductor thin film in a region irradiated with the laser light; and inspecting the crystallinity degree of the crystalline semiconductor thin film. The step of inspecting includes the steps of determining a contrast between the luminance of a crystallized region and the luminance of a non-crystallized region by applying light to the crystalline semiconductor thin film and the amorphous semiconductor thin film, and performing screening of the crystalline semiconductor thin film on the basis of the determined contrast. | 2012-09-13 |
20120231560 | LIGHT-EMITTING DEVICE HAVING A THINNED STRUCTURE AND THE MANUFACTURING METHOD THEREOF - A semiconductor light-emitting device having a thinned structure comprises a thinned structure formed between a semiconductor light-emitting structure and a carrier. The manufacturing method comprises the steps of forming a semiconductor light-emitting structure above a substrate; attaching the semiconductor light-emitting structure to a support; thinning the substrate to form a thinned structure; forming or attaching a carrier to the thinned substrate; and removing the support. | 2012-09-13 |
20120231561 | REMOVAL OF METAL - Methods of removing metal from a portion of a substrate are useful in integrated circuit fabrication. Methods include exposing the substrate to an oxidizing environment comprising at least one oxidizing agent and at least one reducing agent, and exposing the substrate to a reducing environment comprising at least one reducing agent and at least one oxidizing agent. | 2012-09-13 |
20120231562 | SEMICONDUCTOR MANUFACTURING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING ELECTRONIC DEVICE - A semiconductor manufacturing apparatus includes: a treatment chamber treating a treated film of a wafer using a desired chemical fluid; a film thickness measurement unit measuring an initial film thickness of the treated film before treatment and a final film thickness of the treated film after treatment; and a main body controlling unit calculating a treatment speed of the chemical fluid from the initial film thickness, the final film thickness, and a chemical fluid treatment time taken from the initial film thickness to the final film thickness to calculate a chemical fluid treatment time for a wafer to be treated next from the calculated treatment speed. | 2012-09-13 |
20120231563 | OPERATING METHOD OF HARDWIRED SWITCH - An operating method of a hardwired switch is provided. First, a first die is provided. The first die is configured as the first die in the hardwired switch. Next, a function of the first die is inspected to obtain an inspected result. Upon the inspected result, whether a second TSV is selectively disposed between the first landing pad and the fifth landing pad, between the second landing pad and the sixth landing pad, between the third landing pad and the seventh landing pad, or between the fourth landing pad and the eighth landing pad or not is determined. The first die is stacked above a second die, so that the second surface is located between the first die and the second die. | 2012-09-13 |
20120231564 | MONITORING TEST ELEMENT GROUPS (TEGS) FOR ETCHING PROCESS AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - Disclosed is a monitoring TEG for an etching process in a semiconductor device. The TEG includes an etch stopping layer on a substrate and a target layer to be etched provided on the etch stopping layer. The target layer to be etched includes a first opening portion formed by etching a portion of the target layer to be etched and a second opening portion formed by etching another portion of the target layer to be etched. The second opening portion has a smaller depth than the first opening portion. A depth of a partial contact hole formed by a first partial etching process may be measured. | 2012-09-13 |
20120231565 | PROCESS FOR PRODUCING A SUBSTRATE FOR A LIQUID EJECTION HEAD - Provided is a process for producing a substrate for a liquid ejection head, including forming a liquid supply port in a silicon substrate, the process including the steps of (a) forming an etch stop layer at a portion of a front surface of the silicon substrate at which portion the liquid supply port is to be formed; (b) performing dry etching using a Bosch process from a rear surface side of the silicon substrate up to the etch stop layer with use of an etching mask formed on a rear surface of the silicon substrate to thereby form the liquid supply port; and (c) simultaneously removing the etch stop layer and a deposition film formed inside the liquid supply port. | 2012-09-13 |
20120231566 | METHOD OF FABRICATING LIGHTWEIGHT AND THIN LIQUID CRYSTAL DISPLAY DEVICE - A method of fabricating a liquid crystal display device includes forming a first adhesive pattern on a first auxiliary substrate; forming a first process panel by attaching a first substrate to the first auxiliary substrate using the first adhesive pattern; forming an array element on the first substrate; forming a second adhesive pattern on a second auxiliary substrate; forming a second process panel by attaching a second substrate to the second auxiliary substrate using the second adhesive pattern; forming a color filter element on the second substrate; attaching the first and second process panels with a liquid crystal panel between the first and second process panels; weakening an adhesive strength of the first and second adhesive patterns; and detaching the first and second auxiliary substrates from the first and second substrates, respectively. | 2012-09-13 |
20120231567 | METHOD OF FORMING METAL PATTERN AND METHOD OF MANUFACTURING DISPLAY SUBSTRATE HAVING THE SAME - A method of forming a metal pattern includes forming a precursor layer including a metal precursor on a substrate, irradiating a light on the precursor layer to form a metal seed layer having a predetermined pattern, and electroless-plating the metal seed layer to form a metal pattern layer. | 2012-09-13 |
20120231568 | SEMICONDUCTOR DEVICE PRODUCTION PROCESS - (a) On a growth substrate, a void-containing layer that is made of a group III nitride compound semiconductor and contains voids is formed. (b) On the void-containing layer, an n-type layer that is made of an n-type group III nitride compound semiconductor and serves to close the voids is formed. (c) On the n-type layer, an active layer made of a group III nitride compound semiconductor is formed. (d) On the active layer, a p-type layer made of a p-type group III nitride compound semiconductor is formed. (e) A support substrate is bonded above the p-type layer. (f) The growth substrate is peeled off at the boundary where the voids are produced. In the above step (a) or (b), the supply of at least part of the materials that form the layer is decreased, while heating, before the voids are closed. | 2012-09-13 |
20120231569 | OPTOELECTRONIC COMPONENT WITH THREE-DIMENSION QUANTUM WELL STRUCTURE AND METHOD FOR PRODUCING THE SAME - An optoelectronic component with three-dimension quantum well structure and a method for producing the same are provided, wherein the optoelectronic component comprises a substrate, a first semiconductor layer, a transition layer, and a quantum well structure. The first semiconductor layer is disposed on the substrate. The transition layer is grown on the first semiconductor layer, contains a first nitride compound semiconductor material, and has at least a texture, wherein the texture has at least a first protrusion with at least an inclined facet, at least a first trench with at least an inclined facet and at least a shoulder facet connected between the inclined facets. The quantum well structure is grown on the texture and shaped by the protrusion, the trench and the shoulder facet. | 2012-09-13 |
20120231570 | SINGLE WAFER FABRICATION PROCESS FOR WAVELENGTH DEPENDENT REFLECTANCE FOR LINEAR OPTICAL SERIALIZATION OF ACCELEROMETERS - A plurality of Fabry-Perot interferometric sensors are optically coupled in series with each other to form an ordered optical series. Each Fabry-Perot interferometric sensor has a unique signalband and a passband. Each Fabry-Perot interferometric sensor has its unique signalband within the passbands of all of the next higher ordered Fabry-Perot interferometric sensors in the optical series so that a corresponding unique fringe signal from each of the Fabry-Perot interferometric sensors is a multiplexed output from the optical series. | 2012-09-13 |
20120231571 | METHOD FOR PRODUCING A SOLAR CELL - A method for producing a solar cell, including printing a conductive paste on a crystalline silicon substrate, and firing the conductive paste to form a light incident side electrode, wherein the conductive paste comprises conductive particles, glass frits, an organic binder and a solvent, wherein the conductive particles comprise (A) silver, and (B) one or more metals selected from the group consisting of copper, nickel, aluminum, zinc and tin, and the weight proportion (A):(B) is 5:95 to 90:10. | 2012-09-13 |
20120231572 | METHOD FOR FABRICATING NOVEL SEMICONDUCTOR AND OPTOELECTRONIC DEVICES - A method for fabricating an integrated device, the method including, overlying a first crystalline layer onto a second crystalline layer to form a combined layer, wherein one of the first and second crystalline layers is an image sensor layer and at least one of the first and second crystalline layers has been transferred by performing an atomic species implantation, and wherein at least one of the first and second crystalline layers includes single crystal transistors. | 2012-09-13 |
20120231573 | BACK SIDE ILLUMINATION IMAGE SENSOR AND A PROCESS THEREOF - A process and structure of a backside illumination (BSI) image sensor are disclosed. An n-type doped region is formed in a substrate, and a transfer gate is formed on top of the semiconductor substrate. A p-type doped region is formed in the n-type doped region either using the transfer gate as a mask or is non-self aligned formed. | 2012-09-13 |
20120231574 | Continuous Electroplating Apparatus with Assembled Modular Sections for Fabrications of Thin Film Solar Cells - An electroplating production line or apparatus that can be assembled with modular plating sections in a roll-to-roll or reel-to-reel continuous plating process is provided. The length of the plating cell for a modular plating section can be readily changed to fit different current densities required in a roll-to-roll or reel-to-reel process. In addition, the electrolyte solution tanks can be simply connected or disconnected from the modular plating sections and moved around. With these designs, a multiple layers of coating with different metals, semiconductors or their alloys can be electrodeposited on this production line or apparatus with a flexibility to easily change the plating orders of different materials. This apparatus is particularly useful in manufacturing Group IB-IIIA-VIA and Group IIB-VIA thin film solar cells such as CIGS and CdTe solar cells on flexible conductive substrates through a continuous roll-to-roll or reel-to-reel process. | 2012-09-13 |
20120231575 | METHOD FOR PRODUCING SOLAR CELL - The occurrence of internal stress is reduced during the solar cell production process, thereby reducing crystal defects and recombination loss. Provided is a method for producing a solar cell having a p-n junction, which involves a step for forming a p-type layer on a semiconductor substrate by applying a coating liquid for diffusion containing impurity which serves as an acceptor, and by diffusing the impurity by means of thermal diffusion and/or a step for forming an n-type layer on a semiconductor substrate by applying a coating liquid for diffusion containing impurity which serves as a donor, and by diffusing the impurity through a thermal diffusion treatment. | 2012-09-13 |
20120231576 | Aerosol Jet (R) Printing System for Photovoltaic Applications - Method and apparatus for depositing multiple lines on an object, specifically contact and busbar metallization lines on a solar cell. The contact lines are preferably less than 100 microns wide, and all contact lines are preferably deposited in a single pass of the deposition head. There can be multiple rows of nozzles on the deposition head. Multiple materials can be deposited, on top of one another, forming layered structures on the object. Each layer can be less than five microns thick. Alignment of such layers is preferably accomplished without having to deposit oversized alignment features. Multiple atomizers can be used to deposit the multiple materials. The busbar apparatus preferably has multiple nozzles, each of which is sufficiently wide to deposit a busbar in a single pass. | 2012-09-13 |
20120231577 | ANODE FOR AN ORGANIC ELECTRONIC DEVICE - There is provided an anode for an organic electronic device. The anode is a conducting inorganic material having an oxidized surface layer. The surface layer is non-conductive and hole-transporting. | 2012-09-13 |
20120231578 | FABRICATING METHOD OF ORGANIC THIN FILM TRANSISTOR HAVING A HYDROPHOBIC LAYER - A fabricating method of an organic thin film transistor having a hydrophobic layer is provided. The organic thin film transistor including a gate, a gate insulator covering the gate, a source, a drain, an organic semiconductor layer, a hydrophobic layer and a protecting droplet. A hydrophobic region is formed by forming the hydrophobic layer on a surface of the source and a surface of the drain, respectively. Meanwhile, a hydrophilic region is formed on the organic semiconductor layer exposed by the hydrophobic layer. The protecting droplet is self-assemblingly formed on the organic semiconductor layer to protect the device characteristic by using the surface tension thereof. | 2012-09-13 |
20120231579 | Methods Of Depositing Antimony-Comprising Phase Change Material Onto A Substrate And Methods Of Forming Phase Change Memory Circuitry - A method of depositing an antimony-comprising phase change material onto a substrate includes providing a reducing agent and vaporized Sb(OR) | 2012-09-13 |
20120231580 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed. The transistor formed using the oxide semiconductor film can have high reliability because the amount of change in the threshold voltage of the transistor by a bias-temperature stress test (BT test) is reduced. | 2012-09-13 |
20120231581 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a process of manufacturing a transistor including an oxide semiconductor layer, an amorphous oxide semiconductor layer which includes a region containing excess oxygen as compared to a stoichiometric composition ratio of an oxide semiconductor in a crystalline state is formed over a silicon oxide film, an aluminum oxide film is formed over the amorphous oxide semiconductor layer, and then heat treatment is performed so that at least part of the amorphous oxide semiconductor layer is crystallized and an oxide semiconductor layer which includes a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor layer is formed. | 2012-09-13 |
20120231582 | DEVICE INCLUDING A SEMICONDUCTOR CHIP - A device including a semiconductor chip and method. One embodiment provides a method of manufacturing a module, including providing a first device having a first semiconductor chip and a plurality of first external contact elements electrically coupled to the first semiconductor chip. The method further includes providing a second device having a second semiconductor chip, a plurality of second external contact elements and a metal layer including a first face and a second face opposite to the first face, the first face of the metal layer facing the second semiconductor chip and the second face of the metal layer facing the plurality of second external contact elements. The first external contact elements are soldered to the first face of the metal layer. | 2012-09-13 |
20120231583 | DIE-BONDING FILM AND USE THEREOF - A die-bonding film contains a glycidyl-group-containing acrylic copolymer (a) having a weight-average molecular weight of 500,000 or more and a phenolic resin (b), wherein the weight ratio (x/y) of the content x of the glycidyl-group-containing acrylic copolymer (a) to the content y of the phenolic resin (b) is 5 or more and 30 or less, and the die-bonding film substantially does not contain an epoxy resin having a weight-average molecular weight of 5000 or less. Thus, a die-bonding film having a high reliability is provided by which a sufficient adhering strength and an elastic modulus at a high temperature can be obtained before and after curing; the workability is good; air bubbles (voids) do not stay at the boundary between the die-bonding film and the adherend; and the die-bonding film can withstand a humidity resistance solder reflow test. | 2012-09-13 |
20120231584 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method for manufacturing a semiconductor device includes: a step of producing a semiconductor package intermediate by injecting a resin into a forming die in which electrodes, a heat dissipating pad, and a semiconductor element are disposed, providing a peel-off film on one side of the resin in the form of a still-uncured resin body opposite from the other side facing the heat dissipating pad and a rigid material on one side of the peel-off film, and curing the uncured resin body to form a sealant resin body; a step of forming a solder layer by reflow soldering between a substrate and the intermediate; and a step of removing the rigid material from the peel-off film, wherein the rigid material is integrated into the intermediate so as to make the thermal expansion coefficient and rigidity of the intermediate approximately equal to those of the substrate. | 2012-09-13 |
20120231585 | METHOD FOR PACKAGING A SEMICONDUCTOR STRUCTURE - The present application provides a method and semiconductor packaging structure comprising a conductive substrate having a first surface, a first lateral surface and a second lateral surface adjacent to the first surface. A first electrode line with two ends are provided on the first surface and the first lateral surface, and a second electrode line with two ends are provided on the first surface and a second lateral surface respectively. A semiconductor device is provided on the first surface of the conductive substrate which electrically connected to the first electrode line and the second electrode line, a protective plate with through holes covers the first surface, and a sheathing overlays the semiconductor device. | 2012-09-13 |
20120231586 | POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A method of manufacturing includes arranging an integral resin sleeve formed by integrating a plurality of sleeve parts so that the sleeve parts are respectively fitted with a plurality of electrode terminals. There is a press-fitting of the sleeve parts to the electrode terminals by performing mold clamping on molds to apply a force downward on the integral resin sleeve. Further, there is a filling of a molding resin into a hollow cavity of the molds. | 2012-09-13 |
20120231587 | METHODS OF FORMING VOLTAGE LIMITING DEVICES - Embodiments include methods for forming an electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, where the ESD protection device includes first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first and second widths. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vt1, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage. | 2012-09-13 |
20120231588 | MANUFACTURING METHOD OF THIN FILM TRANSISTOR - A manufacturing method of thin film transistors is provided. The manufacturing method includes: providing a substrate; forming a gate electrode; forming a gate insulating layer; forming a patterned oxide semiconductor layer; forming a source electrode and a drain electrode; and executing a localized laser treatment. A laser beam is used to irradiate at least a part of the patterned oxide semiconductor layer in the localized laser treatment. An electrical resistitivity of the patterned oxide semiconductor layer irradiated by the laser beam is lower than an electrical resistitivity of the patterned oxide semiconductor layer without being irradiated by the laser beam. | 2012-09-13 |
20120231589 | THIN-FILM TRANSISTOR ARRAY DEVICE MANUFACTURING METHOD - The following processes are included: preparing a substrate; forming a first gate electrode above the substrate; forming a second gate electrode above the substrate and adjacent to the first gate electrode; forming a gate insulating film on the first gate electrode and the second gate electrode; forming, on the gate insulating film, a noncrystalline semiconductor film at least in a first region above the first gate electrode and a second region above the second gate electrode; irradiating the noncrystalline semiconductor film a laser beam having continuous convex light intensity distributions; and forming a first source electrode and a first drain electrode above the first region, and a second source electrode and a second drain electrode above the second region. In the irradiating, when irradiating the first region with an inner region of the laser beam, the second region is irradiated with an outer region of the laser beam. | 2012-09-13 |
20120231590 | Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device - A method of setting a work function of a filly silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a suicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the suicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction. | 2012-09-13 |
20120231591 | METHODS FOR FABRICATING CMOS INTEGRATED CIRCUITS HAVING METAL SILICIDE CONTACTS - Methods are provided for fabricating CMOS integrated circuits. In accordance with one embodiment the methods include forming a gate electrode structure overlying an N-doped portion of a semiconductor substrate and growing an embedded silicon germanium area in the N-doped portion in alignment with the gate electrode structure. A layer of silicon is selectively grown overlying the embedded silicon germanium area and a nickel silicide contact is made to the layer of silicon. | 2012-09-13 |
20120231592 | Methods Of Fabricating A Memory Device - A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced. | 2012-09-13 |
20120231593 | METHOD FOR FABRICATING 3D-NONVOLATILE MEMORY DEVICE - A method for fabricating a 3D-nonvolatile memory device includes forming a sub-channel over a substrate, forming a stacked layer over the substrate, the stacked layer including a plurality of interlayer dielectric layers that are alternatively stacked with conductive layers, selectively etching the stacked layer to form a first open region exposing the sub-channel, forming a main-channel conductive layer to gap-fill the first open region, selectively etching the stacked layer and the main-channel conductive layer to form a second open region defining a plurality of main channels, and forming an isolation layer to gap-fill the second open region. | 2012-09-13 |
20120231594 | FLASH CELL WITH FLOATING GATE TRANSISTORS FORMED USING SPACER TECHNOLOGY - Methods for forming split gate flash cell structures provide for symmetrical cells that are immune to misalignment of the photoresist pattern when forming the control gates. Spacers are utilized to form the floating gates in the floating gate transistors used in the flash cells. The spacers may be oxide spacers used to mask a polysilicon layer that will form the floating gates or the spacers may be polysilicon spacers that will themselves form the floating gates. The inter-gate oxide of the floating gate transistors may be formed using HTO or may be deposited. Hard mask spacers are used in conjunction with the control gate photoresist patterning operation to control the size and configuration of the control gate and the channel length. | 2012-09-13 |
20120231595 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure is provided. A second area is between first and third areas. An epitaxial layer is formed on a substrate. A first gate is formed in the epitaxial layer and partially in first and second areas. A second gate is formed in the epitaxial layer and partially in second and third areas. A body layer is formed in the epitaxial layer in first and second areas. A doped region is formed in the body layer in the first area. All of the doped region, the epitaxial layer and the second gate are partially removed to form a first opening in the doped region and in the body layer in the first area, and form a second opening in the epitaxial layer in the third area and in a portion of the second gate. A first metal layer is filled in first and second openings. | 2012-09-13 |
20120231596 | QUANTUM WELL MOSFET CHANNELS HAVING UNI-AXIAL STRAIN CAUSED BY METAL SOURCE/DRAINS, AND CONFORMAL REGROWTH SOURCE/DRAINS - Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well. | 2012-09-13 |
20120231597 | Manufacturing Method for High Voltage Transistor - A manufacturing method for a high voltage transistor includes the following steps. A substrate is provided. A P-type epitaxial (P-epi) layer is provided above the substrate. An N-well is formed in the P-epi layer. A P-well is formed in the P-epi layer. Field oxide (FOX) layers are formed above the P-epi layer. A gate oxide (GOX) layer is formed between the FOX layers. P-type implants are doped into the P-well or N-type implants are doped into the N-well to adjust an electrical function of the high voltage transistor. | 2012-09-13 |
20120231598 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region. | 2012-09-13 |
20120231599 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing semiconductor devices includes forming a plurality of patterns spaced apart from each other on a semiconductor substrate, forming a filling layer, not removed in a subsequent process of forming a mask pattern and where the filling layer formed to have a lower height than the plurality of patterns, between the plurality of patterns, forming a mask layer on the entire structure where the filling layer is formed, and forming the mask pattern by removing some of the mask layer so that some of the plurality of patterns is removed. | 2012-09-13 |
20120231600 | SEMICONDUCTOR PROCESS HAVING DIELECTRIC LAYER INCLUDING METAL OXIDE AND MOS TRANSISTOR PROCESS - A semiconductor process having a dielectric layer including metal oxide is provided. The semiconductor process includes: A substrate is provided. A dielectric layer including metal oxide is formed on the substrate, wherein the dielectric layer has a plurality of oxygen-related vacancies. A first oxygen-importing process is performed to fill the oxygen-related vacancies with oxygen. Otherwise, three MOS transistor processes are also provided, each of which has a gate dielectric layer including a high dielectric constant, and a first oxygen-importing process is performed to fill the oxygen-related vacancies with oxygen. | 2012-09-13 |
20120231601 | Methods of fabricating a semiconductor device having metallic storage nodes - The present disclosure describes methods of fabricating a semiconductor device. An exemplary method includes forming a metal pattern on a substrate and etching the metal pattern using an etchant including at least an alkaline solution and an oxidant to form a metal electrode, where at least a portion of the surface of the metal electrode is uneven. | 2012-09-13 |
20120231602 | REVERSE CONSTRUCTION INTEGRATED CIRCUIT - A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate. | 2012-09-13 |
20120231603 | Methods of forming phase change material layers and methods of manufacturing phase change memory devices - A phase change material layer includes a Ge-M-Te (GMT) ternary phase change material, where Ge is germanium, M is a heavy metal, and Te is tellurium. The GMT ternary phase change material may also include a dopant. | 2012-09-13 |
20120231604 | MEMORY DEVICES WITH ENHANCED ISOLATION OF MEMORY CELLS, SYSTEMS INCLUDING SAME AND METHODS OF FORMING SAME - Memory cells of a memory device including a variable resistance material have a cavity between the memory cells. Electronic systems include such memory devices. Methods of forming a memory device include providing a cavity between memory cells of the memory device. | 2012-09-13 |
20120231605 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING A RECESSED CHANNEL - A method including forming an isolation trench; forming first and second liners on the isolation trench; filling the isolation trench an insulating material to form an isolation region and an active region; forming a preliminary gate trench including a first region across the isolation region to expose the first liner, the second liner, and the insulating material, and a second region across the active region to expose a portion of the substrate, the first region having a first sidewall with a planar shape, and the second region having a second sidewall with a concave central area such that an interface between the first and second regions has a pointed portion; removing a portion of the first liner exposed by the first region to form a dent having a first depth by which the pointed portion protrudes; removing the pointed portion to form a gate trench; and forming a gate electrode. | 2012-09-13 |
20120231606 | MULTI-LAYER STRUCTURES AND PROCESS FOR FABRICATING SEMICONDUCTOR DEVICES - The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing. | 2012-09-13 |
20120231607 | METHOD FOR FORMING A SILICON LAYER ON ANY SUBSTRATE USING LIGHT IRRADIATION - A method for forming a silicon layer according to inventive concept comprises: preparing an SOI substrate; applying an etchant or vapor of the etchant to the SOI substrate; and irradiating a light to the SOI substrate. | 2012-09-13 |
20120231608 | PRODUCTION PROCESS FOR SEMICONDUCTOR DEVICE - (a) Forming on a growth substrate a void-containing layer that is made of a group III nitride compound semiconductor and contains voids. (b) Forming on the void-containing layer an n-type layer that is made of an n-type group III nitride compound semiconductor and serves to close the voids. (c) Forming on the n-type layer an active layer made of a group III nitride compound semiconductor. (d) Forming on the active layer a p-type layer made of a p-type group III nitride compound semiconductor. (e) Bonding a support substrate above the p-type layer. (f) Peeling off the growth substrate at the boundary where the void are produced. (g) Planarizing the n-type layer. Step (b) comprises (b1) forming part of the n-type layer under conditions where horizontal growth is relatively weak and (b2) forming the remaining part of the n-type layer under conditions where horizontal growth is relatively strong. | 2012-09-13 |
20120231609 | VAPOR-PHASE GROWING APPARATUS AND VAPOR-PHASE GROWING METHOD - According to one embodiment, a vapor-phase growing apparatus, includes: a reactor containing a gas introduction portion and a gas reaction portion continued from the gas introduction portion; a susceptor, of which a surface is exposed in an interior space of the gas reaction portion of the reactor, for disposing and fixing a substrate on the surface thereof; a plurality of gas inlet conduits which are arranged subsequently along a direction of height of the reactor in the gas introduction portion of the reactor; and a switching device, which is provided in an outside of the reactor, for switching gases to be supplied to the gas inlet conduits, respectively. | 2012-09-13 |
20120231610 | VAPOR-PHASE GROWING APPARATUS AND VAPOR-PHASE GROWING METHOD - According to one embodiment, a vapor-phase growing apparatus, includes: a reactor containing a plurality of gas introduction portions and a gas reaction portion located below the gas introduction portions; a susceptor, of which a surface is exposed in an interior space of the gas reaction portion of the reactor, for disposing and fixing a substrate on the surface thereof; a gas distributor provided between the gas introduction portions and the gas reaction portion of the reactor; a plurality of gas inlet conduits which are connected with the gas introduction portions, respectively; and a switching device, which is provided in an outside of the reactor, for switching gases to be supplied to the gas inlet conduits, respectively. | 2012-09-13 |
20120231611 | DIHALIDE GERMANIUM(II) PRECURSORS FOR GERMANIUM-CONTAINING FILM DEPOSITIONS - Disclosed are GeX | 2012-09-13 |
20120231612 | METHOD FOR MANUFACTURING SILICON EPITAXIAL WAFER - A method for manufacturing a silicon epitaxial wafer, including vapor-phase growing a silicon single crystal thin film on a silicon single crystal substrate in a hydrogen atmosphere while supplying a source gas; and cooling a silicon epitaxial wafer having the formed silicon single crystal thin film by calculating a temperature at which a standard value or a process average value of concentration of an evaluation target impurity present in the silicon single crystal thin film coincides with solubility limit concentration of the evaluation target impurity and setting a cooling rate of the silicon epitaxial wafer after the film formation to be less than 20° C./sec in a temperature range of at least plus or minus 50° C. from the calculated temperature. | 2012-09-13 |
20120231613 | 3D MEMORY ARRAY ARRANGED FOR FN TUNNELING PROGRAM AND ERASE - A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory. | 2012-09-13 |
20120231614 | METHOD OF SEMICONDUCTOR MANUFACTURING PROCESS - The present invention related to a method for manufacturing a semiconductor, comprising steps of: providing a growing substrate; forming a semiconductor substrate on the growing substrate; forming a first structure with plural grooves and between the growing substrate and the semiconductor substrate; and changing the temperature of the growing substrate and the semiconductor substrate. | 2012-09-13 |
20120231615 | SEMICONDUCTOR THIN-FILM MANUFACTURING METHOD, SEMICONDUCTOR THIN-FILM MANUFACTURING APPARATUS, SUSCEPTOR, AND SUSCEPTOR HOLDER - Substrates are mounted on a plurality of susceptors respectively. The plurality of susceptors on which respective substrates are mounted are placed on a rotational mechanism so that the susceptors are vertically spaced at a predetermined interval. The rotational mechanism on which the plurality of susceptors are placed is rotated. The plurality of susceptors on which the substrates are mounted respectively are heated. Semiconductor thin-films are deposited by supplying a source gas to each of the susceptors that are heated while being rotated, the source gas having been heated while passing through gas flow paths of respective path lengths substantially equal to each other. | 2012-09-13 |
20120231616 | SEMICONDUCTOR STRUCTURE MADE USING IMPROVED MULTIPLE ION IMPLANTATION PROCESS - Methods and apparatus provide for: a first source of plasma, wherein the plasma includes a first species of ions; a second source of plasma, wherein the plasma includes a second species of ions; selection of the plasma from the first and second sources; and acceleration the first species of ions or the second species of ions toward a semiconductor wafer. | 2012-09-13 |
20120231617 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon dioxide on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including an oxygen atom. | 2012-09-13 |
20120231618 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon nitride on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including a nitrogen atom. | 2012-09-13 |
20120231619 | METHOD OF FABRICATING AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - A method of fabricating a semiconductor memory device includes preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region. Signal lines may be formed in a lower layer in a cell region. An insulation layer may be formed on the lower layer. Signal lines connected to cell region signal lines may be formed on an insulation layer of the peripheral region. A capping layer may be formed on the insulation layer and the core and peripheral signal lines. The capping layer may be etched to expose the lower layer of the cell array region and an etch stop may be formed on the lower layer and the core and peripheral region. | 2012-09-13 |
20120231620 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: diffusion layers formed at the front surface of a substrate; low-resistance parts formed at the front surfaces of the diffusion layers so as to have resistance lower than the diffusion layer; and rear contact electrodes passing through the substrate from the rear surface of the substrate to be connected to the low-resistance parts through the diffusion layers. | 2012-09-13 |
20120231621 | Manufacturing Method Of A Semiconductor Load Board - A manufacturing method of a semiconductor load board is disclosed. The manufacturing method includes a first conductive layer forming step, a first patterning step, a dielectric layer forming step, a drilling step, a second conductive layer forming step, a second patterning step or a two-times patterning step, and a solder connecting step. In a second patterning step or a two-times patterning step, a solder pads is formed in the opening of the dielectric layer, wherein each solder pad has a height higher than the height of the dielectric, and the width of each solder pad is equal to or smaller than the maximum width of the opening, such that wider intervals are provided in the same area and the problems of short circuit failure and electrical interference can be reduced. | 2012-09-13 |
20120231622 | SELF-ALIGNED DUAL DAMASCENE BEOL STRUCTURES WITH PATTERNABLE LOW- K MATERIAL AND METHODS OF FORMING SAME - A self-aligned interconnect structure is provided that includes a first patterned and cured low-k material located on a surface of a substrate, wherein the first patterned and cured low-k material includes at least one first interconnect pattern (via or trench pattern) therein. A second patterned and cured low-k material having at least one second interconnect pattern that is different from the first interconnect pattern is located atop the first patterned and cured low k material. A portion of the second patterned and cured low-k material partially fills the at least one first interconnect within the first patterned and cured low-k material. A conductive material fills the at least one first interconnect pattern and the at least one second interconnect pattern. A method of forming such a self-aligned interconnect structure is also provided. | 2012-09-13 |
20120231623 | METHOD OF MANUFACTURING A HIGH-RELIABILITY SEMICONDUCTOR DEVICE - A semiconductor device is provided, which includes a substrate, an insulator film formed over the substrate, and plural metal wirings with different widths containing copper as a main component and an impurity which is different from copper. The plural metal wirings includes a first metal wiring having a concentration profile where the concentration of the impurity metal increases from the center part of the stacking direction to the surface and the second metal wiring having a concentration profile where the concentration of the impurity metal decreases from the bottom surface of the stacking direction to the surface. Moreover, the width of the second metal wiring may be larger than the width of the first metal wiring. | 2012-09-13 |
20120231624 | Process for Producing Vertical Interconnections Through Structured Layers - A process is provided for producing at least one interconnecting well to achieve a conductive pathway between at least two connection layers of a component comprising a stack of at least one first substrate and one second substrate which are electrically insulated from one another, the process including defining a surface contact region of a surface connection layer over a surface of the stack and of at least one first contact region embedded in the stack starting from a first embedded connection layer of the first substrate. A region devoid of material is positioned between the first substrate and second substrates and which comprises a stage of producing a interconnecting well which passes through the second substrate and extends between the surface contact region and the first embedded contact region and passes through the region devoid of material, and also a first layer which covers the first embedded connection layer. | 2012-09-13 |
20120231625 | METHOD OF FORMING WIRING OF A SEMICONDUCTOR DEVICE - A method of forming wiring of a semiconductor device includes: forming an insulating resin on a main surface of a substrate such that an opening portion defining a wiring pattern is provided in the insulating resin; forming a first wiring layer made of a first metal on a bottom surface and side surfaces of the opening portion surrounding and a surface of the insulating resin opposite to the main surface of the substrate, the first wiring layer having a bottom portion formed on the bottom surface of the opening portion and side portions formed on the side surfaces, the bottom portion having a thickness greater than a thickness of at least one of the side portions; and cutting the insulating resin and the first wiring layer such that the insulating resin and the first wiring layer are exposed. | 2012-09-13 |
20120231626 | FORMATION OF LINER AND BARRIER FOR TUNGSTEN AS GATE ELECTRODE AND AS CONTACT PLUG TO REDUCE RESISTANCE AND ENHANCE DEVICE PERFORMANCE - The invention provides a method of forming a film stack on a substrate, comprising performing a silicon containing gas soak process to form a silicon containing layer over the substrate, reacting with the silicon containing layer to form a tungsten silicide layer on the substrate, depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer. | 2012-09-13 |
20120231627 | PROCESS FOR REMOVING A BULK MATERIAL LAYER FROM A SUBSTRATE AND A CHEMICAL MECHANICAL POLISHING AGENT SUITABLE FOR THIS PROCESS - An aqueous chemical mechanical polishing (CMP) agent (A) comprising solid particles (a1) containing (a11) a corrosion inhibitor for metals, and (a12) a solid material, the said solid particles (a1) being finely dispersed in the aqueous phase; and its use in a process for removing a bulk material layer from the surface of a substrate and planarizing the exposed surface by chemical mechanical polishing until all material residuals are removed from the exposed surface, wherein the CMP agent exhibits at the end of the chemical mechanical polishing, without the addition of supplementary materials, —the same or essentially the same static etch rate (SER) as at its start and a lower material removal rate (MRR) than at its start, —a lower SER than at its start and the same or essentially the same MRR as at its start or—a lower SER and a lower MRR than at its start; such that the CMP agent exhibits a soft landing behavior. | 2012-09-13 |
20120231628 | REDUCTION OF A PROCESS VOLUME OF A PROCESSING CHAMBER USING A NESTED DYNAMIC INERT VOLUME - A substrate processing chamber includes a lift actuator that moves a pedestal between a substrate loading position and a substrate processing position. An adjustable seal defines an expandable sealed volume between a bottom surface of the pedestal and a bottom surface of the substrate processing chamber and is moveable between the substrate loading position and the substrate processing position. When the pedestal is in the substrate processing position, the pedestal and the adjustable seal define a first inert volume and a first process volume. When the pedestal is in the substrate loading position, the pedestal and the adjustable seal define a second inert volume and a second process volume. The second inert volume is less than the first inert volume and the second process volume is greater than the first process volume. | 2012-09-13 |
20120231629 | TEMPLATE AND PATTERN FORMING METHOD - A template for imprinting in which a pattern is transferred onto a first substrate applied curable resin thereon, including a second substrate having a surface to be contacted with the curable resin, a concave portion provided on the surface and corresponding to a pattern to be transferred onto the first substrate, and at least one convex portion arranged in the concave portion to decrease volume of | 2012-09-13 |
20120231630 | Etching Gas - Disclosed is an etching gas provided containing CHF | 2012-09-13 |
20120231631 | PLASMA GENERATING APPARATUS AND PLASMA ETCHING METHOD USING THE SAME - A plasma generating apparatus and a plasma etching method are provided. The apparatus includes a chamber, a barrier, a susceptor, and a Radio Frequency (RF) power. The chamber forms a reaction space isolated from the external. The barrier divides the chamber into an upper chamber and a lower chamber. The barrier has a plurality of through-holes through formed to communicate the upper chamber and the lower chamber. The susceptor is installed in the lower chamber. The RF power supplies a bias power to the susceptor. | 2012-09-13 |
20120231632 | Novel Etching Composition - This disclosure relates to an etching composition containing at least one sulfonic acid, at least one compound containing a halide anion, the halide being chloride or bromide, at least one compound containing a nitrate or nitrosyl ion, and water. The at least one sulfonic acid can be from about 25% by weight to about 95% by weight of the composition. The halide anion can be chloride or bromide, and can be from about 0.01% by weight to about 0.5% by weight of the composition. The nitrate or nitrosyl ion can be from about 0.1% by weight to about 20% by weight of the composition. The water can be at least about 3% by weight of the composition. | 2012-09-13 |
20120231633 | OFF-ANGLED HEATING OF THE UNDERSIDE OF A SUBSTRATE USING A LAMP ASSEMBLY - Disclosed are method and apparatus for treating a substrate. The apparatus is a dual-function process chamber that may perform both a material process and a thermal process on a substrate. The chamber has an annular radiant source disposed between a processing location and a transportation location of the chamber. Lift pins have length sufficient to maintain the substrate at the processing location while the substrate support is lowered below the radiant source plane to afford radiant heating of the substrate. A method of processing a substrate having apertures formed in a first surface thereof includes depositing material on the first surface in the apertures and reflowing the material by heating a second surface of the substrate opposite the first surface. A second material can then be deposited, filling the apertures partly or completely. Alternately, a cyclical deposition/reflow process may be performed. | 2012-09-13 |
20120231634 | TEMPLATE DERIVATIVE FOR FORMING ULTRA-LOW DIELECTRIC LAYER AND METHOD OF FORMING ULTRA-LOW DIELECTRIC LAYER USING THE SAME - A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer. | 2012-09-13 |
20120231635 | TEMPLATE DERIVATIVE FOR FORMING ULTRA-LOW DIELECTRIC LAYER AND METHOD OF FORMING ULTRA-LOW DIELECTRIC LAYER USING THE SAME - A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer. | 2012-09-13 |
20120231636 | PROCESS FOR TREATING A SEMICONDUCTOR-ON-INSULATOR STRUCTURE - A process for treating a semiconductor-on-insulator structure that has, in succession, a support substrate, a layer of an oxide or oxynitride of a semiconductor material, and a thin semiconductor layer of the semiconductor material. The process includes providing, on the surface of the thin layer, a mask defining exposed regions of the thin layer; providing a layer of nitride or oxynitride of the semiconductor material on the exposed regions of the thin layer; and applying a heat treatment causing at least some of the oxygen in the oxide or oxynitride layer to diffuse through the exposed regions. The nitride or oxynitride layer is provided at a thickness sufficient to provide a ratio of the rate of oxygen diffusion though the exposed regions to that through the regions covered with the mask that is greater than 2. | 2012-09-13 |
20120231637 | BOARD-TO-BOARD CONNECTOR - A board-to-board connector has such a configuration that at least one a first reinforcing bracket of a first connector and a second reinforcing bracket of a second connector is provided with a bent portion having a crank shape, viewed from the insertion/removal direction of the first and second connectors. Owing to such a configuration, deformation of the first reinforcing bracket and/or the second reinforcing bracket can be prevented, and a firm engagement state between the first and second reinforcing brackets is achieved. As a result, a strong removal force is required for releasing the engagement state, and a stable engagement between the first connector and the second connector can be maintained. | 2012-09-13 |
20120231638 | WIRING MEMBER - A wiring member is provided that can suppress an influence due to deviation of a position of connection as much as possible so as to maintain a good wiring state. The wiring member | 2012-09-13 |
20120231639 | SURFACE-MOUNT CONNECTER AND SUBSTRATE UNIT - A surface-mount connector includes an enclosure, and a plurality of terminals that is mounted in the enclosure, one end of each of terminals being joined to a surface of a substrate, another end of each terminal fitting into a terminal of a connector that is to be fitted into the surface-mount connector, wherein each of the terminals is mounted in the enclosure so as to be movable within a restricted range in directions to come into contact with and separate from the substrate. | 2012-09-13 |
20120231640 | BATTERY CONNECTING STRUCTURE - The present invention is to provide a battery connecting structure to prevent a joint between a terminal and an electric wire from getting wet with water. The battery connecting structure includes a plurality of bus bars connecting a plurality of batteries in series by connecting a positive electrode and a negative electrode of the adjacent battery, said batteries overlapped with each other in a manner that the positive electrode and the negative electrode are arranged in the straight line alternately; a plurality of terminals respectively overlapped with each bus bar; a plurality of electric wires respectively connected with each terminal; and a plate receiving them. The plate includes a plurality of first receiving portion for receiving each bus bar and each terminal overlapped with the bus bar, a second receiving portion for receiving the electric wires connected to each terminal, and a plurality of third receiving portion for leading each electric wire connected to each terminal from each first receiving portion to the second receiving portion. Further, a bus bar connecting and a wire connecting portions of each terminal are received in each first receiving portion. | 2012-09-13 |
20120231641 | UNIT CELL CONNECTING DEVICE, ASSEMBLED BATTERY HAVING THE SAME, AND METHOD OF PRODUCING THE ASSEMBLED BATTERY - A unit cell connecting device is provided for connecting a plurality of unit cells (electric cells) arranged vertically and horizontally in rows such that positive electrodes (anodes) and negative electrodes (cathodes) thereof are aligned on same planes, respectively. The unit cell connecting device includes a plurality of inner connecting pieces and at least one outer connecting piece for connecting the inner connecting pieces. Each of the inner connecting pieces is configured to connect the positive electrodes and the negative electrodes of the electric cells. The outer connecting piece is configured to have a lead section formed at one end section thereof so as to protrude outwardly, so that the outer connecting piece is configured to connect a lead wire. As a result, it is possible to provide the unit cell connecting device resistant against a large current that flows in a high-capacity assembled battery. | 2012-09-13 |
20120231642 | CABLE SYSTEM WITH INTEGRATED ADAPTOR - A power cable or data cable system includes an integrated electrical connection adaptor configured to be mechanically coupled to the cable system when not in use. The adaptor is coupled to the cable system using clasping features formed in the body of the adaptor or a tethering element. Thus, the adaptor is conveniently located for use and cannot be lost. In some embodiments, the tethering element serves as a cable management system that enhances portability of the cable system by bundling loops of the cable system together. | 2012-09-13 |
20120231643 | Connection Plug For Portable Device - A connection plug for a portable device is configured such that a single case is provided with different kinds of plug connection terminal units, which allows the single connection plug to perform functions of two kinds of connection plugs. The connection plug includes a case having an upper plug connection terminal unit and a lower plug connection terminal unit which are spaced apart from each other and disposed along upper and lower portions of the case respectively. | 2012-09-13 |
20120231644 | VEHICLE CHARGE CABLE SOCKET CONNECTOR - Electrical connection reliability of a vehicle charge cable socket connector is maintained for a long period. Dust particles and rain drops that inevitably get into a socket contact can be let out through a contact through hole and a housing through hole that extend from inside the socket contact to outside a housing. Such a configuration can avoid adverse effects of dust particles and drain drops on electrical contact and maintain high connection reliability for a long period. | 2012-09-13 |
20120231645 | CONDUIT GROUNDING CLIP - A wireless raceway ( | 2012-09-13 |
20120231646 | CONNECTOR - It is the object of the present invention to provide a connector | 2012-09-13 |
20120231647 | ELECTRICAL CARD CONNECTOR - An electrical card connector ( | 2012-09-13 |
20120231648 | CONNECTOR ASSEMBLY WITH ROBUST LATCHING MEANS - A connector assembly ( | 2012-09-13 |
20120231649 | CABLE CONNECTOR ASSEMBLY FOR CONNECTING HARD DISK DRIVE - A cable connector assembly includes a first cable connector, a second cable connector, a locking member, and a retaining frame. The first cable connector includes a first base portion. The second cable connector includes a second base portion. The retaining frame includes a front wall. The front wall defines a mounting hole. The first base portion and the second base portion are received in the mounting hole with the second base portion contacted to the first base portion. The locking member is detachably mounted in the mounting hole at one side of the second base portion. When the locking member is slid to the second base portion and pressing on the second base portion, the second base portion presses on the first base portion. The first base portion and the second base portion are locked in the mounting hole. | 2012-09-13 |
20120231650 | SIM Card Slot Having a Fool-proof Function and Electronic Apparatus Containing the SIM Card Slot - The embodiments of the present invention provide a SIM card slot having a fool-proof function and electronic apparatus containing the SIM card slot. The SIM card slot comprises: an accommodating space for accommodating the SIM card; and a cover, which may be of metal, positioned above the accommodating space; wherein a recessed zone is arranged in the cover, the recessed zone constituting a stopping sheet for blocking the insertion of the bevel edge of the SIM card. The wrong insertion of the SIM card of the electronic apparatus, such as a mobile terminal, may be prevented by the SIM card slot having a fool-proof function and electronic apparatus containing the SIM card slot of the present invention. | 2012-09-13 |
20120231651 | COMPONENT FIXING STRUCTURE - A plug of a connector includes plug-side electrode terminals arranged therein, the plug having a first engagement part on one end side in a direction of arrangement of the plug-side electrode terminals and a second engagement part on the other end side. A jack of the connector includes jack-side electrode terminals arranged therein, the jack having a third engagement part on one end side in a direction of arrangement of the jack-side electrode terminals and a fourth engagement part on the other end side. A guide member has a fifth engagement part and a sixth engagement part, the fifth engagement part configured to engage with the first engagement part of the plug and the third engagement part of the jack, the sixth engagement part configured to engage with the second engagement part of the plug and the fourth engagement part of the jack. | 2012-09-13 |
20120231652 | WATERPROOF SIMPLEX RECEPTACLE WITH INSULATION DISPLACEMENT - A receptacle ( | 2012-09-13 |
20120231653 | STRAIN-RELIEF MEMBERS FOR CABLES AND METHODS FOR MAKING THE SAME - Aesthetically pleasing strain-relief members for cables and methods for making the same are disclosed. The strain-relief members are constructed to have one or more tuning members that provide selective strain relief for the cable. Each tuning member can vary the wall thickness of the strain relief member, and depending on several factors such as how many tuning members are present, their shape, and their positions within the strain-relief member, the strain-relief member can be specifically tailored to meet desired strain relief characteristics. | 2012-09-13 |
20120231654 | ELECTRICAL CORD AND APPARATUS USING SAME - An electricity conducting cord has first and second ends, one of the ends comprising an electrical connection member engageable with a power connection member of an apparatus having an apparatus power rating, at least one of the power connection member and the electrical connection member comprising electrical connectors and a physical cord identification member, the physical cord identification member is configured to inhibit the electricity conducting cord being electrically connected to the power connection member if the electricity conducting cord has a power rating lower than the apparatus power rating. | 2012-09-13 |
20120231655 | ELECTRICAL CONNECTOR - An electrical connector includes an insulating housing, and a plurality of electrical contacts assembled in the insulating housing respectively. At least two of the electrical contacts having the same transmitting action are short connected together in the process of manufacturing the electrical contacts. So the process of utilizing a wire to achieve a short connection between the corresponding electrical contacts, as described in the prior art, is omitted, and it saves a lot of manpower and material resources, and further simplifies the process for achieving the short connection effect. | 2012-09-13 |