37th week of 2017 patent applcation highlights part 56 |
Patent application number | Title | Published |
20170263522 | ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME - An electronic component package includes a frame, an electronic component, an encapsulant, a metal layer, and a redistribution layer. The frame has a through hole. The electronic component is disposed in the through hole of the frame and has an active surface on which electrode pads are formed and an inactive surface opposing the active surface. The encapsulant covers the inactive surface of the electronic component and is disposed between the frame and the electronic component within the through hole. The metal layer is formed on a surface of the encapsulant. The redistribution layer is disposed adjacently to the active surface of the electronic component and electrically connected to the electrode pads. | 2017-09-14 |
20170263523 | WAFER-LEVEL CHIP-SIZE PACKAGE WITH REDISTRIBUTION LAYER - A wafer-level chip-size package includes a semiconductor structure. A bonding pad is formed over the semiconductor structure, including a plurality of conductive segments. A conductive component is formed over the semiconductor structure, being adjacent to the bonding pad. A passivation layer is formed, exposing a portions of the conductive segments of the first bonding pad. A conductive redistribution layer is formed over the portions of the conductive segments of the first bonding pad exposed by the passivation layer. A planarization layer is formed over the passivation layer and the conductive redistribution layer, exposing a portion of the conductive redistribution layer. A UBM layer is formed over the planarization layer and the portion of the conductive redistribution layer exposed by the planarization layer. A conductive bump is formed over the UBM layer. | 2017-09-14 |
20170263524 | ELEMENT CHIP AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing an element chip includes a protection film stacking step of staking a protection film to the element region, and the dividing region, the part of the exposed second damaged region and a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region by exposing the substrate to second plasma and remaining the protection film for covering the part of the second damaged region. Furthermore, the method for manufacturing an element chip includes a plasma dicing step of dividing the substrate to a plurality of element chips by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member. | 2017-09-14 |
20170263525 | ELEMENT CHIP AND METHOD FOR MANUFACTURING THE SAME - A method of manufacturing an element chip includes an isotropic etching step of removing the first damaged region and the second damaged region through etching the first layer isotropically by exposing the substrate to first plasma after the laser scribing step. The method of manufacturing an element chip further includes a plasma, dicing step of dividing the substrate to a plurality of element chips including the element region through etching the first layer anisotropically by exposing the substrate to second plasma in a state where the second main surface is supported by a supporting member, after the isotropic etching step. | 2017-09-14 |
20170263526 | ELEMENT CHIP AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing an element chip includes a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region through etching the protection film anisotropically by exposing the substrate to first plasma and remaining the protection film for covering an end surface of the element region. Furthermore, the method for manufacturing an element chip includes an isotropic etching step of etching the dividing region isotropically by exposing the substrate to second plasma and a plasma dicing step of dividing the substrate to a plurality of element chips including the element region by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member. | 2017-09-14 |
20170263527 | SEMICONDUCTOR MODULE - A semiconductor module comprises a semiconductor device; a substrate, on which the semiconductor device is attached; a molded encasing, into which the semiconductor device and the substrate are molded; at least one power terminal partially molded into the encasing and protruding from the encasing, which power terminal is electrically connected with the semiconductor device; and an encased circuit board at least partially molded into the encasing and protruding over the substrate in an extension direction of the substrate, wherein the encased circuit board comprises at least one receptacle for a pin, the receptacle being electrically connected via the encased circuit board with a control input of the semiconductor device. | 2017-09-14 |
20170263528 | SEMICONDUCTOR DEVICE - Certain embodiments provide a semiconductor device of an example including a semiconductor substrate, a semiconductor layer provided on the semiconductor substrate, a drain electrode and source electrode provided on the semiconductor layer, a gate electrode provided between the drain electrode and the source electrode on the semiconductor layer, and a heat transfer unit provided so as to fill a groove which penetrates the semiconductor layer right below the drain electrode till reaches the semiconductor substrate. The heat transfer unit includes a material different from that of the drain electrode and having thermal conductivity higher than that of the semiconductor substrate and the semiconductor layer under an operating temperature of the semiconductor device. | 2017-09-14 |
20170263529 | THICK-SILVER LAYER INTERFACE - A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer. | 2017-09-14 |
20170263530 | ENCAPSULATED POWER SEMICONDUCTOR DEVICE HAVING A METAL MOULDED BODY AS A FIRST CONNECTING CONDUCTOR - A power semiconductor device has a metal moulded body forming a first connecting conductor, with a first main surface of the metal moulded body there is a first recess having a first base in which a first power semiconductor component is arranged which faces the first base and is connected in an electrically conductive manner. From a second main surface of the metal moulded body, a second recess has a second base and a second power semiconductor component is arranged with the first contact surface thereof associated with the second base connected in an electrically conductive manner to this base. An insulating material layer is on both main surfaces, filling and completely covering the recess, wherein the first insulating layer has an electrically conductive first via which connects a second contact surface of the first power semiconductor component in an electrically conductive manner to a first conducting surface arranged on the first insulating layer. | 2017-09-14 |
20170263531 | POWER ELECTRONICS ASSEMBLIES HAVING A WIDE BANDGAP SEMICONDUCTOR DEVICE AND AN INTEGRATED FLUID CHANNEL SYSTEM - A power electronics assembly having a semiconductor device stack having a wide bandgap semiconductor device, a first electrode electrically coupled the wide bandgap semiconductor device, and a second electrode electrically coupled the wide bandgap semiconductor device. A substrate layer is coupled to the semiconductor device stack such that the first electrode is positioned between the substrate layer and the wide bandgap semiconductor device. The substrate layer includes a substrate inlet port and a substrate outlet port. An integrated fluid channel system extends between the substrate inlet and outlet ports and includes a substrate fluid inlet channel extending from the substrate inlet port into the substrate layer, a substrate fluid outlet channel extending from the substrate outlet port into the substrate layer, and one or more semiconductor fluid channels extending into the wide bandgap semiconductor device in fluid communication with the substrate fluid inlet and outlet channels. | 2017-09-14 |
20170263532 | POWER ELECTRONICS ASSEMBLIES HAVING A SEMICONDUCTOR COOLING CHIP AND AN INTEGRATED FLUID CHANNEL SYSTEM - A power electronics assembly includes a semiconductor device stack having a wide bandgap semiconductor device, a semiconductor cooling chip thermally coupled to the wide bandgap semiconductor device, and a first electrode electrically coupled to the wide bandgap semiconductor device and positioned between the wide bandgap semiconductor device and the semiconductor cooling chip. The semiconductor cooling chip is positioned between a substrate layer and the wide bandgap semiconductor device. The substrate layer includes a substrate inlet port and a substrate outlet port. An integrated fluid channel system extends between the substrate inlet port and the substrate outlet port and includes a substrate fluid inlet channel extending from the substrate inlet port into the substrate layer, a substrate fluid outlet channel extending from the substrate outlet port into the substrate layer, and one or more cooling chip fluid channels extending into the semiconductor cooling chip. | 2017-09-14 |
20170263533 | POWER SEMICONDUCTOR MODULE, FLOW PATH MEMBER, AND POWER-SEMICONDUCTOR-MODULE STRUCTURE - The invention is provided with a metal base plate including a first surface and a second surface and a cooling case including a bottom wall and a side wall formed around the bottom wall, in which one end of the side wall being joined to a second surface side of the metal base plate, and a coolant can be circulated in a space enclosed by the metal base plate, the bottom wall, and the side wall, in which the cooling case has an inlet portion and an outlet portion for the coolant which are connected to either the bottom wall or the side wall and disposed along a peripheral edge of the second surface of the metal base plate, and includes a first flange disposed at an inlet opening side of the inlet portion and a second flange disposed at an outlet opening side of the outlet portion. | 2017-09-14 |
20170263534 | HEAT SINK FOR COOLING OF POWER SEMICONDUCTOR MODULES - A heat sink for cooling at least one power semiconductor module, and that includes a basin for containing a cooling liquid. The basin has a contact rim for receiving the base plate and that includes a surface that is sloped inwards to the basin. | 2017-09-14 |
20170263535 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor module | 2017-09-14 |
20170263536 | CHIP PACKAGE HAVING TILTED THROUGH SILICON VIA - A chip package includes at least one integrated circuit die. The integrated circuit die includes a substrate portion having an internal plane between a front side and a back side, an electrical interconnect portion on the front side, a plurality of first connection terminals on an upper surface of the electrical interconnect portion, a plurality of second connection terminals on the back side of the substrate portion, a plurality of connection wirings electrically connecting the first connection terminals and the second connection terminals, a chip selection terminal between the internal plane of the substrate portion and the upper surface of the electrical interconnect portion, and a chip selection wiring connected to the chip selection terminal and one of the second connection terminals and the first connection terminals. At least one of the chip selection wiring and the plurality of connection wirings includes a tilted portion with respect to the back side of the substrate portion. | 2017-09-14 |
20170263537 | SEMICONDUCTOR PACKAGE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor package includes a die pad; a plurality of external connection terminals located around the die pad; a semiconductor chip located on a top surface of the die pad and electrically connected with the plurality of external connection terminals; and a sealing member covering the die pad, the plurality of external connection terminals and the semiconductor chip and exposing an outer terminal of each of the plurality of external connection terminals. A side surface of the outer terminal of each of the plurality of external connection terminals includes a first area, and the first area is plated. | 2017-09-14 |
20170263538 | PACKAGED SEMICONDUCTOR DEVICE HAVING BENT LEADS AND METHOD FOR FORMING - A package device has a first lead frame having a first flag. A first integrated circuit is on the first flag. A first encapsulant is over the first integrated circuit. A first plurality of leads is electrically bonded to the first integrated circuit. A first lead of the first plurality of leads has an inner portion covered by the first encapsulant and an outer portion extending outside the encapsulant. The outer portion has a hole and a bend at the hole. The outer portion extends above the first encapsulant. | 2017-09-14 |
20170263539 | POWER OVERLAY STRUCTURE AND METHOD OF MAKING SAME - A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface. | 2017-09-14 |
20170263540 | STACKED CHIP-ON-BOARD MODULE WITH EDGE CONNECTOR - A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. | 2017-09-14 |
20170263541 | MITIGATION OF WHISKER GROWTH IN TIN COATINGS BY ALLOYING WITH INDIUM - A method comprising incorporating indium into an entire Sn film for preventing the growth of whiskers from the Sn film, wherein the Sn film is applied to a metallic substrate. The indium is present in the entire thickness of the Sn film. | 2017-09-14 |
20170263542 | PREFORMED LEAD FRAME DEVICE AND LEAD FRAME PACKAGE INCLUDING THE SAME - A preformed lead frame device includes a molding layer and a plurality of spaced-apart lead frame units. The molding layer is made of a polymer material, and includes a plurality of framed portions, and a plurality of longitudinal and transverse frame sections intersecting each other to frame the framed portions. The lead frame units are arranged in an array and made of metal. Each of the lead frame units is embedded in a respective one of the framed portions and includes a plurality of spaced-apart leads. | 2017-09-14 |
20170263543 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A thin semiconductor device with enhanced edge protection, and a method of manufacturing thereof. For example and without limitation, various aspects of this disclosure provide a thin semiconductor device comprising a substrate with an edge-protection region, and a method of manufacturing thereof. | 2017-09-14 |
20170263544 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor device with enhanced interposer quality, and method of manufacturing thereof. For example and without limitation, various aspects of the present disclosure provide an interposer die that comprises a first signal distribution structure comprising at least a first dielectric layer and a first conductive layer, wherein the signal distribution structure is protected at lateral edges by a protective layer. Also for example, various aspects of the present disclosure provide a method of manufacturing a semiconductor device comprising such an interposer die. | 2017-09-14 |
20170263545 | WIRING BOARD AND SEMICONDUCTOR DEVICE - A wiring board includes: a first insulating layer; a first wiring layer formed on a lower surface of the first insulating layer; a first through hole which penetrates the first insulating layer; a first via wiring including: a filling portion formed to fill the first through hole; and a protruding portion protruding upward from an upper surface of the first insulating layer; a second wiring layer including a land, wherein the land includes an outer circumferential portion and a central portion, a second insulating layer formed on the upper surface of the first insulating layer; a second through hole which penetrates the second insulating layer in the thickness direction; a second via wiring formed to fill the second through hole; and a third wiring layer formed on an upper surface of the second insulating layer. | 2017-09-14 |
20170263546 | WIRING BOARD WITH ELECTRICAL ISOLATOR AND BASE BOARD INCORPORATED THEREIN AND SEMICONDUCTOR ASSEMBLY AND MANUFACTURING METHOD THEREOF - A wiring board includes an electrical isolator laterally surrounded by a base board and a molding compound. The electrical isolator is inserted into a through opening of the base board and has a thickness greater than that of the base board. The molding compound covers the top side of the base board and sidewalls of the electrical isolator, and provides a reliable interface for deposition of a routing circuitry thereon. The base board can serve as an alignment guide for isolator placement or/and provide another routing to enhance electrical routing flexibility for the wiring board. | 2017-09-14 |
20170263547 | METALLIC BLOCKING LAYER FOR RELIABLE INTERCONNECTS AND CONTACTS - A semiconductor structure is provided that includes a first interconnect dielectric layer containing a first interconnect metal structure embedded therein. A second interconnect dielectric layer containing a second interconnect metal structure embedded therein is located atop the first interconnect dielectric layer. A metallic blocking layer is present that separates a surface of the second interconnect metal structure from a surface of the first interconnect metal structure. The metallic blocking layer has a lower resistivity than the first and second interconnect metal structures. The metallic blocking layer prevents electromigration of metallic ions from the first and second interconnect metal structure. | 2017-09-14 |
20170263548 | STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE - Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate. The method also includes forming an opening in the dielectric layer. A dielectric constant of a first portion of the dielectric layer is less than that of a second portion of the dielectric layer surrounding the opening. The method further includes forming a conductive feature in the opening. The second portion is between the first portion and the conductive feature. In addition, the method includes modifying an upper portion of the first portion to increase the dielectric constant of the upper portion of the first portion. The method also includes removing the upper portion of the first portion and the second portion. | 2017-09-14 |
20170263549 | STRUCTURE AND FORMATION METHOD OF INTERCONNECT STRUCTURE OF SEMICONDUCTOR DEVICE - Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The dielectric layer has a protection region and a lower portion that is between the protection region and the semiconductor substrate. The protection region contains more carbon than the dielectric layer. The semiconductor device structure also includes a conductive feature penetrating through the protection region, and a lower portion of the conductive feature is surrounded by the lower portion of the dielectric layer. | 2017-09-14 |
20170263550 | SEMICONDUCTOR DEVICE AND DESIGNING METHOD THEREOF - A metal wiring layer includes a plurality of hierarchical blocks each divided by a side that serves as a boundary. One of the hierarchical blocks is placed to extend along the outer periphery of the self hierarchical block, and includes: a shield ring wire formed by a single metal wire or by a plurality of metal wires; and a plurality of metal wires that are placed inside the shield ring wire and extend in a preferential direction determined in advance. The shield ring wire has a first section extending in the preferential direction and a second section extending in a non-preferential direction perpendicular to the preferential direction. | 2017-09-14 |
20170263551 | NOVEL METHOD FOR CREATING ALTERNATE HARDMASK CAP INTERCONNECT STRUCTURE WITH INCREASED OVERLAY MARGIN - Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer. | 2017-09-14 |
20170263552 | SEMICONDUCTOR DEVICE STRUCTURES - A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. | 2017-09-14 |
20170263553 | STRUCTURE AND METHOD TO SELF ALIGN VIA TO TOP AND BOTTOM OF TIGHT PITCH METAL INTERCONNECT LAYERS - Embodiments of the invention include interconnect structures with overhead vias and through vias that are self-aligned with interconnect lines and methods of forming such structures. In an embodiment, an interconnect structure is formed in an interlayer dielectric (ILD). One or more first interconnect lines may be formed in the ILD. The interconnect structure may also include one or more second interconnect lines in the ILD that arranged in an alternating pattern with the first interconnect lines. Top surfaces of each of the first and second interconnect lines may be recessed below a top surface of the ILD. The interconnect structure may include a self-aligned overhead via formed over one or more of the first interconnect lines or over one or more of the second interconnect lines. In an embodiment, a top surface of the self-aligned overhead via is substantially coplanar with a top surface of the ILD. | 2017-09-14 |
20170263554 | FUSE FORMED FROM III-V ASPECT RATIO STRUCTURE - A fuse structure is provided above a first portion of a semiconductor material. The fuse structure includes a first end region containing a first portion of a metal structure having a first thickness, a second end region containing a second portion of the metal structure having the first thickness, and a neck region located between the first and second end regions. The neck region contains a third portion of the metal structure having a second thickness that is less than the first thickness, wherein a portion of the neck region is located in a gap positioned between a bottom III-V compound semiconductor material portion and a top III-V compound semiconductor material portion. | 2017-09-14 |
20170263555 | Semiconductor Device and Method - A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer. | 2017-09-14 |
20170263556 | CONDUCTIVE STRUCTURES, SYSTEMS AND DEVICES INCLUDING CONDUCTIVE STRUCTURES AND RELATED METHODS - Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures. | 2017-09-14 |
20170263557 | CONTACTS HAVING A GEOMETRY TO REDUCE RESISTANCE - A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dieletric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region. | 2017-09-14 |
20170263558 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to the embodiment, the semiconductor device includes: a substrate; a stacked body; and a plurality of columnar portions. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The stacked body includes a stacked portion and a staircase portion. The plurality of electrode layers includes a first portion and a second portion. The columnar portions are provided in the stacked portion of the stacked body. The columnar portions extend in a stacking direction of the stacked body. The columnar portions include a semiconductor body extending in the stacking direction and a charge storage film. The second portion includes a third portion. A thickness of the third portion along the stacking direction is thinner than a thickness of the first portion along the stacking direction. | 2017-09-14 |
20170263559 | POWER AND GROUND ROUTING OF INTEGRATED CIRCUIT DEVICES WITH IMPROVED IR DROP AND CHIP PERFORMANCE - An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal. | 2017-09-14 |
20170263560 | Interconnect Structure, Printed Circuit Board, Semiconductor Device, and Manufacturing Method for Interconnect Structure - An object of the present invention is to provide an interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing miniaturization of signal lines and increasing film thickness. To accomplish this object, the present invention is configured as an interconnect structure including a resin layer; and interconnects formed on the resin layer, wherein the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves. | 2017-09-14 |
20170263561 | TECHNIQUES FOR OBSERVING AN ENTIRE COMMUNICATION BUS IN OPERATION - A routing apparatus includes a PCB having first and second arrays of contact pads, an interposer having third, fourth and fifth arrays of contact pads, the third and fourth arrays of contact pads being disposed on opposing surfaces of the interposer, the third array of contact pads being electrically connected to the first array of contact pads. First and second integrated circuits are respectively mounted on the second and fourth arrays of contact pads. The interposer includes a first group of conductive traces insulated from one another, a first array of conductive vias extending perpendicularly to the first group of conductive traces, the first array of conductive vias including through-vias connecting the third array of contact pads to corresponding contact pads in the fourth array of contact pads. The interposer further including isolation resistors embedded within the first array of conductive vias, each isolation resistor being configured to produce a copy of a signal flowing through the conductive via that is coupled to one end of the isolation resistor on the conductive trace that is coupled to an opposite end of the isolation resistor. | 2017-09-14 |
20170263562 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device is disclosed. The device includes a substrate, and a first interconnect on the substrate. The first interconnect includes a first catalyst layer capable of growing graphene, a graphene layer in contact with a side surface of the first catalyst layer. The device further includes a non-catalyst layer in contact with a bottom surface of the graphene layer, and incapable of growing graphene. | 2017-09-14 |
20170263563 | Semiconductor Constructions - Some embodiments include a construction having conductive structures spaced from one another by intervening regions. Insulative structures are within the intervening regions. The insulative structures include dielectric spacers and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. The dielectric capping material is between the dielectric spacers and not over upper surfaces of the dielectric spacers. Some embodiments include a construction having a first conductive structure with an upper surface, and having a plurality of second conductive structures electrically coupled with the upper surface of the first conductive structure and spaced from one another by intervening regions. Air gap/spacer insulative structures are within the intervening regions. The air gap/spacer insulative structures have dielectric spacers along sidewalls of the second conductive structures and air gaps between the dielectric spacers. Dielectric capping material is over the air gaps. | 2017-09-14 |
20170263564 | DISPLAY DEVICE HAVING AN ALIGNMENT MARK - A display device according to an exemplary embodiment includes a substrate including a display area and a non-display area. An alignment mark is positioned in the non-display area. A protective layer is positioned around the alignment mark in the non-display area and separated from the alignment mark in a direction parallel to an upper surface of the substrate. A supporting member is positioned between the alignment mark and the protective layer. | 2017-09-14 |
20170263565 | INTEGRATED CIRCUIT (IC) PACKAGE WITH A GROUNDED ELECTRICALLY CONDUCTIVE SHIELD LAYER AND ASSOCIATED METHODS - An integrated circuit (IC) package includes a substrate and an IC die carried by the substrate. An encapsulated body is over the IC die. At least one grounding wire is within the encapsulated body and has a proximal end coupled to the substrate and a distal end exposed on an outer surface of the encapsulated body. An electrically conductive shield layer is on the outer surface of the encapsulated body and in contact with the exposed distal end of the at least one grounding wire. | 2017-09-14 |
20170263566 | METHOD FOR MAKING A SHIELDED INTEGRATED CIRCUIT (IC) PACKAGE WITH AN ELECTRICALLY CONDUCTIVE POLYMER LAYER - A method for making shielded integrated circuit (IC) packages includes providing spaced apart IC dies carried by a substrate and covered by a common encapsulating material, and cutting through the common encapsulating material between adjacent IC dies to define spaced apart IC packages carried by the substrate. An electrically conductive layer is positioned over the spaced apart IC packages and fills spaces between adjacent IC packages. The method further includes cutting through the electrically conductive layer between adjacent IC packages and through the substrate to form the shielded IC packages. | 2017-09-14 |
20170263567 | SUBSTRATE HAVING POWER DELIVERY NETWORK FOR REDUCING ELECTROMAGNETIC INTERFERENCE AND DEVICES INCLUDING THE SUBSTRATE - A semiconductor package includes an integrated circuit mounted on a substrate, a first power line disposed on or above the substrate and configured to transmit an operating voltage to the integrated circuit, and a second power line disposed on or above the substrate and configured to transmit a ground voltage to the integrated circuit, in which each of the first power line and the second power line has a first width, the first power line is spaced apart from the second power line by a first distance, thicknesses of each of the first power line and the second power line are less than or equal to 20 μm, and a ratio of the first width to the first distance is greater than 2.5. | 2017-09-14 |
20170263568 | SEMICONDUCTOR DEVICE HAVING CONDUCTIVE WIRE WITH INCREASED ATTACHMENT ANGLE AND METHOD - A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire. | 2017-09-14 |
20170263569 | System-in-Package Devices With Magnetic Shielding - Electrical components may be packaged using system-in-package configurations or other component packages. Integrated circuit dies and other electrical components may be soldered or otherwise mounted on printed circuits. A layer of encapsulant may be used to encapsulate the integrated circuits. A shielding layer may be formed on the encapsulant layer to shield the integrate circuits. The shielding layer may include a sputtered metal seed layer and an electroplated layer of magnetic material. The electroplated layer may be a magnetic material that has a high permeability such as permalloy or mu metal to provide magnetic shielding for the integrated circuits. Integrated circuits may be mounted on one or both sides of the printed circuit. A temporary carrier and sealant may be used to hold the encapsulated integrated circuits during electroplating. | 2017-09-14 |
20170263570 | SEMICONDUCTOR PACKAGE ASSEMBLY - The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate having a first pad and a second pad thereon. A logic die is mounted on the substrate. The logic die includes a first logic die pad coupled to the first pad. A memory die is mounted on the substrate. The memory die includes a first memory die pad. A first redistribution layer (RDL) trace has a first terminal and a second terminal. The first terminal is coupled to the first pad through the first memory die pad. The second terminal is coupled to the second pad rather than the first pad. | 2017-09-14 |
20170263571 | ELECTRONIC COMPONENT BUILT-IN SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - An electronic component built-in substrate includes an insulating substrate having a through hole and an inner wall surrounding the through hole, an electronic component accommodated in the through hole of the substrate, a sealing member filling the through hole such that the sealing member is covering the electronic component in the through hole of the substrate and exposing a terminal of the electronic component on a first side of the substrate, and a shield layer structure including a first metal film and a second metal film formed such that the first metal film is formed on the inner wall of the substrate and surrounding the through hole of the substrate and that the second metal film is formed on a second side of the substrate on the opposite side with respect to the first side and covering an opening of the through hole on the second side of the substrate. | 2017-09-14 |
20170263572 | EMI/RFI SHIELDING FOR SEMICONDUCTOR DEVICE PACKAGES - An encapsulated semiconductor device package with an overlying conductive EMI or RFI shield in contact with an end of a grounded conductive component at a lateral side of the package, and methods of making the semiconductor device package. | 2017-09-14 |
20170263573 | FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME - A fan-out semiconductor package includes a redistribution layer, an interconnection member, a semiconductor chip, and a protective layer. The interconnection member has a through hole disposed on the redistribution layer. The semiconductor chip is disposed on the redistribution layer exposed within the through hole. The protective layer is formed between the redistribution layer and the interconnection member, and coupled to the interconnection member to protect the interconnection member. | 2017-09-14 |
20170263574 | SEMICONDUCTOR CHIP WITH ANTI-REVERSE ENGINEERING FUNCTION - A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent. | 2017-09-14 |
20170263575 | FDSOI WITH ON-CHIP PHYSICALLY UNCLONABLE FUNCTION - An integrated circuit includes an array of devices including a physically unclonable function (PUF) for chip authentication. A logic pattern is stored in the devices. The logic pattern is determined in accordance with processing variations during manufacture of the array. The logic pattern is represented with a first state for one or more devices with contact shorts and a second state with one or more devices without contact shorts. | 2017-09-14 |
20170263576 | SIGNAL ISOLATION STRUCTURES FOR EM COMMUNICATION - Methods, systems, and apparatus for EM isolation structures. One of the apparatus includes a communication module, the communication module including: a printed circuit board; a plurality of integrated circuit packages, each integrated circuit package including at least one transmitter, receiver, or transceiver; and one or more metallic blocking structures configured to at least partially encircle a corresponding one of the plurality of integrated circuit packages, wherein each metallic blocking structure is configured to reduce signal leakage from the corresponding integrated circuit package. | 2017-09-14 |
20170263577 | SEMICONDUCTOR DEVICE - A semiconductor device is provided with: a semiconductor integrated circuit having a bump mounting surface; and a thin-film capacitor portion connected to the bump mounting surface via a bump. The semiconductor integrated circuit includes a first power supply pad, and a second power supply pad. The thin-film capacitor portion includes a first electrode layer connected to the first power supply pad, a second electrode layer connected to the second power supply pad, and a dielectric layer formed between the first electrode layer and the second electrode layer. The semiconductor device is provided with an electric power supply path configured to supply electric power to the semiconductor integrated circuit, and a thin plate-shaped metal resistor portion provided in the electric power supply path and made from a metal based high-resistance material having a volume resistivity higher than a volume resistivity of the first electrode layer and the second electrode layer. | 2017-09-14 |
20170263578 | ELECTRONIC DEVICE AND ELECTRONIC EQUIPMENT - An electronic device includes a first electronic component including a first signal line and a first ground conductor surface, a second electronic component that is placed above the first electronic component and includes a second signal line and a second ground conductor surface opposed to the first ground conductor surface, a waveguide including the first ground conductor surface, the second ground conductor surface, and a pair of first ground conductor walls that are opposed to each other and are placed between the first ground conductor surface and the second ground conductor surface, a first transducing part that transduces a signal between the first signal line and the waveguide, and a second transducing part that transduces a signal between the second signal line and the waveguide. | 2017-09-14 |
20170263579 | PACKAGE SUBSTRATE WITH DOUBLE SIDED FINE LINE RDL - A package substrate has a sandwiched redistribution layers is disclosed. A middle redistribution layer functions as a core redistribution layer sandwiched by a top redistribution layer and a bottom redistribution layer. A top surface of the top redistribution layer is made adaptive for at least one chip to mount, and a bottom surface of the bottom redistribution layer is made adaptive for at least one chip to mount. A line width of each circuit of the middle redistribution layer is wider than a circuit of either the top redistribution layer or the bottom redistribution layer. | 2017-09-14 |
20170263580 | HIGH VOLTAGE TOLERANT BONDING PAD STRUCTURE FOR TRENCH-BASED SEMICONDUCTOR DEVICES - Apparatus and associated methods relate to a bonding pad structure for a trench-based semiconductor device. The bonding pad structure reduces a peak magnitude of the electric field between a metal bonding pad and the underlying semiconductor. The bonding pad structure includes a plurality of trenches vertically extending from a top surface of a semiconductor. Each of the plurality of trenches has dielectric sidewalls and a dielectric bottom, the dielectric sidewalls and dielectric bottom electrically isolating a conductive core within each of the trenches from a region of semiconductor outside of and adjacent to each of the plurality of trenches. The bonding pad structure includes a metal bonding pad disposed above the plurality of trenches, the metal bonding pad electrically isolated from the region of semiconductor outside of the trenches. The conductive core can be biased to reduce the magnitude of the field between adjacent trenches. | 2017-09-14 |
20170263581 | ELECTRONIC DEVICE, PART MOUNTING BOARD, AND ELECTRONIC APPARATUS - [Object] To provide an electronic device, a part mounting board, and an electronic apparatus that are capable of preventing warpage of a board from occurring. [Solving Means] An electronic device according to an embodiment of the present technology includes a first circuit board and a second circuit board. The first circuit board includes a first main surface, a second main surface, and a plurality of external terminals. The plurality of external terminals include a first terminal group located at an outermost periphery of the first main surface, and are arranged on the first main surface in a matrix pattern. The second circuit board includes a terminal surface facing the second main surface, and a plurality of connection terminals. The plurality of connection terminals include a second terminal group that is arranged on the terminal surface and faces at least a part of the first terminal group, and are electrically connected to the second main surface. | 2017-09-14 |
20170263582 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes a wiring substrate, a first semiconductor element, a second semiconductor element, a bump, a bonding portion, and a resin portion. The second semiconductor element is between the wiring substrate and the first semiconductor element. The bump is between the first and second semiconductor elements and electrically connects the first and second semiconductor elements. The bonding portion is between the first and second semiconductor elements, bonds the first semiconductor element to the second semiconductor element, and has a first elastic modulus. The resin portion has a second elastic modulus higher than the first elastic modulus. The resin portion is between the first and second semiconductor elements. The first semiconductor element is between a second portion of the resin portion and the wiring substrate. A third portion of the resin portion is overlapped with the first and second semiconductor elements. | 2017-09-14 |
20170263583 | SEMICONDUCTOR DEVICE HAVING CONDUCTIVE BUMPS OF VARYING HEIGHTS - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate including a plurality of conductive traces and a recess filled with a conductive material electrically coupled to at least one of the plurality of conductive traces. The semiconductor structure also includes semiconductor chip. The semiconductor chip includes a plurality of conductive pads correspondingly electrically connected with the plurality of conductive traces through a plurality of conductive bumps. A height of each of the plurality of conductive bumps is determined by a minimum distance between the plurality of conductive pads and the corresponding conductive traces thereof. | 2017-09-14 |
20170263584 | COLLET - A collet for attachment to distal portion ( | 2017-09-14 |
20170263585 | METHOD FOR MANUFACTURING ELECTRONIC COMPONENT AND MANUFACTURING APPARATUS OF ELECTRONIC COMPONENT - A method for manufacturing an electronic component includes positioning a first surface of a first component facing a second surface of a second component in a first state. The first surface has a first pad having a first center. The second surface has a second pad having a second center. At least one of the first or second pads includes a metal member. The method includes melting the metal member and moving the first and second components until the melted metal member contacts both pads, moving at least one of the first or second components in a direction along the first surface, and solidifying the metal member in a second state. A first distance in a direction along the first surface between the first and second centers in the first state is longer than a second distance in the direction between the first and second centers in the second state. | 2017-09-14 |
20170263586 | METHODS AND APPARATUSES FOR HIGH TEMPERATURE BONDING AND BONDED SUBSTRATES HAVING VARIABLE POROSITY DISTRIBUTION FORMED THEREFROM - Methods and systems of bonding substrates include disposing a low melting point material and one or more high melting point materials having a higher melting temperature than a melting temperature of the low melting point material between a first substrate and a second substrate to form a substrate assembly including a contacting surface comprising first and second areas; applying a first force at the first area; and applying heat to form a bond layer between the first and second substrates. A first formed porosity of the bond layer is aligned with the first area of the contacting surface. A second formed porosity of the bond layer is aligned with the second area of the contacting surface to which the first force was not applied, and the first formed porosity is different from the second formed porosity. | 2017-09-14 |
20170263587 | SEMICONDUCTOR DEVICE - Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH. | 2017-09-14 |
20170263588 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor device is disclosed. The semiconductor device includes: a first die including a signal pad region and a power pad region; a redistribution layer (RDL) over the first die; a plurality of first connectors over the RDL and at a side of the RDL opposite to the first die; a plurality of second connectors over the RDL and at the side opposite to the first die; a second die including a signal pad region and a power pad region, wherein the second die is face-to-face and electrically connected to the first die through the first connectors and the RDL, wherein a center of the second die is laterally shifted with respect to a center of the first die so as to correspond the signal pad region of the first die to the signal pad region of the second die. An associated method for fabricating the same is also disclosed. | 2017-09-14 |
20170263589 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device package includes a package substrate, a first electronic device, a second electronic device and a first molding layer. The package substrate includes a first surface, a second surface opposite to the first surface, and an edge. The first electronic device is positioned over and electrically connected to the package substrate through the first surface. The second electronic device is positioned over and electrically connected to the first electronic device. The first molding layer is positioned over the package substrate, and the first molding layer encapsulates a portion of the first surface and the edge of the package substrate. | 2017-09-14 |
20170263590 | SEMICONDUCTOR DEVICE COMPRISING PN JUNCTION DIODE AND SCHOTTKY BARRIER DIODE - A semiconductor device includes a MOSFET including a PN junction diode. A unipolar device is connected in parallel to the MOSFET and has two terminals. A first wire connects the PN junction diode to one of the two terminals of the unipolar device. A second wire connects the one of the two terminals of the unipolar device to an output line, so that the output line is connected to the MOSFET and the unipolar device via the first wire and the second wire. In one embodiment the connection of the first wire to the diode is with its anode, and in another the connection is with the cathode. | 2017-09-14 |
20170263591 | LIGHT-EMITTING APPARATUS AND ILLUMINATION APPARATUS - A light-emitting apparatus is provided. The light-emitting apparatus includes a first and second light-emitting elements disposed on a substrate. A sealing layer is above the first and second light-emitting elements for sealing the first and second light-emitting elements. A first phosphor layer is above a first portion of the sealing layer. The first phosphor layer includes at least one first phosphor. A second phosphor layer is above a second portion of the sealing layer. The second phosphor layer includes at least one second phosphor. The first phosphor layer is configured to emit light, which is emitted as a result of emission by the first light-emitting element, having a first color. The second phosphor layer is configured to emit light, which is emitted as a result of emission by the second light-emitting element, having a second color different from the first color. | 2017-09-14 |
20170263592 | PC-LED MODULE WITH ENHANCED WHITE RENDERING AND CONVERSION EFFICIENCY - The invention provides a lighting device (100) comprising: a first solid state light source ( | 2017-09-14 |
20170263593 | TRANSFERRING METHOD, MANUFACTURING METHOD, DEVICE AND ELECTRONIC APPARATUS OF MICRO-LED - The present invention discloses a transferring method, a manufacturing method, a device and an electronic apparatus of micro-LED. The method for transferring micro-LED comprises: forming a micro-LED on a laser-transparent original substrate; bringing the micro-LED into contact with a pad preset on a receiving substrate; and irradiating the original substrate with laser from the original substrate side to lift-off the micro-LED from the original substrate. | 2017-09-14 |
20170263594 | LIGHT-MIXING MULTICHIP PACKAGE STRUCTURE - A light-mixing multichip package structure includes a circuit substrate, a first light-emitting module, a first package body, a second light-emitting module and a second package body. The first light-emitting module includes a plurality of first light-emitting elements disposed on the circuit substrate and electrically connected to the circuit substrate. The first package body is disposed on the circuit substrate to enclose the first light-emitting elements. The second light-emitting module includes a plurality of second light-emitting elements disposed on the circuit substrate and electrically connected to the circuit substrate, and the first light-emitting module and the first package body are surrounded by the second light-emitting elements. The second package body is disposed on the circuit substrate to enclose the first light-emitting module, the second light-emitting module and the first package body. | 2017-09-14 |
20170263595 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, at first, a compound semiconductor layer is bonded to a position straddling a plurality of chip formation regions arranged on a substrate. One of the chip formation regions has a first size, and the compound semiconductor layer has a second size smaller than the first size. Thereafter, the compound semiconductor layer is processed to provide compound semiconductor elements on the chip formation regions. Then, the substrate is divided to correspond to the chip formation regions. | 2017-09-14 |
20170263596 | EQUIPMENT FOR MANUFACTURING SEMICONDUCTOR DEVICES AND METHOD FOR USE OF SAME FOR MANUFACTURING SEMICONDUCTOR PACKAGE COMPONENTS - Provided are an apparatus for manufacturing a semiconductor device and a method of manufacturing a semiconductor package using the same. The manufacturing apparatus may include a base with a plurality of through holes and weight blocks respectively bound by the through holes. | 2017-09-14 |
20170263597 | NOVEL DUMMY GATE TECHNOLOGY TO AVOID SHORTING CIRCUIT - Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell. | 2017-09-14 |
20170263598 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first bidirectional diode of a ring shape surrounding a central region and including a first connection section and a second connection section which is provided to the inner side of the ring shape from the first connection section, a semiconductor element in the central region including a first semiconductor element electrode, a second semiconductor element electrode, and a control electrode, the first semiconductor element electrode electrically connected to the first connection section and the second semiconductor element electrode electrically connected to the control electrode, a first resistor including a first resistor electrode and a second resistor electrode, the first resistor electrode electrically connected to the second connection section and the control electrode, a second bidirectional diode electrically connected to the second resistor electrode and to the second semiconductor element electrode, and a second resistor element electrically connected to the second resistor electrode. | 2017-09-14 |
20170263599 | ELECTROSTATIC DISCHARGE PROTECTION - A bipolar junction transistor is configured to provide electrostatic discharge (ESD) protection for an integrated circuit. The bipolar junction transistor includes a substrate configured to function as a gate for the bipolar junction transistor. At least one drain finger extends in a first direction on a first surface of the substrate and is configured to function as a collector for the bipolar junction transistor. At least one source finger extends in the first direction on the first surface of the substrate and is configured to function as an emitter for the bipolar junction transistor. The at least one source finger includes a pickup region that is configured to set a substrate potential. | 2017-09-14 |
20170263600 | OLED LIGHTING DEVICE WITH SHORT TOLERANT STRUCTURE - An OLED panel having a plurality of OLED circuit elements is provided. Each OLED circuit element may include a fuse or other component that can be ablated or otherwise opened to render the component essentially non-conductive. Each OLED circuit element may comprise a pixel that may include a first electrode, a second electrode, and an organic electroluminescent (EL) material disposed between the first and the second electrodes. Each of the OLED circuit elements may not be electrically connected in series with any other of the OLED circuit elements. | 2017-09-14 |
20170263601 | ELECTROSTATIC DISCHARGE DEVICES AND METHODS OF MANUFACTURE - Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material. | 2017-09-14 |
20170263602 | FIN-TYPE RESISTOR - A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a fin extending away from a substrate, a plurality of epitaxially grown regions disposed along a top surface of the fin, and at least two contacts that provide electrical contact to the fin. The plurality of epitaxially grown regions are arranged to alternate with regions having no epitaxial material grown on the top surface of the fin. A resistance exists between the two contacts that is at least partially based on the arrangement of the plurality of epitaxially grown regions. | 2017-09-14 |
20170263603 | SEMICONDUCTOR DEVICE - The re-combination center introduction region has re-combination centers introduced therein so that a density of the re-combination centers in the re-combination center introduction region is higher than a density of re-combination centers in a periphery of the re-combination center introduction region. The re-combination center introduction region continuously extends from the diode region to the peripheral region along a longitudinal direction of the diode region. | 2017-09-14 |
20170263604 | ENLARGING SPACER THICKNESS BY FORMING A DIELECTRIC LAYER OVER A RECESSED INTERLAYER DIELECTRIC - The method may include steps of receiving a device that includes a source/drain, a gate, a gate spacer formed on a sidewall of the gate, and a dielectric component formed over the source/drain, forming a recess in a top surface of the dielectric component; forming a dielectric layer over the top surface of the dielectric component and over the recess, such that a portion of the dielectric layer assumes a recessed shape; and etching a contact hole through the dielectric layer and the dielectric component, the contact hole exposing the source/drain. | 2017-09-14 |
20170263605 | SEMICONDUCTOR DEVICE - Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop. | 2017-09-14 |
20170263606 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode. | 2017-09-14 |
20170263607 | METHOD FOR FABRICATING A DEVICE WITH A TENSILE-STRAINED NMOS TRANSISTOR AND A UNIAXIAL COMPRESSION STRAINED PMOS TRANSISTOR - Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphisation recrystallisation then germanium condensation. | 2017-09-14 |
20170263608 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses. | 2017-09-14 |
20170263609 | SEMICONDUCTOR DEVICE - To provide a semiconductor device with excellent charge retention characteristics, an OS transistor is used as a transistor whose gate is connected to a node for retaining charge. Charge is stored in a first capacitor, and data at the node for retaining charge is read based on whether the stored charge is transferred to a second capacitor. Since a Si transistor, in which leakage current through a gate insulating film occurs, is not used as a transistor connected to the node for retaining charge, charge retention characteristics of the node are improved. In addition, the semiconductor device operates in data reading without requiring transistor performance equivalent to that of a Si transistor. | 2017-09-14 |
20170263610 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a memory structure and a capacitor structure including at least one array of capacitors. The memory structure is disposed in a first region of the device. The capacitor structure is disposed in a second region of the device. The capacitor structure may include a first capacitor array, a second capacitor array, a third capacitor array and a first landing pad. The first landing pad is disposed between the substrate and lower electrodes of capacitors of the first and second capacitor arrays, and contacts the lower electrodes so as to electrically connect the first capacitor array and the second capacitor array. Upper electrodes of capacitors of the second and third capacitor arrays are integral such that the second capacitor array and the third capacitor array are electrically connected to each other. | 2017-09-14 |
20170263611 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film on the first film. The method further includes simultaneously flowing a first gas with a second gas containing a metal element to form a first opening in the second film and forming a third film containing the metal element on a side surface of the first opening. The method further includes forming a second opening in the first film below the first opening using the second film as a mask. | 2017-09-14 |
20170263612 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor memory device includes a plurality of first electrode layers stacked in a first direction; a semiconductor layer extending in the first direction in the plurality of first electrode layers; a first insulating layer extending in the first direction along the semiconductor layer between the semiconductor layer and each of the plurality of first electrode layers; a second insulating layer covering the periphery of the plurality of first electrode layers; a resistive body provided on the second insulating layer; and a third insulating layer provided between the resistive body and the second insulating layer, the third insulating layer including the same material as the material of the first insulating layer. | 2017-09-14 |
20170263613 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a substrate and a semiconductor layer. The device further includes a first electrode layer that is provided on a side surface of the semiconductor layer with a first insulating film interposed therebetween. The device further includes a charge storage layer provided on a side surface of the first electrode layer with the second insulating film interposed therebetween. | 2017-09-14 |
20170263614 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device according to an embodiment, includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film. | 2017-09-14 |
20170263615 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment, includes a first semiconductor member, a second semiconductor member, an insulating member, a plurality of electrode films, a first electrode, and a second electrode. The first semiconductor member and the second semiconductor member are separated in a first direction and extending in a second direction. The second direction crosses the first direction. The insulating member is provided between the first semiconductor member and the second semiconductor member. The plurality of electrode films are arranged to be separated from each other along the second direction. Each of the electrode films surrounds the first semiconductor member, the second semiconductor member, and the insulating member when viewed from the second direction. The first electrode is provided between the first semiconductor member and the electrode film. The second electrode is provided between the second semiconductor member and the electrode film. | 2017-09-14 |
20170263616 | EMBEDDED NONVOLATILE MEMORY AND FORMING METHOD THEREOF - A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process. | 2017-09-14 |
20170263617 | LOW COST HIGH PERFORMANCE EEPROM DEVICE - Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second lower sub-gates of first and second transistors are formed in the cell area. A common upper sub-gate of the first and second transistors is formed. The common upper sub-gate and first and second lower sub-gates are separated by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates. | 2017-09-14 |
20170263618 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body. | 2017-09-14 |
20170263619 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor memory device includes a first structural body, a second structural body and interconnections. The first and the second structural bodies are separated in a first direction and extend in a second direction. The interconnections are provided between the first structural body and the second structural body, extend in the second direction, and are separated from each other along a third direction. The first and the second structural bodies each includes an insulating member, a column-shaped body and an insulating film. The insulating member and the column-shaped body are disposed in an alternating manner along the second direction and extend in the third direction. The insulating members of the first and second structural bodies make contact with the interconnections. | 2017-09-14 |
20170263620 | MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - There are provided a memory device and a manufacturing method thereof. A method of manufacturing a memory device may include forming, on a substrate, a conductive layer, a sacrificial layer, and a stack structure. The method may include forming a plurality of vertical holes by etching a portion of the stack structure. The method may include forming a memory layer and a channel layer along internal surfaces of the vertical holes. The method may include forming a slit trench exposing a portion of the sacrificial layer therethrough by etching a portion of the stack structure between the vertical holes. The method may include exposing a portion of the channel layer and the first conductive layer through a lower portion of the stack structure by removing portions of the sacrificial layer and the memory layer. The method may include forming another conductive layer along surfaces of the exposed portion of the channel layer and the first conductive layer. The method may include forming a slit insulating layer in the slit trench. | 2017-09-14 |
20170263621 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a stacked body includes a plurality of metal layers stacked with an insulator interposed. A semiconductor body extends in a stacking direction through the stacked body. A charge storage portion is provided between the semiconductor body and one of the metal layers. A metal nitride film has a first portion and a second portion. The first portion is provided between the charge storage portion and one of the metal layers. The second portion is thicker than the first portion and is provided between one of the metal layers and the insulator. | 2017-09-14 |