37th week of 2011 patent applcation highlights part 15 |
Patent application number | Title | Published |
20110220908 | Organic light emitting display device - An organic light emitting display device includes a substrate, a plurality of sub-pixels on the substrate, each sub-pixel including a first region configured to emit light and a second region configured to transmit external light, a plurality of thin film transistors disposed in the first region of the each sub-pixel, a plurality of first electrodes disposed in the first region of each sub-pixel and electrically connected to the thin film transistors, a first insulating layer on at least a portion of the first region of each sub-pixel to cover a portion of the first electrode, an organic emission layer on the first electrode, a second insulating layer on at least a portion of the second region of each sub-pixel, the second insulating layer including a plurality of openings therein, and a second electrode covering the organic emission layer, the first insulating layer, and the second insulating layer. | 2011-09-15 |
20110220909 | BACKPLANE STRUCTURES FOR SOLUTION PROCESSED ELECTRONIC DEVICES - There is provided a backplane for an organic electronic device. The backplane has a TFT substrate having a multiplicity of electrode structures thereon. There are spaces around the electrode structures and a layer of inorganic filler in the spaces. The thickness of the layer of inorganic filler is the same as the thickness of the electrode structures. | 2011-09-15 |
20110220910 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, an insulating film, a first interconnection, a second interconnection, a barrier metal layer, a first metal pillar, a second metal pillar, and a resin. The semiconductor layer has a first major surface, a second major surface formed on an opposite side to the first major surface, and a light emitting layer. The first electrode is provided on the second major surface of the semiconductor layer. The second electrode is provided on the second major surface of the semiconductor layer and includes a silver layer. The insulating film is provided on the second major surface side of the semiconductor layer. The barrier metal layer is provided between the second electrode and the insulating film and between the second electrode and the second interconnection to cover the second electrode. | 2011-09-15 |
20110220911 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - According to one embodiment, a semiconductor light-emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a light-emitting layer, a third semiconductor layer and a first electrode. The light-emitting layer is provided between the first and second semiconductor layers. The third semiconductor layer is provided on opposite side of the first semiconductor layer from the light-emitting layer, has a lower impurity concentration than the first semiconductor layer, and includes an opening exposing part of the first semiconductor layer. The first electrode is in contact with the first semiconductor layer through the opening. The third semiconductor layer further includes a rough surface portion which is provided on opposite side from the first semiconductor layer and includes a surface asperity larger than wavelength in the third semiconductor layer of peak wavelength of emission light emitted from the light-emitting layer. | 2011-09-15 |
20110220912 | Semi-insulating Group III Metal Nitride and Method of Manufacture - A large-area, high-purity, low-cost single crystal semi-insulating gallium nitride that is useful as substrates for fabricating GaN devices for electronic and/or optoelectronic applications is provided. The gallium nitride is formed by doping gallium nitride material during ammonothermal growth with a deep acceptor dopant species, e.g., Mn, Fe, Co, Ni, Cu, etc., to compensate donor species in the gallium nitride, and impart semi-insulating character to the gallium nitride. | 2011-09-15 |
20110220913 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device provided with a structure, which prevents withstand voltage deterioration and may be manufactured at a low cost, is provided. The semiconductor device is provided with a semiconductor substrate, a first conductive type semiconductor layer formed of silicon carbide formed on the substrate, an active region formed on a surface of the semiconductor layer, a second conductive type first semiconductor region formed on the surface of the semiconductor layer so as to surround the active region, a second semiconductor region provided on the surface of the semiconductor layer so as to contact the outside of the first semiconductor region to surround the first semiconductor region in which a second conductive type impurity region having impurity concentration and a depth identical to those of the first semiconductor region is formed into a mesh shape, a first electrode provided on the active region, and a second electrode provided on a backside of the semiconductor substrate. | 2011-09-15 |
20110220914 | POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate | 2011-09-15 |
20110220915 | Off-Axis Silicon Carbide Substrates - A method of epitaxial growth of a material on a crystalline substrate includes selecting a substrate having a crystal plane that includes a plurality of terraces with step risers that join adjacent terraces. Each terrace of the plurality or terraces presents a lattice constant that substantially matches a lattice constant of the material, and each step riser presents a step height and offset that is consistent with portions of the material nucleating on adjacent terraces being in substantial crystalline match at the step riser. The method also includes preparing a substrate by exposing the crystal plane; and epitaxially growing the material on the substrate such that the portions of the material nucleating on adjacent terraces merge into a single crystal lattice without defects at the step risers. | 2011-09-15 |
20110220916 | ELECTRONIC CIRCUIT DEVICE - A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET. | 2011-09-15 |
20110220917 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - A semiconductor device of the present invention has a semiconductor element region | 2011-09-15 |
20110220918 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A high-performance semiconductor device capable of suppressing a leak current with little electric field concentration, reducing an invalid region in a PN junction region, securing a sufficient area for a Schottky junction region, and achieving efficient and easy manufacturing, in which, in one surface of a semiconductor substrate ( | 2011-09-15 |
20110220919 | FLUORESCENT SUBSTANCE, PROCESS FOR PRODUCTION OF FLUORESCENT SUBSTANCE, LIGHT-EMITTING DEVICE AND LIGHT-EMITTING MODULE - The embodiment provides a process for production of an oxynitride fluorescent substance. An compound containing In or Ga is adopted in the process as a material thereof. The red fluorescent substance produced by the process can be combined with a semiconductor light-emitting element, so as to be used in a light-emitting device or a light-emitting module. | 2011-09-15 |
20110220920 | METHODS OF FORMING WARM WHITE LIGHT EMITTING DEVICES HAVING HIGH COLOR RENDERING INDEX VALUES AND RELATED LIGHT EMITTING DEVICES - Methods of forming a light emitting device are provided in which a solid state lighting source is heated and a luminescent solution is applied to the heated solid state lighting source to form the light emitting device. The luminescent solution includes a first material that down-converts the radiation emitted by the solid state lighting source to radiation that has a peak wavelength in the green color range and that has a full width half maximum emission bandwidth that extends into the cyan color range, and at least one additional material that down-converts the radiation emitted by the solid state lighting source to radiation having a peak wavelength in another color range. | 2011-09-15 |
20110220921 | Organic light emitting display apparatus - An organic light emitting display apparatus includes a plurality of sub-pixels, each of the sub-pixels having a first electrode, a second electrode facing the first electrode, and an intermediate layer disposed between the first and second electrodes, the intermediate layer having a plurality of layers including an organic emission layer, at least one layer of the plurality of layers in the intermediate layer being commonly shared by two sub-pixels arranged in a first direction and by at least two sub-pixels arranged in a second direction perpendicular to the first direction. | 2011-09-15 |
20110220922 | Organic light emitting display device and method of manufacturing the same - An organic light emitting display device includes a substrate, a plurality of pixels on the substrate having a first region configured to emit light and a second region configured to transmit external light, a plurality of pixel circuit units, a plurality of first electrodes, a first organic layer on the plurality of first electrodes, a second organic layer on the first organic layer, the second organic layer including an emission layer, a third organic layer on the second organic layer, the third organic layer being positioned in the first region and outside a central portion of the second region, and a second electrode having a first portion only on the third organic layer. | 2011-09-15 |
20110220923 | Conductor Structure, Pixel Structure, and Methods of Forming the Same - A method for forming a conductor structure is provided. The method comprises: (1) providing a substrate; (2) forming a patterned dielectric layer with a first opening which exposes a portion of the substrate; forming a patterned organic material layer on the dielectric layer with a second opening which corresponds to the first opening and expose the exposed portion of the substrate; (3) forming a first barrier layer on the organic material layer and the exposed portion of the substrate; (4) forming a metal layer on the first barrier layer; and (5) removing the organic material layer, the first barrier layer thereon and the metal layer thereon. | 2011-09-15 |
20110220924 | DISPLAY APPARATUS - A display apparatus including a self-luminous type light emitting device with which view angle characteristics of luminance are able to be improved is provided. An organic EL device (light emitting sections | 2011-09-15 |
20110220925 | LIGHT EMITTING DIODE WAFER-LEVEL PACKAGE WITH SELF-ALIGNING FEATURES - Several embodiments of light emitting diode packaging configurations including a substrate with a cavity are disclosed herein. A patterned wafer has a plurality of individual LED attachment sites, and an alignment wafer has a plurality of individual cavities. The patterned wafer and the alignment wafer are superimposed with the LED attachment sites corresponding generally to the cavities of the alignment wafer. At least one LED is placed in the cavities using the cavity to align the LED relative to the patterned wafer. The LED is electrically connected to contacts on the patterned wafer, and a phosphor layer is formed in the cavity to cover at least a part of the LED. | 2011-09-15 |
20110220926 | LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM INCLUDING THE SAME - Provided are a light emitting device package and a lighting system including the same. The light emitting device package includes: a body, a plurality of electrode layers, a light emitting device, and a molding member. The body includes a plurality of pits. The electrode layers include first protrusions disposed in the pits, and second protrusions protruding in a direction opposite to the first protrusions. The light emitting device is disposed on at least one of the plurality of electrode layers. The molding member is disposed on the light emitting device. | 2011-09-15 |
20110220927 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package is provided. The light emitting device package may include a main body having a cavity including side surfaces and a bottom, and a first reflective cup and a second reflective cup provided in the bottom of the cavity of the main body and separated from each other. A first light emitting device may be provided in the first reflective cup, and a second light emitting device may be provided in the second reflective cup. | 2011-09-15 |
20110220928 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting element includes a stacked body, a first and second electrode, a support substrate, a protective film and a dielectric film. The stacked body includes a first semiconductor, a second semiconductor layer and a light emitting portion. The first electrode is provided on a first major surface of the stacked body. The second electrode is provided on a second major surface of the stacked body. The support substrate is provided on the second major surface via a bonding metal. The protective film is provided on at least a side surface of the stacked body except the second major surface. The dielectric film is provided between the bonding metal and a region of the second major surface not provided with the second electrode, and between the bonding metal and a surface of the protective film on the second major surface side. | 2011-09-15 |
20110220929 | WARM WHITE LEDS HAVING HIGH COLOR RENDERING INDEX VALUES AND RELATED LUMINOPHORIC MEDIUMS - Light emitting devices include a solid state lighting source and a recipient luminophoric medium for down-converting at least some of the radiation emitted by the solid state lighting source. The recipient luminophoric medium includes a first material that down-converts the radiation emitted by the solid state lighting source to radiation having a peak wavelength in the green color range that has a full width half maximum emission bandwidth that extends into the cyan color range, and at least one additional material that down-converts the radiation emitted by the solid state lighting source to radiation having a peak wavelength in another color range. | 2011-09-15 |
20110220930 | Light-Emitting Devices with Textured Active Layer - A device includes a textured substrate having a trench extending from a top surface of the textured substrate into the textured substrate, wherein the trench comprises a sidewall and a bottom. A light-emitting device (LED) includes an active layer over the textured substrate. The active layer has a first portion parallel to the sidewall of the trench and a second portion parallel to the bottom of the trench. | 2011-09-15 |
20110220931 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes, a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a first interconnection, and a second interconnection. The first semiconductor layer has a first major surface, a second major surface provided on an opposite side to the first major surface, a protrusion selectively provided on the second major surface, and a trench formed from the second major surface to the first major surface. The second semiconductor layer is stacked on the protrusion of the first semiconductor layer and includes a light emitting layer. The first electrode is provided on the second major surface of the first semiconductor layer and a side surface of the trench. The second electrode is provided on a surface of the second semiconductor layer on an opposite side to the first semiconductor layer. | 2011-09-15 |
20110220932 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - According to one embodiment, a semiconductor light-emitting device includes a first semiconductor layer, a second semiconductor layer, a light-emitting layer, a third semiconductor layer and a first electrode. The first semiconductor layer of a first conductivity type has a first major surface provided with a first surface asperity. The second semiconductor layer of a second conductivity type is provided on an opposite side of the first semiconductor layer from the first major surface. The light-emitting layer is provided between the first and second semiconductor layers. The first semiconductor layer is disposed between a third semiconductor layer and the light-emitting layer. The third semiconductor layer has an impurity concentration lower than an impurity concentration of the first semiconductor layer, and includes an opening exposing the first surface asperity. The first electrode is in contact with the first surface asperity through the opening, and reflective to emission light emitted from the light-emitting layer. | 2011-09-15 |
20110220933 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device has a light emitting element, and first and second electrodes. The light emitting element has a nitride-based III-V compound semiconductor on a substrate. The first and second electrodes are disposed on both sides of the light emitting element, respectively. The light emitting element has a light emitting layer, a first conductive type semiconductor layer, and a second conductive type semiconductor layer. The first conductive type semiconductor layer is disposed between the light emitting layer and the first electrode. The second conductive type semiconductor layer is disposed between the light emitting layer and the second electrode. One surface of the first conductive type semiconductor layer contacts the first electrode and is a light extraction surface which is roughly processed so as to have two or more kinds of oblique angles. | 2011-09-15 |
20110220934 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device has a support substrate, a light emitting element, and underfill material. The light emitting element includes a nitride-based group III-V compound semiconductor layer contacted via a bump on the support substrate. The underfill material is disposed between the support substrate and the light emitting element, the underfill material comprising a rib portion disposed outside of an end face of the light emitting element to surround the end surface of the light emitting element. | 2011-09-15 |
20110220935 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device has a light emitting element, a first electrode layer, a second electrode layer, a seed electrode layer and a plated layer. The light emitting element has a nitride-based III-V compound semiconductor on a substrate. The light emitting element having a light extraction surface. The first electrode layer on the light extraction surface. The second electrode layer is provided on a surface opposite to the light extraction surface of the light emitting element. The seed electrode layer is configured to cover the entire surface of the second electrode layer. The plated layer is provided on the seed electrode layer. The light emitting element has a light emitting layer, a first conductive type semiconductor layer, and a second conductive type semiconductor layer. The light emitting element has a forward tapered shape of a width which gradually narrows in order of the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer. | 2011-09-15 |
20110220936 | SEMICONDUCTOR LIGHT-EMITTING DEVICE, LIGHTING INSTRUMENT EMPLOYING THE SAME AND PROCESS FOR PRODUCTION OF THE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device according to the embodiment includes a substrate, a compound semiconductor layer, a metal electrode layer provided with particular openings, a light-extraction layer, and a counter electrode. The light-extraction layer has a thickness of 20 to 120 nm and covers at least partly the metal part of the metal electrode layer; or otherwise the light-extraction layer has a rugged structure and covers at least partly the metal part of the metal electrode layer. The rugged structure has projections so arranged that their summits are positioned at intervals of 100 to 600 nm, and the heights of the summits from the surface of the metal electrode layer are 200 to 700 nm. | 2011-09-15 |
20110220937 | LIGHT EMITTING DEVICE AND LIGTH EMITTING DEVICE PAKAGE - Provided are a light emitting device and a light emitting device package. The light emitting device includes a first electrode, a light emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer on the first electrode, a second electrode on the light emitting structure, and a reflective member on at least lateral surface of the second electrode. | 2011-09-15 |
20110220938 | SUBSTRATE FOR FABRICATING LIGHT EMITTING DEVICE AND METHOD FOR FABRICATING THE LIGHT EMITTING DEVICE - Provided is a substrate for fabricating a light emitting device and a method for fabricating the light emitting device. The method for fabricating the light emitting device may include forming a sacrificial layer having band gap energy less than energy of a laser irradiated on a substrate, forming a growth layer on the sacrificial layer, forming a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer on the growth layer, and irradiating the laser onto the sacrificial layer to pass through the substrate, thereby to lift-off the substrate. | 2011-09-15 |
20110220939 | LIGHT-EMITTING DEVICE - To provide a light-emitting device mounting a light-emitting element having a metal film on the rear side surface, which is excellent in light extraction efficiency since it has high heat dissipating properties and high light reflection efficiency, and which can suppress the reduction of light extraction efficiency due to the deterioration with time. | 2011-09-15 |
20110220940 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND LIGHTING SYSTEM - Provided are a light emitting device, a light emitting device package, and a lighting system. The light emitting device may include a reflective metal support including at least two pairs of first and second reflective metal layers, a light emitting structure layer including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor and the second conductive type semiconductor layer on the reflective metal support, and an electrode on the light emitting structure layer. The reflective metal support includes at least one of Al, Ag, an APC(Ag—Pd—Cu) alloy, and an Au—Ni alloy. | 2011-09-15 |
20110220941 | Light Emitting Device, Method of Manufacturing the Light Emitting Device, Light Emitting Device Package, and Lighting Unit - Provided are a light emitting device, a method for fabricating the light emitting device, a light emitting device package, and a lighting unit. The light emitting device includes a conductive support substrate, a first reflective layer on the conductive support substrate, a second reflective layer in which at least portion thereof is disposed on a side surface of the first reflective layer, a light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer on the first and second reflective layers, and an electrode on the light emitting structure. The second reflective layer schottky-contacts the light emitting structure. | 2011-09-15 |
20110220942 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - Disclosed are a light emitting device and a light emitting device package. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer, an adhesive layer contacting a top surface of the first conductive semiconductor layer, a first electrode contacting a top surface of the first conductive semiconductor and a top surface of the adhesive layer, and a second electrode contacting the second conductive semiconductor layer, wherein the adhesive layer contacting the first electrode is spaced apart from the second electrode. | 2011-09-15 |
20110220943 | Quantum Dot LED Device And Method - An improved solid-state light source ( | 2011-09-15 |
20110220944 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE - Disclosed are a light emitting device and a light emitting device package. The light emitting device includes a first electrode, a light emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer on the first electrode, a nano-tube layer including a plurality of carbon nano tubes on the light emitting structure, and a second electrode on the light emitting structure. | 2011-09-15 |
20110220945 | LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE PACKAGE HAVING THE SAME - Disclosed are a light emitting device and a light emitting device package having the same. The light emitting device includes a first semiconductor layer doped with N type dopants, a first active layer on the first semiconductor layer, a second semiconductor layer doped with P type dopants on the first active layer, a second active layer on the second semiconductor layer, and a third semiconductor layer doped with N type dopants on the second active layer. A thickness of the second semiconductor layer is in a range of about 2000 Åto about 4000 Å, and doping concentration of the P type dopants doped in the second semiconductor layer is in a range of about 10 | 2011-09-15 |
20110220946 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND LIGHTING SYSTEM - Provided is a light emitting device. The light emitting device includes a first conductive type semiconductor layer, an active layer on the first conductive type semiconductor layer, a second conductive type semiconductor layer on the active layer, an undoped semiconductor layer disposed on the second conductive type semiconductor layer and comprising a plurality of first holes, and a third conductive type semiconductor layer disposed on the undoped semiconductor layer and comprising a plurality of second holes. | 2011-09-15 |
20110220947 | LIGHT EMITTING DIODE UNIT - A light emitting diode (LED) unit includes a carrier, a plurality of LED dies, a reflecting element and a molding material. A length-width ratio of the carrier is greater than or equal to 5. The LED dies are disposed on the carrier along a longitudinal direction of the carrier. The reflecting element has two reflecting portions disposed on the carrier along the longitudinal direction. The LED dies are disposed between the reflecting portions. The molding material covers the LED dies and contacts with the reflecting element. | 2011-09-15 |
20110220948 | DIODE HAVING HIGH BRIGHTNESS AND METHOD THEREOF - A light emitting diode includes a transparent substrate and a GaN buffer layer on the transparent substrate. An n-GaN layer is formed on the buffer layer. An active layer is formed on the n-GaN layer. A p-GaN layer is formed on the active layer. A p-electrode is formed on the p-GaN layer and an n-electrode is formed on the n-GaN layer. A reflective layer is formed on a second side of the transparent substrate. Also, a cladding layer of AIGaN is between the p-GaN layer and the active layer. | 2011-09-15 |
20110220949 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package is provided. The light emitting device package comprises a package body comprising a first cavity, and a second cavity connected to the first cavity; a first lead electrode, at least a portion of which is disposed within the second cavity; a second lead electrode, at least a portion of which is disposed within the first cavity; a light emitting device disposed within the second cavity; a first wire disposed within the second cavity, the first wire electrically connecting the light emitting device to the first lead electrode; and a second wire electrically connecting the light emitting device to the second lead electrode. | 2011-09-15 |
20110220950 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package is provided. The light emitting device package comprises a package body comprising a first cavity, and a second cavity connected to the first cavity; a first lead electrode, at least a portion of which is disposed within the second cavity; a second lead electrode, at least a portion of which is disposed within the first cavity; a light emitting device disposed within the second cavity; a first wire disposed within the second cavity, the first wire electrically connecting the light emitting device to the first lead electrode; and a second wire electrically connecting the light emitting device to the second lead electrode. | 2011-09-15 |
20110220951 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package is provided. The light emitting device package comprises a package body comprising a first cavity, and a second cavity connected to the first cavity; a first lead electrode, at least a portion of which is disposed within the second cavity; a second lead electrode, at least a portion of which is disposed within the first cavity; a light emitting device disposed within the second cavity; a first wire disposed within the second cavity, the first wire electrically connecting the light emitting device to the first lead electrode; and a second wire electrically connecting the light emitting device to the second lead electrode. | 2011-09-15 |
20110220952 | LIGHT EMITTING DEVICE PACKAGE AND LIGHT UNIT HAVING THE SAME - Discussed is a semiconductor LED package. The semiconductor LED package includes a packet body having a cavity, a semiconductor light emitting device in the cavity of the package body; and a plurality of reflective frames, each of the reflective frames having a bottom frame in the cavity of the package body, and at least two sidewall frames extending from the bottom frame and inclined with respect to the bottom frame, wherein the plurality of reflective frames are electrically separated from each other. | 2011-09-15 |
20110220953 | LED ASSEMBLY - A light emission diode (LED) assembly, comprising a LED die ( | 2011-09-15 |
20110220954 | OPTICAL SEMICONDUCTOR PACKAGE AND OPTICAL SEMICONDUCTOR DEVICE | 2011-09-15 |
20110220955 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device. The light emitting device includes a body, a plurality of electrodes in the body, a light emitting chip installed in the body and electrically connected to the electrodes to generate light, and a thermo electric cooler module electrically connected to the electrodes and formed at a lower portion of the light emitting chip to cool the light emitting chip. | 2011-09-15 |
20110220956 | SILICON LIGHT-EMITTING ELEMENT - A silicon light-emitting element includes a first conductivity type silicon substrate | 2011-09-15 |
20110220957 | SHORTS PREVENTION IN ORGANIC LIGHT-EMITTING DIODES - An organic light emitting diode comprising a first electrode layer, a second electrode layer, a stack of functional layers, including an organic light-emitting layer, sandwiched between said first electrode layer and said second electrode layer, and an passivation layer arranged adjacent to said first electrode layer is disclosed. The passivation layer reacts with the first electrode layer to form an oxide at a reaction temperature that is induced by an evolving short circuit between the first electrode layer and the second electrode layer. The passivation layer is unreactive at temperatures lower than the reaction temperature. | 2011-09-15 |
20110220958 | ILLUMINATION DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a method for easily manufacturing an illumination device in which a surface mount chip-type LED is used, and a wiring board is formed into a truncated conical or another shape. The method includes, in a flexible strip-like wiring board having a partial ring or a linear shape, providing a through-hole T for filling with solder paste S at a wiring end portion L to be connected with a terminal of an LED, temporarily fixing the LED with bond B onto the wiring board held in a plate-like state, filling the through-hole T with the solder paste S from a back surface of the wiring board, rounding the wiring board mounted with the LED into a truncated conical or cylindrical shape, and reflowing the wiring board in the rounded state to solder the LED. | 2011-09-15 |
20110220959 | High-Frequency Bridge Suspended Diode - A high-frequency metal-insulator-metal (MIM) type diode is constructed as a bridge suspended above a substrate to significantly reduce parasitic capacitances affecting the operation frequency of the diode thereby permitting improved high-frequency rectification, demodulation, or the like. | 2011-09-15 |
20110220960 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The present invention improves the performance of a semiconductor device formed with a triac. A thyristor is formed between a back surface electrode and an electrode by p-type semiconductor regions, an n-type substrate region, p-type semiconductor regions and an n-type semiconductor region. A thyristor is formed therebetween by the p-type semiconductor regions, the n-type substrate region, the p-type semiconductor regions and an n-type semiconductor region. The two thyristors are opposite in the direction of currents flowing between the back surface electrode and the electrode. The p-type semiconductor region of a high impurity concentration is formed so as to be internally included in the p-type semiconductor region of a low impurity concentration. The p-type semiconductor region of a low impurity concentration is interposed between the p-type semiconductor region of a high impurity concentration and the n-type substrate region. | 2011-09-15 |
20110220961 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a first control electrode, a first main electrode, a fifth semiconductor region of the first conductivity type, a sixth semiconductor region of the second conductivity type, a second main electrode and a semiconductor element. The semiconductor element is connected between the first main electrode and the third semiconductor region. In addition, the semiconductor element includes a channel using part of the first semiconductor region and a second control electrode configured to control the channel on the one major surface of the first semiconductor region. | 2011-09-15 |
20110220962 | SEMICONDUCTOR DEVICE HAVING INSULATED GATE SEMICONDUCTOR ELEMENT, AND INSULATED GATE BIPOLAR TRANSISTOR - A semiconductor device having an IGBT includes: a substrate; a drift layer and a base layer on the substrate; trenches penetrating the base layer to divide the base layer into base parts; an emitter region in one base part; a gate element in the trenches; an emitter electrode; and a collector electrode. The one base part provides a channel layer, and another base part provides a float layer having no emitter region. The gate element includes a gate electrode next to the channel layer and a dummy gate electrode next to the float layer. The float layer includes a first float layer adjacent to the channel layer and a second float layer apart from the channel layer. The dummy gate electrode and the first float layer are coupled with a first float wiring on the base layer. The dummy gate electrode is isolated from the second float layer. | 2011-09-15 |
20110220963 | METHOD AND APPARATUS OF FORMING BIPOLAR TRANSISTOR DEVICE - The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate. The transistor includes a collector region that is formed in a portion of the substrate. The transistor includes a base region that is surrounded by the collector region. The transistor includes an emitter region that is surrounded by the based region. The transistor includes an isolation structure that is disposed adjacent the emitter region. The transistor includes a gate structure that is disposed over a portion of the emitter region and a portion of the isolation structure. | 2011-09-15 |
20110220964 | SEMICONDUCTOR DEVICE HAVING FIELD EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an epitaxial pattern that fills a depression region formed at a semiconductor substrate of one side of a gate pattern. The gate pattern is disposed on a body located at one side of the depression region. The sidewall of the depression region adjacent to the body includes inner surfaces of tapered recesses that taper toward the body, or has an inner surface of a taper recess and a vertical lower sidewall. | 2011-09-15 |
20110220965 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a compound semiconductor device, includes: forming a compound semiconductor lamination structure over a substrate; forming a metal film over the compound semiconductor lamination structure; forming a source electrode and a drain electrode over the metal film; forming one of a metal oxide film and a metal nitride film by one of oxidizing and nitriding a part of the metal film; and forming a gate electrode over the metal oxide film or the metal nitride film. | 2011-09-15 |
20110220966 | ROBUST TRANSISTORS WITH FLUORINE TREATMENT - A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabricating a semiconductor device comprises providing a substrate and growing epitaxial layers on the substrate. Negative ions are introduced into the epitaxial layers to form a negative ion region to counter operating electric (E) fields in the semiconductor device. Contacts can be deposited on the epitaxial layers, either before or after formation of the negative ion region. | 2011-09-15 |
20110220967 | PROCESS FOR FORMING LOW DEFECT DENSITY HETEROJUNCTIONS - A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound. | 2011-09-15 |
20110220968 | DEVICE - A device includes a semiconductor substrate, a first local bit line formed in the semiconductor substrate and elongated in a first direction, a first insulating layer on the semiconductor substrate, a first global bit line formed on the first insulating layer, a first path formed in the first insulating layer to couple a first end of the first local bit line with the first global bit line, and a second path formed in the first insulating layer to couple a second end of the first local bit line with the first global bit line. | 2011-09-15 |
20110220969 | SOLID STATE IMAGING DEVICE - Each pixel of a solid state imaging device comprises: a first semiconductor layer; a second semiconductor layer; a third semiconductor layer and fourth semiconductor layer formed on the lateral side of the upper region of the second layer not to be in contact with the top surface of the second semiconductor layer; a gate conductor layer formed on the lower side of the second semiconductor layer; a conductor electrode formed on the side of the fourth semiconductor layer via an insulating film; and a fifth semiconductor layer formed on the top surface of the second semiconductor layer, wherein at least the third semiconductor layer, upper region of the second semiconductor layer, fourth semiconductor layer, and fifth semiconductor layer are formed in the shape of an island. A specific voltage is applied to the conductor electrode to accumulate holes in the surface region of the fourth semiconductor layer. | 2011-09-15 |
20110220970 | SOLID STATE IMAGING DEVICE - In one embodiment, a semiconductor substrate has first and second principal surfaces opposite to each other, and has a penetration hole extending from the first principal surface to the second principal surface. An imaging element portion is formed on the first principal surface side. A first insulating film is formed on the first principal surface side. An interconnection electrode is formed in the first insulating film and connected to the imaging element portion. A second insulating film is provided to cover a surface of the penetration hole and the second principal surface except at least a portion facing the interconnection electrode. The second insulating film contains particles and is configured to intercept an infrared ray and to transmit a visible light. A conductor film contacts the interconnection electrode and is formed on the second insulating film. | 2011-09-15 |
20110220971 | PHOTOSENSITIVE IMAGING DEVICES AND ASSOCIATED METHODS - Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction. | 2011-09-15 |
20110220972 | SOLID-STATE IMAGE PICKUP ELEMENT, SOLID-STATE IMAGE PICKUP DEVICE AND PRODUCTION METHOD THEREFOR - It is intended to provide a solid-state image pickup element capable of reducing an area of a read channel to increase a ratio of a surface area of a light-receiving section to the overall surface area of one pixel. The solid-state image pickup element comprises a first-conductive type planar semiconductor layer formed on a second-conductive type planar semiconductor layer, a hole portion formed in the first-conductive type planar semiconductor layer to define a hole therein, a first-conductive type high-concentration impurity region formed in a bottom wall of the hole portion, a first-conductive type high-concentration impurity-doped element isolation region formed in a part of a sidewall of the hole portion and connected to the first-conductive type high-concentration impurity region, a second-conductive type photoelectric conversion region formed beneath the first-conductive type high-concentration impurity region and in a part of a lower region of the remaining part of the sidewall of the hole portion, and adapted to undergo a change in charge amount upon receiving light, a transfer electrode formed on the sidewall of the hole portion through a gate dielectric film, a second-conductive type CCD channel region formed in a top surface of the first-conductive type planar semiconductor layer and in a part of an upper region of the remaining part of the sidewall of the hole portion, and a read channel formed in a region of the first-conductive type planar semiconductor layer sandwiched between the second-conductive type photoelectric conversion region and the second-conductive type CCD channel region. | 2011-09-15 |
20110220973 | JUNCTION-FIELD-EFFECT-TRANSISTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A junction-field-effect-transistor (JFET) device includes a substrate of a first-type impurity, a first well region of a second-type impurity in the substrate, a pair of second well regions of the first-type impurity separated from each other in the first well region, a third well region of the first-type impurity between the pair of second well regions, a first diffused region of the second-type impurity between the third well region and one of the second well regions, and a second diffused region of the second-type impurity between the third well region and the other one of the second well regions. | 2011-09-15 |
20110220974 | SEMICONDUCTOR DEVICE - According to an embodiment, the present invention provides a semiconductor device that is easily integrated with other electronic circuits and functions as an oscillator with high frequency accuracy. The semiconductor device includes: a semiconductor substrate; an element region; an element isolation region that surrounds the element region; a field effect transistor including a gate electrode that is formed on the element region, source and drain regions, and a channel region that is interposed between the source region and the drain region; gate, source, and drain terminals that are used to apply a voltage to the gate electrode, the source region, and the drain region, respectively; and an output terminal that is electrically connected to the channel region. When the threshold voltage of the field effect transistor is V | 2011-09-15 |
20110220975 | METHOD OF FORMING A SEMICONDUCTOR DEVICE FEATURING A GATE STRESSOR AND SEMICONDUCTOR DEVICE - A semiconductor device is formed in a semiconductor layer. A gate stack is formed over the semiconductor layer and comprises a first conductive layer and a second layer over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species is implanted into the second layer. Source/drain regions are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack. | 2011-09-15 |
20110220976 | SOLID-STATE IMAGING DEVICE - Certain embodiments provide a solid-state imaging device including: a semiconductor substrate of a first conductivity type having a first face and a second face that is the opposite side from the first face; a plurality of pixels provided on the first face of the semiconductor substrate, each of the pixels including a semiconductor region of a second conductivity type that converts incident light into signal charges, and stores the signal charges; a readout circuit provided on the second face of the semiconductor substrate to read the signal charges stored in the pixels; an ultrafine metal structure placed at intervals on a face on a side of the semiconductor region, the light being incident on the face; and an insulating layer provided between the ultrafine metal structure and the semiconductor region. | 2011-09-15 |
20110220977 | SEMICONDUCTOR DEVICES WITH BURIED BIT LINES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device, comprising: a vertical pillar transistor (VPT) formed on a silicon-on-insulator (SOI) substrate, the VPT including a body that has a lower portion and an upper portion, a source/drain node disposed at an upper end portion of the upper portion of the body and a drain/source node disposed at the lower portion of the body; a buried bit line (BBL) formed continuously on sidewalls and an upper surface of the lower portion, the BBL includes metal sificide; and a word line that partially enclosing the upper portion of the body of the VPT, wherein the BBL extends along a first direction and the word line extends in a second direction substantially perpendicular to the first direction. An offset region is disposed immediately beneath the word line. | 2011-09-15 |
20110220978 | SEMICONDUCTOR DEVICE - In an embodiment, provided is a semiconductor device in which a normally-on type FET; a capacitor having one electrode electrically connected to a gate of the FET and the other electrode electrically connected to an input terminal; and a diode having an anode electrode electrically connected to the gate of the FET and a cathode electrode electrically connected to a source of the FET are formed on the same chip on which the FET is formed. Also, the capacitor may have a structure in which an insulation film such as a dielectric substance is formed on a gate drawn electrode of the FET, and a metallic layer is formed on the insulation layer. | 2011-09-15 |
20110220979 | SEMICONDUCTOR DEVICE AND MULTI-LAYERED WIRING SUBSTRATE - There is provided a semiconductor device in which a wiring inductance of a DC/DC converter formed on a multi-layered wiring substrate can be reduced and the characteristics can be improved. In the semiconductor device, in an input-side capacitor, one capacitor electrode is electrically connected to a power-supply pattern between a control power MOSFET and a synchronous power MOSFET, and the other capacitor electrode is electrically connected to a ground pattern therebetween. The multi-layered wiring substrate includes: a via conductor arranged at a position of the one capacitor electrode for electrically connecting among a plurality of power-supply patterns in a thickness direction; and a via conductor arranged at a position of the other capacitor electrode for electrically connecting among a plurality of ground patterns in a thickness direction. | 2011-09-15 |
20110220980 | MEMORY HAVING BURIED DIGIT LINES AND METHODS OF MAKING THE SAME - A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F | 2011-09-15 |
20110220981 | NON-VOLATILE FINFET MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - Methods for fabricating an electronic device and electronic devices therefrom are provided. A method includes forming one or more masking layers on a semiconducting surface of a substrate and forming a plurality of dielectric isolation features and a plurality of fin-type projections using the masking layer. The method also includes processing the masking layers and the plurality of fin-type projections to provide an inverted T-shaped cross-section for the plurality of fin-type projections that includes a distal extension portion and a proximal base portion. The method further includes forming a plurality of bottom gate layers on the distal extension portion and forming a plurality of control gate layers on the plurality of dielectric isolation features and the plurality of bottom gate layers. | 2011-09-15 |
20110220982 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROCESS OF MANUFACTURING THE SAME - In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film. | 2011-09-15 |
20110220983 | METHOD FOR DELETING DATA FROM NAND TYPE NONVOLATILE MEMORY - To provide a method of releasing charges which have been injected into charge accumulating layers of nonvolatile memory elements without using a substrate terminal such as a p well or an n well, as a method for deleting data from a NAND-type nonvolatile memory. In the method for deleting data from the NAND-type nonvolatile memory, charges stored in a charge accumulating layer of a first nonvolatile memory element are released by applying a first potential to a bit line and a source line, a second potential to a control gate of the first nonvolatile memory element, and a third potential which is different from the second potential to a control gate of a second nonvolatile memory element. | 2011-09-15 |
20110220984 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an aspect of the invention, there is provided a semiconductor device including a plurality of memory cells, comprising a plurality of floating gate electrodes which are formed on a tunnel insulating film formed on a semiconductor substrate and have an upper portion which is narrower in a channel width direction than a lower portion, an interelectrode insulating film formed on the floating gate electrodes, and a control gate electrode which is formed on the interelectrode insulating film formed on the floating gate electrodes and partially buried between the floating gate electrodes opposing each other. | 2011-09-15 |
20110220985 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate. | 2011-09-15 |
20110220986 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device including a substrate, a conductive layer, a charge storage layer, first and second dopant regions and first and second cell dopant regions is provided. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first and second dopant regions having a first conductive type are configured in the substrate under bottoms of the trenches and in an upper portion of the substrate between two adjacent trenches, respectively. The first and second cell dopant regions having a second conductive type are configured in the substrate between lower portions of side surfaces of the trenches and in the substrate adjacent to the bottoms of the second dopant regions, respectively. The first and the second conductive types are different dopant types. | 2011-09-15 |
20110220987 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, an interconnection, and a contact plug. The base includes a substrate and a peripheral circuit formed on a surface of the substrate. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base. The memory film is provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers. The memory film includes a charge storage film. The interconnection is provided below the stacked body. The interconnection electrically connects the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region and the peripheral circuit. The contact plug pierces the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region. | 2011-09-15 |
20110220988 | METHOD FOR MANUFACTURING NAND MEMORY CELLS - A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI in the substrate through the patterned hard mask and removing the patterned hard mask to define a plurality of recesses; forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures. | 2011-09-15 |
20110220989 | Memory Cells, Methods Of Forming Dielectric Materials, And Methods Of Forming Memory Cells - Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material. | 2011-09-15 |
20110220990 | SHIELDED GATE TRENCH MOS WITH IMPROVED SOURCE PICKUP LAYOUT - A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device. | 2011-09-15 |
20110220991 | SEMICONDUCTOR DEVICE - A semiconductor device | 2011-09-15 |
20110220992 | SEMICONDUCTOR DEVICE - In one aspect, a semiconductor device includes a semiconductor substrate; and a transistor element including a parallel structure of a first-conductivity-type drift region and a second-conductivity-type column region, and a second-conductivity-type base region, the transistor element being formed on the semiconductor substrate. An outer peripheral region located outside an element forming region has a parallel structure of a first-conductivity-type drift region and a second-conductivity-type column region, and a second-conductivity-type annular diffusion region which is formed at a side of the base region and which is spaced apart from the base region. An innermost end and a neighboring portion thereof of the annular diffusion region are located on the column region, and an outermost end of the annular diffusion region is located outside an outermost peripheral column region. A field insulating film that covers the annular diffusion region is stacked on the semiconductor layer in the outer peripheral region. | 2011-09-15 |
20110220993 | METHOD FOR FABRICATING SEMICONDUCTOR MEMOERY DEVICE - A method for manufacturing a semiconductor device comprises forming a first spacer layer at sidewalls of one or more gate electrodes, forming a trench by etching an isolation insulating layer exposed between the gate electrodes, forming a second spacer layer on sidewalls of the gate electrodes and an inner surface of the trench and forming an interlayer insulating layer between the gate electrodes. | 2011-09-15 |
20110220994 | Method of Forming a DRAM Array of Devices with Vertically Integrated Recessed Access Device and Digitline - A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate. | 2011-09-15 |
20110220995 | Semiconductor Device Having Multi-Thickness Gate Dielectric - A semiconductor device is provided that, in an embodiment, is in the form of a high voltage MOS (HVMOS) device. The device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. The gate structure includes a gate dielectric which has a first portion with a first thickness and a second portion with a second thickness. The second thickness is greater than the first thickness. A gate electrode is disposed on the first and second portion. In an embodiment, a drift region underlies the second portion of the gate dielectric. A method of fabricating the same is also provided. | 2011-09-15 |
20110220996 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, an element isolation insulating film, a source layer, a drain layer, a gate electrode, a gate insulating film, a first punch-through stopper layer, and a second punch-through stopper layer. The semiconductor substrate is a first conductivity type. The element isolation insulating film divides an upper layer portion of the semiconductor substrate into a plurality of first active regions. The source layer and the drain layer are a second conductivity type and are formed in spaced to each other in an upper portion of each of the first active regions. The gate electrode is provided in a region directly above a channel region on the semiconductor substrate located between the source layer and the drain layer. The gate insulating film is provided between the semiconductor substrate and the gate electrode. The first punch-through stopper layer of the first conductivity type is formed in a region of the first active region directly below the source layer and the second punch-through stopper layer of the first conductivity type is formed in a region of the first active region directly below the drain layer. The first punch-through stopper layer and the second punch-through stopper layer each has an effective impurity concentration higher than the semiconductor substrate. The first punch-through stopper layer and the source layer are separated in the channel region. The second punch-through stopper layer and the drain layer are separated in the channel region. | 2011-09-15 |
20110220997 | LDMOS Device Having Increased Punch-Through Voltage and Method For Making Same - The present invention discloses an LDMOS device having an increased punch-through voltage and a method for making same. The LDMOS device includes: a substrate; a well of a first conductive type formed in the substrate; an isolation region formed in the substrate; a body region of a second conductive type in the well; a source in the body region; a drain in the well; a gate structure on the substrate; and a first conductive type dopant region beneath the body region, for increasing a punch-through voltage. | 2011-09-15 |
20110220998 | Devices Containing Permanent Charge - An edge termination structure includes a final dielectric trench containing permanent charge. The final dielectric trench is surrounded by first conductivity type semiconductor material (doped by lateral outdiffusion from the trenches), which in turn is laterally surrounded by second conductivity type semiconductor material. | 2011-09-15 |
20110220999 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs | 2011-09-15 |
20110221000 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a first gate electrode on a semiconductor substrate in a first transistor region; forming a channel dose region; and forming a first source extension region, wherein the channel dose region is formed by using a first mask as a mask and by ion-implanting a first dopant of the first conductivity type, and the first mask covering a drain side of the first gate electrode and covering a drain region, and the first source extension region is formed by using a second mask and the gate electrode as masks and by ion-implanting a second dopant of a second conductivity type that is a conductivity type opposite to the first conductivity type, the second mask covering the drain side of the first gate electrode and covering the drain region. | 2011-09-15 |
20110221001 | Memory cell structures, memory arrays, memory devices, memory controllers, and memory systems, and methods of manufacturing and operating the same - Example embodiments are directed to memory cell structures, memory arrays, memory devices, memory controllers, and memory systems using bipolar junction transistor (BJT) operation. | 2011-09-15 |
20110221002 | MOS-TYPE ESD PROTECTION DEVICE IN SOI AND MANUFACTURING METHOD THEREOF - The present invention discloses a MOS ESD protection device for SOI technology and a manufacturing method for the device. The MOS ESD protection device comprises: an epitaxial silicon layer grown on top of an SOI substrate; a first side-wall spacer disposed on both sides of the epitaxial silicon layer so as to isolate the ESD protection device from the intrinsic active structures; a source region and a drain region disposed respectively on two sides of the epitaxial silicon layer; a poly silicon gate and a gate dielectric formed on top of the epitaxial silicon layer; and a second side-wall spacer disposed on both sides of the poly silicon gate of . ESD leakage current passes down to the SOI substrate for protection. Because ESD protection device and intrinsic MOS transistor are located in the same plane, this fabrication process can be inserted in the current MOS process flow. | 2011-09-15 |
20110221003 | MOSFETs WITH REDUCED CONTACT RESISTANCE - A method and structure for forming a field effect transistor with reduced contact resistance are provided. The reduced contact resistance is manifested by a reduced metal semiconductor alloy contact resistance and a reduced conductively filled via contact-to-metal semiconductor alloy contact resistance. The reduced contact resistance is achieved in this disclosure by texturing the surface of the transistor's source region and/or the transistor's drain region. Typically, both the source region and the drain region are textured in the present disclosure. The textured source region and/or the textured drain region have an increased area as compared to a conventional transistor that includes a flat source region and/or a flat drain region. A metal semiconductor alloy, e.g., a silicide, is formed on the textured surface of the source region and/or the textured surface of the drain region. A conductively filled via contact is formed atop the metal semiconductor alloy. | 2011-09-15 |
20110221004 | Semiconductor Constructions, And Semiconductor Processing Methods - Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction, and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions. | 2011-09-15 |
20110221005 | Integrated circuit package for semiconductior devices with improved electric resistance and inductance - A semiconductor integrated circuit package having a leadframe ( | 2011-09-15 |
20110221006 | NAND ARRAY SOURCE/DRAIN DOPING SCHEME - An electronic device includes a substrate having isolation features defining active regions coextending over a surface of the substrate. The device also includes coextending line patterns crossing over the active regions, including string and ground selection lines and word lines between the string and ground selection lines. The device further includes first implant regions of a first conductivity type in the active regions between the word lines and having a first carrier concentration. The device further includes second implant regions of the first conductivity type in the active regions between edge ones of the word lines and an adjacent one of the string selection line and the ground selection line. In the device, the second implant region includes a low doping portion abutting the edge word lines and a high doping portion spaced from the edge word line by the low doping portion and having a second carrier concentration greater than the first carrier concentration. | 2011-09-15 |
20110221007 | SEMICONDUCTOR MEMORY DEVICE - In a multipart SRAM memory cell of the present invention, an access transistor of a first port is disposed in a p-type well, and an access transistor of a second port is disposed in a p-type well. The gates of all of transistors disposed in a memory cell extend in the same direction. With the configuration, a semiconductor memory device having a low-power consumption type SRAM memory cell with an increased margin of variations in manufacturing, by which a bit line can be shortened in a multiport SRAM memory cell or an associative memory, can be obtained. | 2011-09-15 |