37th week of 2011 patent applcation highlights part 59 |
Patent application number | Title | Published |
20110225314 | Method for streaming media playback and terminal device - A method for streaming media playback and a terminal device, the method comprising receiving a media data stream by a terminal device via a wireless connection; buffering the received media data stream; playing back the buffered media data stream by the terminal device; and altering the speed of the playback of the buffered media data stream, wherein the altering of the speed of the playback of the buffered media data stream comprises slowing down the speed of the playback of the buffered media data stream a) in response to the wireless connection becoming unavailable to the terminal device, or b) in response to the signal strength of the wireless connection experienced by the terminal device falling below a first predetermined threshold value. | 2011-09-15 |
20110225315 | MULTI-STREAM BIT RATE ADAPTATION - A method for communication includes providing an item of media content for streaming in a plurality of versions having different, respective bit rates. The media content is streamed from a server to a client by transmitting a first version of the item over a network at a first bit rate from the server to the client via a server buffer associated with the server and monitoring a fill level of the server buffer while streaming the media content. The server switches to transmitting a second version of the item at a second bit rate, different from the first bit rate, to the client in response to a change in the fill level of the server buffer. | 2011-09-15 |
20110225316 | METHOD, DEVICE, AND SYSTEM FOR CONTROLLING STREAMING MEDIA PLAY - A method for controlling streaming media play includes: receiving from a terminal a PAUSE message requesting to pause the playing of a current streaming media file; pausing the sending of a media stream of the current streaming media file to the terminal and obtaining a first play time parameter, where the first play time parameter is about the time when the current streaming media file is paused; receiving from the terminal a PLAY message that carries a second play time parameter used to locate a play position of the streaming media file; and comparing the first play time parameter and the second play time parameter, and play, according to the comparison result, another streaming media file in the play list to which the current streaming media file belongs. This facilitates the selection of streaming media files by the user and enhances the user experience. | 2011-09-15 |
20110225317 | Content rate selection for media servers with proxy-feedback-controlled frame transmission - In a method for dynamically setting a content rate of a multimedia session for a client in a network, a proxy server receives a channel condition feedback message from a network controller and determines whether a receiver report message has been received from the client since a most recent previous channel condition feedback message. The channel condition feedback message includes current channel condition information for the network. The proxy server sends one of an extended feedback report message and a short feedback report message to a media server based on the determining step. The short feedback report message includes at least a maximum transmission rate parameter for the multimedia session. The extended feedback report message includes at least information contained in the receiver report message. The extended feedback report message may, in addition, include the maximum transmission rate parameter for the multimedia session. | 2011-09-15 |
20110225318 | Network Scheduling for Energy Efficiency - A network comprising a plurality of network devices is configured to implement scheduling for energy efficiency. In one aspect, a set of network devices interconnected in a line within a network is identified, and a common frame size is established. For each of the network devices of the line, active and inactive periods for that network device are scheduled in a corresponding frame having the common frame size, with the frames in the respective network devices of the line being time shifted relative to one another by designated offsets. For each of one or more of the active periods of each of the network devices of the line, received packets are scheduled for processing in that network device. | 2011-09-15 |
20110225319 | ROUTE OPTIMIZATION METHOD, ROUTE OPTIMIZATION SYSTEM, MOBILE COMMUNICATION DEVICE, MOVEMENT MANAGEMENT DEVICE, PARTNER COMMUNICATION DEVICE AND HOME BASE STATION - Disclosed is a technique to allow a network operator of a mobile node to securely reject an unfavorable address for use in route optimization. According to the technique, when receiving a HoTI message | 2011-09-15 |
20110225320 | Method For Mechanically Generating Content For Messages - A method for inserting content through a service delivery hub includes the steps of designating a set of tags to be made available through an API, providing the API for use by third parties; intercepting a communication from the third party; interrogating the communication for a data tag, substituting content for the data tag and delivering the communication to an intended recipient. The method may further include that the content substituted for the data tag is dependent upon a parameter such as the MSISDN. | 2011-09-15 |
20110225321 | IMAGE PROCESSING DEVICE, DEVICE MANAGEMENT SYSTEM, AND IMAGE PROCESSING METHOD - An image processing device is connected to a device management apparatus via a network and includes device information in accordance with the Common Information Model CIM. In the image processing device, a first transform part transforms, when a query described in a general-purpose language to include a request of data handling of device information with respect to jobs is received, CIM objects, generated from the device information with respect to the jobs, into XML data items. A combining part combines the XML data items into XML data and generates the combined XML data. An extracting part extracts an XML data item associated with the request from the combined XML data. A second transform part transforms the XML data item into a CIM object. The data handling of the CIM object is performed and a result of the data handling is transmitted. | 2011-09-15 |
20110225322 | REAL-TIME MULTI-BLOCK LOSSLESS RECOMPRESSION - Exemplary methods, computer systems, and computer program products for processing a previously compressed data stream in a computer environment are provided. In one embodiment, the computer environment is configured for separating a previously compressed data stream into an input data block including a header input block having a previously compressed header. Sequences of bits are included with the input data block. Compression scheme information is derived from the previously compressed header. The input data block is accessed and recompressed following the header input block in the previously compressed data stream one at a time using block-image synchronization information. Access to the block-image synchronization information is initialized by the compression scheme information to generate an output data block. The block-image synchronization information is used to provide decompression information to facilitate decompression of the results of the output data block. | 2011-09-15 |
20110225323 | SELF-TUNING INPUT OUTPUT DEVICE - A method, system, and computer usable program product for a self-tuning I/O device are provided in the illustrative embodiments. A change is detected in an adapter communicating with the I/O device, the I/O device being a consolidator configured to communicate with the adapter in a data network. A type of the adapter is determined. Values for each parameter in a set of parameters corresponding to the type of the adapter are determined. The values of a first subset of the parameters are applied to the consolidator, applying the values of the first subset causing the consolidator to be configured to operate in a preferred configuration with the adapter. | 2011-09-15 |
20110225324 | APPARATUS AND METHOD FOR STORING CONTEXT INFORMATION ON AN ELECTRONIC DEVICE - An electronic device includes a storage slot for storing context information for a storage device. The electronic device is configured to apply settings related to the context information to the storage device upon detecting connection of the storage device to the electronic device. A method of operating the electronic device may include acquiring context information from the storage device, storing the context information within a storage slot of the electronic device, and applying settings to the storage device. The settings may be related to the context information and may be applied upon detecting a reconnection of the storage device to the electronic device. | 2011-09-15 |
20110225325 | DATA TRANSFER CIRCUIT AND METHOD - In one cycle for transferring data, a controller forming a data transfer circuit stores pointer information P_A for periodic transfer and pointer information P_B for non-periodic transfer read from a memory respectively in first and second storage areas. The controller sequentially transfers, to a communication bus, data D_A for periodic transfer and data D_B for non-periodic transfer read from the memory by referring to the P_A and P_B. If transfer by a data length indicated in the P_B has not been completed upon the transfer of the D_B, the controller updates the data length to a data length of the remaining data, and updates an address indicated in the P_B to an address on the memory of the remaining data. In the next cycle for transferring data, the controller reads the remaining data from the memory by referring to the P_B, and transfers the remaining data to the communication bus. | 2011-09-15 |
20110225326 | Multi-Mode Processing Module and Method of Use - A method of enabling access to resources includes detecting an input to access a resource of a multi-mode processing module coupled to a host processor and a control module. The method can further include detecting an operating mode of the host processor and the control module and an availability of independent peripheral resources of the multi-mode processing module. Additionally, the method can enable the multi-mode processing module in response to the detecting the operating mode and the availability of the independent peripheral resources. | 2011-09-15 |
20110225327 | SYSTEMS AND METHODS FOR CONTROLLING AN ELECTRONIC DEVICE - Systems and methods ( | 2011-09-15 |
20110225328 | METHOD AND APPARATUS FOR ENHANCING UNIVERSAL SERIAL BUS APPLICATIONS - A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host. | 2011-09-15 |
20110225329 | Method for simultaneously switching energy-saving modes of plural computer devices via KVM switc - The present invention is to provide a method for simultaneously switching energy-saving modes of plural computer devices via a KVM switch including a CPU, a plurality of connection ports, a real-time clock (RTC) and a memory unit, wherein the memory unit stores a timetable containing at least one scheduled time and at least one corresponding energy-saving procedure each including a control instruction. The CPU reads the current time of the RTC and, after determining that the timetable contains a scheduled time corresponding to a current time, reads the control instruction in the energy-saving procedure corresponding to the scheduled time. Then, the CPU sends an energy-saving instruction to the computer device connected to each of the connection ports that are specified in the control instruction, thereby switching the energy-saving modes (e.g., a hibernation mode, sleep mode, OFF mode or ON mode) of the specified computer devices simultaneously. | 2011-09-15 |
20110225330 | PORTABLE UNIVERSAL COMMUNICATION DEVICE - Embodiments of the invention provide a portable device comprising at least one processor. The portable device also comprises a memory coupled to the processor comprising data. Further, the portable device comprises a detector configured to detect at least one external device. The at least one external device is configured to connect to the portable device. Further, the portable device comprises an interface to connect to the at least one external device. The interface is configured to transmit or receive one or more control signals excluding the data. Furthermore, the portable device comprises a controller configured to enable controlling of the portable device from the at least one external device; and controlling of the at least one external device from the portable device through the interface. | 2011-09-15 |
20110225331 | GENERIC INTERFACE - A system and process for ensuring the smooth flow of electronic ink is described. Dynamic rendering is given priority over other event handlers. Priority may be the use of one or more queues to order when events occur and may be performing dynamic rendering prior to other steps. | 2011-09-15 |
20110225332 | Data transmission device and control method - The present invention provides a data transmission device with high speed serial transmission interfaces and control method thereof, and includes a control unit, at least one first storage device connected to the control unit and at least one second storage device, at least one switching device, which is used to switch data transmission lines; each of the switching devices being connected to the control unit, the second storage device and a computer. Accordingly, the switching devices enable the storage devices to connect to the computer to implement data transmission, or the switching devices switch connection to form an independently operable data transmission control system to enable implementing data transmission between the storage devices. Moreover, an automatic detection mode and a manual mode can be used to control connection to the computer or enable independent operation of the data transmission device. | 2011-09-15 |
20110225333 | Interconnect Coupled to Master Device Via at Least Two Different Connections - An interconnect coupled to a master device via at least two different connections is disclosed. In a particular embodiment, a system is disclosed that includes a first interconnect and a second interconnect coupled to the first interconnect. The first interconnect is coupled to a first master device via a single connection and the first interconnect is coupled to a second master device via at least two different connections. The second interconnect is coupled to a memory via a memory controller. | 2011-09-15 |
20110225334 | PROCESSOR BUS BRIDGE FOR NETWORK PROCESSORS OR THE LIKE - Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a command from a first bus, the command having an identification field having a value. The command is then entered into a buffer in the bridge unless another command having the same identification field value exists in the buffer. Once the command with the same identification field value is removed from the buffer, the received command is entered into the buffer. Next, the buffered command is transmitted over a second bus. A response to the command is eventually received from the second bus, the response is transmitted over the first bus, and the command is then removed from the buffer. By not entering the received command until a similar command with the same identification value is removed from the buffer, command ordering is enforced even though multiple commands are pending in the buffer. | 2011-09-15 |
20110225335 | USING A DUAL MODE READER WRITER LOCK - A method, system, and computer usable program product for using a dual mode reader writer lock. A contention condition is detected in the use of a lock in a data processing system, the lock being used for managing read and write access to a resource in the data processing system. A determination of the data structure used for implementing the lock is made. If the data structure is a data structure of a reader writer lock (RWL), the data structure is transitioned to a second data structure suitable for implementing the DML. A determination is made whether the DML has been expanded. If the DML is not expanded, the DML is expanded such that the data structure includes an original lock and a set of expanded locks. The original lock and each expanded lock in the set of expanded locks forms an element of the DML. | 2011-09-15 |
20110225336 | IMAGE FORMING APPARATUS AND CONTROL METHOD THEREOF - An image forming apparatus and a control method thereof. The image forming apparatus includes a plurality of image processors which process an image to be formed on a printing medium corresponding to a plurality of colors, a processor which executes an interrupt routine with respect to the plurality of image processors, and a controller which generates an interrupt signal and transmits the interrupt signal to the processor if at least two of the plurality of image processors generate interrupt requests so that the processor executes the interrupt routine. | 2011-09-15 |
20110225337 | TRANSACTION PERFORMANCE MONITORING IN A PROCESSOR BUS BRIDGE - Described embodiments provide a system having a bridge for connecting two different processor buses. A process monitor within the bridge allows for measuring latency of commands issued on a first bus, passing through the bridge, and executed by clients coupled to the second bus. By using identification fields associated with the command, measuring the latency of each command begins with matching the identification field of the command to an integer. As the bridge passes acknowledgements back to the first bus, the monitoring of the command is stopped when an identification field associated with an acknowledgement matches the identification field of the command being monitored. Data collected include the minimum, maximum, total latency, and the number of commands monitored. From this data, the average latency can be easily calculated. | 2011-09-15 |
20110225338 | INTERFACE DEVICE FOR COORDINATING CONTROL OF AN OUTPUT DEVICE BY MULTIPLE CONTROL CONSOLES - A system and method for interfacing multiple inputs and outputs in a control system is provided. A digital input/output system provides a localized interface between multiple operator consoles and at least one output device to coordinate and monitor the operation of the at least one output device. The digital input/output system includes an interface device which re-routes discrete lines to and from the operator consoles and output devices and eliminates conflicting signals sent from the operator consoles to the output devices. | 2011-09-15 |
20110225339 | DATA TRANSMISSION SYSTEM AND A PROGRAMMABLE SPI CONTROLLER - A data transmission system is provided. The data transmission system includes a serial peripheral interface (SPI) and a programmable controller. The SPI is coupled between a first device and at least one second device. The programmable controller controls the SPI to switch between a single port data transmission mode and a multi-port data transmission mode. When there are more than one second device coupled to the SPI, the SPI is switched to the multi-port data transmission mode so as to perform multi-port data transmission between the first device and the second devices. At this time, the first device concurrently transmits data to each of the second devices via a first transmission bus terminal, and concurrently receives data from each of the second devices via a second transmission bus terminal. | 2011-09-15 |
20110225340 | EMULATOR INTERFACE DEVICE AND METHOD THEREOF - An interface device for an emulator is disclosed. The interface device includes a connection unit, a transmission unit, and an interface unit. The connection unit receives data, to be used to emulate a logic, from a host computer, and transmits result data, output from the logic, to the host computer. The transmission unit receives the data from the connection unit and stores (writes) the data in the first area of a register array. If the result data is stored in the second area of the register array, the transmission unit reads the result data and transmits the result data to the connection unit. The interface unit includes at least one register array, outputs a clock, set using the data stored in the first area, to the logic, and stores the result data, output from the logic, in the second area. | 2011-09-15 |
20110225341 | COMMUNICATION APPARATUS, COMMUNICATION SYSTEM AND ADAPTER - A communication apparatus for carrying out communications to and from an external apparatus that includes a first interconnecting unit and a first non-transparent port and effects an interconnection for communications via the first non-transparent port is provided. The communication apparatus includes a second interconnecting unit that includes a second non-transparent port communicably connected to the first non-transparent port. The second interconnecting unit effects an interconnection for communications via the second non-transparent port. The second interconnecting unit performs, when the communication apparatus carries out communications to and from the external apparatus, address translation between an address for use by the communication apparatus and an address for use by the second non-transparent port. | 2011-09-15 |
20110225342 | OPPORTUNISTIC PAGE CACHING FOR VIRTUALIZED SERVERS - A system described herein includes a receiver component that receives an indication that at least one page in virtual memory is free and the at least one page in virtual memory is classified as short-lived memory, wherein the virtual memory is accessible to at least one virtual machine executing on a computing device. The system also includes a cache updater component that dynamically updates a cache to include the at least one page, wherein the cache is accessible to the at least one virtual machine. | 2011-09-15 |
20110225343 | COMPUTER SYSTEM, DATA STORAGE METHOD, AND PROGRAM - In a computer system that can configure a virtual machine being able to transit to a hibernation state data of a main memory of the virtual machine stored in an auxiliary storage device is reduced. At a point in time when the virtual machine has transitioned to a hibernation state, from consideration as to whether the data of the main memory of the virtual machine stored in the auxiliary storage device is unnecessary, data stored in the auxiliary storage device is rewritten in order to reduce the data. | 2011-09-15 |
20110225344 | Method for Dynamic Configuration of an Electronic System with Variable Input and Output Signals - To enable dynamic configuration of an electronic system ( | 2011-09-15 |
20110225345 | Storage System Having Volatile Memory and Non-Volatile Memory - The present invention allows a save target stored in a volatile memory, to be reliably saved to a non-volatile memory and reduces the time required for the save processing as much as possible. The charging state of a battery is regularly of irregularly checked. It is determined, according to the checked charging state, which information element stored in the volatile memory should be made a save target at the time of the occurrence of a power interruption. Among a plurality of information elements stored in the volatile memory, a predetermined information element is made a non-save target of save processing, according to a state related to the predetermined information element. | 2011-09-15 |
20110225346 | GARBAGE COLLECTION IN A STORAGE DEVICE - In general, this disclosure relates to garbage collection in a storage device. Aspects of this disclosure describe techniques to identify one or more candidate memory storage blocks that should be recycled during garbage collection. The one or more candidate memory storage blocks may be identified based at least on monitored soft metrics of the candidate memory storage blocks. During garbage collection, the identified one or more candidate memory storage blocks may be recycled to free up storage space. | 2011-09-15 |
20110225347 | LOGICAL BLOCK STORAGE IN A STORAGE DEVICE - In general, this disclosure relates to storage of logical blocks in a storage device. Aspects of this disclosure describe techniques to monitor the frequency of access of one or more logical blocks referenced by one or more logical block addresses. Based on the frequency of access, in non-limiting aspects of this disclosure, a controller may select one or more physical blocks of a common memory storage block. The storage device may store the logical blocks in the selected physical blocks. | 2011-09-15 |
20110225348 | ELECTRONIC DEVICES USING REMOVABLE AND PROGRAMMABLE ACTIVE PROCESSING MODULES - System and methods for assembling electronic devices ( | 2011-09-15 |
20110225349 | Firmware Flashing of a Portable Device Using a Serial Bus Hub - System and method for configuring a portable device. The portable device includes a serial bus hub, one or more processors coupled to the serial bus hub via a serial bus, and a flash memory coupled to the serial bus hub via the serial bus. A degraded signal is received to a serial bus hub included in the portable device via a serial bus, where the degraded signal includes code to be written to the flash memory to initialize or update firmware for the portable device. The serial bus hub restores the degraded signal, thereby generating a restored signal, and sends the restored signal to at least one of the one or more processors to initialize or update the firmware in the flash memory for the portable device. | 2011-09-15 |
20110225350 | Methods and Apparatus for Soft Data Generation for Memory Devices Based Using Reference Cells - Methods and apparatus are provided for soft data generation for memory devices using reference cells. At least one soft data value is generated in a memory device by writing a known data to one or more reference cells; reading one or more of the reference cells; obtaining a read statistic based on the read one or more reference cells; and obtaining the at least one soft data value based on the obtained read statistic. The read statistics can optionally be obtained for one or more desired locations of a memory array; or for a given pattern, PATT, in one or more aggressor cells. The read statistic can optionally comprise asymmetric statistics obtained for a plurality of possible values. | 2011-09-15 |
20110225351 | MEMORY CARD AND MEMORY SYSTEM HAVING THE SAME - A memory card includes: a first memory chip responding to all commands input externally; and a second memory chip responding to commands, among the commands input externally, relevant to reading, programming, and erasing operations with data. Card identification information stored in the first memory chip includes capacity information corresponding to a sum of sizes of the first and second memory chips. The plurality of memory chips of the memory card are useful in designing the memory card with storage capacity in various forms. | 2011-09-15 |
20110225352 | APPARATUS AND SYSTEM FOR OBJECT-BASED STORAGE SOLID-STATE DRIVE - An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary configurations include a call interface, a physical layer interface, an object-based storage solid-state device (OSD-SSD), and are further characterized by the presence of a storage processor capable of processing object-based storage device algorithms interleaved with processing of physical storage device management. Embodiments include a storage controller capable of executing recognition, classification and tagging of application files, especially including image, music, and other media. Also disclosed are methods for initializing and configuring an OSD-SSD device. | 2011-09-15 |
20110225353 | REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) WRITE CACHE SUB-ASSEMBLY - In at least some embodiments, a computing system includes a processor and a communication bus external to the processor. The computing system also includes a Redundant Array of Independent Disks (RAID) write cache sub-assembly coupled to the communication bus, the RAID write cache sub-assembly having non-volatile memory. | 2011-09-15 |
20110225354 | ELECTRONIC APPARATUS - An electronic apparatus includes a memory control circuit that controls a first memory and a second memory, the first memory is connected to the memory control circuit through a first data bus, the second memory is connected to the memory control circuit through the first data bus and a second data bus, and a sum of bus widths of the first data bus and the second data bus is larger than the bus width of the first data bus by a times. When the memory control circuit receives an access request for the second memory, the memory control circuit generates a command for accessing the second memory b times on the basis of an address of the access request point and accesses the second memory. | 2011-09-15 |
20110225355 | SEMICONDUCTOR DEVICE, REFRESH CONTROL METHOD THEREOF AND COMPUTER SYSTEM - A semiconductor device comprises a first memory cell array, a register storing information of whether or not one of the word lines in an active state exists in a unit area and storing address information, and a control circuit controlling a refresh operation for a refresh word line based on the information in the register when receiving a refresh request. When the one of the word lines in an active state does not exist, memory cells connected to the refresh word line are refreshed. When the one of the word lines in an active state exists, the one of the word lines in an active state is set into an inactive state temporarily and the memory cells connected to the refresh word line are refreshed after precharging bit lines of the memory cells. | 2011-09-15 |
20110225356 | Method for Determining Allocation of Tape Drive Resources for a Secure Data Erase Process - A method and computer program product are provided to ensure a timely secure data erase by determining whether allocating an additional tape drive would improve secure data erase performance by evaluating a quantity of physical volumes to be secure data erased, a maximum queued threshold, an average time to an erasure deadline and a minimum expiration threshold. An additional tape drive is allocated for the secure data erase process when it is determined that allocating an additional tape drive would improve secure data erase performance. | 2011-09-15 |
20110225357 | System for Determining Allocation of Tape Drive Resources for a Secure Data Erase Process - A system is provided to ensure a timely secure data erase by determining whether allocating an additional tape drive would improve secure data erase performance by evaluating a quantity of physical volumes to be secure data erased, a maximum queued threshold, an average time to an erasure deadline and a minimum expiration threshold. An additional tape drive is allocated for the secure data erase process when it is determined that allocating an additional tape drive would improve secure data erase performance. | 2011-09-15 |
20110225358 | DISK ARRAY DEVICE, DISK ARRAY SYSTEM AND CACHE CONTROL METHOD - The invention proposes a disk array device that can improve response performance while maintaining data consistency even in the case a write request is received from a host device by a controller that does not have master authority. The disk array device includes a master controller and a slave controller. Upon adding identifying information indicating that write data has been stored in a buffer memory to the write request, the slave controller transmits, to the master controller, the write request to which the identifying information has been added as well as the write data. After having stored the write data, the master controller transmits the write request to which the identifying information has been added to the slave controller. Upon receiving the write request, the slave controller alters the attributes of the buffer memory where the write data has been stored, from the buffer memory to the cache memory. | 2011-09-15 |
20110225359 | FAST MIGRATION OF VIRTUAL STORAGE PARTITION DATA ACROSS STORAGE SYSTEMS - A method includes reading a superblock of a read-only replica of a source virtual volume in a source virtual storage partition associated with a source aggregate of a source storage system at the destination storage system, modifying the superblock of the read-only replica in a memory of the destination storage system, and associating the modified superblock with one or more virtual volume block number(s) configured to be previously associated with the superblock of the read-only replica of the source virtual volume without initiating a destination consistency point (DCP) at the destination storage system to render the destination virtual volume writable. The method also includes modifying a disk group label to reflect an association of the destination storage disk with the writable destination virtual volume, and initiating the DCP to ensure that the modified superblock and the modified disk group label are flushed to the destination storage disk. | 2011-09-15 |
20110225360 | DISPERSED STORAGE NETWORK RESOURCE ALLOCATION - A dispersed storage managing unit allocates resources within a dispersed storage network by determining a state of a dispersed storage unit supporting a vault associated with at least one user of the dispersed storage network and provisioning storage within the dispersed storage unit based on the state thereof. | 2011-09-15 |
20110225361 | DISPERSED STORAGE NETWORK FOR MANAGING DATA DELETION - A dispersed storage device manages deletion of data objects stored within a dispersed storage network by receiving a data delete request to delete a data object stored throughout a set of dispersed storage units within a dispersed network memory of the dispersed storage network, determining a deletion policy for the data object and selectively generating and transmitting, based on the deletion policy, a delete command to the set of dispersed storage units. | 2011-09-15 |
20110225362 | ACCESS CONTROL IN A DISPERSED STORAGE NETWORK - A method begins by a processing module receiving a data storage request that includes data and determining dispersed storage error encoding parameters for dispersed error encoding storage of data. The method continues with the processing module dispersed storage error encoding the data in accordance with the dispersed storage error encoding parameters to produce a set of encoded data slices and establishing access control information for each encoded data slice of the set encoded data slices in accordance with the dispersed storage error encoding parameters to produce a set of access control information. The method continues with the processing module appending a corresponding one of the set of access control information to each of the set of encoded data slices to produce a set of appended slices and outputting the set of appended slices to a set of dispersed storage units. | 2011-09-15 |
20110225363 | STORAGE PROCESSING DEVICE - A storage processing device to which a plurality of removable hard disk drives and the like are connected and includes: a RAID controller for controlling RAID including the removable hard disk drives and the like, and an available storage capacity setting unit for setting an available storage capacity which is a storage capacity actually available for a predetermined storage unit that is one of the storage units connected to the storage processing in the disk array, on the basis of the real storage capacity of the predetermined storage unit, when the predetermined storage unit is connected to the storage processing device. | 2011-09-15 |
20110225364 | EXTENSION OF WRITE ANYWHERE FILE LAYOUT WRITE ALLOCATION - A plurality of storage devices is organized into a physical volume called an aggregate, and the aggregate is organized into a global storage space, and a data block is resident on one of the storage devices of the plurality of storage devices. A plurality of virtual volumes is organized within the aggregate and he data block is allocated to a virtual volume. A physical volume block number (pvbn) is selected for the data block from a pvbn space of the aggregate, and virtual volume block number (vvbn) for the data block is selected from a vvbn space of the selected vvol. Both the selected pvbn and the selected vvbn are inserted in a parent block as block pointers to point to the allocated data block on the storage device. | 2011-09-15 |
20110225365 | EMULATING A COMPUTER SYSTEM ON A REMOVABLE STORAGE DEVICE - A removable storage device with a processor and a non-volatile memory, and a method for using a removable storage device, are provided to emulate the computer system. The storage device stores in the non-volatile memory data it obtained from a first computer system, the data containing computer applications. When the storage device is removably connected to a second computer system and the second computer system is associated with a computer peripheral device, the processor in the storage device is instructed to emulate the original process environment of the first computer system. | 2011-09-15 |
20110225366 | Dual-Mode, Dual-Display Shared Resource Computing - A dual-mode, dual-display shared resource computing (SRC) device is usable to stream SRC content from a host SRC device while in an on-line mode and maintain functionality with the content during an off-line mode. Such remote SRC devices can be used to maintain multiple user-specific caches and to back-up cached content for multi-device systems. | 2011-09-15 |
20110225367 | MEMORY CACHE DATA CENTER - A data center system includes a memory cache coupled to a data center controller. The memory cache includes volatile memory and stores data that is persisted in a database in a different data center system that is located remotely from the data center system rather than in the first data center system. The data center controller reads data from the memory cache and writes data to the memory cache. | 2011-09-15 |
20110225368 | Apparatus and Method For Context-Aware Mobile Data Management - A context of a mobile device is determined. A context preference of a user associated with the mobile device is determined. The context of the mobile device and the user context preference is transmitted to another node and responsively returned data is received. Available free space in the mobile device is determined. All data whose timestamp is within a predetermined threshold is cached. The data is cached in at least a portion of the free space. | 2011-09-15 |
20110225369 | MULTIPORT DATA CACHE APPARATUS AND METHOD OF CONTROLLING THE SAME - A multiport data cache apparatus and a method of controlling the same are provided. The multiport data cache apparatus includes a plurality of cache banks configured to share a cache line, and a data cache controller configured to receive cache requests for the cache banks, each of which including a cache bank identifier, transfer the received cache requests to the respective cache banks according to the cache bank identifiers, and process the cache requests independently from one another. | 2011-09-15 |
20110225370 | NON-VOLATILE STORAGE DEVICE, ACCESS DEVICE, AND NON-VOLATILE STORAGE SYSTEM - When multiple pieces of content data are being recorded continuously to a nonvolatile storage device having page cache function, a preparation time before starting next content data recording is reduced. When a cache releasing section of a nonvolatile storage device ( | 2011-09-15 |
20110225371 | DATA PREFETCH FOR SCSI REFERRALS - A method for communication between an initiator system and a storage cluster. The method comprises receiving an initial I/O request from the initiator system to a first storage system; providing a referral response from the first storage system to the initiator system, the referral response providing information for directing the initiator system to a second storage system; notifying the second storage system regarding the referral response via a prefetch notice, the prefetch notice including an operation type and address information for accessing requested data; when the initial I/O request is a read request, prefetching at least a portion of the requested data stored in the second storage system in to a cache; receiving a second I/O request from the initiator system to the second storage system; and providing to the initiator system the portion of the prefetched data from the cache of the second storage system. | 2011-09-15 |
20110225372 | CONCURRENT, COHERENT CACHE ACCESS FOR MULTIPLE THREADS IN A MULTI-CORE, MULTI-THREAD NETWORK PROCESSOR - Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A state engine operates on instructions received from the multi-thread instruction engine, the instruction including a cache access request to a local cache of the state engine. A cache line entry manager of the state engine translates between a logical index value of data corresponding to the cache access request and a physical address of data stored in the local cache. The cache line entry manager manages data coherency of the local cache and allows one or more concurrent cache access requests to a given cache data line for non-overlapping data units. | 2011-09-15 |
20110225373 | COMPUTER SYSTEM AND METHOD OF DATA CACHE MANAGEMENT - A computer system including: a file server, cache servers, and a cache management server, wherein: the cache server obtains the authority information from the cache management server, in a case of receiving a command to process a file, wherein the cache server refers to the obtained authority information, wherein the cache server executes the command to process the file, in a case where the cache server has an administration right of the cache data of the file, wherein the cache management server sends to the cache server an update command for transferring the administration right of the cache data to the other cache server, wherein the cache server sends the update command to the other cache server after receiving the update command, and executes a update procedure in which a lock management information is updated. | 2011-09-15 |
20110225374 | SELF-ADJUSTING SCSI STORAGE PORT QUEUE - A method for managing storage space in a storage port queue includes establishing a watermark for the storage port queue. The method further receives, at the storage port associated with the storage port queue, a command having an initiator-target-LUN (ITL) nexus associated therewith. Upon receiving the command, the method determines whether the used space in the storage port queue has reached the watermark. In the event the used space has not reached the watermark, the method processes the command. In the event the used space has reached the watermark and a specified number of commands for the ITL nexus are already present in the storage port queue, the method rejects the command. Otherwise, the method may process the command. A corresponding apparatus and computer program product are also disclosed herein. | 2011-09-15 |
20110225375 | Concurrent Execution of Critical Sections by Eliding Ownership of Locks - One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section. | 2011-09-15 |
20110225376 | MEMORY MANAGER FOR A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE - Described embodiments provide a memory manager for a network processor having a plurality of processing modules and a shared memory. The memory manager allocates blocks of the shared memory to requesting ones of the plurality of processing modules. A free block list tracks availability of memory blocks of the shared memory. A reference counter maintains, for each allocated memory block, a reference count indicating a number of access requests to the memory block by ones of the plurality of processing modules. The reference count is located with data at the allocated memory block. For subsequent access requests to a given memory block concurrent with processing of a prior access request to the memory block, a memory access accumulator (i) accumulates an incremental value corresponding to the subsequent access requests, (ii) updates the reference count associated with the memory block, and (iii) updates the memory block with the accumulated result. | 2011-09-15 |
20110225377 | DATA STORAGE APPARATUS, DATA MANAGEMENT APPARATUS AND CONTROL METHOD THEREOF - A data storage apparatus, connected to an information processing apparatus, includes a library unit, a storage unit, and a control unit. The storage unit is configured to store a plurality of data including first and second data received from the information processing apparatus, and the control unit is configured to perform control, when performing processing to write the plurality of data from the storage unit to a recording medium in the library unit. If an update request for updating the second data specified to be written later than the first data is received from the information processing apparatus, the second data is written to the recording medium in the library unit before the first data is written. | 2011-09-15 |
20110225378 | Data Processing Apparatus, Data Processing Method, and Computer-Readable Recording Medium for Writing and Reading Data to and from a Storage - A data processing apparatus includes a storage controller and a processor. The storage controller is configured to write a series of data blocks constituting a particular unit of data to a storage and read out the series of data blocks from the storage. The processor is further configured to generate a write-side process and a read-side process, notify the read-side process from the write-side process of an identifier of a storage area in the storage, cause the storage controller to sequentially write the series of data blocks to the storage area using the write-side process, and cause the storage controller to read the series of data blocks from the storage area corresponding to the identifier using the read-side process after the identifier is received in the read-side process. | 2011-09-15 |
20110225379 | VOLUME MANAGEMENT APPARATUS AND STORAGE SYSTEM - The present invention allocates a suitable physical device to each volume page according to the state transition command relating to paired volumes. A plurality of logical devices forming a logical storage area of a plurality of physical devices of varying performance are tiered according to the performance of the physical devices to form a pool volume, and each of the areas of the primary logical volume, secondary logical volume and pool volume are managed by a controller, divided into a primary page, secondary page and pool page. Upon receiving a pair formation-related command from the host computer, the controller allocates pool pages belonging to the same tier to the primary page and secondary page, and upon subsequently receiving a pair-related state transition command, the controller allocates a pool page, in a different tier from the primary page, to the secondary page. | 2011-09-15 |
20110225380 | MULTIPLE BACKUP PROCESSES - Handling multiple backup processes comprises detecting that a defined storage volume is present in a first cascade of storage volumes, detecting that the defined storage volume is also present in a second cascade of storage volumes, receiving a data write for either the defined storage volume or the last storage volume in the first cascade of storage volumes, and performing a cleaning data write on the defined storage volume in the second cascade of storage volumes, the cleaning data write corresponding to the received data write. | 2011-09-15 |
20110225381 | NONVOLATILE STORAGE DEVICE, ACCESS DEVICE AND NONVOLATILE STORAGE SYSTEM - A memory controller includes a reading/writing control unit for controlling writing and reading of data to and from a physical block of a nonvolatile memory, a writing mode table for storing one of a first writing mode of protecting data against a power shutdown during writing and a second writing mode of writing data at a higher speed than the first writing mode, and a setting unit for setting the writing mode received from an access device in a writing mode table. The reading/writing control unit performs data writing based on the writing mode that has been set in the writing mode table. | 2011-09-15 |
20110225382 | INCREMENTAL REPLICATION USING SNAPSHOTS - A first snapshot is taken of a first block storage resource that is initially identical in content to a second block storage resource. A second snapshot of the first block storage resource is taken at a later time. A record is kept of all blocks modified on the first block storage resource. Only those blocks modified between the time of the first and second snapshots are written to the second block storage resource. After all the modified blocks are written to the second block storage resource, a snapshot is taken of the second block storage resource to maintain a consistent snapshot of the second block storage resource in case of communication failure during the next round. The first snapshot is then deleted, the second takes the role of the first, and the next round of replication begins. | 2011-09-15 |
20110225383 | METHOD FOR SECURELY STORING DATA IN A MEMORY OF A PORTABLE DATA CARRIER - A method for securely storing data in a multilevel memory of a portable data carrier. The multilevel memory includes one or several multilevel memory cells (SZ) which can assume respectively at least three levels (E, NE). The at least three levels represent a different data content, regarding which respective levels (E, NE) of a memory cell (SZ) are defined as valid or invalid. The levels (E, NE) of a respective memory cell (SZ) are selectively defined as valid or invalid in dependence on a required security level. | 2011-09-15 |
20110225384 | FLASH STORAGE PARTIAL PAGE CACHING - Methods and apparatus may operate to receive allocation requests from a processor configured to manage memory comprising a non-volatile memory device configurable as a plurality of blocks comprising a plurality of sectors, assign partial page blocks from the plurality of blocks for memory storage, fill some of the sectors by storing data bits associated with the allocation request in the at least one of the plurality of sectors, determine that the sectors are full, assigning a full page block from the plurality of blocks, and transfer the data bits associated with the allocation request from the partial page blocks to the full page block. Other apparatus, systems, and methods are disclosed. | 2011-09-15 |
20110225385 | CONTROLLING CONFIGURABLE VARIABLE DATA REDUCTION - Example apparatus, methods, and computers control configurable, variable data reduction. One example method includes identifying data reduction controlling attributes in an object to be data reduced by a configurable variable data reducer. The attributes provide information upon which decisions concerning whether and/or how to data reduce the object can be based. The example method also includes controlling a configurable variable data reducer to selectively data reduce the object based, at least in part, on the data reduction controlling attributes. The control exercised can determine whether, where, when, and/or how data reduction will proceed. | 2011-09-15 |
20110225386 | DISPERSED STORAGE UNIT CONFIGURATION - A dispersed storage (DS) unit for use within a dispersed storage network is capable of self-configuring using registry information provided to the DS unit. The registry information includes a slice name assignment indicating a range of slice names corresponding to a plurality of potential data slices of potential data objects to be stored in the DS unit. Based on the registry information, the DS unit allocates a portion of physical memory to store the potential data slices. | 2011-09-15 |
20110225387 | Unified Virtual Contiguous Memory Manager - Memory management methods and computing apparatus with memory management capabilities are disclosed. One exemplary method includes mapping an address from an address space of a physically-mapped device to a first address of a common address space so as to create a first common mapping instance, and encapsulating an existing processor mapping that maps an address from an address space of a processor to a second address of the common address space to create a second common mapping instance. In addition, a third common mapping instance between an address from an address space of a memory-management-unit (MMU) device and a third address of the common address space is created, wherein the first, second, and third addresses of the common address space may be the same address or different addresses, and the first, second, and third common mapping instances may be manipulated using the same function calls. | 2011-09-15 |
20110225388 | Data Storage Device And Computing System Including The Same - A data storage device includes a storage medium configured to store data; and a controller configured to control the storage medium, the controller including address mapping information. The controller is configured to divide the address mapping information into at least a first address mapping table and a second address mapping table based on information regarding temporary data received at the controller. The first address mapping table is configured to map one or more addresses of valid data and to be backed up to the storage medium. The second mapping address table being configured to map one or more addresses of the temporary data and to not be backed up to the storage medium. | 2011-09-15 |
20110225389 | Translation table control - Memory address translation circuitry | 2011-09-15 |
20110225390 | Micro-Tile Memory Interfaces - In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder. | 2011-09-15 |
20110225391 | HASH PROCESSING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE - Described embodiments provide a hash processor for a system having multiple processing modules and a shared memory. The hash processor includes a descriptor table with N entries, each entry corresponding to a hash table of the hash processor. A direct mapped table in the shared memory includes at least one memory block including N hash buckets. The direct mapped table includes a predetermined number of hash buckets for each hash table. Each hash bucket includes one or more hash key and value pairs, and a link value. Memory blocks in the shared memory include dynamic hash buckets available for allocation to a hash table. A dynamic hash bucket is allocated to a hash table when the hash buckets in the direct mapped table are filled beyond a threshold. The link value in the hash bucket is set to the address of the dynamic hash bucket allocated to the hash table. | 2011-09-15 |
20110225392 | Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller - Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported. | 2011-09-15 |
20110225393 | DEVICE ACTIVATING UNIT AND CPU - A register circuit having a plurality of registers enabling the writing and reading of data by the specification of an address; a register controlling circuit monitoring data of a plurality of registers of the register circuit through the specification of an address, and writing, to a register pre-established in the register circuit, for activating devices; and a signal transmitting circuit causing a device to execute a specific operation, based on a specified address and on data read from the register circuit are provided; and not only is a collection of first bits for controlling jointly the individual operations of the plurality of devices assigned in a first register that is established in advance in the plurality of registers, but also second bits for controlling individually the individual operations in the plurality of devices are assigned respectively in a plurality of respective second registers that differ from the first register. | 2011-09-15 |
20110225394 | INSTRUCTION BREAKPOINTS IN A MULTI-CORE, MULTI-THREAD NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE - Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate threads of contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes instructions corresponding to threads received from the scheduler. The multi-thread instruction engine executes instructions by fetching an instruction of the thread from an instruction memory of the packet classifier and determining whether a breakpoint mode of the network processor is enabled. If the breakpoint mode is enabled, and breakpoint indicator of the fetched instruction is set, the packet classifier enters a breakpoint mode. Otherwise, if the breakpoint indicator of the fetched instruction is not set, the multi-thread instruction engine executes the fetched instruction. | 2011-09-15 |
20110225395 | DATA PROCESSING SYSTEM AND CONTROL METHOD THEREOF - In a data processing system which includes a processor performing a processing in correspondence with a fetched instruction and a DRC capable of dynamically reconfiguring a circuit configuration in correspondence with configuration data, when the processor fetches the instruction, a configuration data decoder identifies whether or not the instruction is a configuration data instruction. When the instruction is the configuration data instruction, the configuration data is read from the configuration data memory in which the configuration data is housed and supplied to the DRC based on address information included in the configuration data instruction, thereby to enable the configuration data to be supplied to the DRC at a timing the same as a timing at which the instruction is fetched, so that the configuration data can be supplied at a high speed. | 2011-09-15 |
20110225396 | Methods and Apparatus for Storing Expanded Width Instructions in a VLIW Memory for Deferred Execution - Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved indirect deferred execution processor (DXP) VLIW architecture is described which supports a scalable array of memory centric processor elements that do not require local load and store units. | 2011-09-15 |
20110225397 | Mapping between registers used by multiple instruction sets - A processor | 2011-09-15 |
20110225398 | ADVANCED PROCESSOR SCHEDULING IN A MULTITHREADED SYSTEM - An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner. | 2011-09-15 |
20110225399 | PROCESSOR AND METHOD FOR SUPPORTING MULTIPLE INPUT MULTIPLE OUTPUT OPERATION - A processor for supporting a MIMO operation and method of processing a MIMO instruction are provided. The MIMO operation supporting processor may include a scheduler and at least one functional unit. The scheduler may map multiple inputs of the MIMO instruction to a plurality of sequential input cycles, respectively, and may map multiple outputs of the MIMO instruction to a plurality of sequential output cycles, respectively. The output cycles may be followed by the input cycles and a predetermined number of cycles for a MIMO operation. A functional unit may read a register during sequential input cycles, may perform a MIMO operation during a predetermined number of execution cycles, and may write the result of the MIMO operation into a register during sequential output cycles. | 2011-09-15 |
20110225400 | Device for Testing a Multitasking Computation Architecture and Corresponding Test Method - A device and method for testing a multitasking computation architecture is provided. Sequences of test instructions are generated corresponding to programming rules for the computation architecture. The execution of the instruction sequences is controlled so that the sequences are alternately executed within the computation architecture. | 2011-09-15 |
20110225401 | PREFETCHING BRANCH PREDICTION MECHANISMS - A method comprising receiving a branch instruction, decoding a branch address and the branch instruction, executing a branch action associated with the branch address, determining whether a branch associated with the branch action was taken, and saving an identifier of the branch instruction and in indicator that the branch action was taken in a prefetch history table responsive to determining that the branch associated with the branch action was taken. | 2011-09-15 |
20110225402 | Apparatus and method for handling exception events - Processing circuitry | 2011-09-15 |
20110225403 | OPERATING SYSTEM AND METHOD OF RUNNING THEREOF - A method of running an operating system comprises a two-step process. Firstly, in a set-up phase, there is carried out the loading of a driver when the operating system is booted, an operating system component transmitting a call to a kernel component for a function table, the driver intercepting the call from the operating system component to the kernel component, the driver replacing a specific callout in the function table with a replacement callout to the driver, the driver supplying the amended function table to the operating system component, the operating system component invoking the replacement callout to the driver, the driver invoking the original callout to the kernel component for a second function table, the driver replacing a specific function call in the second function table with a replacement function call to the driver, and the driver supplying the amended second function table to the operating system component. In the second phase, the operating system component invokes the replacement function call to the driver, the driver invoking the original function call to the kernel component for a result, the driver changing the received result to TRUE, and the driver supplying the replacement result to the operating system component. | 2011-09-15 |
20110225404 | METHOD FOR BOOTING PORTABLE OBJECTS WITH MULTIPLE COMMUNICATION INTERFACES - A boot sequence method comprises a determination step | 2011-09-15 |
20110225405 | MANAGING A COMPUTING DEVICE - Methods, computer-readable media, and systems are provided for managing a target computing device. One method for managing the target computing device includes loading a service operating system into non-persistent memory of the target computing device having a persistent memory that is initially devoid of a functional operating system. The service operating system includes an embedded global shell agent. The global shell agent is executed thereby configuring the target computing device for remote management within an interactive command shell function before loading an operating system into persistent memory of the target computing device. The global shell agent is operable to examine and modify filesystems on the target computing device. | 2011-09-15 |
20110225406 | System and Method for Pre-Operating System Encryption and Decryption of Data - Systems and methods for reducing problems and disadvantages associated with traditional approaches to encryption and decryption of data are provided. An information handling system may include a processor, a memory communicatively coupled to the processor, an encryption accelerator communicatively coupled to the processor, and a computer-readable medium communicatively coupled to the processor. The encryption accelerator may be configured to encrypt or decrypt data in response to a command from the processor to perform an encryption or decryption task upon data associated with an input/output operation. The computer-readable medium may have instructions stored thereon, the instructions configured to, when executed by the processor: (i) monitor for input/output operations occurring prior to loading of an operating system into the memory; and (ii) in response to detection of an input/output operation, communicate a command to the encryption accelerator to perform an encryption or decryption task upon data associated with an input/output operation. | 2011-09-15 |
20110225407 | System and Method for Recovering From an Interrupted Encryption and Decryption Operation Performed on a Volume - Systems and methods for reducing problems and disadvantages associated with traditional approaches to encryption and decryption of data are provided. An information handling system may include a processor, a memory communicatively coupled to the processor, and a computer-readable medium communicatively coupled to the processor. The computer-readable medium may have instructions stored thereon, the instructions configured to, when executed by the processor: (i) periodically store, during an encryption or decryption operation performed on the computer-readable medium, one or more variables indicative of an encryption status of a volume of the computer-readable medium; (ii) determine, based on the one or more variables, whether the volume is in a partially encrypted or decrypted state; and (iii) in response to a determination that the volume is in a partially encrypted or decrypted state, boot from the volume and continue the encryption or decryption operation. | 2011-09-15 |
20110225408 | CACHE BOOT MECHANISM - A block device driver performs system boot using cache data and thus provides a mechanism that reduces disk/IO waiting time during system boot. | 2011-09-15 |
20110225409 | Method and Apparatus for Software Boot Revocation - A composite customer ID (CCID) is stored in the OTP memory of integrated circuit chipsets used by a number of different customers. The CCID includes individual customer IDs (CIDs) at defined index positions, each corresponding to a different customer. Each chipset allows or disallows software booting, based reading a certificate index value from a given customer's certificate, reading an OTP CID from OTP, as pointed to the by certificate index value, and evaluating the OTP CID with a certificate CID read from the certificate. Thus, while CCID carries information for a plurality of customers, each customer's certificate points only to that customer's OTP CID, which can be changed to revoke that customer's certificate without revoking the other customers' certificates. The CCID also may include a version number, where the chipsets allow or disallow software booting based on evaluating the certificate version number in view of the CCID version number. | 2011-09-15 |
20110225410 | ELECTRONIC DEVICE AND BOOTING UP METHOD - An electronic device includes a micro control unit (MCU), a non-volatile random access memory (NVRAM), and a watch dog. The electronic device detects a standby instruction and then enters a standby mode according to the standby instruction. A boot loader stored in the NVRAM boots the electronic device when the MCU detects a starting instruction. The electronic device triggers the watch dog to time a preset period when the boot loader boots the electronic device and boots up with a fast mode. The electronic device determines if the watch dog times out, and boots up with a normal mode when the electronic device does not boot up with the fast mode before the watch dog times out. | 2011-09-15 |
20110225411 | STORAGE PROCESSING DEVICE AND PROGRAM | 2011-09-15 |
20110225412 | BOOTING AN OPERATING SYSTEM OF A SYSTEM USING A READ AHEAD TECHNIQUE - In one embodiment, the present invention includes a method for generating a list of files accessed during an operating system (OS) boot process to profile the OS boot process, and optimizing the list of files to generate an optimized file list for use in future OS boot processes, where the optimizing is according to a first optimization technique if the files were accessed from a solid state medium and according to a second optimization technique if the files were accessed from a rotating medium. Other embodiments are described and claimed. | 2011-09-15 |
20110225413 | METHOD, SYSTEM AND ARTICLE OF MANUFACTURE FOR SYSTEM RECOVERY - Provided are a method, system, and article of manufacture for system recovery. An operating system and a backup copy of the operating system are both maintained in a partition of a computational device. A boot loader receives an indication to load the backup copy of the operating system. The boot loader loads the backup copy of the operating system. The computational device is rebooted with the loaded backup copy of the operating system. | 2011-09-15 |