37th week of 2010 patent applcation highlights part 15 |
Patent application number | Title | Published |
20100230672 | PRODUCTION OF INTEGRATED CIRCUITS COMPRISING DIFFERENT COMPONENTS - It is described a method for producing an integrated circuit element comprising a first electric component of a first type and a second electric component of a second type, wherein the two components require different measurement conditions for testing the components as to be defective or as to be defect free. The production method comprises the steps of (a) forming the first and the second component on a substrate, (b) providing a conductor path on the substrate in order to contact the first and the second component, the conductor path comprising a galvanic gap, wherein the galvanic gap provides the possibility to individually connect the first component with a measurement device, (c) accomplishing a test of the first component with the measurement device and (d) in case the test shows a defect free first component, closing the galvanic gap with a conductive connection, and in case the test shows a defective first component, identifying the corresponding integrated circuit element as to be defective. Furthermore, there is described a method for producing an integrated circuit comprising a plurality of circuit elements, a circuit element and an integrated circuit. | 2010-09-16 |
20100230673 | Semiconductor Fuse Structure and a Method of Manufacturing a Semiconductor Fuse Structure - The invention relates to a semiconductor fuse structure comprising a substrate ( | 2010-09-16 |
20100230674 | METHOD FOR FORMING NON-ALIGNED MICROCAVITIES OF DIFFERENT DEPTHS - The invention relates to a method for forming microcavities ( | 2010-09-16 |
20100230675 | DISPLAY DEVICE - A display device having a photosensor which exhibits excellent photoelectric conversion efficiency is provided. In a display device which forms photosensors on a substrate thereof, the photosensor is formed by sequentially stacking a gate electrode, a gate insulation film and a semiconductor layer in such an order or in an opposite order from a substrate side, and electrodes are connected to both sides of the semiconductor layer respectively, the semiconductor layer is formed of a stacked body consisting of a crystalline semiconductor layer and an amorphous semiconductor layer, and the crystalline semiconductor layer is arranged on the gate insulation film side. | 2010-09-16 |
20100230676 | TFT ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A TFT array substrate includes a substrate, at least one gate line and gate electrode, a gate insulating layer, and at least one channel component, source electrode, drain electrode and data line. The gate line and gate electrode are disposed on the substrate, wherein both of the gate line and gate electrode have first and second conductive layers, the first conductive layer is formed on the substrate, the first conductive layer contains molybdenum nitride, the second conductive layer is formed on the first conductive layer, and the second conductive layer contains copper. The gate insulating layer is disposed on the gate line, gate electrode and the substrate. The channel component is disposed on the gate insulating layer. The source electrode and drain electrode are disposed on the channel component, and data line is disposed on the gate insulating layer. | 2010-09-16 |
20100230677 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A thin film transistor in which deterioration at initial operation is not likely to be caused and a manufacturing method thereof. A transistor which includes a gate insulating layer at least whose uppermost surface is a silicon nitride layer, a semiconductor layer over the gate insulating layer, and a buffer layer over the semiconductor layer and in which the concentration of nitrogen in the vicinity of an interface between the semiconductor layer and the gate insulating layer, which is in the semiconductor layer is lower than that of the buffer layer and other parts of the semiconductor layer. Such a thin film transistor can be manufactured by exposing the gate insulating layer to an air atmosphere and performing plasma treatment on the gate insulating layer before the semiconductor layer is formed. | 2010-09-16 |
20100230678 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A space is provided under part of a semiconductor layer. Specifically, a structure in which an eaves portion (a projecting portion, an overhang portion) is formed in the semiconductor layer. The eaves portion is formed as follows: a stacked-layer structure in which a conductive layer, an insulating layer, and a semiconductor layer are stacked in this order is etched collectively to determine a pattern of a gate electrode; and a pattern of the semiconductor layer is formed while side-etching is performed. | 2010-09-16 |
20100230679 | CONTACT PORTION OF WIRE AND MANUFACTURING METHOD THEREOF - A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut. | 2010-09-16 |
20100230680 | LIQUID CRYSTAL DISPLAY DEVICE INCLUDING COMMON ELECTRODE AND REFERENCE ELECTRODE - A liquid crystal display includes; a first substrate, a gate line disposed on the first substrate, a data line intersecting the gate line, a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, an interlayer insulating layer disposed on the pixel electrode, a common electrode disposed on the interlayer insulating layer and including a plurality of electrically connected common electrode lines extending substantially parallel to each other, a second substrate disposed substantially opposite to the first substrate, a reference electrode disposed on substantially an entire surface of the second substrate, and a liquid crystal layer disposed between the first substrate and the second substrate, and having negative dielectric anisotropy. | 2010-09-16 |
20100230681 | Display unit - A display unit with which lowering of long-term reliability of a transistor is decreased is provided. The display unit includes a display section having a plurality of organic EL devices with light emitting color different from each other and a plurality of pixel circuits that are singly provided for every said organic EL device for every pixel. The pixel circuit has a first transistor for writing a video signal, a second transistor for driving the organic EL device based on the video signal written by the first transistor, and a retentive capacity, and out of the first transistor and the second transistor, a third transistor provided correspondingly to a second organic EL device adjacent to a first organic EL device is arranged farther from the first organic EL device than a first retentive capacity provided correspondingly to the second organic EL device out of the retentive capacity. | 2010-09-16 |
20100230682 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - The present invention provides an array substrate comprising: a substrate, having a thin film transistor (TFT) formed thereupon, the TFT having a gate electrode, a source electrode and a drain electrode; a first metal layer, formed on the substrate, and comprising a gate line and the gate electrode of the TFT; a first insulating layer, covering the first metal layer and the substrate; a semiconductor layer, an ohmic contact layer, and a second metal layer, which are sequentially formed on the first insulating layer; a second insulating layer, covering the semiconductor layer, the ohmic contact layer, and the second metal layer; a pixel electrode, provided on the second insulating layer and is connected to the drain electrode. The second metal layer further comprises an etch-blocking pattern in the peripheral area of the pixel electrode within the overlapping region between the pixel electrode and the first metal layer. | 2010-09-16 |
20100230683 | THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, DISPLAY DEVICE, AND MANUFACTURING METHOD THEREOF - Disclosed is a manufacturing method of a thin film transistor, which enables the formation of a thin film transistor by using only one photomask. The method includes: over a substrate sequentially forming a first insulating film, a first conductive film, a second insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film; forming a resist mask thereover using a first photomask; performing a first etching to allow the side surface of the layers including an upper portion of the first insulating film, the first conductive film, the second insulating film, the semiconductor film, the impurity semiconductor film, and the second conductive film to be coplanar to a side surface of the resist mask; and performing a second etching to selectively etch the first conductive film to allow the side surface of the first conductive film is located inside the side surface of the layers. | 2010-09-16 |
20100230684 | SEMICONDUCTOR DEVICE - A semiconductor device includes a channel layer, an electron-supplying layer provided on the channel layer, a cap layer provided on the electron-supplying layer and creating lattice match with the channel layer, and ohmic electrodes provided on the cap layer. The cap layer has a composition of (In | 2010-09-16 |
20100230685 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM INCLUDING THE SAME - Provided are a light emitting device, a light emitting device package and a lighting system including the same. The light emitting device (LED) comprises a light emitting structure comprising a second conductive type semiconductor layer, an active layer, and a first conductive type semiconductor layer and a first electrode over the light emitting structure. A portion of the light emitting structure is sloped at a predetermined angle. | 2010-09-16 |
20100230686 | LIGHT EMITTING DEVICE - Disclosed are a light emitting device and a method of manufacturing the same. The light emitting device includes a plurality of compound semiconductor layers that includes a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, and a second conductive semiconductor layer under the active layer. An electrode is formed on the compound semiconductor layers. A groove is formed at an upper portion of the compound semiconductor layers. An electrode layer is formed under the compound semiconductor layers. | 2010-09-16 |
20100230687 | III NITRIDE ELECTRONIC DEVICE AND III NITRIDE SEMICONDUCTOR EPITAXIAL SUBSTRATE - In a group III nitride hetero junction transistor | 2010-09-16 |
20100230688 | LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, DISPLAY, AND ELECTRONIC EQUIPMENT - Provided is a light-emitting element including a cathode; an anode; a first light-emitting layer that is disposed between the cathode and the anode and emits in a first color; a second light-emitting layer that is disposed between the first light-emitting layer and the cathode and emits in a second color that is different from the first color; and an intermediate layer that is disposed between the first light-emitting layer and the second light-emitting layer so as to be in contact with these layers and has a function of controlling the migration of holes and electrons between the first light-emitting layer and the second light-emitting layer. The intermediate layer is constituted of a first layer that is in contact with the first light-emitting layer and is constituted of a hole-transporting material serving as a main material and a second layer that is in contact with the first layer and also with the second light-emitting layer and is constituted of a material mixture, serving as a main material, of a material having an acene skeleton and a hole-transporting material. | 2010-09-16 |
20100230689 | Novel Metal Core Multi-LED SMD Package and Method of Producing the Same - A new SMD (surface mount devices) package design for efficiently removing heat from LED Chip(s) is involved in this invention. Different from the regular SMD package, which electrical isolated materials like Alumina or AlN are used, the substrate material here is metal like Copper, Aluminum and so on. Also, different from regular design, which most time only has one LED chip inside, current design will at least have two or more LED chips (or chip groups) in one package. All chips are electrical connected via metal blocks, traces or wire-bond. This type of structure is generally fabricated via chemical etching and then filled with dielectric material inside to form a strong package. Because the thermal conductivity of the metal is much higher than the ceramics, the package thermal resistance is much lower than the ceramics based package. Also, the cost of the package is much lower than ceramics package. Moreover, emitting area in one package is much larger than the current arts. | 2010-09-16 |
20100230690 | GROUP III NITRIDE SEMICONDUCTOR DEVICE, EPITAXIAL SUBSTRATE, AND METHOD OF FABRICATING GROUP III NITRIDE SEMICONDUCTOR DEVICE - A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device | 2010-09-16 |
20100230691 | Ferrous-Metal-Alkaline-Earth-Metal Silicate Mixed Crystal Phosphor and Light Emitting Device using The Same - A ferrous-metal-alkaline-earth-metal mixed silicate based phosphor is used in form of a single component or a mixture as a light converter for a primarily visible and/or ultraviolet light emitting device. The phosphor has a rare earth element as an activator. The rare earth element is europium (Eu). Alternatively, the phosphor may have a coactivator formed of a rare earth element and at least one of Mn, Bi, Sn, and Sb. | 2010-09-16 |
20100230692 | LAMP AND PRODUCTION METHOD OF LAMP - The present invention provides a lamp comprising a substrate composed of a base substrate and a covering member which are made of an inorganic insulator and are joined through a joining metal layer; and a semiconductor light emitting device mounted on said substrate, wherein a concave portion is provided in a covering member-side surface of said substrate, said semiconductor light emitting device is accommodated in said concave portion, an end face of said metal layer is positioned on a region of the lateral surface of said concave portion which faces said semiconductor light emitting device, and a light reflection portion, which reflects light emitted from said semiconductor light emitting device, is composed of said end face. | 2010-09-16 |
20100230693 | White light emitting diode package and method of making the same - A white light emitting diode (LED) package with multilayered encapsulation structure and the packaging methods are disclosed. The white LED package structure includes metal electrodes, a heat dissipation base, a PPA plastic for fixing the electrodes and the heat dissipation base together, at least one LED die, a die attaching material, gold wires for electrically connecting the LED die to the electrodes, a first type of silicone encapsulant, a second type of silicone encapsulant, and a phosphor containing layer. The invention utilizes a low-refractive index silicone (the second type of silicone encapsulant) to separate the phosphor containing layer away from the first type of silicone, which covers the LED die, to prevent/reduce emitted light going backward and hitting the LED die. | 2010-09-16 |
20100230694 | Optoelectronical Component Emitting Electromagnetic Radiation and Method for Producing an Optoelectronical Component - An optoelectronic component is specified that emits a useful radiation. It comprises a housing having a housing base body with a housing cavity, and a light-emitting diode chip arranged in the housing cavity. At least one base body material of the housing base body has radiation-absorbing particles admixed in a targeted manner to reduce its reflectivity. According to another embodiment of the component, the housing additionally or alternatively has a housing material transmissive for the useful radiation that has radiation-absorbing particles admixed in a targeted manner to reduce its reflectivity. In addition, a method for manufacturing such a component is specified. | 2010-09-16 |
20100230695 | LED package structure - An LED package structure includes an LED chip, an internal transparent colloidal layer, a fluorescent colloidal layer, and an external transparent colloidal layer. The internal transparent colloidal layer is interposed between the LED chip (such as a blue-light LED chip) and the fluorescent colloidal layer (such as a yellow fluorescent colloidal layer), and that the external transparent colloidal layer, in cooperation with the internal transparent colloidal layer, sandwiches and envelops the fluorescent colloidal layer so as to lower the possibility that light emitted from the LED chip may be absorbed by the LED chip itself because the light is scattered backward by particles of the fluorescent powder. This will increase overall lumen output and decrease thermal energy of the LED chip, and will as well provide a more desirable moisture insulation for the fluorescent powder. | 2010-09-16 |
20100230696 | WIRING MEMBER, METAL COMPONENT WITH RESIN AND RESIN SEALED SEMICONDUCTOR DEVICE, AND PROCESSES FOR PRODUCING THEM - There is provided a semiconductor device that suppresses the occurrence of resin burrs to ensure favorable electrical connectivity and bond strength, and a manufacturing method for such semiconductor device. Also provided is an LED device which ensures stronger adhesion between a silicone resin and a wiring lead and thus achieves favorable light emitting properties, and a manufacturing method for such LED device. Also provided is an LED device that can present superior luminous efficiency by the provision of a sufficient reflectivity even when emitting relatively short wavelength light, and a manufacturing method for such LED device. Also provided is a film carrier tape with which a superior Sn plating coat is formed, mechanical strength and connectivity are achieved. Also provided is a manufacturing method for such film carrier tape that can avoid damage to the wiring pattern layer during an Sn plating step while maintaining favorable manufacturing efficiency. Specifically, an organic coat | 2010-09-16 |
20100230697 | OPTO-ELECTRONIC SEMICONDUCTOR MODULE AND METHOD FOR THE PRODUCTION THEREOF - An optoelectronic semiconductor module includes a chip carrier, a light emitting semiconductor chip mounted on the chip carrier and a cover element with an at least partly light transmissive cover plate, which is arranged on the side of the semiconductor chip facing away from the chip carrier, and has a frame part, wherein the frame part laterally encloses the semiconductor chip, is joined to the cover plate in a joining-layer free fashion and is joined to the chip carrier on its side remote from the cover plate. | 2010-09-16 |
20100230698 | Optoelectronic Semiconductor Body - An optoelectronic semiconductor body includes a substrate with a front side for emitting electromagnetic radiation. The optoelectronic semiconductor body has a semiconductor layer sequence that is arranged on a rear side of the substrate and has an active layer suitable for generating the electromagnetic radiation. The optoelectronic semiconductor body also includes first and second electrical connection layers that are arranged on a first surface of the semiconductor body that faces away from the substrate. | 2010-09-16 |
20100230699 | LIGHT EMITTING DEVICE - A light emitting device including a light emitting structure having a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; a first electrode on the light emitting structure; and a photon escape layer on the light emitting structure. Further, the photon escape layer has a refractive index that is between a refractive index of the light emitting structure and a refractive index of an encapsulating material with respect to the light emitting structure such that an escape probability for photons emitted by the light emitting structure is increased. | 2010-09-16 |
20100230700 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package is provided. The light emitting device package may include a package body having a cavity formed therein, a lead frame, and a light emitting device positioned in the cavity and electrically connected to the lead frame. The lead frame may penetrate the package body such that one end of the lead frame is positioned in the cavity and the other end of the lead frame is exposed to an outside of the package body. The lead frame may be partially coated with a thin metal layer. | 2010-09-16 |
20100230701 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM INCLUDING THE SAME - A light emitting device, a light emitting device package and a lighting system including the same are provided. The light emitting device may include a light emitting structure, a dielectric pattern, a second electrode layer, and a resonator structure. The light emitting structure may include a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer. The dielectric pattern may be disposed on the second conductive type semiconductor layer. The second electrode layer may be disposed on the second conductive type comprising the dielectric pattern. The resonator structure may be disposed on the light emitting structure. | 2010-09-16 |
20100230702 | LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME, LIGHT EMITTING APPARATUS, AND LIGHTING SYSTEM - Disclosed is a light emitting device including a conductive substrate; a reflective layer on the conductive substrate; an etching protective layer on a peripheral portion of a top surface of the conductive substrate; and a light emitting structure, which is formed on the reflective layer and the etching protective layer such that the etching protective layer is partially exposed and includes a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer between the first and second conductive semiconductor layers, wherein the etching protective layer includes a first refractive layer having a first refractive index and a second refractive layer having a second refractive index greater than the first refractive index. | 2010-09-16 |
20100230703 | LIGHT EMITTING DEVICE FABRICATION METHOD THEREOF, AND LIGHT EMITTING APPARATUS - A light emitting device is provided. The light emitting device comprises a conductive substrate, a reflection layer, a support layer, an ohmic contact layer, and a light emitting semiconductor layer. The reflection layer is disposed on the conductive substrate. The support layer is disposed partially on the reflection layer. The ohmic contact layer is disposed at the side of the support layer. The light emitting semiconductor layer is disposed on the ohmic contact layer and the support layer. | 2010-09-16 |
20100230704 | LIGHT EMITTING APPARATUS, AND METHOD FOR MANUFACTURING THE SAME, AND LIGHTING SYSTEM - A light emitting apparatus includes: a substrate including a first conductive type impurity; a first heatsink and a second heatsink on a first region and a second region of the substrate; second conductive type impurity regions on the substrate and electrically connected to the first heatsink and the second heatsink, respectively; a first electrode electrically connected to the first heatsink on the substrate; a second electrode electrically connected to the second heatsink on the substrate; and a light emitting device electrically connected to the first electrode and the second electrode on the substrate. | 2010-09-16 |
20100230705 | LIGHT EMITTING DEVICE, METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE, AND LIGHT EMITTING APPARATUS - A light emitting device according to the embodiment includes a reflecting layer; an adhesion layer including an oxide-based material on the reflecting layer; an ohmic contact layer on the adhesion layer; and a light emitting structure layer on the ohmic contact layer. | 2010-09-16 |
20100230706 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - The invention discloses a semiconductor light-emitting device, which includes a substrate, a first conductive type semiconductor material layer, a second conductive type semiconductor material layer, a light-emitting layer, a first electrode, a second electrode, and a plurality of bump structures. The first conductive type semiconductor material layer is formed on the substrate and has an upper surface which includes a first region and a second region distinct from the first region. The first electrode is formed on the first region. The light-emitting layer and the second conductive type semiconductor material layer are formed on the second region. The bump structures are formed on the upper surface of the first conductive type semiconductor material layer and between the first region and the second region. At least one recess is formed in the sidewall of each bump structure. Alternatively, the sidewall of each bump structure has a curved contour. | 2010-09-16 |
20100230707 | LIGHT-EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF - An LED package is provided. The LED package comprises a metal plate, circuit patterns, and an LED. The metal plate comprises grooves. The insulating layer is formed on the metal plate. The circuit patterns are formed on the insulating layer. The LED is electrically connected with the circuit pattern on the insulating layer. | 2010-09-16 |
20100230708 | Leadframe package for light emitting diode device - An LED leadframe package with surface tension function to enable the production of LED package with convex lens shape by using dispensing method is disclosed. The LED leadframe package of the invention is a PPA supported package house for LED packaging with metal base, four identical metal electrodes, and PPA plastic to fix the metal electrodes and the heat dissipation base together, four ring-alike structures with a sharp edge and with a tilted inner surface, and three ring-alike grooves formed between sharp edge ring-alike structures. | 2010-09-16 |
20100230709 | Optical semiconductor device, socket, and optical semiconductor unit - An optical semiconductor unit of the present invention has an LED device provided with an LED (Light Emitting Diode) and a socket to which the LED device is mounted, the LED device has a main body to which the LED is mounted, the main body has a first surface to which block-shaped electrode portions are connected. | 2010-09-16 |
20100230710 | LIGHT EMITTING DEVICE PACKAGE - Embodiments include a light emitting device package. The light emitting device package comprises a housing including a cavity; a light emitting device positioned in the cavity; a lead frame including a first section electrically connected to the light emitting device in the cavity, a second section, which penetrates the housing, extending from the first section and a third section, which is exposed to outside air, extending from the second section; and a metal layer positioned on an area defined by a distance which is distant from the housing in the second section of the lead frame. | 2010-09-16 |
20100230711 | FLIP-CHIP SEMICONDUCTOR OPTOELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating flip-chip semiconductor optoelectronic devices initially flip-chip bonds a semiconductor optoelectronic chip attached to an epitaxial substrate to a packaging substrate. The epitaxial substrate is then separated using lift-off technology. | 2010-09-16 |
20100230712 | LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a light emitting device and a method of fabricating the same. The light emitting device comprises a first conductive type substrate, first to fourth metal electrodes, and a light emitting diode. The first conductive type substrate comprises P-N junction first to fourth diodes. The first metal electrode is connected to the first diode and the fourth diode. The second metal electrode is connected to the third diode and the second diode. The third metal electrode is connected to the first diode and the third diode. The fourth metal electrode is connected to the second diode and the fourth diode. The light emitting diode is electrically connected to the third metal electrode and the fourth metal electrode. | 2010-09-16 |
20100230713 | SEMICONDUCTOR LIGHT EMITTING ELEMENT, GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SUCH GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE - An object of the present invention is to obtain, with respect to a semiconductor light-emitting element using a group III nitride semiconductor substrate, a semiconductor light-emitting element having an excellent light extraction property by selecting a specific substrate dopant and controlling the concentration thereof. The semiconductor light-emitting element comprises a substrate composed of a group III nitride semiconductor comprising germanium (Ge) as a dopant, an n-type semiconductor layer composed of a group III nitride semiconductor formed on the substrate, an active layer composed of a group III nitride semiconductor formed on the n-type semiconductor layer, and a p-type semiconductor layer composed of a group III nitride semiconductor formed on the active layer in which the substrate has a germanium (Ge) concentration of 2×10 | 2010-09-16 |
20100230714 | METHOD FOR PRODUCING GALLIUM NITRIDE BASED COMPOUND SEMICONDUCTOR LIGHT EMITTING DEVICE, GALLIUM NITRIDE BASED COMPOUND SEMICONDUCTOR LIGHT EMITTING DEVICE, AND LAMP USING THE SAME - A method for producing a gallium nitride based compound semiconductor light emitting device that is excellent in terms of light emission efficiency and is also capable of operating at a low driving voltage, a gallium nitride based compound semiconductor light emitting device, and a lamp using the device are provided, and the method for producing a gallium nitride based compound semiconductor light emitting device includes a first crystal growth step in which an n-type semiconductor layer | 2010-09-16 |
20100230715 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor body with a semiconductor device structure including at least a first electrode and a second electrode. Between the two electrodes, a drift region is arranged, the drift region including charge compensation zones and drift zones arranged substantially parallel to one another. At least one charge carrier storage region which is at least partially free of charge compensation zones is arranged in the semiconductor body. | 2010-09-16 |
20100230716 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a drift layer of a first conductivity type; a base layer of a second conductivity type provided on the drift layer; an emitter layer of the first conductivity type provided in part of an upper portion of the base layer; a buffer layer of the first conductivity type provided below the drift layer; a high-resistance layer of the first conductivity type provided below the buffer layer; a collector layer of the second conductivity type provided in a partial region on a lower surface of the high-resistance layer; a contact layer of the first conductivity type provided in another partial region on the lower surface of the high-resistance layer; a trench gate electrode extending through the emitter layer and the base layer into the drift layer; and a gate insulating film provided between the emitter layer, the base layer, and the drift layer on one hand and the trench gate electrode on the other. | 2010-09-16 |
20100230717 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer of non-doped Al | 2010-09-16 |
20100230718 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE - A semiconductor device has a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type complementary to the first conductivity type arranged in or on the first semiconductor layer. Further, the semiconductor device has a region of the first conductivity type arranged in the second semiconductor layer. A first electrode contacts the region of the first conductivity type and the second semiconductor layer. A first trench extends into the first semiconductor layer, and a voltage dependent short circuit diverter structure includes electrically conductive material arranged in the first trench and coupled to the first electrode and a highly-doped diverter region of the second conductivity type. The diverter region of the voltage dependent short circuit diverter structure has the second conductivity type and is arranged to provide a diverter channel region of the second conductivity type between the diverter region and the second semiconductor layer in the event of a short circuit. | 2010-09-16 |
20100230719 | ESD PROTECTION ELEMENT - In an aspect of the present invention, an ESD (Electrostatic Discharge) protection element includes a bipolar transistor comprising a collector diffusion layer connected with a first terminal and an emitter diffusion layer; and current control resistances provided for a plurality of current paths from a second terminal to the collector diffusion layer through the emitter diffusion layer, respectively. The bipolar transistor further includes a base diffusion region connected with the second terminal through a first resistance which is different from the current control resistances. | 2010-09-16 |
20100230720 | SEMICONDUCTOR DEVICE AND METHOD - The present invention is directed to a semiconductor device that includes at least one p-n junction including a p-type material, an n-type material, and a depletion region. The at least one p-n junction is configured to generate bulk photocurrent in response to incident light. The at least one p-n junction is characterized by a conduction band energy level, a valence band energy level and a surface Fermi energy level. The surface Fermi energy level is pinned either near or above the conduction band energy level or near or below the valence band energy level. A unipolar barrier structure is disposed in a predetermined region within the at least one p-n junction. The unipolar barrier is configured to raise the conduction band energy level if the surface Fermi energy level is pinned near or above the conduction band energy level or lower the valence band energy level if the surface Fermi energy level is pinned near or below the valence band energy level such that the unipolar barrier is configured to propagate the bulk photocurrent and substantially block surface leakage current. The at least one p-n junction and the unipolar barrier are integrally formed. | 2010-09-16 |
20100230721 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device may include a gate electrode formed on a gate insulation film on a main surface of a semiconductor substrate of a first conductivity type; source/drain regions formed to sandwich a channel region formed below the gate electrode, the source/drain regions having a structure in which a first semiconductor layer and a second semiconductor layer are stacked in this order, the first semiconductor layer containing a first element and an impurity of a second conductivity type that are forgiving strain to the channel region, and containing a second element that is for suppressing a diffusion of the impurity of the second conductivity type, the second semiconductor layer containing the first element and the impurity of the second conductivity type; and source/drain extension regions adjacent to the channel region, the extension regions extending respectively from the second semiconductor layers. | 2010-09-16 |
20100230722 | HIGH ELECTRON MOBILITY FIELD EFFECT TRANSISTOR (HEMT) DEVICE - A High Electron Mobility Transistor (HEMT) device, which is formed by connecting a plurality of low power flip-chip type High Electron Mobility Transistor (HEMT) elements in parallel, or connected them in parallel and in series in combination into a tree-shaped structure, and then connecting said structure to an input terminal and an output terminal. Distances between each of the flip-chip type HEMT elements, from each element to said input terminal, and from each element to said output terminal are designed to be equal, such that powers consumed by each of the flip-chip type HEMT elements are equal, currents flowing through are evenly distributed, and heat generated is liable to be dissipated. A spike leakage protection layer, such as zinc-oxide (ZnO) amorphous layer or poly-crystal layer, is further included, hereby further enhancing the efficiency of said flip-chip type HEMT element and prolonging its service life. | 2010-09-16 |
20100230723 | High Electron Mobility Transistor, Field-Effect Transistor, and Epitaxial Substrate - Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor ( | 2010-09-16 |
20100230724 | METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES, AND RELATED STRUCTURES - Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods, for example. | 2010-09-16 |
20100230725 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a semiconductor integrated circuit device, a plurality of electrode pads for external connection are arranged in a zigzag pattern. Some electrode pads of the electrode pads of the plurality of I/O cells which are closer to a side of the semiconductor chip, each have an end portion closer to the side of the semiconductor chip, the end portion being set at the same position as that of an end portion of the corresponding I/O cell. A power source-side protective circuit and a ground-side protective circuit against discharge of static electricity are provided with the power source-side protective circuit being closer to the scribe region. A distance between a center position of one of the electrode pads and the ground-side protective circuit of the corresponding I/O cell and a distance between a center position of the other one electrode pad and the ground-side protective circuit of the corresponding I/O cell are both short and are substantially equal between each I/O cell. | 2010-09-16 |
20100230726 | POWER LINE LAYOUT TECHNIQUES FOR INTEGRATED CIRCUITS HAVING MODULAR CELLS - An integrated circuit (IC) chip includes a first memory cell array block having a first metal layer containing at least two power lines, and a second memory cell array block containing at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first memory cell array block do not extend into the second memory cell array block, and all the power lines on the first metal layer serving the second memory cell array block do not extend into the first memory cell array block. | 2010-09-16 |
20100230727 | Electric Circuit with Vertical Contacts - An electrical circuit includes at least two unit cells configured on a planar substrate which extends in one plane. The unit cells respectively have at least two contact points with a different function and include at least one dielectric layer disposed on the substrate and/or on the unit cells and at least two contact surfaces which are disposed parallel to the plane above the contact points and/or the substrate. The contact points with the same function are connected electrically to at least one common contact surface for at least a part of the contact points of the same function via at least one through-contacting through the dielectric layer and able to be contacted in common from outside via the corresponding contact surfaces. | 2010-09-16 |
20100230728 | MANUFACTURING METHOD OF PHOTOELECTRIC CONVERSION DEVICE - A noise generated by a constitution of widening an incident aperture of light of a photoelectric conversion element is reduced. In a manufacturing method of a photoelectric conversion device, first electroconductor arranged in a first hole arranged in the first interlayer insulation layer electrically connects a first semiconductor region to a gate electrode of an amplifying MOS transistor not through wirings included in a wiring layer. Moreover, a second electroconductor electrically connects a second semiconductor region different from the first semiconductor region to a wiring. In a constitution of that second electroconductor, a third electroconductor arranged in a second hole arranged in the first interlayer insulation layer and a fourth electroconductor arranged in a third hole arranged in the second interlayer insulation layer are stacked and electrically connected to each other. And the step of forming the first electroconductor, and the step of forming the third electroconductor are performed simultaneously. | 2010-09-16 |
20100230729 | PIXEL SENSOR CELL INCLUDING LIGHT SHIELD - CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate | 2010-09-16 |
20100230730 | SOLID-STATE IMAGING DEVICE AND IMAGING APPARATUS - A solid-state imaging device includes: an imaging region including a plurality of light-receiving parts; a first transfer section provided on the imaging region and transferring, in a first direction, signals generated by the light-receiving parts; a second transfer section provided at a first side of the imaging region and transferring, in a second direction intersecting the first direction, the signals transferred from the first transfer section; an output circuit for outputting the signals; and bonding pads provided at the first side of the imaging region with the second transfer section sandwiched between the imaging region and the bonding pads. The bonding pads are arranged in a plurality of rows each extending in the second direction. Each of the bonding pads in one of the rows at least partially overlaps one of the bonding pads in another one of the rows when viewed in the first direction. | 2010-09-16 |
20100230731 | Circuitry and method - An electrochemical transistor device is provided, comprising a source contact, a drain contact, at least one gate electrode, an electrochemically active element arranged between, and in direct electrical contact with, the source and drain contacts, which electrochemically active element comprises a transistor channel and is of a material comprising an organic material having the ability of electrochemically altering its conductivity through change of redox state thereof, and a solidified electrolyte in direct electrical contact with the electrochemically active element and said at least one gate electrode and interposed between them in such a way that electron flow between the electrochemically active element and said gate electrode(s) is prevented. In the device, flow of electrons between source contact and drain contact is controllable by means of a voltage applied to said gate electrode(s). | 2010-09-16 |
20100230732 | FIELD EFFECT TRANSISTOR WITH AIR GAP DIELECTRIC - A field effect transistor (FET) that includes a drain formed in a first plane, a source formed in the first plane, a channel formed in the first plane and between the drain and the source and a gate formed in the first plane. The gate is separated from at least a portion of the body by an air gap. The air gap is also in the first plane. | 2010-09-16 |
20100230733 | VERTICAL GATED ACCESS TRANSISTOR - According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of shallow trenches and the plurality of deep trenches are parallel to each other. The method further comprises depositing a layer of conductive material over the first region and a second region of the substrate. The method further comprises etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate. The method further comprises masking the second region of the substrate. The method further comprises removing the plurality of lines from the first region of the substrate, thereby creating a plurality of exposed areas from which the plurality of lines were removed. The method further comprises etching a plurality of elongate trenches in the plurality of exposed areas while the second region of the substrate is masked. | 2010-09-16 |
20100230734 | SEMICONDUCTOR DEVICE AND ARRANGEMENT METHOD OF COMPENSATION CAPACITOR OF SEMICONDUCTOR DEVICE - A semiconductor device comprises a circuit cell and a basic end cell. The circuit cell includes a plurality of elements aligned in a first direction, and the basic end cell is arranged adjacent to the circuit cell in the first direction and has a compensation capacitor capable of being connected to a supply voltage of the circuit cell. In the semiconductor device, a diffusion layer forming the compensation capacitor extends along the first direction in a predetermined region of the circuit cell. | 2010-09-16 |
20100230735 | Deep Trench Capacitor on Backside of a Semiconductor Substrate - A pair of through substrate vias is formed through a stack including a lightly doped semiconductor and a bottom semiconductor layer in a semiconductor substrate. The top semiconductor layer includes semiconductor devices such as field effect transistors. At least one deep trench is formed on the backside of the semiconductor substrate in the bottom semiconductor layer and at least one dielectric layer thereupon. A node dielectric and a conductive inner electrode are formed in each of the at least one deep trench. Substrate contact vias abutting the bottom semiconductor layer are also formed in the at least one dielectric layer. Conductive wiring structures on the backside of the semiconductor substrate provide lateral connection between the through substrate vias and the at least one conductive inner electrode and the substrate contact vias. | 2010-09-16 |
20100230736 | High Voltage Deep Trench Capacitor - A semiconductor process and apparatus provide a high voltage deep trench capacitor structure ( | 2010-09-16 |
20100230737 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device comprises forming a first layer on an impurity diffusion region in a semiconductor substrate by a selective epitaxial growth method, forming a second layer on the first layer by the selective epitaxial growth method, forming a contact hole penetrating an interlayer insulating film in a thickness direction thereof and reaching the second layer, and filling a conductive material into the contact hole to form a contact plug including the first and second layers and the conductive material. | 2010-09-16 |
20100230738 | NOR FLASH MEMORY STRUCTURE WITH HIGHLY-DOPED DRAIN REGION AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a NOR flash memory structure, a highly-doped ion implantation process is performed to form a highly-doped drain region to overlap with a lightly-doped drain region. Therefore, the flash memory structure can have a reduced drain junction depth to improve the short channel effect while protecting the lightly-doped drain region from being punched through during an etching process for forming a contact hole. | 2010-09-16 |
20100230739 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROCESS OF MANUFACTURING THE SAME - In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film. | 2010-09-16 |
20100230740 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - First and second memory cells have first and second channels, first and second tunnel insulating films, first and second charge storage layers formed of an insulating film, first and second block insulating films, and first and second gate electrodes. A first select transistor has a third channel, a first gate insulating film, and a first gate electrode. The first channel includes a first-conductivity-type region and a second-conductivity-type region which is formed on at least a part of the first-conductivity-type region and whose conductivity type is opposite to the first conductivity type. The third channel includes the first-conductivity-type region and the second-conductivity-type region formed on the first-conductivity-type region. The number of data stored in the first memory cell is smaller than that of data stored in the second memory cell. | 2010-09-16 |
20100230741 | SEMICONDUCTOR DEVICES WITH AN AIR GAP IN TRENCH ISOLATION DIELECTRIC - A tunnel insulating layer and a charge storage layer are sequentially stacked on a substrate. A recess region penetrates the charge storage layer, the tunnel insulating layer and a portion of the substrate. The recess region is defined by a bottom surface and a side surface extending from the bottom surface. A first dielectric pattern includes a bottom portion covering the bottom surface and inner walls extending from the bottom portion and covering a portion of the side surface of the recess region. A second dielectric pattern is in the recess region between the inner walls of the first dielectric pattern, and the second dielectric pattern enclosing an air gap. The air gap that is enclosed by the second dielectric pattern may extend through a major portion of the second dielectric pattern in a direction away from the bottom surface of the recess region. | 2010-09-16 |
20100230742 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a plurality of memory cell regions including a plurality of bit lines, a plurality of word lines intersecting the plurality of bit lines, and a first insulating film formed in a region between any two adjacent bit lines, a bit line contact region including bit line contacts connected to the plurality of bit lines, a first UV light shielding film covering at least a portion of the semiconductor substrate in the bit line contact region, an interlayer insulating film, and a second UV light shielding film covering the plurality of memory cell regions. The first UV light shielding film effectively reduces or blocks UV light generated during a fabrication step. | 2010-09-16 |
20100230743 | SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH FOR FLASH MEMORY AND OTHER SEMICONDUCTOR APPLICATIONS - A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer. | 2010-09-16 |
20100230744 | RELIABLE MEMORY CELL - A method of forming a semiconductor device is presented. A substrate prepared with a second gate is provided. The second gate is processed to form a second gate with a rounded corner and a first gate is formed on the substrate. The first gate is adjacent to and overlaps a portion of the second gate and the rounded corner. | 2010-09-16 |
20100230745 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device according to an embodiment of the present invention includes a first semiconductor layer of a first or second conductivity type, a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, a third semiconductor layer of the second conductivity type selectively formed on a surface of the second semiconductor layer, at least one trench formed in a periphery of the third semiconductor layer on the surface of the second semiconductor layer, a depth of a bottom surface of the at least one trench being deeper than a bottom surface of the third semiconductor layer, and shallower than a top surface of the first semiconductor layer, and some or all of the at least one trench being in contact with a side surface of the third semiconductor layer, at least one insulator buried in the at least one trench, a first main electrode electrically connected to the first semiconductor layer, and a second main electrode electrically connected to the third semiconductor layer. | 2010-09-16 |
20100230746 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an epitaxial layer having a first conduction type, a base layer formed adjacent and on the epitaxial layer and having an opposite second conduction type to the first conduction type, a source layer formed selectively on the base layer and having the first conduction type, a trench which passes through the base layer and the source layer and which reaches the epitaxial layer, an insulation film formed along an interior wall of the trench, a control electrode formed within the trench via the insulation film, and a semiconductor region formed along the bottom part of the trench at the epitaxial layer and having the first conduction type. | 2010-09-16 |
20100230747 | PROCESS FOR MANUFACTURING A POWER DEVICE WITH A TRENCH-GATE STRUCTURE AND CORRESPONDING DEVICE - An embodiment for realizing a power device with trench-gate structure integrated on a semiconductor substrate, and including etching the semiconductor substrate to make a first trench having first side walls and a first bottom; and further etching said semiconductor substrate to make a second trench inside the first trench, realized in a self-aligned way and below this first trench, the first trench and the second trench defining the trench-gate structure with a bird beak-like transition profile suitable for containing a gate region. | 2010-09-16 |
20100230748 | Semiconductor device and method of manufacturing the same - A high breakdown voltage MOS transistor capable of reducing a leakage current while reducing an element size as compared with conventional ones is realized. On a P type well, with a channel area ch in between, an N type first impurity diffusion area including a drain area and drain side drift area, and an N type second impurity diffusion area including a source area and a source side drift area are formed. Moreover, a gate electrode is formed, via a gate oxide film, above a part of the first impurity diffusion area, above the channel area and above a part of the second impurity diffusion area. The gate electrode is doped with an N type, and an impurity concentration of portions located above the first and the second impurity diffusion areas is lower than an impurity concentration of a portion located above the channel area. | 2010-09-16 |
20100230749 | SEMICONDUCTOR DEVICES AND FORMATION METHODS THEREOF - A semiconductor device is provided and includes a substrate of a first conductivity type, a deep well of a second conductivity type, and a first high-side device. The deep well is formed on the substrate. The first high-side device is disposed within the deep well and includes an insulation layer of the second conductivity type, a well of the first conductivity type, first and second regions of the second conductivity type, and a first poly-silicon material. The insulation layer is formed on the substrate. The well is formed within the deep well. The first and second regions are formed within the well. The first poly-silicon material is disposed between the first region and the second region and on the deep well. | 2010-09-16 |
20100230750 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type formed on the first semiconductor layer and alternately arranged along at least one direction parallel to a surface of the first semiconductor layer; a first main electrode; a fourth semiconductor layer of the second conductivity type selectively formed in a surface of the second semiconductor layer and a surface of the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively formed in a surface of the fourth semiconductor layer; a second main electrode; and a control electrode. At least one of the second and the third semiconductor layers has a dopant concentration profile along the one direction, the dopant concentration profile having a local minimum at a position except both ends thereof. | 2010-09-16 |
20100230751 | SELF-ALIGNED SCHOTTKY DIODE - A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of a first conductivity type, which is the opposite of the second conductivity type, on one side of a dummy gate electrode and a Schottky barrier structure surrounded by the doped guard ring on the other side. A Schottky barrier region may be laterally surrounded by the dummy gate electrode and the doped guard ring. The doped guard ring includes an unmetallized portion of a gate-side second-conductivity-type-doped semiconductor region having a doping of a second conductivity type. A Schottky barrier region may be laterally surrounded by a doped guard ring including a gate-side doped semiconductor region and a STI-side doped semiconductor region. Design structures for the inventive Schottky barrier diode are also provided. | 2010-09-16 |
20100230752 | SOI (SILICON ON INSULATOR) SUBSTRATE IMPROVEMENTS - A structure, and a method for forming the same. The structure includes a semiconductor substrate which includes a top substrate surface, a buried dielectric layer on the top substrate surface, N active semiconductor regions on the buried dielectric layer, N active devices on the N active semiconductor regions, a plurality of dummy regions on the buried dielectric layer, a protection layer on the N active devices and the N active semiconductor regions, but not on the plurality of dummy regions. The N active devices comprise first active regions which comprise a first material. The plurality of dummy regions comprise first dummy regions which comprise the first material. A first pattern density of the first active regions and the first dummy regions is uniform across the structure. A trench in the buried dielectric layer such that side walls of the trench are aligned with the plurality of dummy regions. | 2010-09-16 |
20100230753 | LATERAL HYPERABRUPT JUNCTION VARACTOR DIODE IN AN SOI SUBSTRATE - A varactor diode includes a portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate and a gate electrode located thereupon. A first electrode having a doping of a first conductivity type laterally abuts a doped semiconductor region having the first conductivity type, which laterally abuts a second electrode having a doping of a second conductivity type, which is the opposite of the first conductivity type. A hyperabrupt junction is formed between the second doped semiconductor region and the second electrode. The gate electrode controls the depletion of the first and second doped semiconductor regions, thereby varying the capacitance of the varactor diode. A design structure for the varactor diode is also provided. | 2010-09-16 |
20100230754 | Semiconductor Device and Manufacturing Method Thereof - An object is to provide a semiconductor device which solves a problem that can occur when a substrate having an insulating surface is used. The semiconductor device includes a base substrate having an insulating surface; a conductive layer over the insulating surface; an insulating layer over the conductive layer; a semiconductor layer having a channel formation region, a first impurity region, a second impurity region, and a third impurity region provided between the channel formation region and the second impurity region over the insulating layer; a gate insulating layer configured to cover the semiconductor layer; a gate electrode over the gate insulating layer; a first electrode electrically connected to the first impurity region; and a second electrode electrically connected to the second impurity region. The conductive layer is held at a given potential. | 2010-09-16 |
20100230755 | PROCESS FOR PRODUCING AN MOS TRANSISTOR AND CORRESPONDING INTEGRATED CIRCUIT - A silicon substrate (SOI) is placed on a buried oxide layer (BOX). An MOS transistor is produced in an active zone of the substrate which is defined by an isolating region. A gate region and source and drain regions, which between them define a channel, are produced so that the gate region extends above the channel. The isolating region is produced by localized formation of a zone of material that can be selectively etched with respect to silicon. That material is selectively etched, and a dielectric material is deposited in the etched feature. The etching is carried out after the gate region has been produced. An upper surface of the substrate and an upper surface of the isolating region are flush with each other so as to define a planar surface on which the transistor gate region is formed. | 2010-09-16 |
20100230756 | SEMICONDUCTOR DEVICE WITH SELECTIVELY MODULATED GATE WORK FUNCTION - A semiconductor device is provided which comprises a semiconductor layer ( | 2010-09-16 |
20100230757 | Hybrid STI Gap-Filling Approach - A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming an opening extending from the top surface into the semiconductor substrate; and performing a first deposition step to fill a first dielectric material into the opening. The first dielectric material is then recessed. A second deposition step is performed to fill a remaining portion of the opening with a second dielectric material. The second dielectric material is denser than the first dielectric material. The second dielectric material is recessed until a top surface of the second dielectric material is lower than the top surface of the semiconductor substrate. | 2010-09-16 |
20100230758 | SEMICONDUCTOR DEVICE WITH IMPROVED STRESSOR SHAPE - A formation method and resulting strained semiconductor device are provided, the formation method including forming transistors on a substrate, each transistor having a gate disposed over a channel region, etching or annealing an elongated trench between adjacent channel regions, where the trench has a lower boundary that is deeper towards its ends than towards its center, and conformably embedding an elongated stress region in the trench between adjacent channel regions; and the resulting strained semiconductor device including transistors, each having a gate disposed over a channel region, and elongated stress regions disposed between adjacent channel regions, wherein each of the elongated stress regions has a lower boundary that is deeper towards its ends than towards its center. | 2010-09-16 |
20100230759 | Silicon Chip Having Through Via and Method for Making the Same - The present invention relates to a silicon chip having a through via and a method for making the same. The silicon chip includes a silicon substrate, a passivation layer, at least one electrical device and at least one through via. The passivation layer is disposed on a first surface of the silicon substrate. The electrical device is disposed in the silicon substrate, and exposed to a second surface of the silicon substrate. The through via includes a barrier layer and a conductor, and penetrates the silicon substrate and the passivation layer. A first end of the through via is exposed to the surface of the passivation layer, and a second end of the through via connects the electrical device. When a redistribution layer is formed on the surface of the passivation layer, the redistribution layer will not contact the silicon substrate, thus avoiding a short circuit. Therefore, a lower resolution process can be used, which results in low manufacturing cost and simple manufacturing process. | 2010-09-16 |
20100230760 | Silicon Wafer Having Interconnection Metal - The present invention relates to a silicon wafer having interconnection metal. The silicon wafer includes a silicon substrate, at least one electrical device, a barrier layer, a metal layer, at least one first interconnection metal and at least one second interconnection metal. The electrical device is disposed in the silicon substrate, and exposed to a first surface of the silicon substrate. The barrier layer is disposed on the first surface of the silicon substrate. The metal layer is disposed on a surface of the barrier layer. The first interconnection metal penetrates the barrier layer, and is disposed on the electrical device. The first interconnection metal connects the metal layer and the electrical device. The second interconnection metal penetrates the barrier layer, and is disposed at a corresponding position on the outside of the electrical device. The second interconnection metal connects the metal layer. Thus, after a silicon through via is formed, the silicon through via is connected to the metal layer by the second interconnection metal, so the yield rate is raised. | 2010-09-16 |
20100230761 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To improve the performance of semiconductor devices. Over an n | 2010-09-16 |
20100230762 | INTEGRATED CIRCUIT USING FINFETS AND HAVING A STATIC RANDOM ACCESS MEMORY (SRAM) - An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110). | 2010-09-16 |
20100230763 | ACTIVE DEVICE ARRAY SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A method for fabricating an active device array substrate is provided. A first patterned semiconductor layer, a gate insulator, a first patterned conductive layer and a first dielectric layer is sequentially formed on a substrate. First contact holes exposing the first patterned semiconductor layer are formed in the first dielectric layer and the gate insulator. A second patterned conductive layer and a second patterned semiconductor layer disposed thereon are simultaneously formed on the first dielectric layer. The second conductive layer includes contact conductors and a bottom electrode. The second patterned semiconductor layer includes an active layer. A second dielectric layer having second contact holes is formed on the first dielectric layer, wherein a portion of the second contact holes exposes the active layer. A third patterned conductive layer electrically connected to the active layer through a portion of the second contact holes is formed on the second dielectric layer. | 2010-09-16 |
20100230764 | INTEGRATED CIRCUIT HAVING FIELD EFFECT TRANSISTORS AND MANUFACTURING METHOD - An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel. | 2010-09-16 |
20100230765 | INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS MEMORIZATION TRANSFER - An integrated circuit system that includes: a substrate including a source/drain region defined by a spacer; a gate over the substrate; a gate dielectric between the gate and the substrate; a recrystallized region within the gate and the source/drain region; and a channel exhibiting the characteristics of stress memorization. | 2010-09-16 |
20100230766 | SENSOR DEVICE AND METHOD - A sensor device and method. One embodiment provides a first semiconductor chip having a sensing region. A porous structure element is attached to the first semiconductor chip. A first region of the porous structure element faces the sensing region of the first semiconductor chip. An encapsulation material partially encapsulates the first semiconductor chip and the porous structure element. | 2010-09-16 |
20100230767 | MEMS SENSOR, MEMS SENSOR MANUFACTURING METHOD, AND ELECTRONIC DEVICE - An MEMS sensor includes: a movable weight which is connected with a fixed frame via an elastic deformation portion and has a cavity portion around the movable weight, wherein the movable weight has a laminated layer structure including a plurality of conductive layers, a plurality of between-layers insulation layers each of which is disposed between the adjoining conductive layers of the plural conductive layers, and plugs which are inserted into predetermined embedding groove patterns penetrating through the respective layers of the plural between-layers insulation layers and have specific gravity larger than that of the between-layers insulation layers, and the plugs formed on the respective layers have wall portions in wall shapes extending in one or plural longitudinal directions. | 2010-09-16 |
20100230768 | SEMICONDUCTOR DEVICE WITH INTEGRATED PIEZOELECTRIC ELEMENTS AND SUPPORT CIRCUITRY - A semiconductor device suitable for use in a pressure sensor is disclosed. A uniformly thin die is provided by chemically etching a backside of a wafer. Piezoelectric elements formed integrally within the die generate electrical signals in response to flexing the die. Conductive leads formed integrally within the die electrically communicate the generated electrical signals to support circuitry formed integrally within the die proximate the piezoelectric elements. In an example embodiment, the piezoresistive elements take the form of silicon resistors formed integrally via doping and diffusion in a Wheatstone bridge configuration. In one application, the die serves as a deformable diaphragm, seated atop an aperture of a threaded pressure sensor housing. | 2010-09-16 |
20100230769 | Magnetoresistive element, magnetic random access memory and method of manufacturing the same - A magnetoresistive element includes: a lower magnetic layer; a barrier layer; and an upper magnetic layer. The barrier layer is provided on the lower magnetic layer. The upper magnetic layer is provided on the barrier layer. One of magnetization directions of the lower magnetic layer and the upper magnetic layer is fixed. The barrier layer has a first surface which includes a surface contacted with an upper surface of the lower magnetic layer. The upper magnetic layer has a second surface which includes a surface contacted with an upper surface of the barrier layer. Each of the first surface and the second surface is larger than the upper surface of the lower magnetic layer in area. | 2010-09-16 |
20100230770 | MAGNETORESISTIVE ELEMENT AND MAGNETORESISTIVE RANDOM ACCESS MEMORY INCLUDING THE SAME - The present invention provides a low-resistance magnetoresistive element of a spin-injection write type. A crystallization promoting layer that promotes crystallization is formed in contact with an interfacial magnetic layer having an amorphous structure, so that crystallization is promoted from the side of a tunnel barrier layer, and the interface between the tunnel barrier layer and the interfacial magnetic layer is adjusted. With this arrangement, it is possible to form a magnetoresistive element that has a low resistance so as to obtain a desired current value, and has a high TMR ratio. | 2010-09-16 |
20100230771 | METHODS AND ARRANGEMENT FOR DIFFUSING DOPANTS INTO SILICON - A method for diffusing two dissimilar dopant materials onto a semiconductor cell wafer in a single thermal processing step. The method includes placing a first dopant source on a semiconductor cell wafer, placing said cell wafer into a thermal processing chamber comprising one or more cell wafer slots, subjecting said cell wafer to a thermal profile; and annealing said cell wafer in the presence of a second dopant source. | 2010-09-16 |