38th week of 2020 patent applcation highlights part 64 |
Patent application number | Title | Published |
20200294931 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A back alignment mark on a surface of a semiconductor substrate is detected and a resist mask patterned into a circuit pattern corresponding to a surface element structure is formed on a back of the semiconductor substrate. Detection of the back alignment mark is performed by using a detector opposing the back of the semiconductor substrate and measuring contrast based on the intensity of reflected infrared light irradiated from the back of the semiconductor substrate. The back alignment mark is configured by a step formed by the surface of the semiconductor substrate and bottoms of trenches formed from the surface of the semiconductor substrate. A polysilicon film is embedded in the trenches. The back alignment mark has, for example, a cross-shaped planar layout in which three or more trenches are disposed in a direction parallel to the surface of the semiconductor substrate. | 2020-09-17 |
20200294932 | Transmission line structures for III-N devices - IC structures that include transmission line structures to be integrated with III-N devices are disclosed. An example transmission line structure includes a transmission line of an electrically conductive material provided above a stack of a III-N semiconductor material and a polarization material. The transmission line structure further includes means for reducing electromagnetic coupling between the line and charge carriers present below the interface of the polarization material and the III-N semiconductor material. In some embodiments, said means include a shield material of a metal or a doped semiconductor provided over portions of the polarization material that are under the transmission line. In other embodiments, said means include dopant atoms implanted into the portions of the polarization material that are under the transmission line, and into at least an upper portion of the III-N semiconductor material under such portions of the polarization material. | 2020-09-17 |
20200294933 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure is provided, the semiconductor structure includes a front oxide layer on a backside oxide layer, a front electronic component in the front oxide layer, a backside electronic component in the backside oxide layer, and a shield structure disposed between the front oxide layer and the backside oxide layer, the shield structure includes a patterned buried metal layer, two front contact structures disposed on a front surface of the patterned buried metal layer, and two back contact structures disposed on a backside of the patterned buried metal layer. | 2020-09-17 |
20200294934 | SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment includes a semiconductor substrate comprising a first face, and a second face on an opposite side to the first face. A semiconductor element is provided on the first face of the semiconductor substrate. A polycrystalline or non-crystalline first material layer is provided at least on an outer edge of the first face of the semiconductor substrate. A second material layer is provided on the second face of the semiconductor substrate. The second material layer transmits laser light. | 2020-09-17 |
20200294935 | REINFORCED SEMICONDUCTOR DIE AND RELATED METHODS - Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die. | 2020-09-17 |
20200294936 | SEMICONDUCTOR PACKAGE - Some embodiments relate to a semiconductor package. The package includes a redistribution layer (RDL), and a first semiconductor die disposed over the RDL. The first semiconductor die includes a plurality of contact pads electrically coupled to the RDL. The RDL enables fan-out connection of the first semiconductor die. A die package is disposed over the first semiconductor die and over the RDL. The die package is coupled to a first surface of the RDL by a plurality of conductive bump structures. The plurality of conductive bump structures laterally surround the plurality of contact pads and have uppermost surfaces that are level with an uppermost surface of the first semiconductor die. | 2020-09-17 |
20200294937 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - A semiconductor package and a method of forming the same are disclosed. A method of forming a semiconductor package includes the following operations. A polymer layer is formed over a die. A metal feature is formed in the polymer layer. An argon-containing plasma treatment is performed to the polymer layer and the metal feature. | 2020-09-17 |
20200294938 | METHODS TO PATTERN TFC AND INCORPORATION IN THE ODI ARCHITECTURE AND IN ANY BUILD UP LAYER OF ORGANIC SUBSTRATE - Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes. | 2020-09-17 |
20200294939 | THROUGH-SUBSTRATE WAVEGUIDE - Embodiments may relate to a semiconductor package that includes a die and a package substrate. The package substrate may include one or more cavities that go through the package substrate from a first side of the package substrate that faces the die to a second side of the package substrate opposite the first side. The semiconductor package may further include a waveguide communicatively coupled with the die. The waveguide may extend through one of the one or more cavities such that the waveguide protrudes from the second side of the package substrate. Other embodiments may be described or claimed. | 2020-09-17 |
20200294940 | WAVEGUIDE INTERCONNECT FOR PACKAGES - Embodiments may relate to a semiconductor package that includes a package substrate coupled with a die. The package may further include a waveguide coupled with the first package substrate. The waveguide may include two or more layers of a dielectric material with a waveguide channel positioned between two layers of the two or more layers of the dielectric material. The waveguide channel may convey an electromagnetic signal with a frequency greater than 30 gigahertz (GHz). Other embodiments may be described or claimed. | 2020-09-17 |
20200294941 | MICROWAVE INTEGRATED CIRCUIT - Provided is a microwave integrated circuit including: a semiconductor substrate; a plurality of amplification units that are formed in the semiconductor substrate; a wiring that is formed in one layer wiring excluding an uppermost layer wiring and a lowermost layer wiring among a plurality of layer wirings formed on the semiconductor substrate and is used for supplying power to the plurality of amplification units; and a plurality of vias that connect a plurality of conductive regions formed in the layer wiring with the wiring interposed therebetween and other conductive regions formed in a region interposing the wiring in the two layer wirings immediately above and immediately below the layer wiring, in which each of the plurality of vias forms a via structure connected to the conductive regions of the lowermost layer wiring by a plurality of other vias. | 2020-09-17 |
20200294942 | METHOD AND APPARATUS FOR HEAT SINKING HIGH FREQUENCY IC WITH ABSORBING MATERIAL - A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and integrated circuits on the laminar substrate. Each integrated circuit is a high frequency integrated circuit configured to control receipt and/or transmission of signals by the plurality of elements in the patch phased array. In addition, each integrated circuit has a substrate side coupled with the laminar substrate, and a back side. The phased array also has a plurality of heat sinks. Each integrated circuit is coupled with at least one of the heat sinks. At least one of the integrated circuits has a thermal interface material in conductive thermal contact with its back side. The thermal interface material thus is between the at least one integrated circuit and one of the heat sinks. Preferably, the thermal interface material has a magnetic loss tangent value of between 0.5 and 4.5. | 2020-09-17 |
20200294943 | INTEGRATED FAN-OUT PACKAGE - An integrated fan-out (InFO) package includes a plurality of dies, an encapsulant, an insulating layer, a redistribution structure, a plurality of conductive structures, an antenna confinement structure, and a slot antenna. The encapsulant laterally encapsulates the dies. The insulating layer is disposed over the dies and the encapsulant. The redistribution structure is sandwiched between the insulating layer and the dies. The conductive structures and the antenna confinement structure are embedded in the insulating layer. The slot antenna is disposed on the insulating layer. | 2020-09-17 |
20200294944 | PACKAGE STRUCTURE - A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer. | 2020-09-17 |
20200294945 | APPARATUSES INCLUDING REDISTRIBUTION LAYERS AND RELATED MICROELECTRONIC DEVICES - A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two. | 2020-09-17 |
20200294946 | FINNED CONTACT - A finned contact of an IC device may be utilized to electrically connect the IC device to external circuitry. The finned contact may be fabricated by forming a base upon the IC device and subsequently forming two or more fins upon the base. Each fin may be formed of the same and/or different material(s) as the base. Each fin may include layer(s) of one or materials. The fins may be located upon the base inset from the sidewall(s) of the base. The fins may be arranged as separated ring portions that are concentric with the base. The fins may drive current into the external circuitry connected thereto. Solder may be drawn towards the center of the base within an inner void that is internal to the fins, thereby limiting the likelihood of solder bridging with a neighboring contact. | 2020-09-17 |
20200294947 | ELECTRONIC COMPONENT - A electronic component includes a connection electrode on a wiring layer. An electrically conductive layer is connected to the wiring layer via the connection electrode. A protective film covers a cover portion and the electrically conductive layer. A solder bump is electrically connected to the electrically conductive layer via an opening. An alloy layer is between the solder bump and the electrically conductive layer in a thickness direction to join the solder bump to the electrically conductive layer and differs in composition and/or elements from the solder bump. The connection electrode does not overlap the solder bump. The surface of the electrically conductive layer that is located on a protective film side is in contact with the protective film between the alloy layer and an edge of the electrically conductive layer that is located on a connection electrode side. | 2020-09-17 |
20200294948 | FLIP CHIP PACKAGE UTILIZING TRACE BUMP TRACE INTERCONNECTION - A flip chip package includes a substrate having a die attach surface, and a die mounted on the die attach surface with an active surface of the die facing the substrate. The die includes a base, a passivation layer overlying the base, a topmost metal layer overlying the passivation, and a stress buffering layer overlying the topmost metal layer, wherein at least two openings are disposed in the stress buffering layer to expose portions of the topmost metal layer. The die is interconnected to the substrate through a plurality of conductive pillar bumps on the active surface. At least one of the conductive pillar bumps is electrically connected to one of the exposed portions of the topmost metal layer through one of the at least two openings. | 2020-09-17 |
20200294949 | HOTSPOT THERMAL MANAGEMENT OF POWER ELECTRONIC PACKAGE WITH NANO DIE ATTACH MATERIAL - Embodiments herein are directed to semiconductor package assemblies and methods of forming. In some embodiments, a semiconductor package assembly includes a substrate, a first metallization layer disposed adjacent the substrate, and a semiconductor die disposed in thermal contact with the first metallization layer. The semiconductor package assembly may further include a die attach layer disposed between the semiconductor die and the first metallization layer, the die attach layer including a polymer matrix and a nano-metal particle filler. | 2020-09-17 |
20200294950 | METHOD FOR THE MANUFACTURE OF INTEGRATED DEVICES INCLUDING A DIE FIXED TO A LEADFRAME - A method for soldering a die obtained using the semiconductor technique with a leadframe, comprising the steps of providing a leadframe, which has at least one surface made at least partially of copper; providing a die, which has at least one surface coated with a metal layer; applying to the surface a solder alloy comprising at least 40 wt % of tin or at least 50% of indium or at least 50% of gallium, without lead, and heating the alloy to a temperature of at least 380° C. to form a drop of solder alloy; providing a die, which has at least one surface coated with a metal layer; and setting the metal layer in contact with the drop of solder alloy to form the soldered connection with the leadframe. Moreover, a device obtained with said method is provided. | 2020-09-17 |
20200294951 | SHEET FOR SINTERING BONDING AND SHEET FOR SINTERING BONDING WITH BASE MATERIAL - To provide a sheet for sintering bonding and a sheet for sintering bonding with a base material that are suited for properly supplying a material for sintering bonding to a face planned to be bonded of a bonding object. A sheet for sintering bonding | 2020-09-17 |
20200294952 | SHEET FOR SINTERING BONDING, SHEET FOR SINTERING BONDING WITH BASE MATERIAL, AND SEMICONDUCTOR CHIP WITH LAYER OF MATERIAL FOR SINTERING BONDING - A sheet for sintering bonding | 2020-09-17 |
20200294953 | SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREFOR - A semiconductor module is provided, including: a semiconductor chip having an upper surface electrode and a lower surface electrode opposite to the upper surface electrode; a metal wiring plate electrically connected to the upper surface electrode of the semiconductor chip; and a sheet-like low elastic sheet provided on the metal wiring plate, the low elastic sheet having elastic modulus lower than that of the metal wiring plate. A manufacturing method for a semiconductor module is provided, including: providing a semiconductor chip; solder-bonding a metal wiring plate above said semiconductor chip; and applying a sheet-like low elastic sheet having the elastic modulus lower than that of said metal wiring plate to said metal wiring plate. | 2020-09-17 |
20200294954 | ELECTRONIC DEVICE - The electronic device includes first and second semiconductor components. And, the electronic device includes a sealing body for sealing the first semiconductor component (i.e., the logic chip). A plurality of through conductors electrically connected to the first semiconductor component and/or the second semiconductor component is formed in the sealing body. In plan view, the sealing body has a first region in which the first semiconductor component is located, a second region located on a periphery of a first surface of the sealing body, a third region located between the second region and the first region, and a fourth region located between the second region and the third region. The plurality of through conductors is arranged most in the second region. The number of the plurality of through conductors located in the third region is larger than the number of the plurality of through conductors located in the fourth region. | 2020-09-17 |
20200294955 | PACKAGE STRUCTURES AND METHODS OF FORMING THE SAME - A package structure includes a first die, at least one second die, a semiconductor substrate and a glue layer. The semiconductor substrate includes no active devices. The glue layer is disposed between the at least one second die and the semiconductor substrate. The glue layer has a top surface adhered to the least one second die and a bottom surface adhered to a topmost surface of the semiconductor substrate. A total area of the bottom surface of the glue layer is substantially equal to a total area of the topmost surface of the semiconductor substrate, and a total thickness of the first die is substantially equal to only a total thickness of the at least one second die, the semiconductor substrate and the glue layer. | 2020-09-17 |
20200294956 | Arrangement and Method for Joining at Least Two Joining Partners - An arrangement for joining two joining members includes a first part having a support surface, a first carrier element configured to carry at least one foil, a transportation unit configured to arrange the first carrier element such that the foil is arranged above the support surface in a vertical direction, and a second part configured to exert pressure to a joining stack, when the joining stack is arranged on the support surface. The joining stack includes a first joining member arranged on the support surface, a second joining member, and an electrically conductive connection layer arranged between the joining members. When pressure is exerted to the joining stack, the foil is arranged between the second part and the joining stack and is pressed onto the joining stack and the joining stack is pressed onto the first part, compressing the connection layer and forming a substance-to-substance bond between the joining members. | 2020-09-17 |
20200294957 | WIRE BONDING DEVICE, CIRCUIT FOR WIRE BONDING DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention comprises: a spool ( | 2020-09-17 |
20200294958 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a first wafer or a first chip including a first insulator and a first pad. The device further includes a second wafer or a second chip including a second insulator in contact with the first insulator, and a second pad opposed to the first pad and electrically connected to the first pad. Moreover, the first insulator includes a first trench extending to the first pad, and/or the second insulator includes a second trench extending to the second pad. | 2020-09-17 |
20200294959 | SEMICONDUCTOR PACKAGING STRUCTURE AND METHOD OF FABRICATING SAME - A semiconductor packaging structure manufactured in a manner which does not leave the chip damaged or susceptible to damage upon the removal of temporary manufacturing supports includes at least one electrical conductor, at least one conductive layer, a chip, and a colloid. The chip is spaced from the conductive layer, the electrical conductor is disposed between the conductive layer and the chip and electrically connects the conductive layer to the chip. The colloid covers all outer surfaces of the chip. A method of fabricating such a semiconductor packaging structure is also provided. | 2020-09-17 |
20200294960 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to an embodiment, a temperature of an inside of a furnace is set to fall within a range of a reduction temperature or more of a carboxylic acid and less than a melting temperature of a solder bump, and the inside is concurrently set to have a first carboxylic acid gas concentration. Thereafter, the temperature of the inside is raised up to the melting temperature, and the inside is concurrently set to have a second carboxylic acid gas concentration. The second carboxylic acid gas concentration is lower than the first carboxylic acid gas concentration, and is a concentration containing a minimum amount of carboxylic acid gas defined to achieve reduction on an oxide film of the solder bump. The inside has the second carboxylic acid gas concentration at least at a time when the temperature of the inside reaches the melting temperature. | 2020-09-17 |
20200294961 | SHEET FOR SINTERING BONDING AND SHEET FOR SINTERING BONDING WITH BASE MATERIAL - To provide a sheet for sintering bonding and a sheet for sintering bonding with a base material that are suited for being made with a good operational efficiency and that are also suited for realizing a satisfactory operational efficiency in a sintering process in a process of producing a semiconductor device that goes through sintering bonding of semiconductor chips. A sheet for sintering bonding | 2020-09-17 |
20200294962 | Method for Producing a Connection Between Component Parts, and Component Made of Component Parts - A method for producing a connection between component parts and a component made of component parts are disclosed. In an embodiment, a includes providing a first component part having a first exposed insulation layer and a second component part having a second exposed insulation layer, wherein each of the insulation layers has at least one opening, joining together the first and second component parts such that the opening of the first insulation layer and the opening of the second insulation layer overlap in top view, wherein an Au layer and a Sn layer are arranged one above the other in at least one of the openings and melting the Au layer and the Sn layer to form an AuSn alloy, wherein the AuSn alloy forms a through-via after cooling electrically conductively connecting the first component part to the second component part. | 2020-09-17 |
20200294963 | METHOD OF SEPARATING BONDED SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE DEVICE, AND SUBSTRATE SEPARATION APPARATUS - A method of an embodiment separates a bonded substrate including first and second substrates. The bonded substrate includes a carbon film on a first surface of the first substrate, a memory cell on the carbon film, a first connection terminal on the memory cell, a transistor on a first surface of the second substrate, and a second connection terminal on the transistor. In opposing direction of the first surfaces of the first and second substrates, a side of the first substrate on which the memory cell is located and a side of the second substrate on which the transistor is located are joined together, and the first and second connection terminals are mutually connected. The method includes removing the carbon film, and separating the bonded substrate into the first substrate with the first surface exposed and the second substrate on which the memory cell and the transistor are located. | 2020-09-17 |
20200294964 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package structure includes a conductive structure, a first semiconductor chip, a second semiconductor chip, a first encapsulant and an upper semiconductor chip. The first semiconductor chip is electrically connected to the conductive structure. The first semiconductor chip includes at least one first conductive element disposed adjacent to a second surface thereof. The second semiconductor chip is electrically connected to the conductive structure and disposed next to the first semiconductor chip. The second semiconductor chip includes at least one second conductive element disposed adjacent to a second surface thereof. The first encapsulant is disposed on the conductive structure to cover the first semiconductor chip and the second semiconductor chip. The first conductive element and the second conductive element are exposed from the first encapsulant. The upper semiconductor chip is disposed on the first encapsulant and electrically connected to the first conductive element and the second conductive element. | 2020-09-17 |
20200294965 | DIE STACK STRUCTURE AND METHOD OF FABRICATING THE SAME - A die stack structure includes a first die, a dielectric material layer, a first bonding dielectric layer and a second die. The first die has an active surface and a rear surface opposite to the active surface. The first die includes a through-substrate via (TSV) therein. The TSV protrudes from the rear surface of the first die. The dielectric material layer surrounds and wraps around the first die. The first bonding dielectric layer is disposed on a top surface of the dielectric material layer and the rear surface of the first die and covers the TSV, wherein the TSV penetrates through the first bonding dielectric layer. The second die is disposed on the first die and has an active surface and a rear surface opposite to the active surface. The second die has a second bonding dielectric layer and a conductive feature disposed in the second bonding dielectric layer. The first bonding dielectric layer separates the second bonding dielectric layer from the dielectric material layer, and the first die and the second die are bonded through bonding the second bonding dielectric layer with the first bonding dielectric layer and bonding the conductive feature with the TSV. | 2020-09-17 |
20200294966 | PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - The disclosure provides a method of forming a package structure, and the method includes: bonding a die to a wafer; performing a thinning process on the die, wherein the die has a first total thickness variation (TTV) after performing the thinning process; forming a dielectric layer on the wafer to cover sidewalls and a top surface the die; performing a first removal process to remove a first portion of the dielectric layer and expose the top surface of the die; and performing a second removal process to remove a second portion of the dielectric layer and a portion of the die, wherein after performing the second removal process, the die has a second TTV less than the first TTV. | 2020-09-17 |
20200294967 | Package Structures and Methods of Forming - Methods of forming and structures of packages are discussed herein. In an embodiment, a method includes forming a back side redistribution structure, and after forming the back side redistribution structure, adhering a first integrated circuit die to the back side redistribution structure. The method further includes encapsulating the first integrated circuit die on the back side redistribution structure with an encapsulant, forming a front side redistribution structure on the encapsulant, and electrically coupling a second integrated circuit die to the first integrated circuit die. The second integrated circuit die is electrically coupled to the first integrated circuit die through first external electrical connectors mechanically attached to the front side redistribution structure. | 2020-09-17 |
20200294968 | THREE-DIMENSIONAL MICROELECTRONIC PACKAGE WITH EMBEDDED COOLING CHANNELS - The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs. | 2020-09-17 |
20200294969 | STACKED TRANSISTORS WITH DIELECTRIC BETWEEN SOURCE/DRAIN MATERIALS OF DIFFERENT STRATA - Disclosed herein are stacked transistors with dielectric between source/drain materials of different strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein a dielectric material is between source/drain materials of adjacent strata, and the dielectric material is conformal on underlying source/drain material. | 2020-09-17 |
20200294970 | INTEGRATED CIRCUIT CHIP, METHOD OF MANUFACTURING THE INTEGRATED CIRCUIT CHIP, AND INTEGRATED CIRCUIT PACKAGE AND DISPLAY APPARATUS INCLUDING THE INTEGRATED CIRCUIT CHIP - An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner. | 2020-09-17 |
20200294971 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a first chip that includes a first interconnect layer, a first insulator provided on the first interconnect layer, a first metal portion provided on the first interconnect layer and provided in the first insulator and including at least one of palladium, platinum and gold, and a second interconnect layer provided on the first metal portion and provided in the first insulator. The device further includes a second chip that includes a second insulator provided on the first insulator, and a third interconnect layer provided in the second insulator and provided on the second interconnect layer. | 2020-09-17 |
20200294972 | Semiconductor Device And Method For Manufacturing Semiconductor Device - The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device capable of reducing the uppermost semiconductor chip damage and stably performing wire bonding even if an excessive force is applied during a die bonding process or a wire bonding process, and a method for manufacturing the semiconductor device. | 2020-09-17 |
20200294973 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a first direction over a substrate, the first semiconductor layers being thicker than the second semiconductor layers. The method also includes patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction. The method further includes removing the first semiconductor layers of the first fin structure to form a plurality of nanowires. Each of the nanowires has a first height, there is a distance between two adjacent nanowires along the vertical direction, and the distance is greater than the first height. The method includes forming a first gate structure between the second semiconductor layers of the first fin structure. | 2020-09-17 |
20200294974 | PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure. | 2020-09-17 |
20200294975 | DISPLAY PANEL AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE - The present disclosure provides a display panel and a manufacturing method thereof, a display device. The display panel includes: a substrate; a plurality of driving electrodes and a micro light emitting diode located on a surface of the substrate, wherein respective electrodes of the micro light emitting diode are located at a side of the micro light emitting diode facing away from the substrate; and a plurality of driving wires respectively electrically coupling the respective electrodes of the micro light emitting diode to the plurality of driving electrodes. | 2020-09-17 |
20200294976 | METHOD FOR CONSTRUCTING MICRO-LED DISPLAY MODULE - Disclosed is a method for constructing a micro-LED display module. The method includes: retaining micro-LED chips in a matrix on a chip retaining member; picking up the micro-LED chips on the chip retaining member and transferring the picked up micro-LED chips to a planar carrier member; pressing the micro-LED chips on the planar carrier member against a mount substrate; and heating solders disposed on the mount substrate above the melting point of the solders simultaneously with the pressing of the micro-LED chips against the mount substrate to bond the micro-LED chips to the mount substrate. The mount substrate is sucked by a suction chuck during heating of the solders. | 2020-09-17 |
20200294977 | DISPLAY APPARATUS - A display apparatus includes a transparent substrate, light emitting units, and an opaque film. The transparent substrate includes a first transparent surface and a second transparent surface opposing to the first transparent surface. The light emitting units are disposed over the first transparent surface. The opaque film covers on at least one of the first transparent surface and the second transparent surface. | 2020-09-17 |
20200294978 | DISPLAY DRIVER INTEGRATED CIRCUIT DEVICE - A display driver integrated circuit (IC) device includes a first substrate having a first front surface and a first back surface; a first interlayer insulating layer on the first front surface; a wiring layer in the first interlayer insulating layer; a first bonding insulating layer on the first interlayer insulating layer; a second substrate having a second front surface and a second back surface, the second front surface being disposed toward the first front surface; a second interlayer insulating layer on the second front surface a second bonding insulating layer on the second interlayer insulating layer and physically bonded to the first bonding insulating layer; and a back via stack structure penetrating the second substrate, the second interlayer insulating layer, the second bonding insulating layer, the first bonding insulating layer, and the first interlayer insulating layer and electrically connected to the wiring layer. | 2020-09-17 |
20200294979 | PACKAGE-ON-PACKAGE (POP) SEMICONDUCTOR PACKAGE AND ELECTRONIC SYSTEM INCLUDING THE SAME - A package-on-package (PoP) semiconductor package includes an upper package and a lower package. The lower package includes a first semiconductor device in a first area, a second semiconductor device in a second area, and a command-and-address vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection adjacent to the first area. | 2020-09-17 |
20200294980 | MODULE - Provided is a module which has a package-on-package structure including a redistribution layer and can be easily reduced in height. A module includes an upper module including a substrate, a first component, and a sealing resin layer, and a lower module including an intermediate layer and a redistribution layer. The first component is connected to the redistribution layer with a columnar conductor interposed therebetween and provided in the intermediate layer, and both the first component and a second component are rewired by the redistribution layer. By fixing a resin block containing the second component to a lower surface of the substrate by a fixing conductor, positional deviation of the second component can be prevented. Further, by polishing an upper surface of the resin block, it is possible to improve the flatness. | 2020-09-17 |
20200294981 | LED Module - An LED module is disclosed. In an embodiment an LED module includes a thermally conductive substrate made of a multilayer ceramic, at least one LED on the substrate, passive SMD components arranged on the substrate, a passive component integrated in the substrate and a heat spreader configured to dissipate waste heat in horizontal and vertical directions. | 2020-09-17 |
20200294982 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: a printed wiring substrate that includes a substrate, a wiring layer on the substrate, and a first insulating layer on the wiring layer. The wiring layer includes a connection terminal and a wiring electrically connected to the connection terminal. The first insulating layer includes an opening that exposes at least a portion of the connection terminal and at least a portion of the wiring, and at least one of a protrusion portion or a recess portion, provided along an edge of the opening, that overlaps the wiring. The semiconductor device includes a semiconductor chip mounted on the printed wiring substrate; a bonding wire that electrically connects the connection terminal and the semiconductor chip; and a second insulating layer that covers the semiconductor chip, the bonding wire, and the opening. | 2020-09-17 |
20200294983 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process. | 2020-09-17 |
20200294984 | SEMICONDUCTOR COMPONENT, PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package manufacturing having a semiconductor substrate, a bonding layer, at least one semiconductor device, a redistribution circuit structure and an insulating encapsulation. The bonding layer is disposed on the semiconductor substrate. The semiconductor device is disposed on and in contact with a portion of the bonding layer, wherein the bonding layer is located between the semiconductor substrate and the semiconductor device and adheres the semiconductor device onto the semiconductor substrate. The redistribution circuit structure is disposed on and electrically connected to the semiconductor device, wherein the semiconductor device is located between the redistribution circuit structure and the bonding layer. The insulating encapsulation wraps a sidewall of the semiconductor device, wherein a sidewall of the bonding layer is aligned with a sidewall of the insulating encapsulation and a sidewall of the redistribution circuit structure. | 2020-09-17 |
20200294985 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate SUB, a semiconductor layer EP formed on the semiconductor substrate SUB, a buried layer PBL formed between the semiconductor layer EP and the semiconductor substrate SUB, an isolation layer PiSO formed in the semiconductor layer EP so as to be in contact with the buried layer PBL, and a conductive film FG formed over the isolation layer PiSO via an insulating film IF, whereby a first capacitive element including the conductive film FG as an upper electrode, the insulating film IF as a capacitive insulating film, and the isolation layer PiSO as a lower electrode, is formed over the semiconductor substrate SUB. | 2020-09-17 |
20200294986 | DIFFERENTIAL TRENCH FILL FOR EASE OF LAYOUT DESIGN - An integrated circuit structure comprises a plurality of structures above a substrate, wherein spacing between the structures creates a range of different open density regions from a relatively low open density region to a high open density region. A first fill material fills at least a portion of openings between the structures in at least the high open density region to provide a substantially uniform open density across the different open density regions, wherein the first fill material is patterned to include openings therein. A second fill material fills the openings between the structures in the low open density region, and fills the openings in the first fill material in the at least the high open density region. | 2020-09-17 |
20200294987 | FLEXIBLE IMPEDANCE NETWORK SYSTEM - Techniques and architecture are disclosed for a method for making a custom circuit comprising forming a common wafer template, selecting at least two elements of the common wafer template to be chosen elements, and adding at least one metal layer to interconnect the chosen elements to form a circuit. The common wafer template includes a plurality of transistors, a plurality of resistors, a plurality of capacitors, and a plurality of bond pads. Final circuit customization of the common wafer template is accomplished by adding at least one metal layer that forms interconnects to passive and active elements in the template in order to complete the circuit. | 2020-09-17 |
20200294988 | INTEGRATED CIRCUIT INCLUDING ASYMMETRIC ENDING CELLS AND SYSTEM-ON-CHIP INCLUDING THE SAME - An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided. | 2020-09-17 |
20200294989 | SEMICONDUCTOR DEVICE - A gate pad is includes a first portion disposed in a gate pad region and a second portion disposed in a gate resistance region and connected to the first portion, the gate pad has a planar shape in which the second portion protrudes from the first portion. A gate polysilicon layer disposed on a front surface of a semiconductor substrate via a gate insulating film, between the semiconductor substrate and an interlayer insulating film, has a surface area at least equal to that of the gate pad and opposes an entire surface of the gate pad in a depth direction. ESD capability of a first region where the gate pad is provided is greater than ESD capability of a second region where a gate resistance is provided and is greater than ESD capability of a third region where a MOS structure of an active region is provided. | 2020-09-17 |
20200294990 | PROTECTION CIRCUIT - A semiconductor device includes a first well, a first region and fourth regions of a first conductivity type as well as second regions, a third region, a second well of the second conductivity type. A first region is disposed in the first well and coupled to a first reference voltage terminal. Second regions are disposed in the first well, wherein one of the second regions is coupled to the first reference voltage terminal, and the second regions and the first well are included in a first transistor. A third region is disposed in the first well. A first resistive load is coupled between the third region and a second reference voltage terminal. A second well is coupled to the first well. Fourth regions are disposed in the second well, wherein the second well and at least one of the fourth regions are included in a second transistor. | 2020-09-17 |
20200294991 | BOOTSTRAP DIODE WITH LOW SUBSTRATE LEAKAGE CURRENT - A semiconductor device includes a diode, a metal-oxide semiconductor, and a junction field-effect transistor. The diode includes an anode node and a cathode node, wherein the anode node is coupled to a first node. The metal-oxide semiconductor includes a first source/drain terminal, a second source/drain terminal, and a first gate terminal, wherein the first source/drain terminal is coupled to the cathode node and the first gate terminal receives a first control voltage. The junction field-effect transistor includes a third source/drain terminal, a fourth source/drain terminal, and a second gate terminal, wherein the second gate terminal receives a second control voltage, the third source/drain terminal is coupled to the second source/drain terminal, and the fourth source/drain terminal is coupled to a second node. | 2020-09-17 |
20200294992 | LOW-VOLTAGE ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUIT, INTEGRATED CIRCUIT AND METHOD FOR ESD PROTECTION THEREOF - An electrostatic discharge protection circuit for an integrated circuit and a method for electrostatic discharge protection thereof are disclosed. The integrated circuit includes a power source, a ground, a signal input, and a signal output. The integrated circuit further comprises one or more essentially identically configured electrostatic discharge protection circuits, configured to provide electrostatic discharge protection between any two of the power source, the ground, the signal input, and the signal output. A method of providing electrostatic discharge protection includes providing one or more essentially identically configured electrostatic discharge protection circuits coupled between and providing electrostatic discharge protection for any two of the power source, the ground, the signal input, and the signal output. The disclosed integrated circuit and method provide advantages of simplifying the integrated circuit design and reducing design time. | 2020-09-17 |
20200294993 | ELECTROSTATIC DISCHARGE (ESD) ROBUST TRANSISTORS AND RELATED METHODS - An electrostatic discharge robust semiconductor transistor (transistor) includes a semiconductor substrate of a first conductivity type, a substrate contact region of the first conductivity type coupled with the semiconductor substrate, a source region of a second conductivity type, a channel region of the second conductivity type, a gate region of the first conductivity type, a drain region having a first drain region of the first conductivity type and a second drain region of the second conductivity type, and an electrical conductor coupled over the second drain region and a portion of the first drain region. A portion of the first drain region not covered by the electrical conductor forms a resistive electrical ballast region configured to protect the transistor from electrostatic discharge (ESD) induced voltage pulses. In implementations the transistor includes a silicon controlled rectifier (SCR) junction field effect transistor (SCR JFET) or a laterally diffused metal-oxide semiconductor (SCR LDMOS). | 2020-09-17 |
20200294994 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND ELECTRONIC DEVICE THEREOF - An electrostatic discharge protection circuit and a semiconductor device are provided. The circuit includes: a power source terminal, a ground terminal, and a discharge path. The discharge path includes a clamp transistor and a MOS transistor connected in series and integrated into a same semiconductor substrate with different types. For the MOS transistor, a gate electrode is electrically connected to a substrate terminal; a first electrode is one of a source electrode and a drain electrode; a second electrode is another one of the source electrode and the drain electrode; the first electrode is electrically connected to a gate electrode of the clamp transistor; and the second electrode is electrically connected to the ground terminal. When an electrostatic discharge occurs, the MOS transistor is turned on to form parasitic current between a substrate terminal of the clamp transistor and the second electrode of the MOS transistor. | 2020-09-17 |
20200294995 | SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME - A semiconductor device including: a lower semiconductor substrate; an upper semiconductor substrate overlapping the lower semiconductor substrate, the upper semiconductor substrate including a first surface and a second surface opposite to the first surface; an upper gate structure on the first surface of the upper semiconductor substrate; a first interlayer insulation film which covers the upper gate structure, wherein the first interlayer insulation film is between the lower semiconductor substrate and the upper semiconductor substrate; and an upper contact connected to the lower semiconductor substrate, wherein the upper contact is on a side surface of the upper gate structure, wherein the upper contact includes a first portion penetrating the upper semiconductor substrate, and a second portion having a side surface adjacent to the side surface of the upper gate structure, and a width of the first portion decreases toward the second surface. | 2020-09-17 |
20200294996 | SWITCH CIRCUIT, HIGH-FREQUENCY MODULE, AND COMMUNICATION APPARATUS - A switch circuit provided on a substrate includes a first series switch and a second series switch disposed in series on a path connecting a first terminal and a second terminal, a third series switch and a fourth series switch disposed in series on a path connecting the first terminal and a third terminal, a first shunt switch connected to a common ground terminal and a first node between the first series switch and the second series switch, and a second shunt switch connected to the common ground terminal and a second node between the third series switch and the fourth series switch. | 2020-09-17 |
20200294997 | ON-CHIP SECURITY CIRCUIT - Methods and system of generating a code are described. A device can receive a request to generate a code. The device can select a set of cells among a plurality of cells. The device can determine current through the selected cells in a forward mode. The device can determine current through the selected cells in a reverse mode. The device can determine a set of differences between the currents of the forward mode and the reverse mode. The set of differences corresponds to the set of selected cells. The device can transform the set of differences into the code. The device can output the code to respond to the request. | 2020-09-17 |
20200294998 | BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES - Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure. | 2020-09-17 |
20200294999 | INTEGRATED CIRCUIT AND STANDARD CELL LIBRARY - Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region. | 2020-09-17 |
20200295000 | Enlarging Spacer Thickness by Forming a Dielectric Layer Over a Recessed Interlayer Dielectric - An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region. | 2020-09-17 |
20200295001 | METAL GATE MODULATION TO IMPROVE KINK EFFECT - The present disclosure relates to an integrated chip. The integrated chip includes a source region and a drain region disposed within an upper surface of a substrate. One or more dielectric materials are disposed within a trench within the substrate. The trench surrounds the source region and the drain region. A gate structure is disposed over the substrate between the source region and the drain region. The gate structure includes a first gate metal having a first sidewall and a second gate metal having a first outer sidewall that contacts the first sidewall directly over the upper surface of the substrate. | 2020-09-17 |
20200295002 | NON-PLANAR TRANSISTORS WITH CHANNEL REGIONS HAVING VARYING WIDTHS - Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well. | 2020-09-17 |
20200295003 | STACKED TRANSISTORS HAVING DEVICE STRATA WITH DIFFERENT CHANNEL WIDTHS - Disclosed herein are stacked transistors having device strata with different channel widths, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein different channel materials of different strata have different widths. | 2020-09-17 |
20200295004 | CMOS-BASED INTEGRATED CIRCUIT PRODUCTS WITH ISOLATED P-WELLS FOR BODY-BIASING TRANSISTOR DEVICES - One illustrative integrated circuit product disclosed herein comprises a PFET region and an NFET region defined in an active semiconductor layer of an SOI substrate, a deep N-well region positioned in the base semiconductor substrate, first and second isolated P-wells positioned in the base semiconductor substrate below the PFET region and the NFET region, respectively, wherein the first and second isolated P-wells engage the deep N-well region, and a deep isolation structure that extends into the deep N-well region, wherein a first portion of the deep isolation structure is laterally positioned between the first isolated P-well and the second isolated P-well to electrically isolate, in a horizontal direction, the first isolated P-well from the second isolated P-well. The product also includes at least one PFET transistor and at least one NFET transistor. | 2020-09-17 |
20200295005 | Integrated Assemblies Comprising Hydrogen Diffused Within Two or More Different Semiconductor Materials, and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies. | 2020-09-17 |
20200295006 | Semiconductor Device and Memory Device Including the Semiconductor Device - To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven. | 2020-09-17 |
20200295007 | Devices Having a Transistor and a Capacitor Along a Common Horizontal Level, and Methods of Forming Devices - Some embodiments include an assembly having a stack of first and second alternating levels. The first levels are insulative levels. The second levels are device levels having integrated devices. Each of the integrated devices has a transistor coupled with an associated capacitor, and the capacitor is horizontally offset from the transistor. The transistors have semiconductor channel material, and have transistor gates along the semiconductor channel material. Each of the transistors has a first source/drain region along one side of the semiconductor channel material and coupled with the associated capacitor, and has a second source/drain region. Wordlines extend horizontally along the device levels and are coupled with the transistor gates. Digit lines extend vertically through the device levels and are coupled with the second source/drain regions. Some embodiments include methods of forming integrated structures. | 2020-09-17 |
20200295008 | Integrated Assemblies Comprising Memory Cells and Shielding Material Between the Memory Cells, and Methods of Forming Integrated Assemblies - Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies. | 2020-09-17 |
20200295009 | SEMICONDUCTOR DRAM CELL STRUCTURE AND MANUFACTURE METHOD THEREOF - This invention discloses a DRAM cell includes an asymmetric transistor coupled to a capacitor. The asymmetric transistor includes a drain region extending upward from an isolator region; a gate region extends upward from a gate dielectric or the isolator; a source region of asymmetric transistor extends upward from a first portion of an isolating layer. The upward extending directions of the drain region, the gate region, and the source region are perpendicular or substantially perpendicular to an original silicon surface. Moreover, the capacitor is partially formed in a concave and the isolating layer is positioned in the concave. The capacitor extends upward from a second portion of the isolating layer. The upward extending directions of the upright portion of the capacitor electrode, the third portion of the insulating layer and the counter electrode are perpendicular or substantially perpendicular to the original silicon surface. | 2020-09-17 |
20200295010 | METHOD FOR FABRICATING A MEMORY DEVICE - A method for fabricating a memory device includes: forming a first dielectric layer disposed on a substrate, and a first opening in the first dielectric layer; filling a lower portion of the first opening with a first conductive material layer; conformally forming a lining layer over sidewalls of an upper portion of the first opening and a top surface of the first conductive material layer; filling the upper portion of the first opening with a second conductive material layer; etching back the second conductive material layer and the lining layer to form a recess; conformally forming a protection layer on sidewalls and a bottom portion of the recess and a top surface of the first dielectric layer; forming a second opening that penetrates through the protection layer, the second conductive material layer, the lining layer and the first conductive material layer; forming a pair of contacts in the first opening. | 2020-09-17 |
20200295011 | Integrated Circuity, DRAM Circuitry, Methods Used In Forming Integrated Circuitry, And Methods Used In Forming DRAM Circuitry - A method used in forming integrated circuitry comprises forming a plurality of conductive vias comprising conductive material. The conductive vias are spaced relative one another by intermediate material. A discontinuous material is formed atop the conductive material of the vias and atop the intermediate material that is between the vias. Metal material is formed atop, directly against, and between the discontinuous material and atop and directly against the conductive material of the vias. The metal material is of different composition from that of the discontinuous material and is above the intermediate material that is between the vias. The metal material with discontinuous material there-below is formed to comprise a conductive line that is atop the intermediate material that is between the vias and is directly against individual of the vias. Structures independent of method are disclosed. | 2020-09-17 |
20200295012 | STATIC RANDOM ACCESS MEMORY CELL EMPLOYING N-DOPED PFET GATE ELECTRODES AND METHODS OF MANUFACTURING THE SAME - Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion. | 2020-09-17 |
20200295013 | SEMICONDUCTOR DEVICE COMPRISING WORK FUNCTION METAL PATTERN IN BOUNDRY REGION AND METHOD FOR FABRICATING THE SAME - A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension. | 2020-09-17 |
20200295014 | Implantations for Forming Source/Drain Regions of Different Transistors - A method includes forming a first transistor including forming a first gate stack, epitaxially growing a first source/drain region on a side of the first gate stack, and performing a first implantation to implant the first source/drain region. The method further includes forming a second transistor including forming a second gate stack, forming a second gate spacer on a sidewall of the second gate stack, epitaxially growing a second source/drain region on a side of the second gate stack, and performing a second implantation to implant the second source/drain region. An inter-layer dielectric is formed to cover the first source/drain region and the second source/drain region. The first implantation is performed before the inter-layer dielectric is formed, and the second implantation is performed after the inter-layer dielectric is formed. | 2020-09-17 |
20200295015 | DOUBLE CHANNEL MEMORY DEVICE - A semiconductor device includes a substrate, a fin structure, an insulating layer, a select gate, a memory gate, and a charge trapping layer. The fin structure includes a first portion and a second extend from the substrate. Each of the first portion and the second portion includes a first sidewall and a second sidewall, and the second sidewalls are between the first sidewalls. The insulating layer is disposed between the second sidewalls of the first and second portions. The select gate and the memory gate extend across the fin structure and the insulating layer. The charge trapping layer is disposed between the memory gate and the select gate, between the memory gate and the insulating layer, and between the memory gate and the fin structure, and the second sidewalls of the first and second portions are free from in contact with the charge trapping layer. | 2020-09-17 |
20200295016 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment includes first to third conductive layers, first and second pillars, first and second contacts, and first to third members. The first pillar penetrates the first and second conductive layers in a first area. A second pillar penetrates the first and third conductive layers in the first area. The first and second contacts are provided on the second and third conductive layers respectively in a second area. The first and second members are provided between the second and third conductive layers in the first and second area, respectively. The third member penetrates the first conductive layers. The third member is in contact with each of the second and third conductive layers, and the first and second members. | 2020-09-17 |
20200295017 | MULTI-LEVEL FERROELECTRIC MEMORY CELL - The present disclosure relates to semiconductor structures and, more particularly, to a multi-level ferroelectric memory cell and methods of manufacture. The structure includes: a first metallization feature; a tapered ferroelectric capacitor comprising a first electrode, a second electrode and ferroelectric material between the first electrode and the second electrode, the first electrode contacting the first metallization feature; and a second metallization feature contacting the second electrode. | 2020-09-17 |
20200295018 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a fin that is a portion of a semiconductor substrate, protrudes from a main surface of the semiconductor substrate, has a width in a first direction, and extends in a second direction; a control gate electrode that is arranged on the fin via a first gate insulating film and extends in the first direction; and a memory gate electrode that is arranged on the fin via a second gate insulating film and extends in the first direction. Further, a width of the fin in a region in which the memory gate electrode is arranged via the second gate insulating film having a film thickness larger than the first gate insulating film is smaller than a width of the fin in a region in which the control gate electrode is arranged via the first gate insulating film. | 2020-09-17 |
20200295019 | STAIRCASE STRUCTURE FOR MEMORY DEVICE - A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads. where each landing pad is disposed over another portion of the second material layer of a respective layer stack. | 2020-09-17 |
20200295020 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes: first interconnect layers; second interconnect layers; a first memory pillar extending through the first interconnect layers; a second memory pillar extending through the second interconnect layers; a first film provided above the first interconnect layers, having a planar shape corresponding to the first interconnect layers and extending in the first direction; and a second film provided above the second interconnect layers, separate from the first film in the second direction, having a planar shape corresponding to the second interconnect layers and extending in the first direction. The first and second films have a compressive stress higher than a silicon oxide film. | 2020-09-17 |
20200295021 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device includes a memory cell array layer that includes a plurality of nonvolatile memory cells connected in series in a vertical direction above a semiconductor substrate, a plurality of word lines respectively connected to gates of the plurality of nonvolatile memory cells, a select gate transistor layer that is located above the memory cell array and includes at least first and second select gate transistors connected in series in the vertical direction and to the plurality of nonvolatile memory cells, and at least first and second select gate lines respectively connected to the at least first and second select gate transistors, and a control circuit configured to execute a read operation on the nonvolatile memory cells, such that during a read period of the read operation, signals having different voltage levels are supplied to the at least first and second select gate lines. | 2020-09-17 |
20200295022 | SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device according to one embodiment is the semiconductor storage device that includes: a cell array region having a plurality of memory cells; and an outer edge portion arranged at an end portion to surround the cell array region. A stacked body in which a plurality of conductive layers are stacked via a first insulating layer and which has a stair portion in which end portions of the plurality of conductive layers form a stair shape is provided inside the cell array region, the stair portion facing the outer edge portion. A center of at least one step of the stair portion has a recess directed to an inner side of the cell array region. | 2020-09-17 |
20200295023 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion. | 2020-09-17 |
20200295024 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes first high-potential wirings, second high-potential wirings, a first low-potential wiring, a second low-potential wiring, a first branch wiring, and a second branch wiring formed in a wiring layer between a memory cell array and a semiconductor substrate and each extending in a first direction. The first branch wiring is electrically connected to the first low-potential wiring, and is adjacent to the first low-potential wiring on one side in a second direction perpendicular to the first direction of the first low-potential wiring. The second branch wiring is electrically connected to the second low-potential wiring, and is adjacent to the second low-potential wiring on the other side in the second direction of the second low-potential wiring. A first via is provided to contact the first branch wiring, and a second via is provided to contact the second branch wiring. | 2020-09-17 |
20200295025 | HYBRID BONDING CONTACT STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE - Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The memory device includes an alternating layer stack disposed on a first substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further includes a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, multiple through array contacts in the first region, each through array contact extending vertically through the alternating dielectric stack, an array interconnection layer in contact with the through array contacts, a peripheral circuit formed on a second substrate. and a peripheral interconnection layer on the peripheral circuit. The array interconnection layer is bonded on the peripheral interconnection layer, such that the peripheral circuit is electrically connected with at least one through array contact. | 2020-09-17 |
20200295026 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes a base body, a stacked body, a plurality of columns, and a plurality of first contacts. The base body includes a substrate, a semiconductor element on the substrate, a lower wiring layer above the semiconductor element in a thickness direction of the base body and connected to the semiconductor element, and a lower conductive layer above the lower wiring layer in the thickness direction. The stacked body is above the lower conductive layer and including an alternating stack of conductive layers and insulating layers. Each of the columns includes a semiconductor body extending through the stacked body and electrically connected to the lower conductive layer. The plurality of first contacts extend through the stacked body and electrically connected to the lower conductive layer. The lower conductive layer is separately provided under each of the plurality of first contacts. | 2020-09-17 |
20200295027 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor storage device includes a first stacked body, a second stacked body, a first division film, a second division film, and a plurality of discrete films. The a first stacked body includes first electrode layers stacked in a first direction. The second stacked body, above the first stacked body, includes second electrode layers stacked in the first direction. The second semiconductor layer is electrically connected to the first semiconductor layer. The first division film, extending in the first direction through the first stacked body, divides the first stacked body in a second direction crossing the first direction. The second division film, extending in the first direction through the second stacked body, divides the second stacked body in the second direction. The discrete films, extending in the first direction through the second stacked body, are disposed above the first division film. | 2020-09-17 |
20200295028 | VERTICAL SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall. | 2020-09-17 |
20200295029 | THREE-DIMENSIONAL MEMORY DEVICE HAVING BONDING STRUCTURES CONNECTED TO BIT LINES AND METHODS OF MAKING THE SAME - Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies. | 2020-09-17 |
20200295030 | THREE-DIMENSIONAL MEMORY DEVICE WITH ON-AXIS SELF-ALIGNED DRAIN-SELECT-LEVEL ISOLATION STRUCTURE AND METHODS OF MANUFACTURING THE SAME - A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures located within a respective one of the memory openings. A multi-pillared dielectric isolation structure extends through upper sections of a neighboring pair of memory openings. The multi-pillared dielectric isolation structure includes a plurality of dielectric pillar portions located within a respective one of the memory openings, and at least one horizontally-extending portion adjoining each of the plurality of dielectric pillar portions and located between a vertically neighboring pair of insulating layers within the alternating stack. The at least one horizontally-extending portion laterally separates laterally neighboring strips of at least one electrically conductive layer within the alternating stack. | 2020-09-17 |