38th week of 2014 patent applcation highlights part 221 |
Patent application number | Title | Published |
20140281305 | Memory Image Capture via Memory Write from a Running System - Techniques for memory image capture via memory write from a running system are described. In at least some embodiments, a request is received for an image of a portion of memory. Images of memory can be used for a variety of purposes, such as diagnosing and repairing error conditions for hardware and/or software, detecting unwanted and/or malicious processes (e.g., malware), general systems maintenance, and so forth. According to one or more embodiments, various techniques can be implemented to capture an image of a portion of memory. For example, an intermediate write to memory can be employed to write the image of the portion of memory to a memory buffer. Alternatively or additionally, an image of a portion of memory can be captured directly to storage. | 2014-09-18 |
20140281306 | METHOD AND APPARATUS OF NON-DISRUPTIVE STORAGE MIGRATION - Example implementations described herein are directed to non-disruptive I/O storage migration between different storage types. In example implementations, virtual volume migration techniques such as snapshot, thin-provisioning, tier-provisioning, de-duplicated virtual volume, and so forth, are conducted between different storage types by using pool address re-mapping. In example implementations, asynchronous remote copy volume migration is performed without the initial secondary volume copy. | 2014-09-18 |
20140281307 | HANDLING SNAPSHOT INFORMATION FOR A STORAGE DEVICE - Techniques are disclosed relating to handling snapshot data for a storage device. In one embodiment, a computing system maintains information that indicates the state of data associated with an application at a particular point in time. In this embodiment, the computing system assigns an epoch number to a current epoch, where the current epoch is an interval between the particular point in time and a future point in time. In this embodiment, the computing system writes, during the current epoch, a block of data to the storage device. In this embodiment, the writing the block of data includes storing the epoch number with the block of data. | 2014-09-18 |
20140281308 | STORAGE UNIT SELECTION FOR VIRTUALIZED STORAGE UNITS - Performance information for storage units located at a virtual data center is determined by executing storage administrator logic whose execution is controlled by a management entity different than the virtual data center provider. Performance expectations are automatically determined based on the determined performance information. In response to determining that a particular storage unit is incompatible with performance expectations applicable to the particular storage unit, embodiments cause a reduction in utilization of the particular storage unit. Based on determined performance information, another embodiment determines that a performance pattern indicating a physical co-location of a first storage unit and a second storage unit has occurred. In response to determining that the performance pattern indicating a physical co-location of a first storage unit and a second storage unit has occurred, the embodiment disables use of a selected storage unit of the first storage unit or the second storage unit for at least a particular purpose. | 2014-09-18 |
20140281309 | TRANSFORMING A SHARED VIRTUALIZED SPACE TO AN ENCLOSED SPACE - Provided are techniques for allocating disk space for a virtualized file space; designating files within a global disk space as files to be privatized with respect to the virtualized file space; copying the designated files to the allocated disk space; storing an indicator specifying that the designated files have been copied; and in response to a startup of the virtualized file space subsequent to the allocating, designating and copying, detecting the indicator; and in response to detecting the indicator, redirect references in the virtualized file space to the designated files to the copied. | 2014-09-18 |
20140281310 | Transforming a Shared Virtualized Space to an Enclosed Space - Provided are techniques for allocating disk space for a virtualized file space; designating files within a global disk space as files to be privatized with respect to the virtualized file space; copying the designated files to the allocated disk space; storing an indicator specifying that the designated files have been copied; and in response to a startup of the virtualized file space subsequent to the allocating, designating and copying, detecting the indicator; and in response to detecting the indicator, redirect references in the virtualized file space to the designated files to the copied. | 2014-09-18 |
20140281311 | SYSTEMS AND METHODS FOR MEMORY SYSTEM MANAGEMENT BASED ON THERMAL INFORMATION OF A MEMORY SYSTEM - Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described. | 2014-09-18 |
20140281312 | APPARATUS AND METHOD FOR TRANSLATION FROM MULTI-DIMENSIONAL TOLINEAR ADDRESS SPACE IN STORAGE - A translation system can translate a storage request having multiple fields to a physical address using the fields as keys to traverse a map. By using a map table, multiple storage services can be condensed into a single map traversal. The map can be made of nodes that include one or more node entries. The node entries can be stored in a hashed storage area or sorted storage area of a node. A node entry of root nodes or inner nodes can include a link to a next node. A node entry of a leaf node can include a physical address. Using the request fields as a key to a node, a node entry can be determined. A pointer in a root node entry or inner node entry can be followed to a next node. A physical address in a leaf node can be the translation of the storage request. | 2014-09-18 |
20140281313 | APPARATUS AND METHOD FOR CLONING AND SNAPSHOTTING IN MULTI-DIMENSIONAL TO LINEAR ADDRESS SPACE TRANSLATION - A translation system can translate a storage request to a physical address using fields as keys to traverse a map of nodes with node entries. A node entry can include a link to a next node or a physical address. Using a portion of the key as noted in node metadata, a node entry can be determined. When snapshotting a dataset, a snapshot value can be updated in a root node entry. New data can be added under the new snaphsot value, preventing overwriting of the prior data, providing deduplication and quick snapshotting. When cloning a dataset, a new root node entry can be made for the clone. The new root entry can reference the original root entry of the original dataset. Metadata of nodes of the clone branch can identify whether the current branch contains updated data or whether the data exists off of the original root entry. | 2014-09-18 |
20140281314 | DUAL SYSTEM - A dual system according to the present invention includes: a memory copying unit configured to, when an arithmetic device of a first computer module is installed into the dual system, execute a memory copy process of copying data in a memory region of a second computer module into a memory region of the first computer module; a substitute processing unit configured to execute a service substitute process that is executed by a different arithmetic device from an arithmetic device executing the memory copy process and that is part of processes involved in the information processing service by the dual system; and a shared memory that stores data of the service substitute process by the substitute processing unit. The shared memory is excluded from the target of the memory copy process. | 2014-09-18 |
20140281315 | MASS STORAGE DEVICE AND METHOD OF OPERATING THE SAME TO BACK UP DATA STORED IN VOLATILE MEMORY - A mass storage memory device is disclosed. The device includes a nonvolatile memory, a volatile memory configured to store logical to physical (L2P) data associating logical addresses of data stored in the nonvolatile memory with physical locations of the nonvolatile memory at which the data is stored, and a controller. The controller writes L2P data in the nonvolatile memory so the L2P data can be preserved through a power failure. The controller also writes L2P data stored in the nonvolatile memory to the volatile memory to rebuild the L2P table. | 2014-09-18 |
20140281316 | DATA MANAGEMENT DEVICE AND METHOD FOR COPYING DATA - In response to a first copy command, a first copying unit writes a first dataset read out of a volatile storage device into a first continuous area and a fourth continuous area, as well as a second dataset read out of the volatile storage device into a second continuous area and a third continuous area. In response to a second copy command, a second copying unit reads the first dataset out of the first continuous area by making sequential access thereto, in parallel with the second dataset out of the third continuous area by making sequential access thereto. The second copying unit writes the first dataset and second dataset back into the volatile storage device. | 2014-09-18 |
20140281317 | PROVIDING EXECUTING PROGRAMS WITH RELIABLE ACCESS TO NON-LOCAL BLOCK DATA STORAGE - Techniques are described for managing access of executing programs to non-local block data storage. In some situations, a block data storage service uses multiple server storage systems to reliably store block data that may be accessed over one or more networks by programs executing on other physical computing systems. Users may create block data storage volumes that are each stored by at least two of the server block data storage systems, and may initiate use of such volumes by one or more executing programs, such as in a reliable manner by enabling an automatic switch to a second volume copy if a first volume copy becomes unavailable. A group of multiple server block data storage systems that store block data volumes may in some situations be co-located at a data center, and programs that use volumes stored there may execute on other physical computing systems at that data center. | 2014-09-18 |
20140281318 | EFFICIENTLY SEARCHING AND MODIFYING A VARIABLE LENGTH QUEUE - Embodiments relate to ensuring that serialization is maintained between separate transactions while searching and/or modifying a variable length queue is provided. An aspect includes searching a queue using a transaction. A first sequence number is retrieved from a queue header and a second sequence number is retrieved from local storage for the transaction. The first sequence number is compared with the second sequence number according to embodiments. The search of the queue is resumed using an address of a next element saved from a previous transaction responsive to the first sequence number matching the second sequence number. The search of the queue is restarted at a first element responsive to the first sequence number not matching the second sequence number. | 2014-09-18 |
20140281319 | SYSTEM AND METHOD FOR PROTECTING DATA - A system and method are provided for protecting data. In operation, a request to read data from memory is received. Additionally, it is determined whether the data is stored in a predetermined portion of the memory. If it is determined that the data is stored in the predetermined portion of the memory, the data and a protect signal are returned for use in protecting the data. In certain embodiments of the invention, data stored in the predetermined portion of the memory may be further processed and written hack to the predetermined portion of the memory. In other embodiments of the invention, such processing may involve unprotected data stored outside the predetermined portion of the memory. | 2014-09-18 |
20140281320 | Forensic Computer Examination Systems and Methods - Systems, methods, and computer program products for facilitating write-protected virtual access to a target computing device, wherein the use and inspection of the computer device may occur without altering the digital data thereon, are disclosed. In an aspect, a user inserts a virtualization media device, which will boot the computer system in a write-protected mode. The computing device will operate through an operating system on the target computing device and instantiate the subject computer through a virtual machine environment. Such virtualization will protect target computing device files from accidental alteration during, for example, investigatory searches of the target computing device storage device. | 2014-09-18 |
20140281321 | REGISTER ACCESS WHITE LISTING - A system employs a white list of authorized transactions to control access to system registers. In an embodiment, the white list is loaded into filter registers during system boot. Routing logic monitors a logical interconnect fabric of the system for register access requests. The routing logic parses source, destination information from a request to index the white list. If the white list includes an entry corresponding to the processing entity indicated in the source information and the register indicated in the destination information, the routing logic will permit the requested access. | 2014-09-18 |
20140281322 | Temporal Hierarchical Tiered Data Storage - Embodiments of the invention includes identifying the priority of data sets based on how frequently they are accessed by data center compute resources or by other measures assigning latency metrics to data storage resources accessible by the data center, moving data sets with the highest priority metrics to data storage resources with the fastest latency metrics, and moving data sets with lower priority metrics to slower data storage resources with slower latency metrics. The invention also may be compatible with or enable new forms of related applications and methods for managing the data center. | 2014-09-18 |
20140281323 | MIGRATION DIRECTIVES IN A UNIFIED VIRTUAL MEMORY SYSTEM ARCHITECTURE - One embodiment of the present invention sets forth a computer-implemented method for altering migration rules for a unified virtual memory system. The method includes detecting that a migration rule trigger has been satisfied. The method also includes identifying a migration rule action that is associated with the migration rule trigger. The method further includes executing the migration rule action. Other embodiments of the present invention include a computer-readable medium, a computing device, and a unified virtual memory subsystem. One advantage of the disclosed approach is that various settings of the unified virtual memory system may be modified during program execution. This ability to alter the settings allows for an application to vary the manner in which memory pages are migrated and otherwise manipulated, which provides the application the ability to optimize the unified virtual memory system for efficient execution. | 2014-09-18 |
20140281324 | MIGRATING PAGES OF DIFFERENT SIZES BETWEEN HETEROGENEOUS PROCESSORS - One embodiment of the present invention sets forth a computer-implemented method for migrating a memory page from a first memory to a second memory. The method includes determining a first page size supported by the first memory. The method also includes determining a second page size supported by the second memory. The method further includes determining a use history of the memory page based on an entry in a page state directory associated with the memory page. The method also includes migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history. | 2014-09-18 |
20140281325 | SYNCHRONIZATION AND ORDER DETECTION IN A MEMORY SYSTEM - Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted. | 2014-09-18 |
20140281326 | DUAL ASYNCHRONOUS AND SYNCHRONOUS MEMORY SYSTEM - Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains. | 2014-09-18 |
20140281327 | SYSTEM AND METHOD TO DYNAMICALLY DETERMINE A TIMING PARAMETER OF A MEMORY DEVICE - A particular method includes receiving, from a processor, a first memory access request at a memory device. The method also includes processing the first memory access request based on a timing parameter of the memory device. The method further includes receiving, from the processor, a second memory access request at the memory device. The method also includes modifying a timing parameter of the memory device based on addresses identified by the first memory access request and the second memory access request to produce a modified timing parameter. The method further includes processing the second memory access request based on the modified timing parameter. | 2014-09-18 |
20140281328 | MEMORY INTERFACE OFFSET SIGNALING - A memory interface includes circuitry configured for applying a variable delay to a portion of a data signal and applying a variable delay to a data strobe. The delayed data strobe samples the delayed portion of the data signal. Delayed portions of the data signal are spaced away from non-delayed portions of the data signal by alternating the routing of delayed bits and non-delayed bits of the data signal. A training block determines and sets a value of the variable delay corresponding to a largest value of a number of recorded eye aperture widths. | 2014-09-18 |
20140281329 | Priority Command Queues for Low Latency Solid State Drives - A method, apparatus, and system of a priority command queues for low latency solid state drives are disclosed. In one embodiment, a system of a storage system includes a command sorter to determine a target storage device for at least one of a solid state drive (SSD) command and a hard disk drive (HDD) command and to place the command in a SSD ready queue if the SSD command is targeted to a SSD storage device of the storage system and to place the HDD command to a HDD ready queue if the HDD command is targeted to an HDD storage device of the storage system, a SSD ready queue to queue the SSD command targeted to the SSD storage device, and a HDD ready queue to queue the HDD command targeted to the HDD storage device. | 2014-09-18 |
20140281330 | Apparatus and Method for Resource Alerts - A method of managing resource allocations in a storage system provisioning system, including monitoring write applications that result in new storage block allocations during a current time slice, calculating a time remaining to exceed actual capacity of allocated storage blocks, if the calculated remaining time does exceed length of next time slice immediately transmitting an alert when an estimated number of future write requests exceeds a predetermined threshold, and if the calculated remaining time does exceed length of next time slice immediately transmitting an alert when an estimated number of future write requests exceeds a predetermined threshold, wherein a duration of a time slice is set by a storage system administrator based upon a current storage library setup and a time required to arrange a new storage device when a thin provisioning device is going out of disk space. | 2014-09-18 |
20140281331 | SYSTEMS AND METHODS FOR PROCESSING DATA STORED IN DATA STORAGE DEVICES - A system and method for processing data stored in data storage devices is described. A computing processor acquires blocks of data from a target machine and computes an entropy value associated with each block of the acquired data. The computing processor checks the entropy values of each block to determine whether or not the particular block is deemed to contain useful data, before that block is analyzed. | 2014-09-18 |
20140281332 | EXTERNALLY PROGRAMMABLE MEMORY MANAGEMENT UNIT - A method includes reading, by a processor, one or more configuration values from a storage device or a memory management unit. The method also includes loading the one or more configuration values into one or more registers of the processor. The one or more registers are useable by the processor to perform address translation. | 2014-09-18 |
20140281333 | PAGING ENABLEMENT FOR DATA STORAGE - Techniques are disclosed relating to storing translations in memory that are usable to access data on a recording medium. In one embodiment, a request is sent for a memory allocation within a non-pageable portion of a memory in a computer system. Responsive to the request, allocated memory is received. Translations usable to map logical addresses to physical addresses within a storage device are stored within the allocated memory. In some embodiments, the translations are usable to access an area within the storage device used to store pages evicted from the memory. In one embodiment, a size of the memory allocation is determined based on a size of the area. In another embodiment, a size of the memory allocation is determined based on a size of a partition including the area. In some embodiments, the storage device is a solid-state storage array. | 2014-09-18 |
20140281334 | Address Resource Mapping In A Shared Memory Computer System - An algorithm for mapping memory and a method for using a high performance computing (“HPC”) system are disclosed. The algorithm takes into account the number of physical nodes in the HPC system, and the amount of memory in each node. Some of the nodes in the HPC system also include input/output (“I/O”) devices like graphics cards and non-volatile storage interfaces that have on-board memory; the algorithm also accounts for the number of such nodes and the amount of I/O memory they each contain. The algorithm maximizes certain parameters in priority order, including the number of mapped nodes, the number of mapped I/O nodes, the amount of mapped I/O memory, and the total amount of mapped memory. | 2014-09-18 |
20140281335 | SYSTEM AND METHOD FOR ASSIGNING MEMORY ACCESS TRANSFERS BETWEEN COMMUNICATION CHANNELS - A communication channel controller includes a queue, a memory map, and a scheduler. The queue to store a first memory transfer request received at the communication channel controller. The memory map stores information to identify a memory address range to be associated with a memory. The scheduler to compare a source address of the first memory transfer in the queue to the memory address range in the memory map to determine whether the source address of the first memory transfer request targets the memory, and in response allocate the first memory transfer request to a first communication channel of a plurality of communication channels in response to the first communication channel having all of its outstanding memory transactions to a common source address bank and source address page as a source address bank and a source address page of the first memory transfer request. | 2014-09-18 |
20140281336 | MEMORY ALLOCATION ACCELERATOR - Technologies are generally described for methods and systems effective to implement a memory allocation accelerator. A processor may generate a request for allocation of a requested chunk of memory. The request may be received by a memory allocation accelerator configured to be in communication with the processor. The memory allocation accelerator may process the request to identify an address for a particular chunk of memory corresponding to the request and may return the address to the processor. | 2014-09-18 |
20140281337 | STORAGE SYSTEM, STORAGE APPARATUS, AND COMPUTER PRODUCT - A storage system includes a storage apparatus having a first storage unit having first storage and a first storage control unit controlling access to the first storage, and a first control unit controlling storage units including the first storage unit; a second storage unit having second storage and a second storage control unit controlling access to the second storage; and a second control unit controlling storage units including the second storage unit. The second storage unit and second control unit are added to the storage apparatus. the first control unit includes a memory unit storing allocation information including an allocation state of storage areas of the first and second storage, and a processor configured to execute rearrangement control of an allocated storage area based on the allocation information corresponding to unevenness between a storage capacity of an allocated storage area in the first storage and that in the second storage. | 2014-09-18 |
20140281338 | HOST-DRIVEN GARBAGE COLLECTION - A host receives information related to garbage collection of a storage device, and it controls selective execution of garbage collection by the storage device according to the received information. | 2014-09-18 |
20140281339 | COMPUTING SYSTEM AND CONTROLLING METHODS FOR THE SAME - The computer system, during the course of executing an operation of dynamically allocating a storage area to a virtual volume in response to an access from a host system, detects where a balance of a storage capacity among a plurality of logical areas is disrupted, and subsequently moves a storage area among a plurality of logical areas to maintain balance of the storage capacity. | 2014-09-18 |
20140281340 | MULTIDIMENSIONAL RESOURCE MANAGER/ALLOCATOR - An apparatus and method for multidimensional resource allocation and management are provided. The method includes receiving a request for allocation of a block of a multidimensional memory resource, selecting a grid for tracking spaces of the multidimensional memory resource according to the allocation request, determining whether a block of the multidimensional memory resource corresponding to the request for the allocation of the block of the multidimensional memory resource is unallocated, and allocating the unallocated block of the multidimensional memory resource. | 2014-09-18 |
20140281341 | MULTIPLE, PER SENSOR CONFIGURABLE FIFOS IN A SINGLE STATIC RANDOM ACCESS MEMORY (SRAM) STRUCTURE - A device includes one or more sensors, one or more processors, one or more sensors, and a memory. The memory has a first portion, a second portion, and a third portion. The first portion is allocated to storing instructions for execution by the one or more processors. The second portion is allocated to storing data generated by the one or more processor, and the third portion is allocated to storing data from the one or more sensors. The third portion being a first-in-first-out (FIFO) having one or more FIFO portions, The device further includes a control logic operable to allocate the first, second and third portions of the memory, wherein each of one or more FIFO portions is allocated to each of the one or more sensors. The size each of the FIFO portions depends on the bandwidth of the sensors and the number of sensors. | 2014-09-18 |
20140281342 | MIGRATING AND RETRIEVING QUEUED DATA IN BYTE-ADDRESSABLE STORAGE - In an exemplary embodiment of this disclosure, a computer-implemented method may include storing in a primary storage a plurality of list entries belonging to an ordered list. Free space in the primary storage may be monitored to determine whether a first predetermined condition related to the free space is met. In a secondary storage, a storage block of a predetermined size may be allocated for migration, when the first predetermined condition is met. A cursor may be provided pointing to a first list entry in the primary storage. One or more list entries may be selected at the cursor. The selected list entries may be migrated to the storage block while maintaining their order in the list. | 2014-09-18 |
20140281343 | INFORMATION PROCESSING APPARATUS, PROGRAM, AND MEMORY AREA ALLOCATION METHOD - A processing apparatus includes a plurality of memories and a plurality of processors coupled to the plurality of memories and configured to determine, in accordance with a demand for allocation of a memory area of a first size to store first data used by an operating system, whether or not a memory area of a third size may be secured for each of the plurality of memories, the third size being obtained by adding the memory area of the first size and a memory area of a second size to store data used by an application program, and to store the first data in a first memory among the plurality of memories in a case where the first memory is determined to be capable of securing the memory area of the third size. | 2014-09-18 |
20140281344 | DATA PROCESSING SYSTEM AND METHOD OF OPERATING THE SAME - A method of operating a data processing system includes compressing a first part of uncompressed data, and determining whether to compress a second part of the uncompressed data based on an expected data size of the compressed first part and an actual data size of the compressed first part. The method further includes transmitting one of first transmission data and second transmission data to an external memory device based on a result of the determining. The first transmission data includes the compressed first and second parts, and the second transmission data includes the first and second parts of the uncompressed data. | 2014-09-18 |
20140281345 | Distributed Storage Allocation for Heterogeneous Systems - Allocation of storage budget in a computer-based distributed storage system is described, where associated computer-based storage nodes have heterogeneous access probabilities. The problem is to allocate a given storage budget across the available computer-based nodes so as to store a unit-size data object (e.g. file) with a higher reliability (e.g. increased probability for the storage budget to be recovered). Efficient algorithms for optimizing over one or more classes of allocations are presented. A basic one-level symmetric allocation is presented, where the storage budget is spread evenly over an appropriately chosen subset of nodes. Furthermore, a two-level symmetric allocation is presented, where the budget is divided into two parts, each spread evenly over a different subset of computer-based storage nodes, such that the amount allocated to each node in the first subset is twice that of the second subset. Further expansion of the two-level symmetric allocation is provided with a three-level and a generic k-level symmetric allocation. | 2014-09-18 |
20140281346 | MANAGING CPU RESOURCES FOR HIGH AVAILABILITY MICRO-PARTITIONS - A partition manager relocates a logical partition from a primary shared processor pool to a secondary shared processor pool in response to a predetermined condition, such as a hardware failure. The relocated logical partition is allocated a smaller quantity of processing units from the secondary pool than it was allocated from the primary pool. A quantity of processing units reserved for a second logical partition is identified in the secondary shared processor pool, and a portion of those reserved processing units are allocated to the relocated logical partition. The reserved processing units may be redistributed among multiple relocated logical partitions. | 2014-09-18 |
20140281347 | MANAGING CPU RESOURCES FOR HIGH AVAILABILITY MICRO-PARTITIONS - Profile properties in a partition profile are user-configurable through a management entity such as a management console. A partition manager calculates a secondary processing unit entitlement for a logical partition based in part on a secondary processing unit mode property in the partition profile. The secondary processing unit entitlement may be smaller than a primary processing unit entitlement for the logical partition. The partition manager reserves processing units from a secondary shared processor pool equal to the logical partition's secondary entitlement for the logical partition. The primary and secondary processing unit entitlements may be stored in primary and secondary configuration data structures associated with the logical partition. The partition manager may relocate the logical partition to the secondary shared processor pool in response to a predetermined condition. | 2014-09-18 |
20140281348 | MANAGING CPU RESOURCES FOR HIGH AVAILABILITY MICRO-PARTITIONS - A primary processing unit entitlement is determined for a logical partition. A smaller secondary processing unit entitlement is also determined. A partition manager allocates primary processing units to the logical partition from a primary shared processor pool, and the logical partition is activated. The secondary processing units are reserved for the logical partition from a secondary shared processor pool, and the logical partition can be relocated to the secondary shared processor pool in response to a condition such as a hardware failure. The logical partition can continue to process its workload with the fewer processor resources, and can be restored to the primary processing unit entitlement. | 2014-09-18 |
20140281349 | RECEIVE-SIDE SCALING IN A COMPUTER SYSTEM - A system, method, and computer program product are provided for receiving an incoming data stream. The system comprises a multi-core processor with a memory unit that is configured to include a circular queue that receives a data stream. The circular queue is divided into a plurality of sub-queues determined as a multiple of the number of processing cores, and each sub-queue is assigned to one processing core such that as data is received into a region covered by a particular sub-queue, the processing core assigned to the particular sub-queue processes the data. The system is also configured to update a head pointer and a tail pointer of the circular queue. The head pointer is updated as data is received into the circular queue and the tail pointer is updated by a particular processing core as it processes data in its assigned sub-queue. | 2014-09-18 |
20140281350 | MULTI-LAYERED STORAGE ADMINISTRATION FOR FLEXIBLE PLACEMENT OF DATA - A storage administrator may maintain location information in separate layers. A data storage system may identify the location of particular data by identifying the virtual location of data, such as the logical extent to which the data belongs. Object stores may maintain mappings of virtual locations to physical locations, such as mappings of extent identifiers to virtual storage objects and mappings of virtual storage objects to storage unit locations. When particular data is relocated to a new location, a storage administrator may update mappings used to translate virtual locations to physical locations, such as an extent-object mapping or an object-storage unit mapping. References to the virtual locations, such as references to logical extent identifiers, may not be updated in response to the relocation of data. | 2014-09-18 |
20140281351 | STRIDE-BASED TRANSLATION LOOKASIDE BUFFER (TLB) PREFETCHING WITH ADAPTIVE OFFSET - A processing device implementing stride-based translation lookaside buffer (TLB) prefetching with adaptive offset is disclosed. A processing device of the disclosure includes a data prefetcher to generate a data prefetch address based on a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request, and a TLB prefetch address computation component to generate a TLB prefetch address based on the linear address, the stride, the prefetch distance, or an adaptive offset. The processing device also includes a cross page detection component to determine that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address, and cause a TLB prefetch request to be written to a TLB request queue, the TLB prefetch request for translation of an address of a linear page number (LPN) based on the data prefetch address or the TLB prefetch address. | 2014-09-18 |
20140281352 | MECHANISM FOR FACILITATING DYNAMIC AND EFFICIENT MANAGEMENT OF TRANSLATION BUFFER PREFETCHING IN SOFTWARE PROGRAMS AT COMPUTING SYSTEMS - A mechanism is described for facilitating dynamic and efficient binary translation-based translation lookaside buffer prefetching according to one embodiment. A method of embodiments, as described herein, includes translating code blocks into code translation blocks at a computing device. The code translation blocks are submitted for execution. The method may further include tracking, in runtime, dynamic system behavior of the code translation blocks, and inferring translation lookaside buffer (TLB) prefetching based on the analysis of the tracked dynamic system behavior. | 2014-09-18 |
20140281353 | HARDWARE-BASED PRE-PAGE WALK VIRTUAL ADDRESS TRANSFORMATION - An apparatus includes a processor and a virtual address transformation unit coupled with the processor. The virtual address transformation unit includes a register. The virtual address transformation unit is configured to receive an indication of a virtual address and read, from the register, a current page size of a plurality of available page sizes. The virtual address transformation unit is also configured to determine a shift amount based, at least in part, on the current page size and perform a bit shift of the virtual address, wherein the virtual address is bit shifted by, at least, the determined shift amount. | 2014-09-18 |
20140281354 | CONTINUOUS RUN-TIME INTEGRITY CHECKING FOR VIRTUAL MEMORY - A run-time integrity checking (RTIC) method compatible with memory having at least portions that store data that is changed over time or at least portions configured as virtual memory is provided. For example, the method may comprise storing a table of page entries and accessing the table of page entries by, as an example, an operating system or, as another example, a hypervisor to perform RTIC on memory in which, as an example, an operating system, as another example, a hypervisor, or, as yet another example, application software is stored. The table may, for example, be stored in secure memory or in external memory. The page entry comprises a hash value for the page and a hash valid indicator indicating the validity status of the hash value. The page entry may further comprise a residency indicator indicating a residency status of the memory page. | 2014-09-18 |
20140281355 | VIRTUAL STORAGE POOL - Virtual storage pool creation is simplified by allowing a user to specify what devices to include in virtual storage pool by physical location. The virtual storage pool may be automatically generated based on the simplified user specifications. The user may specify the virtual pool configuration in a configuration file. A configuration application generates the virtual storage pool based on the configuration file. The configuration application utilizes the physical locations of block devices contained in the configuration file to generate the pool. As a result, virtual pool configuration and creation is automated, more efficient and is less error prone than previous methods that involve manually linking between physical device locations and computer generated names. | 2014-09-18 |
20140281356 | MICROCONTROLLER FOR MEMORY MANAGEMENT UNIT - One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased. | 2014-09-18 |
20140281357 | COMMON POINTERS IN UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 2014-09-18 |
20140281358 | MIGRATION SCHEME FOR UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 2014-09-18 |
20140281359 | APPARATUS AND METHOD FOR REFERENCING DENSE AND SPARSE INFORMATION IN MULTI-DIMENSIONAL TO LINEAR ADDRESS SPACE TRANSLATION - A translation system can translate a storage request having multiple fields to a physical address using the fields as keys to traverse a map. The map can be made of nodes that include one or more node entries. The node entries can be stored in a hashed storage area or sorted storage area of a node. A hashed storage area can enable a quick lookup of densely addressed information by using a portion of the key to determine a location of a node entry. A sorted storage area can enable compact storage of sparse information by storing node entries that currently exist and allowing the entries to be searched. By offering both types of storage in a node, a node can be optimized for both dense and sparse information. A node entry can include a link to a next node or the physical address for the storage request. | 2014-09-18 |
20140281360 | APPARATUS AND METHOD FOR INSERTION AND DELETION IN MULTI-DIMENSIONAL TO LINEAR ADDRESS SPACE TRANSLATION - A translation system can translate a storage request to a physical address using fields as keys to traverse a map of nodes with node entries. A node entry can include a link to a next node or a physical address. Using a portion of the key as noted in node metadata, a node entry can be determined. When adding node entries to a node, a node utilization can exceed a threshold value. A new node can be created such that node entries are split between the original and new node. Node metadata of the parent node, new node and original node can be revised to identify which parts of the key are used to identify a node entry. When removing node entries from a node, node utilization can cross a minimum threshold value. Node entries from the node can be merged with a sibling, or the map can be rebalanced. | 2014-09-18 |
20140281361 | NONVOLATILE MEMORY DEVICE AND RELATED DEDUPLICATION METHOD - A nonvolatile memory device comprises an interface configured to receive write data and a logical address of the write data, a data storage device comprising multiple physical blocks and configured to store an address mapping table array, and a controller configured to selectively load at least one address mapping table from the address mapping table array based on the logical address. The controller performs a deduplication operation for the write data by comparing the write data with data stored in a physical block having a physical address in the loaded address mapping table, to the exclusion of data stored in other physical blocks. | 2014-09-18 |
20140281362 | MEMORY ALLOCATION IN A SYSTEM USING MEMORY STRIPING - A system and associated methods are disclosed for allocating memory in a system providing translation of virtual memory addresses to physical memory addresses in a parallel computing system using memory striping. One method comprises: receiving a request for memory allocation, identifying an available virtually-contiguous physically-non-contiguous memory region (VCPNCMR) of at least the requested size, where the VCPNCMR is arranged such that physical memory addresses for the VCPNCMR may be derived from a corresponding virtual memory addresses by shifting a contiguous set of bits of the virtual memory address in accordance with information in a matching row of a virtual memory address matching table, and combining the shifted bits with high-order physical memory address bits also associated with the determined matching row and with low-order bits of the virtual memory address, and providing to the requesting process a starting address of the identified VCPNCMR. | 2014-09-18 |
20140281363 | MULTI-THREADED MEMORY MANAGEMENT - Memory management includes maintaining a first mapping structure for each thread of a multi-threaded process. A second mapping structure is maintained for each core of a multi-core processing device. A global mapping structure for shared memory mappings is maintained. During thread context switches, copying thread context entries without modifying a page-mapping base address register of each core of the multi-core processing device. | 2014-09-18 |
20140281364 | MICROCONTROLLER FOR MEMORY MANAGEMENT UNIT - One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased. | 2014-09-18 |
20140281365 | FRAME BUFFER ACCESS TRACKING VIA A SLIDING WINDOW IN A UNIFIED VIRTUAL MEMORY SYSTEM - One embodiment of the present invention is a memory subsystem that includes a sliding window tracker that tracks memory accesses associated with a sliding window of memory page groups. When the sliding window tracker detects an access operation associated with a memory page group within the sliding window, the sliding window tracker sets a reference bit that is associated with the memory page group and is included in a reference vector that represents accesses to the memory page groups within the sliding window. Based on the values of the reference bits, the sliding window tracker causes the selection a memory page in a memory page group that has fallen into disuse from a first memory to a second memory. Because the sliding window tracker tunes the memory pages that are resident in the first memory to reflect memory access patterns, the overall performance of the memory subsystem is improved. | 2014-09-18 |
20140281366 | ADDRESS TRANSLATION IN A SYSTEM USING MEMORY STRIPING - A system and associated methods are disclosed for translating virtual memory addresses to physical memory addresses in a parallel computing system using memory striping. One method comprises: receiving a virtual memory address, comparing a portion of the received virtual memory address to each of a plurality of entries of a virtual memory address matching table, determining a matching row of the virtual memory address matching table for the portion of the received virtual memory address, shifting a contiguous set of bits of the received virtual memory address, wherein the shifting is performed in accordance with information from the matching row, and combining the shifted contiguous set of bits of the received virtual memory address with high-order physical memory address bits associated with the determined matching row of the virtual memory address matching table, and with low-order bits of the received virtual memory address, to produce a physical memory address. | 2014-09-18 |
20140281367 | ADDRESS CALCULATION FOR RECEIVED DATA - A method of address generation and corresponding index generator for one or more locations in a buffer with received data, determining an offset address for a specific data element in the buffer; calculating a correction factor in parallel with the determining an offset address; and providing an address for the specific data element in the buffer by combining the offset address and the correction factor, the correction factor adjusting for any impact on the offset address resulting from null elements. | 2014-09-18 |
20140281368 | CYCLE SLICED VECTORS AND SLOT EXECUTION ON A SHARED DATAPATH - An example method for executing multiple instructions in one or more slots includes receiving a packet including multiple instructions and executing the multiple instructions in one or more slots in a time shared manner. Each slot is associated with an execution data path or a memory data path. An example method for executing at least one instruction in a plurality of phases includes receiving a packet including an instruction, splitting the instruction into a plurality of phases, and executing the instruction in the plurality of phases. | 2014-09-18 |
20140281369 | APPARATUS AND METHOD FOR SLIDING WINDOW DATA GATHER - An apparatus and method are described for fetching and storing a plurality of portions of a data stream into a plurality of registers. For example, a method according to one embodiment includes the following operations: determining a set of N vector registers into which to read N designated portions of a data stream stored in system memory; determining the system memory addresses for each of the N designated portions of the data stream; fetching the N designated portions of the data stream from the system memory at the system memory addresses; and storing the N designated portions of the data stream into the N vector registers. | 2014-09-18 |
20140281370 | VECTOR PROCESSING ENGINES HAVING PROGRAMMABLE DATA PATH CONFIGURATIONS FOR PROVIDING MULTI-MODE VECTOR PROCESSING, AND RELATED VECTOR PROCESSORS, SYSTEMS, AND METHODS - Embodiments disclosed herein include vector processing engines (VPEs) having programmable data path configurations for providing multi-mode vector processing. Related vector processors, systems, and methods are also disclosed. The VPEs include a vector processing stage(s) configured to process vector data according to a vector instruction executed in the vector processing stage. Each vector processing stage includes vector processing blocks each configured to process vector data based on the vector instruction being executed. The vector processing blocks are capable of providing different vector operations for different types of vector instructions based on data path configurations. Data paths of the vector processing blocks are programmable to be reprogrammable to process vector data differently according to the particular vector instruction being executed. In this manner, a VPE can be provided with its data paths configuration programmable to execute different types of functions based on data path configuration according to the vector instruction being executed. | 2014-09-18 |
20140281371 | TECHNIQUES FOR ENABLING BIT-PARALLEL WIDE STRING MATCHING WITH A SIMD REGISTER - Various embodiments are generally directed to overcoming limitations of vector registers in their use with bit-parallel string matching algorithms. An apparatus includes a processor element; and logic to receive a pattern comprising a first string of elements to employ in a string matching operation, instantiate a test bitmask in a first vector register of the processor element, the first vector register comprising multiple lanes, copy bit values at MSB bit positions of the multiple lanes of the first vector register to a first vector mask as a vector value, bit-shift the vector value as a scalar value, bit-shift the first vector register, employ the vector value of the first vector mask to selectively fill LSB bit positions of lanes of a second vector register of the processor element; and OR the second vector register into the first vector register. Other embodiments are described and claimed. | 2014-09-18 |
20140281372 | VECTOR INDIRECT ELEMENT VERTICAL ADDRESSING MODE WITH HORIZONTAL PERMUTE - An example method for placing one or more element data values into an output vector includes identifying a vertical permute control vector including a plurality of elements, each element of the plurality of elements including a register address. The method also includes for each element of the plurality of elements, reading a register address from the vertical permute control vector. The method further includes retrieving a plurality of element data values based on the register address. The method also includes identifying a horizontal permute control vector including a set of addresses corresponding to an output vector. The method further includes placing at least some of the retrieved element data values of the plurality of element data values into the output vector based on the set of addresses in the horizontal permute control vector. | 2014-09-18 |
20140281373 | DIGITAL SIGNAL PROCESSOR AND BASEBAND COMMUNICATION DEVICE - A digital signal processor has a vector execution unit arranged to execute instructions on multiple data in the form of a vector, comprising a local queue arranged to receive instructions from a program memory and to hold them in the local queue until a predefined condition is fulfilled. The local queue being arranged to receive a sequence of instructions at a time from the program memory and to store the last N instructions, N being an integer. A vector controller in the vector execution unit comprises queue control means arranged to make the local queue repeat a sequence of M instructions stored in the local queue, M being an integer less than or equal to N, a number K of times. This reduces the time the vector execution unit is kept waiting because of IDLE commands in the program memory. | 2014-09-18 |
20140281374 | Identifying Logical Planes Formed Of Compute Nodes Of A Subcommunicator In A Parallel Computer - In a parallel computer, a plurality of logical planes formed of compute nodes of a subcommunicator may be identified by: for each compute node of the subcommunicator and for a number of dimensions beginning with a first dimension: establishing, by a plane building node, in a positive direction of the first dimension, all logical planes that include the plane building node and compute nodes of the subcommunicator in a positive direction of a second dimension, where the second dimension is orthogonal to the first dimension; and establishing, by the plane building node, in a negative direction of the first dimension, all logical planes that include the plane building node and compute nodes of the subcommunicator in the positive direction of the second dimension. | 2014-09-18 |
20140281375 | RUN-TIME INSTRUMENTATION HANDLING IN A SUPERSCALAR PROCESSOR - A method and a computer program for a processor simultaneously handle multiple instructions at a time. The method includes labeling of an instruction ending a relevant sample interval from a plurality of such instructions. Further, the method utilizes a buffer to store N more number of entries than actually required, wherein, N refers to the number of RI instructions younger than the instruction ending a sample interval. Further, the method also includes the step of recording relevant instrumentation data corresponding to the sample interval and providing the instrumentation data in response to identification of the sample interval. | 2014-09-18 |
20140281376 | Creating An Isolated Execution Environment In A Co-Designed Processor - In an embodiment, a processor includes a binary translation (BT) container having code to generate a binary translation of a first code segment and to store the binary translation in a translation cache, a host entity logic to manage the BT container and to identify the first code segment, and protection logic to isolate the BT container from a software stack. In this way, the BT container is configured to be transparent to the software stack. Other embodiments are described and claimed. | 2014-09-18 |
20140281377 | Identifying Logical Planes Formed Of Compute Nodes Of A Subcommunicator In A Parallel Computer - In a parallel computer, a plurality of logical planes formed of compute nodes of a subcommunicator may be identified by: for each compute node of the subcommunicator and for a number of dimensions beginning with a first dimension: establishing, by a plane building node, in a positive direction of the first dimension, all logical planes that include the plane building node and compute nodes of the subcommunicator in a positive direction of a second dimension, where the second dimension is orthogonal to the first dimension; and establishing, by the plane building node, in a negative direction of the first dimension, all logical planes that include the plane building node and compute nodes of the subcommunicator in the positive direction of the second dimension. | 2014-09-18 |
20140281378 | THREE-DIMENSIONAL COMPUTER PROCESSOR SYSTEMS HAVING MULTIPLE LOCAL POWER AND COOLING LAYERS AND A GLOBAL INTERCONNECTION STRUCTURE - A computer processor system includes a plurality of multi-chip systems that are physically aggregated and conjoined. Each multi-chip system includes a plurality of chips that are conjoined together, and a local interconnection and input/output wiring layer. A global interconnection network is connected to the local interconnection and input/output wiring layer of each multi-chip system to interconnect the multi-chip systems together. One or more of the multi-chip systems includes a plurality of processor chips that are conjoined together. | 2014-09-18 |
20140281379 | Hybrid Programmable Many-Core Device with On-Chip Interconnect - The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner. | 2014-09-18 |
20140281380 | EXECUTION CONTEXT SWAP BETWEEN HETEROGENOUS FUNCTIONAL HARDWARE UNITS - Remapping technologies for execution context swap between heterogeneous functional hardware units are described. A computing system includes multiple registers configured to store remote contexts of functional units. A mapping table maps the remote context to the functional units. An execution unit is configured to execute a remapping tool that intercepts an operation to access a remote context of a first functional unit of the plurality of functional units that is taken offline. The remapping tool determines that the first functional unit is remapped to a second functional unit using the mapping table. The operation is performed to access the remote context that is remapped to the second functional unit. The first functional unit and the second functional unit may be heterogeneous functional units. | 2014-09-18 |
20140281381 | SYSTEM-ON-CHIP AND METHOD OF OPERATING THE SAME - A system-on-chip (SoC) includes a slave intellectual property (IP) block, a master IP block, and an update control unit. The slave IP block is configured to perform first processing on first data based on first control information stored in a first storage unit. The master IP block is configured to perform second processing on second data in response to receiving a first processing result obtained by performing the first processing on the first data. Performing the second processing is based on second control information stored in a second storage unit. The update control unit is configured to determine an update time of the first control information or an update time of the second control information in response to performing the first processing and performing the second processing. | 2014-09-18 |
20140281382 | MODIFIED EXECUTION USING CONTEXT SENSITIVE AUXILIARY CODE - A system and method to enhance execution of architected instructions in a processor uses auxiliary code to optimize execution of base microcode. An execution context of the architected instructions may be profiled to detect potential optimizations, resulting in generation and storage of auxiliary microcode. When the architected instructions are decoded to base microcode for execution, the base microcode may be enhanced or modified using retrieved auxiliary code. | 2014-09-18 |
20140281383 | GROUND-REFERENCED SINGLE-ENDED SIGNALING CONNECTED GRAPHICS PROCESSING UNIT MULTI-CHIP MODULE - A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-, ended signaling interface advantageously implements ground-referenced single-ended signaling. | 2014-09-18 |
20140281384 | METHOD AND APPARATUS FOR PREDICTING FORWARDING OF DATA FROM A STORE TO A LOAD - A method for gating a load operation based on entries of a prediction table is presented. The method comprises performing a look-up for the load operation in a prediction table to find a matching entry, wherein the matching entry corresponds to a prediction regarding a behavior of the load operation, and wherein the matching entry comprises: (a) a tag field operable to identify the matching entry; (b) a distance field operable to indicate a distance of the load operation to a prior aliasing store instruction; and (c) a confidence field operable to indicate a prediction strength generated by the prediction table. The method further comprises determining if the matching entry provides a valid prediction and, if valid, retrieving a location for the prior aliasing store instruction using the distance field. It finally comprises performing a gating operation on said load operation. | 2014-09-18 |
20140281385 | CONFIGURABLE MULTICORE NETWORK PROCESSOR - A network processor includes a plurality of processing cores configured to process data packets, and a processing mode mechanism configurable to configure the processing cores between a pipeline processing mode and a parallel processing mode. The processing mode mechanism may include switch elements, or a fabric logic and a bus, configurable to interconnect the processing cores to operate in either the pipeline processing mode or the parallel processing mode. | 2014-09-18 |
20140281386 | CHAINING BETWEEN EXPOSED VECTOR PIPELINES - Embodiments include a method for chaining data in an exposed-pipeline processing element. The method includes separating a multiple instruction word into a first sub-instruction and a second sub-instruction, receiving the first sub-instruction and the second sub-instruction in the exposed-pipeline processing element. The method also includes issuing the first sub-instruction at a first time, issuing the second sub-instruction at a second time different than the first time, the second time being offset to account for a dependency of the second sub-instruction on a first result from the first sub-instruction, the first pipeline performing the first sub-instruction at a first clock cycle and communicating the first result from performing the first sub-instruction to a chaining bus coupled to the first pipeline and a second pipeline, the communicating at a second clock cycle subsequent to the first clock cycle that corresponds to a total number of latch pipeline stages in the first pipeline. | 2014-09-18 |
20140281387 | CONVERTING CONDITIONAL SHORT FORWARD BRANCHES TO COMPUTATIONALLY EQUIVALENT PREDICATED INSTRUCTIONS - A processor is operable to process conditional branches. The processor includes instruction fetch logic to fetch a conditional short forward branch. The conditional short forward branch is to include a conditional branch instruction and a set of one or more instructions that are to sequentially follow the conditional branch instruction in program order. The set of the one or more instructions are between the conditional branch instruction and a forward branch target instruction that is to be indicated by the conditional branch instruction. The processor also includes instruction conversion logic coupled with the instruction fetch logic. The instruction conversion logic is to convert the conditional short forward branch to a computationally equivalent set of one or more predicated instructions. Other processors are also disclosed, as are various methods and systems. | 2014-09-18 |
20140281388 | Method and Apparatus for Guest Return Address Stack Emulation Supporting Speculation - A microprocessor implemented method for maintaining a guest return address stack in an out-of-order microprocessor pipeline is disclosed. The method comprises mapping a plurality of instructions in a guest address space into a corresponding plurality of instructions in a native address space. For each function call instruction in the native address space fetched during execution, the method also comprises performing the following: (a) pushing a current entry into a guest return address stack (GRAS) responsive to a function call, wherein the GRAS is maintained at the fetch stage of the pipeline, and wherein the current entry comprises information regarding both a guest target return address and a corresponding native target return address associated with the function call; (b) popping the current entry from the GRAS in response to processing a return instruction; and (c) fetching instructions from the native target return address in the current entry after the popping from the GRAS. | 2014-09-18 |
20140281389 | METHODS AND APPARATUS FOR FUSING INSTRUCTIONS TO PROVIDE OR-TEST AND AND-TEST FUNCTIONALITY ON MULTIPLE TEST SOURCES - Methods and apparatus are disclosed for fusing instructions to provide OR-test and AND-test functionality on multiple test sources. Some embodiments include fetching instructions, said instructions including a first instruction specifying a first operand destination, a second instruction specifying a second operand source, and a third instruction specifying a branch condition. A portion of the plurality of instructions are fused into a single micro-operation, the portion including both the first and second instructions if said first operand destination and said second operand source are the same, and said branch condition is dependent upon the second instruction. Some embodiments generate a novel test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the novel test instruction through a just-in-time compiler. Some embodiments also fuse the novel test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set. | 2014-09-18 |
20140281390 | SYSTEM AND METHOD FOR ORDERING PACKET TRANSFERS IN A DATA PROCESSOR - A data processor includes a packet selector. The packet selector creates an ordered list of packets, each packet corresponding to a respective communication flow, determines whether each packet in the ordered list of packets is eligible for transfer to a prefetch unit based on whether a preceding packet in the same communication flow has been transferred to the prefetch unit, and sets a selection priority for each packet based on start time constraints for the respective communication flow, and based on a processing status of a preceding packet in the communication flow. | 2014-09-18 |
20140281391 | METHOD AND APPARATUS FOR FORWARDING LITERAL GENERATED DATA TO DEPENDENT INSTRUCTIONS MORE EFFICIENTLY USING A CONSTANT CACHE - A processor to a store constant value (immediate or literal) in a cache upon decoding a move immediate instruction in which the immediate is to be moved (copied or written) to an architected register. The constant value is stored in an entry in the cache. Each entry in the cache includes a field to indicate whether its stored constant value is valid, and a field to associate the entry with an architected register. Once a constant value is stored in the cache, it is immediately available for forwarding to a processor pipeline where a decoded instruction may need the constant value as an operand. | 2014-09-18 |
20140281392 | PROFILING CODE PORTIONS TO GENERATE TRANSLATIONS - The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode. | 2014-09-18 |
20140281393 | REORDER-BUFFER-BASED STATIC CHECKPOINTING FOR RENAME TABLE REBUILDING - Out-of-order CPUs, devices and methods diminish the time penalty from stalling the pipe to rebuild a rename table, such as due to a misprediction. A microprocessor can include a pipe that has a decoder, a dispatcher, and at least one execution unit. A rename table stores rename data, and a check-point table (“CPT”) stores rename data received from the dispatcher. A Re-Order Buffer (“ROB”) stores ROB data, and has a static mapping relationship with the CPT. If the rename table is flushed, such as due to a misprediction, the rename table is rebuilt at least in part by concurrent copying of rename data stored in the CPT, in coordination with walking the ROB. | 2014-09-18 |
20140281394 | METHOD TO IMPROVE SPEED OF EXECUTING RETURN BRANCH INSTRUCTIONS IN A PROCESSOR - An apparatus and method for executing call branch and return branch instructions in a processor by utilizing a link register stack. The processor includes a branch counter that is initialized to zero, and is set to zero each time the processor decodes a link register manipulating instruction other than a call branch instruction. The branch counter is incremented by one each time a call branch instruction is decoded and an address is pushed onto the link register stack. In response to decoding a return branch instruction and provided the branch counter is not zero, a target address for the decoded return branch instruction is popped off the link register stack, the branch counter is decremented, and there is no need to check the target address for correctness. | 2014-09-18 |
20140281395 | Systems, Apparatuses, and Methods for Reducing the Number of Short Integer Multiplications - Systems, methods, and apparatuses for calculating a square of a data value of a first source operand, a square of a data value of a second source operand, and a multiplication of the data of the first and second operands only using one multiplication are described. | 2014-09-18 |
20140281396 | PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO CONSOLIDATE UNMASKED ELEMENTS OF OPERATION MASKS - An instruction processing apparatus of an aspect includes a plurality of operation mask registers. The apparatus also includes a decode unit to receive an operation mask consolidation instruction. The operation mask consolidation instruction is to indicate a source operation mask register, of the plurality of operation mask registers, and a destination storage location. The source operation mask register is to include a source operation mask that is to include a plurality of masked elements that are to be disposed within a plurality of unmasked elements. An execution unit is coupled with the decode unit. The execution unit, in response to the operation mask consolidation instruction, is to store a consolidated operation mask in the destination storage location. The consolidated operation mask is to include the unmasked elements from the source operation mask consolidated together. Other apparatus, methods, systems, and instructions are also disclosed. | 2014-09-18 |
20140281397 | FUSIBLE INSTRUCTIONS AND LOGIC TO PROVIDE OR-TEST AND AND-TEST FUNCTIONALITY USING MULTIPLE TEST SOURCES - Fusible instructions and logic provide OR-test and AND-test functionality on multiple test sources. Some embodiments include a processor decode stage to decode a test instruction for execution, the instruction specifying first, second and third source data operands, and an operation type. Execution units, responsive to the decoded test instruction, perform one logical operation, according to the specified operation type, between data from the first and second source data operands, and perform a second logical operation between the data from the third source data operand and the result of the first logical operation to set a condition flag. Some embodiments generate the test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the test instruction through a just-in-time compiler. Some embodiments also fuse the test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set. | 2014-09-18 |
20140281398 | INSTRUCTION EMULATION PROCESSORS, METHODS, AND SYSTEMS - A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems. | 2014-09-18 |
20140281399 | INSTRUCTION EMULATION PROCESSORS, METHODS, AND SYSTEMS - A processor of an aspect includes decode logic to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Other apparatus are also disclosed as well as methods and systems. | 2014-09-18 |
20140281400 | Systems, Apparatuses,and Methods for Zeroing of Bits in a Data Element - Embodiments of systems, methods and apparatuses for execution a NAME instruction are described. The execution of a VPBZHI causes, on a per data element basis of a second source, a zeroing of bits higher (more significant) than a starting point in the data element. The starting point is defined by the contents of a data element in a first source. The resultant data elements are stored in a corresponding data element position of a destination. | 2014-09-18 |
20140281401 | Systems, Apparatuses, and Methods for Determining a Trailing Least Significant Masking Bit of a Writemask Register - The execution of a KZBTZ finds a trailing least significant zero bit position in an first input mask and sets an output mask to have the values of the first input mask, but with all bit positions closer to the most significant bit position than the trailing least significant zero bit position in an first input mask set to zero. In some embodiments, a second input mask is used as a writemask such that bit positions of the first input mask are not considered in the trailing least significant zero bit position calculation depending upon a corresponding bit position in the second input mask. | 2014-09-18 |
20140281402 | PROCESSOR WITH HYBRID PIPELINE CAPABLE OF OPERATING IN OUT-OF-ORDER AND IN-ORDER MODES - A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode. | 2014-09-18 |
20140281403 | CHAINING BETWEEN EXPOSED VECTOR PIPELINES - Embodiments include a method for chaining data in an exposed-pipeline processing element. The method includes separating a multiple instruction word into a first sub-instruction and a second sub-instruction, receiving the first sub-instruction and the second sub-instruction in the exposed-pipeline processing element. The method also includes issuing the first sub-instruction at a first time, issuing the second sub-instruction at a second time different than the first time, the second time being offset to account for a dependency of the second sub-instruction on a first result from the first sub-instruction, the first pipeline performing the first sub-instruction at a first clock cycle and communicating the first result from performing the first sub-instruction to a chaining bus coupled to the first pipeline and a second pipeline, the communicating at a second clock cycle subsequent to the first clock cycle that corresponds to a total number of latch pipeline stages in the first pipeline. | 2014-09-18 |
20140281404 | SYSTEM AND METHOD TO CLEAR AND REBUILD DEPENDENCIES - A data processing system and method of clearing and rebuilding dependencies, the data processing method including changing a counter associated with a first entry in response to selecting a second entry; comparing the counter with a threshold; and indicating that the first entry is ready to be selected in response to comparing the counter with the threshold; wherein the first entry is dependent on the second entry. | 2014-09-18 |