38th week of 2014 patent applcation highlights part 225 |
Patent application number | Title | Published |
20140281705 | MECHANISM FOR FACILITATING DYNAMIC AND EFFICIENT MANAGEMENT OF INSTRUCTION ATOMICITY VOLATIONS IN SOFTWARE PROGRAMS AT COMPUTING SYSTEMS - A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads. | 2014-09-18 |
20140281706 | GENERATING FAULT TOLERANT CONNECTIVITY API - To make a connection between a user application and a data source fault tolerant, a user may use a wrapper generator to create an API wrapper that retries request that may have failed due to a service disruption. Generally, the wrapper manages a cache and contains the necessary information for retrying a connection after a service disruption. To create the wrapper, the wrapper generator may identify the different commands used by the user application to access the data source. The wrapper generator presents these commands to the user who organizes the commands to generate usage patterns for the different requests the user application may send to the data source. The user may also define a caching preference associated the commands in the usage patterns. To restart the connection, the wrapper may use the cache data to generate a new request to complete the original failed request. | 2014-09-18 |
20140281707 | MEDIA DELIVERY SERVICE PROTOCOL TO SUPPORT LARGE NUMBERS OF CLIENT WITH ERROR FAILOVER PROCESSES - A media delivery service may include a media source, a proxy cache and one or more client devices. The media source may generate coded segments from an input media stream and develop a playlist identifying network locations of the segments. The media source may broadcast the coded segments and their storage locations to a proxy cache in a broadcast channel. The proxy cache may store successfully received coded segments and develop a mapping table identifying the segments' network locations. The client may request segments from the proxy cache based on the received playlist form the media source. If the proxy cache does not store a requested segment, it may so notify the client and the client may request the segment from the media source. | 2014-09-18 |
20140281708 | GENERATING FAULT TOLERANT CONNECTIVITY API - To make a connection between a user application and a data source fault tolerant, a user may use a wrapper generator to create an API wrapper that retries request that may have failed due to a service disruption. Generally, the wrapper manages a cache and contains the necessary information for retrying a connection after a service disruption. To create the wrapper, the wrapper generator may identify the different commands used by the user application to access the data source. The wrapper generator presents these commands to the user who organizes the commands to generate usage patterns for the different requests the user application may send to the data source. The user may also define a caching preference associated the commands in the usage patterns. To restart the connection, the wrapper may use the cache data to generate a new request to complete the original failed request. | 2014-09-18 |
20140281709 | RECOVERY OF APPLICATION FROM SNAPSHOT - The targeted recovery of application-specific data corresponding to an application without performing recovery of the entire volume. The recovery is initiated by beginning to copy the prior state of the content of an application-specific data container from a prior snapshot to the application-specific data container in an operation volume accessible by the application. However, while the content of the application-specific data container is still being copied from the snapshot to the application-specific data container, the application is still permitted to perform read and write operations on the application-specific data container. Thus, the application-specific data container appears to the application to be fully accessible even though recovery of the content of the application-specific data container is still continuing in the background. | 2014-09-18 |
20140281710 | TRANSACTIONS FOR CHECKPOINTING AND REVERSE EXECUTION - A method of backstepping through a program execution includes dividing the program execution into a plurality of epochs, wherein the program execution is performed by an active core, determining, during a subsequent epoch of the plurality of epochs, that a rollback is to be performed, performing the rollback including re-executing a previous epoch of the plurality of epochs, wherein the previous epoch includes one or more instructions of the program execution stored by a checkpointing core, and adjusting a granularity of the plurality of epochs according to a frequency of the rollback. | 2014-09-18 |
20140281711 | MANAGED RUNTIME ENABLING CONDITION PERCOLATION - A method, apparatus, and/or computer program product protects a managed runtime from stack corruption due to native code condition handling. A native condition handler, which is associated with a managed runtime, percolates a condition. A condition handler of the managed runtime receives notification of the condition in a native code portion, and the condition handler of the managed runtime marks a thread associated with the condition. Responsive to a determination by the native code handler to resume execution of the marked thread by either call back into or a return to the managed runtime, the managed runtime determines whether a request is associated with the marked thread. Responsive to a determination that the request is associated with the marked thread, the managed runtime performs diagnostics and the managed runtime is terminated. | 2014-09-18 |
20140281712 | SYSTEM AND METHOD FOR ESTIMATING MAINTENANCE TASK DURATIONS - A computer-implemented method for estimating maintenance task durations is provided. The method is implemented by at least one computing system including at least one processor and at least one memory device coupled to the processor. The method includes receiving a query including a first query maintenance task and a plurality of query factors, and identifying an initial baseline task duration based at least in part on the first query maintenance task. The initial baseline task duration includes a plurality of baseline task factors. The method further includes identifying at least one adjustment factor based at least in part on the differences between the plurality of query factors and the plurality of baseline task factors, calculating a maintenance task duration estimate based at least in part on the initial baseline task duration and the adjustment factors, and planning execution of the first query maintenance task based on maintenance task duration estimate. | 2014-09-18 |
20140281713 | MULTI-STAGE FAILURE ANALYSIS AND PREDICTION - A hierarchical multi-stage model of asset failure risk for complex heterogeneously distributed physical assets is built. The hierarchical multi-stage model considers heterogeneity of failure patterns for the assets. At least one data stream is analyzed to determine whether the hierarchical multi-stage model needs to be updated due to a change in the failure patterns. If the analysis indicates that the hierarchical multi-stage model needs to be updated, the hierarchical multi-stage model is dynamically updated to obtain an updated hierarchical multi-stage model. | 2014-09-18 |
20140281714 | SYSTEM AND METHOD FOR COORDINATING FIELD USER TESTING RESULTS FOR A MOBILE APPLICATION ACROSS VARIOUS MOBILE DEVICES - A system and method for coordinating field user testing results for a mobile application across various mobile devices is provided. The system may comprise a plurality of mobile devices configured to facilitate field user testing of a test application, and a computing device configured to provide analysis related to field user testing of the test application. A testing module of the mobile device may be configured to: perform one or more operations of the test application; collect a plurality of metrics related to an execution of the one or more operations of the test application; determine whether an error occurred with an operation of the test application based on the collected one or more metrics; and transmit, to one or more other mobile devices, one or more metrics related to the execution of the operation at which the error occurred. The testing module may be part of the operating system. | 2014-09-18 |
20140281715 | METHOD AND APPARATUS FOR SCALING NETWORK SIMULATION - Embodiments disclosed herein enable network simulation including a range of networking technologies to be scaled to include large numbers of devices under test (DUTs) even though computing resources, such as a total number of simulation hosts or IP addresses, may be limited. By enabling a network simulator to scale with limited computing resources, developers may be enabled to reduce the requirements for physical space, power, cost, and maintenance for network simulation. For example, developers may be able to determine capacity, such as a total number of DUTs that a network management system (NMS) is capable of managing, even though few simulation hosts or IP addresses may be available for simulation of the DUTs. | 2014-09-18 |
20140281716 | ANALOG BLOCK AND TEST BLOCKS FOR TESTING THEREOF - An apparatus relating generally to a system-on-chip is disclosed. In this apparatus, the system-on-chip has at least one analog block, an input/output interface, a data test block, and a processing unit. The processing unit is coupled to the input/output interface to control access to the at least one analog block. The data test block is coupled to the at least one analog block through the input/output interface. The processing unit is coupled to the data test block and configured to execute test code having at least one test pattern. The data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern. | 2014-09-18 |
20140281717 | BUILT-IN SELF TEST (BIST) WITH CLOCK CONTROL - A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode and a plurality of shift-capture clock generator circuits. Each shift-capture clock generator circuit includes a clock gate circuit and a clock divider circuit and is configured to receive a corresponding one of the plurality of clock signals. At least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode. | 2014-09-18 |
20140281718 | COMPUTER-ON-MODULE DEBUG CARD ASSEMBLY AND A CONTROL SYSTEM THEREOF - A computer-on-Module debug card assembly and a control system thereof comprising: a carrier module with a carrier board and electronic components thereon wherein the carrier board is provided with a plurality of I/O connectors and at least a bus; a debug module electrically connected to the carrier board and comprising a debug card and electronic components thereon wherein the debug card is equipped with a detecting component, at least a bus, and a plurality of switch buttons used to check switching; a COM express system electrically connected to the debug card and comprising a COM express board and electronic components thereon wherein the COM express board is provided with modular components and at least a bus. As such, it is able to identify messages for a CPU-bearing COM express board and a carrier board in the COM express system during debugging, streamlining the procedure and saving time. | 2014-09-18 |
20140281719 | EXPLAINING EXCLUDING A TEST FROM A TEST SUITE - A method, apparatus and product for explaining excluding a test from a test suite. In one embodiment, the method comprising: obtaining a reduced test suite covering test requirements, the reduced test suite excluding a test covering a subset of the test requirements; determining, by a processor, a subset of the reduced test suite covering the subset of the test requirements; and outputting an indication that the subset of the test requirements is covered by the subset of the reduced test suite. | 2014-09-18 |
20140281720 | SYSTEM AND METHOD OF PERFORMING A HEALTH CHECK ON A PROCESS INTEGRATION COMPONENT - In an example embodiment, a method of performing a health check on a process integration (PI) component is provided. A PI health check scenario is loaded into the PI component, the PI health check scenario including a reference to a list of checks. The PI health check scenario is then executed using the PI component, causing one or more checks in the list of checks to be performed at a predetermined frequency. The system can then automatically determine if one or more of the one or more checks fail. | 2014-09-18 |
20140281721 | AUTOMATIC GENERATION OF TEST SCRIPTS - Systems and methods for automatically generating test scripts are described. The systems and methods may access information from a template that includes at least one entry associated with a test case to be applied to a system under testing, apply a translation scheme to the accessed information, and generate a test script in a language that is associated with the translation scheme and that is based on the information accessed from the template. The systems and methods may then utilize the test script to test the functionality of a system under testing, among other things. | 2014-09-18 |
20140281722 | DEBUGGING PROCESSOR HANG SITUATIONS USING AN EXTERNAL PIN - Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, a forced halt sequence can be initiated, which causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction. | 2014-09-18 |
20140281723 | Algorithm Selection For Collective Operations In A Parallel Computer - Algorithm selection for collective operations in a parallel computer that includes a plurality of compute nodes may include: profiling a plurality of algorithms for each of a set of collective operations, including for each collective operation: executing the operation a plurality times with each execution varying one or more of: geometry, message size, data type, and algorithm to effect the collective operation, thereby generating performance metrics for each execution; storing the performance metrics in a performance profile; at load time of a parallel application including a plurality of parallel processes configured in a particular geometry, filtering the performance profile in dependence upon the particular geometry; during run-time of the parallel application, selecting, for at least one collective operation, an algorithm to effect the operation in dependence upon characteristics of the parallel application and the performance profile; and executing the operation using the selected algorithm. | 2014-09-18 |
20140281724 | METHOD AND APPARATUS TO TRIGGER AND TRACE ON-CHIP SYSTEM FABRIC TRANSACTIONS WITHIN THE PRIMARY SCALABLE FABRIC - A fabric trace hook is disclosed to enable debugging operations of agents operating in a peer-to-peer integrated on-chip system fabric. The fabric trace hook, embedded within the IOSF, includes programmable triggering and capturing logic, timestamp capability, and a security feature to disallow tracing of proprietary transactions. The fabric trace hook may operate in a lossy or lossless mode. | 2014-09-18 |
20140281725 | DETECTION OF MEMORY CELLS THAT ARE STUCK IN A PHYSICAL STATE - A method for detecting memory cells that are stuck in a physical state. The method includes performing a diagnostic read of a memory cell in a memory system. The memory system is configured to utilize at least one read threshold value to determine a read data value stored in the memory cell when performing a data read operation on the memory cell. Performing the diagnostic read includes: comparing a measurement property of the memory cell to at least one diagnostic threshold value, where at least one of the diagnostic threshold values is different from all of the read threshold values; and identifying the memory cell as being stuck in a physical state based on the comparing. Based on identifying the memory cell as being stuck in a physical state, an indication that memory cell is stuck is output along with a diagnostic data value associated with the physical state. | 2014-09-18 |
20140281726 | Bottleneck Detector Application Programming Interface - An application programming interface may receive workload identifiers and checkpoint identifiers from which bottleneck detection may be performed. Workloads may be tracked through various checkpoints in an application and timestamps collected at each checkpoint. From these data, bottlenecks may be identified in real time or by analyzing the data in a subsequent analysis. The workloads may be processed by multiple devices which may comprise a large application. In some cases, the workloads may be processed by different devices in sequence or in a serial fashion, while in other cases workloads may be processed in parallel by different devices. The application programming interface may be part of a bottleneck detection service which may be sold on a pay-per-use model, a subscription model, or some other payment scheme. | 2014-09-18 |
20140281727 | GROUPING AND ANALYSIS OF DATA ACCESS HAZARD REPORTS - A method for analyzing race conditions between multiple threads of an application is disclosed. The method comprises accessing hazard records for an application under test. It further comprises creating a graph comprising a plurality of vertices and a plurality of edges using the hazard records, wherein each vertex of the graph comprises information about a code location of a hazard and wherein each edge of the graph comprises hazard information between one or more vertices. Additionally, it comprises assigning each edge with a weight, wherein the weight depends on a number and relative priority of hazards associated with a respective edge. Finally, it comprises traversing the graph to report an analysis record for each hazard represented in the graph. | 2014-09-18 |
20140281728 | COMMUNICATION SYSTEM, COMMUNICATION TERMINAL, AND COMPUTER PROGRAM PRODUCT - A plurality of communication terminals communicate via a communication line in a communication system. The communication system includes: a diagnosis unit configured to diagnose a state of a device built in the communication terminal or a device connected to the communication terminal; a management unit configured to manage diagnosis result data for each of the communication terminals; a determination unit configured to determine a usage of the communication terminal based on diagnosis result data of the communication terminal; and a display processing unit configured to perform a process of displaying, on a display unit, information based on the usage determined by the determination unit together with the diagnosed state of the device of the communication terminal. | 2014-09-18 |
20140281729 | ANALYSIS OF A SYSTEM FOR MATCHING DATA RECORDS - Embodiments disclosed herein provide a system and method for analyzing an identity hub. Particularly, a user can connect to the identity hub, load an initial set of data records, create and/or edit an identity hub configuration locally, analyze and/or validate the configuration via a set of analysis tools, including an entity analysis tool, a data analysis tool, a bucket analysis tool, and a linkage analysis tool, and remotely deploy the validated configuration to an identity hub instance. In some embodiments, through a graphical user interface, these analysis tools enable the user to analyze and modify the configuration of the identity hub in real time while the identity hub is operating to ensure data quality and enhance system performance. | 2014-09-18 |
20140281730 | DEBUGGING SESSION HANDOVER - A method includes, during operation of a software debugging tool on a software program, and upon indication by a first user of the software debugging tool of a step of the operation as a event of interest, collecting data related to that event of interest. A unique identifier is assigned to the collected data. Access to the collected data is enabled for a second user of the software debugging tool. | 2014-09-18 |
20140281731 | MANAGED RUNTIME ENABLING CONDITION PERCOLATION - A method, apparatus, and/or computer program product protects a managed runtime from stack corruption due to native code condition handling. A native condition handler, which is associated with a managed runtime, percolates a condition. A condition handler of the managed runtime receives notification of the condition in a native code portion, and the condition handler of the managed runtime marks a thread associated with the condition. Responsive to a determination by the native code handler to resume execution of the marked thread by either call back into or a return to the managed runtime, the managed runtime determines whether a request is associated with the marked thread. Responsive to a determination that the request is associated with the marked thread, the managed runtime performs diagnostics and the managed runtime is terminated. | 2014-09-18 |
20140281732 | AUTOMATED UPDATE TESTING AND DEPLOYMENT - Systems and methods for testing and deploying an update are provided. A first server can execute a current version of an application in a production environment. A client communication from a client to the first server can be identified. The client communication can be transmitted to a second server in the production environment. The second server can be executing an updated version of the application. A first response to the client communication from the first server and a second response to the client communication from the second server can be received. The first response from the first server can be compared with the second response from the second server to determine whether the updated version of the application is compatible with the production environment. | 2014-09-18 |
20140281733 | PARALLEL SOFTWARE TESTING - A system of testing software is provided. The system comprises a first hardware system having hardware components to execute a first version of the software, and additionally comprises a second hardware system having hardware components to execute a second version of the software. Here, the first version of the software and the second version are different. In addition, the system includes a device configured to test the first hardware system and the second hardware system by providing first input data traffic to the first hardware system, providing second input data traffic to the second hardware system, and accessing performance values from the first hardware system and the second hardware system to evaluate a performance comparison between the first hardware system executing the first version of the software and the second hardware system executing the second version of the software. | 2014-09-18 |
20140281734 | DETERMINING FLASE ALARMS IN AN IT APPLICATION - An example of the present invention provides a method and system for automatically suppressing false alarms in an IT system, such as an IT application. The method includes consolidating abnormal metrics into a single anomaly. A size of the anomaly relative to the IT application is determined, as well as a distribution of the anomaly in the IT application. A false alarm is determined based on the size and the distribution of the anomaly. | 2014-09-18 |
20140281735 | SYSTEM AND METHOD FOR MULTICORE PROCESSING - A method and apparatus for an asynchronous multicore common debugging system is described. Debug signals from a plurality of processor cores are synchronized to a common timing domain. Processing completed within the plurality of processor cores during a common timing interval is tracked. A single debugging tool chain is utilized to provide debugging results in response to the tracking the processing completed within the plurality of processor cores during the common timing interval. | 2014-09-18 |
20140281736 | SELF-DIAGNOSING METHOD OF A VOLATILE MEMORY DEVICE AND AN ELECTRONIC DEVICE PERFORMING THE SAME - In a self-diagnosing method of a volatile memory device, a processor outputs a self-refresh entrance command and enters a power save mode, and a volatile memory device performs a self-diagnosing operation for a plurality of memory cells in response to the self-refresh entrance command while the processor is in the power save mode. | 2014-09-18 |
20140281737 | BROADBAND DIAGNOSTICS SYSTEM - A broadband diagnostics system provides the capability to collect, store and recall historical data for the purpose of comparing to current and existing network elements and conditions. The system allows testing, troubleshooting, tracking, identifying and logging information pertaining to both cable networks and xDSL networks, and their associated elements. The diagnostics system allows for identification and testing of network elements deployed on the customer premises, behind the point of demarcation. In this deployment methodology, the demarcation point is the cable or xDSL modem. The system allows for the identification of bonded channels within the DOCSIS 3.x specification. | 2014-09-18 |
20140281738 | METHOD AND SYSTEM FOR KEY PERFORMANCE INDICATORS ELICITATION WITH INCREMENTAL DATA DECYCLING FOR DATABASE MANAGEMENT SYSTEM - A method for processing signals from a data server system including generating, by a monitoring module on a monitoring facility, a plurality of frequency data items, where the monitoring facility comprises a central processing unit, obtaining, by the monitoring module, a first signal value from the data server system, where the signal value is a measurement of an element of the data server system, and calculating a plurality of fit errors for the plurality of frequency data items using the first signal value. The method further includes selecting a frequency data item of the plurality of frequency data items with a lowest fit error to obtain a selected frequency data item, removing a cyclic component of the first signal value using the selected frequency data item to obtain a first processed signal value, and displaying the first processed signal value on a graph. | 2014-09-18 |
20140281739 | CRITICAL SYSTEMS INSPECTOR - Techniques are described for identifying a root cause of a pattern of performance data in a system including a plurality of services. Embodiments provide dependency information for each of the plurality of services, where at least one of the plurality of services is dependent upon a first one of the plurality of services. Each of the plurality of services is monitored to collect performance data for the respective service. Embodiments further analyze the performance data to identify a cluster of services that each follow a pattern of performance data. The first one of the services in the cluster of services is determined to be a root cause of the pattern of performance data, based on the determined dependency information for each of the plurality of services. | 2014-09-18 |
20140281740 | VULNERABILITY ESTIMATION FOR CACHE MEMORY - A method of determining vulnerability of a cache memory includes associating a first counter with a cache element and periodically incrementing the first counter. When a read or other access that consumes the data in the cache element occurs, a current value of the first counter is accumulated. When a write or other cache access that modifies data in the cache element occurs, the first counter is reset. At the end of an evaluation period, the value in a total counter approximates the number of clock cycles during which data that was consumed was vulnerable. Dividing this value by the number of clock cycles approximates the vulnerability of this cache element. The vulnerability for a subset of all cache elements may be measured and extrapolated to obtain an estimate for the vulnerability of the cache memory as a whole. | 2014-09-18 |
20140281741 | METHOD, USER INTERFACE AND APPARATUS FOR CLOUD SERVICE CONFIDENCE LEVEL GENERATION AND DISPLAY - A method, user interface and system are provided that enable a user to monitor an information technology (“IT”) service that is provided via an electronics communications network. A user is visually presented with values that indicate a probability of IT service degradation or failure. A unified monitor automatically employs a set of parametric sensors to develop a comprehensive view of users cloud service providers and assess the robustness and security of specified services. The monitor combines relevant information that may affect a user's confidence in services and applies algorithms to assess and forecast service reliability at any given time by vendor and dedicated computational assets. The monitor may present service predictions and reliability assessments through a visual dashboard along with available or recommended mitigation actions. The dashboard enables simultaneous visualization of assets, service, and metrics and thereby supports timely intuitive forensic analysis and optionally prompt application of mitigation activities. | 2014-09-18 |
20140281742 | SYSTEMS AND METHODS FOR INCREASING ROBUSTNESS OF A SYSTEM WITH A REMOTE SERVER - Systems and methods for increasing robustness of a system with a remote server are provided. Some methods can include a first system remotely controlling a second system, detecting a failure in the first system or in a communication link between the first system and the second system, and temporarily removing control of the second system from the first system. | 2014-09-18 |
20140281743 | AUTOMATIC RECOVERY OF RESERVOIR SIMULATION RUNS FROM PROCESSING SYSTEM FAILURES - Reservoir simulation is performed for giant reservoir models in a parallel computing platform composed of a number of processor nodes. Automatic precautionary checkpoints are made at regular time intervals when computational time exceeds a preset value. The simulator receives and reacts to signals from a real time monitoring interface tool which monitors the health of the system. Checkpoints are also made done if a system problem which may cause a simulation job to fail is projected. The simulation job is subsequently restarted to continue simulation from the last checkpoint. The monitoring and automatic recovery are done automatically without need for user intervention. | 2014-09-18 |
20140281744 | SYSTEMS AND METHODS FOR MANAGING FAILURE OF APPLICATIONS IN A DISTRIBUTED ENVIRONMENT - A mechanism for managing failure of applications in a distributed environment is disclosed. A method includes detecting failure in an application node among a plurality of application nodes when the application node does not respond to a status message. The method further includes routing, by enterprise application nexus application processing interface (EANA) module, a first lock message to the failed application node and ancestors' nodes of the failed application node when the failed application node is an aware application node. | 2014-09-18 |
20140281745 | Tracking Errors In A Computing System - Tracking errors in a computing system that includes a plurality of current error buckets and a plurality of historical error buckets, including: inserting, by an error repository manager into a current error bucket, error information describing a first error identified by a timestamp; moving, by the error repository manager, the error information in the current error bucket to a historical error bucket upon the expiration of the bucket interval, wherein each historical error bucket has a storage interval determined in dependence upon the base time interval associated with the error and a bucket number associated with the historical error bucket; and moving, by the error repository manager, the error information in a source historical error bucket to a destination historical error bucket upon the expiration of the storage interval associated with the source historical error bucket. | 2014-09-18 |
20140281746 | QUERY REWRITES FOR DATA-INTENSIVE APPLICATIONS IN PRESENCE OF RUN-TIME ERRORS - Embodiments relate to a method and computer program product for error handling. The method includes performing at least one query operation. The processing of query operation also includes generating error information data based at least an error encountered during performance of the query operation and generating a data result relating to any portion of the query operation successfully completed. The data result is processed together with the error information data based on encountering any errors. The data result and error information are provided together in a package but separated by an indicator to distinguish between them. | 2014-09-18 |
20140281747 | Fault Handling at a Transaction Level by Employing a Token and a Source-to-Destination Paradigm in a Processor-Based System - A method for detecting errors in a processing device is disclosed. A data source unit of a processing device transmits data and a qualifier synchronously with the data, the qualifier to indicate the data is uncorrectable. At least one intermediate functional unit in the processing device receives the data and the qualifier. The at least one intermediate functional unit detects the data is uncorrectable based on the qualifier. The at least one intermediate functional unit transmits, without using, the data and the qualifier synchronously with the data to a data consumer unit of the processing device. The data consumer unit receives the data and the qualifier. The data consumer unit detects the data is uncorrectable based on the qualifier. The data consumer unit maintains, without using the data and the qualifier. | 2014-09-18 |
20140281748 | QUERY REWRITES FOR DATA-INTENSIVE APPLICATIONS IN PRESENCE OF RUN-TIME ERRORS - An aspect of error handling includes a parsing block for pre-processing a document indexing application, a filtering block for discarding irrelevant documents, a transformation block to clean up and annotate input data by identifying a document language, and a processor configured for grouping inputs to collect documents for a same entity in a single spot. The processor processes a query operation. An aspect of error handling also includes a data package including a data result component that includes data generated based on successful completion of at least a portion of the query operation. The data package also includes an error information data component based on one or more errors encountered during processing of the query operation. An indicator separates the error information data from the data result. The system also includes a memory associated with a distributed file system for storing a final write output relating to the query operation. | 2014-09-18 |
20140281749 | LINEAR FEEDBACK SHIFT REGISTER WITH SINGLE BIT ERROR DETECTION - A linear feedback shift register machine capable of generating periodic sequences and having means for detecting single point errors in the generated sequences. | 2014-09-18 |
20140281750 | DETECTING EFFECT OF CORRUPTING EVENT ON PRELOADED DATA IN NON-VOLATILE MEMORY - A method includes determining a read threshold voltage corresponding to a group of storage elements in a non-volatile memory of a data storage device. The method also includes determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage. The method includes comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event. | 2014-09-18 |
20140281751 | EARLY DATA DELIVERY PRIOR TO ERROR DETECTION COMPLETION - Embodiments relate to early data delivery prior to error detection completion in a memory system. One aspect is a system that includes a cache subsystem interface with a correction pipeline in a system domain. The system includes a memory control unit interface in a memory controller nest domain and a buffer control block providing an asynchronous boundary layer between the system domain and the memory controller nest domain. A controller is configured to receive a frame of a multi-frame data block and write the frame to the buffer control block. The frame is read by the cache subsystem interface prior to completion of error detection of the multi-frame data block. Error detection is performed on the frame in the memory controller nest domain. Based on detecting an error in the frame, an intercept signal is sent from the memory controller nest domain to the correction pipeline in the system domain. | 2014-09-18 |
20140281752 | REDUNDANT BUS FAULT DETECTION - A system and method for an approach of detecting faults in a redundant bus system based upon four timers. | 2014-09-18 |
20140281753 | Systems, Apparatuses, and Methods for Handling Timeouts - Systems, apparatuses, and method for handling timeouts in a link state training sequence are described. All modules of a port undergoing link state training placed into an intermediate state prior to entry into the lowest power state. | 2014-09-18 |
20140281754 | ON-SITE VISUALIZATION OF COMPONENT STATUS - Apparatus and computer program products implement embodiments of the present invention that enable a portable computing device such as a smartphone or a tablet computer, to capture one or more codes for one or more corresponding components positioned in proximity to the portable computing device, and to convey the one or more codes to a management system. Upon receiving the one or more codes, the management system can be configured to convey, to the portable computing device, an identification and a status of each of the one or more components. The portable computing device can then present the status of the one or more components on a display. | 2014-09-18 |
20140281755 | Identify Failed Components During Data Collection - A mechanism is provided for identifying failed components during data collection. For each data source combination in a plurality of data sources, a determination is made as to whether a standard deviation (σ) for an estimated collection interval of the data source is above a predetermined standard deviation threshold (σ | 2014-09-18 |
20140281756 | METHOD AND APPARATUS FOR TRACKING DEVICE INTERACTION INFORMATION - A system includes a processor configured to attempt to establish communication with a wireless device. The processor is also configured to store instances of connection failure and related error data. Further, the processor is configured to perform interaction with a connected device. The processor is additionally configured to store interaction failures related error data. The processor is also configured to determine that a remote network connection has been established and report all stored data that has not previously been reported relating to the connection failures and errors and interaction failures and error data to a remote network | 2014-09-18 |
20140281757 | Tracking Errors In A Computing System - Tracking errors in a computing system that includes a plurality of current error buckets and a plurality of historical error buckets, including: inserting, by an error repository manager into a current error bucket, error information describing a first error identified by a timestamp; moving, by the error repository manager, the error information in the current error bucket to a historical error bucket upon the expiration of the bucket interval, wherein each historical error bucket has a storage interval determined in dependence upon the base time interval associated with the error and a bucket number associated with the historical error bucket; and moving, by the error repository manager, the error information in a source historical error bucket to a destination historical error bucket upon the expiration of the storage interval associated with the source historical error bucket. | 2014-09-18 |
20140281758 | ON-SITE VISUALIZATION OF COMPONENT STATUS - Methods, apparatus and computer program products implement embodiments of the present invention that enable a portable computing device such as a smartphone or a tablet computer, to capture one or more codes for one or more corresponding components positioned in proximity to the portable computing device, and to convey the one or more codes to a management system. Upon receiving the one or more codes, the management system can be configured to convey, to the portable computing device, an identification and a status of each of the one or more components. The portable computing device can then present the status of the one or more components on a display. | 2014-09-18 |
20140281759 | BUS PROTOCOL CHECKER, SYSTEM ON CHIP INCLUDING THE SAME, BUS PROTOCOL CHECKING METHOD - A system on chip (SoC) includes a system bus; a plurality of intellectual properties (IPs) outputting bus signals via the system bus; and one or more checkers disposed to correspond to at least some of the plurality of IPs, wherein the checker includes: a first environment setting register for setting information about a check target and list, on which a bus protocol check operation will be performed, wherein the setting may be variable according to an access from outside via the system bus; and a check logic receiving the bus signal and performing a bus protocol check operation on a signal included in the bus signal according to the information set in the first environment setting register. | 2014-09-18 |
20140281760 | MANAGEMENT SERVER, MANAGEMENT SYSTEM, AND MANAGEMENT METHOD - It is provided a management server is configured to store an access log including a monitoring subject ID, or a monitoring item ID when a request for outputting a historical data is inputted, an incident data including a time, a monitoring subject ID, or a monitoring item ID when an incident indicating a failure in the each of the devices; associate the incident data with the access log; update data included in the access log to a string of characters abstracted; generate an abstract access log; identify first abstract access log from the generated abstract access log based on the first incident data when a value indicating first incident data is inputted; identify a condition for the historical data to be outputted based on the first abstract access log and the first incident data; and output the identified condition for the historical data. | 2014-09-18 |
20140281761 | Reversible corruption of a digital medium stream by multi-valued modification in accordance with an automatically generated mask - Methods and apparatus create a corruption mask from a sequence that is generated by an n-state sequence generator with n>2. A digital media stream containing n-state symbols is corrupted in accordance with the corruption mask. The corruption takes place by applying a one argument or a two argument n-state logic function. The corruption rate of the digital media stream is preferably less than 100% allowing it to be reviewed. Data related to the corruption mask and the corruption mask are transmitted to a processor based receiver, allowing the receiver to decorrupt the corrupted digital media stream and to display it in its uncorrupted state. | 2014-09-18 |
20140281762 | SYSTEM AND METHOD FOR RANDOM NOISE GENERATION - A random noise generation module for generating noisy LLRs for testing an error correction circuit of a nonvolatile memory storage module. The random noise generation module includes a coefficient generator for generating one or a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module. The random noise generation module further includes a linear random number generator for generating a linear random number and a comparator for comparing the linear random number to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the linear random number belongs to generate a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module. | 2014-09-18 |
20140281763 | METHOD, APPARATUS, AND SYSTEM FOR MEASUREMENT OF NOISE STATISTICS AND BIT ERROR RATIO ESTIMATION - A sample voltage is received from a device at a first slicer element and a second slicer element. A decision by the first slicer element based on the sample voltage is identified and compared with a decision of the second slicer element based on the sample voltage. The decision of the second slicer element is to be generated from a comparison of the sample voltage with a reference voltage for the second slicer element. Comparing the decisions can be the basis of a soft error ration determined for a device. | 2014-09-18 |
20140281764 | DATA PATH MEMORY TEST - A system comprises pipeline registers and an integrated circuit comprising a memory array. The integrated circuit is coupled to the pipeline registers, and a data path incorporating the memory array is used to test the integrated circuit. | 2014-09-18 |
20140281765 | MEMORY CARD - A memory card includes a memory cell, a connector, a controller, and firmware. The memory cell can switch between a plurality of states. The connector can be connected to an external device and exchange signals including commands and data with the external device. The controller exchanges signals with the connector, analyzes a received signal, and accesses the memory cell to record, retrieve or modify data based on the analysis result. The firmware is located within the controller, controls the operation of the controller, and can be set to a test mode or a user mode. When the firmware receives a test command from the external device and the firmware is set to the test mode, the firmware performs a defect test on the memory cell and transmits the result of the defect test to the external device through the connector. | 2014-09-18 |
20140281766 | PROBABILITY-BASED REMEDIAL ACTION FOR READ DISTURB EFFECTS - A method may be performed in a data storage device that includes a memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line. | 2014-09-18 |
20140281767 | RECOVERY STRATEGY THAT REDUCES ERRORS MISIDENTIFIED AS RELIABLE - A method for applying a sequence of sensing/read reference voltages in a read channel includes (A) setting a read window based on an estimate of a read channel, (B) setting first, second, and third values of a sequence of sensing voltages to values corresponding to different ones of (i) a left-hand limit of the read window, (ii) a right-hand limit of the read window; and (iii) a point central to the read window, (C) determining whether first, second and third reads are successful, and (D) if the first, second and third reads are not successful, setting fourth and fifth values of the sequence of sensing voltages to values corresponding to different ones of (i) a point between the left-hand limit and the point central to the read window and (ii) a point between the right-hand limit and the point central to the read window. | 2014-09-18 |
20140281768 | RETENTION LOGIC FOR NON-VOLATILE MEMORY - An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state characterized by a minimum threshold exceeding a selected read bias. A controller includes a stand-by mode, a write mode and a read mode. Retention check logic executes on power-up, or during the stand-by mode, to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells. | 2014-09-18 |
20140281769 | MEMORY SYSTEM AND MEMORY CONTROLLER - According to one embodiment, a memory system includes a non-volatile memory and a memory controller that controls the non-volatile memory. The non-volatile memory includes a memory cell array and an access control unit. The access control unit performs a program operation for changing threshold voltages of memory cells and a read operation for reading data from the memory cells. The memory controller includes a read/write control unit having a first program parameter set and a second program parameter set. The read/write control unit causes the access control unit to perform a program operation based on the first program parameter set, and when a predetermined condition is satisfied, performs switching from the first program parameter set to the second program parameter set and causes the access control unit to perform a program operation based on the second program parameter set. | 2014-09-18 |
20140281770 | METHOD OF READING DATA FROM A NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE, AND METHOD OF OPERATING A MEMORY SYSTEM - In a method of reading data from a nonvolatile memory device, a first read operation for memory cells coupled to a first word line is performed by applying a first read voltage to the first word line, a first read retry is performed to obtain an optimal read level regardless or independent of whether data read by the first read operation is error-correctable, and the optimal read level is stored to perform a subsequent second read operation using the optimal read level. Related methods and devices are also discussed. | 2014-09-18 |
20140281771 | METHOD AND DEVICE FOR OPTIMIZING LOG LIKELIHOOD RATIO (LLR) USED FOR NONVOLATILE MEMORY DEVICE AND FOR CORRECTING ERRORS IN NONVOLATILE MEMORY DEVICE - In a method of optimizing a log likelihood ratio (LLR) used to correct errors related to data stored in a nonvolatile memory device, variation of threshold voltage distribution for a plurality of memory cells included in the nonvolatile memory device is monitored, and the LLR for the memory cells is updated based on a monitoring result. Although the characteristics of the memory cells are deteriorated, the LLR is continuously maintained to the optimal value. | 2014-09-18 |
20140281772 | DETECTING EFFECT OF CORRUPTING EVENT ON PRELOADED DATA IN NON-VOLATILE MEMORY - A method includes determining a read threshold voltage corresponding to a group of storage elements in a non-volatile memory that includes a three-dimensional (3D) memory of a data storage device. The method also includes determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage. The method includes comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event. | 2014-09-18 |
20140281773 | METHOD AND APPARATUS FOR INTERCONNECT TEST - A method of testing interconnected dies can include forming a cell for the interconnected dies, applying at least a first input to the cell to perform an open or short defects test, and applying at least a second input to the cell to perform one or more of a resistive defects test or a burn-in-test. Test circuitry for testing an interconnection between interconnected dies can include a wrapper cell embedded within a die where the wrapper cell includes a scannable data storage element, a hold data module, a selection logic, a transition generation module, and one or more additional input ports for receiving inputs causing the wrapper cell to perform an open or short defects test in a first mode and causing the wrapper cell to perform one or more of a resistive defects test in a second mode or a burn-in-test in a third mode. | 2014-09-18 |
20140281774 | Two-Level Compression Through Selective Reseeding - A scan test system and technique compresses CARE bits and X-control input data into PRPG seeds, thereby providing a first compression. The scan test system includes a plurality of compressor and decompressor structures (CODECs). Each block of the design includes at least one CODEC. An instruction decode unit (IDU) receives scan inputs and determines whether a seed extracted from the scan inputs is broadcast loaded in the CODECs, multicast loaded in a subset of the CODECs, or individual loaded in a single CODEC. This sharing of seeds, exploits the hierarchical nature of large designs with many PRPGs, provides a second compression. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage, diagnosability, and performance. | 2014-09-18 |
20140281775 | System on a Chip FPGA Spatial Debugging Using Single Snapshot - A method for performing on-chip spatial debugging of a user circuit programmed into a user-programmable integrated circuit includes halting an internal clock driving synchronous logic elements in the integrated circuit and reading the states of all synchronous logic elements programmed into the integrated circuit while the internal clock is halted. An interrupt to an embedded processor in the integrated circuit running a user application can also be generated. The output of at least one synchronous logic element can be forced to a desired state while the internal clock is halted. The clock can then be restarted or stepped. | 2014-09-18 |
20140281776 | METHOD AND APPARATUS FOR DEVICE TESTING USING MULTIPLE PROCESSING PATHS - According to some aspects, a method of operating an automatic test system comprising a plurality of paths and programmed with a test pattern is provided. One such method comprises executing vectors in the test pattern with circuitry comprising a plurality of paths, the executing comprising upon processing, in a first of the plurality of paths, the operation portion of a vector specifying an operation capable of generating a branch in the flow of execution of the vectors in the test pattern to a non-sequential location in the test pattern, initiating processing of the test pattern in a second of the plurality of paths from the non-sequential location. Some aspects include a system for executing instructions comprising a plurality of paths comprising control circuitry to initiate processing of operation portions from sequential locations of a memory within an available path of the plurality of paths. | 2014-09-18 |
20140281777 | Localizing Fault Flop in Circuit by Using Modified Test Pattern - A method for localizing at least one scan flop associated with a fault in an integrated circuit. A first test pattern, including a first scan-in data and first control data, is generated. Based on the first control data of the first test pattern, a first fault data is generated by applying the first scan-in data of the first test pattern to scan flops in a test circuit of the integrated circuit. If the first fault data indicates that a fault may be present in the integrated circuit, a second test pattern, including a second scan-in data and a second control data is generated. | 2014-09-18 |
20140281778 | BUILT-IN SELF TEST (BIST) WITH CLOCK CONTROL - A processing system includes a clock generator circuit configured to receive a master clock signal and to output a plurality of clock signals, wherein the plurality of clock signals have a first frequency during a built-in self-test (BIST) mode and a plurality of shift-capture clock generator circuits. Each shift-capture clock generator circuit includes a clock gate circuit and a clock divider circuit and is configured to receive a corresponding one of the plurality of clock signals. At least one of the clock divider circuits changes the first frequency of the one of the plurality of clock signals to a second frequency during the BIST mode. | 2014-09-18 |
20140281779 | ITERATIVE KALMAN FILTERING - Several types of noise limit the performance of remote sensing systems, e.g., systems that determine the location, color, or shape of remote objects. When noise detected by sensors of the remote sensing systems is known and well estimated, a Kalman filter can converge on an accurate value without noise. However, non-Gaussian noise bursts can cause the Kalman filter to diverge from an accurate value. Current approaches arbitrarily boost noise with fixed additive or multiplicative factors. Such approaches slow filter response and; thus, often fail to give timely results. Such noise boosts prevent divergence due to badly corrupted measurements. Disclosed embodiments eliminate a subset of noise measurements having the largest errors from a data set of noise measurements and process the remaining data through the Kalman filter. Advantageously, disclosed embodiments enable a Kalman filter to converge on an accurate value without the introduction of noise boost estimates, which adds processing time. | 2014-09-18 |
20140281780 | ERROR DETECTION AND RECOVERY OF TRANSMISSION DATA IN COMPUTING SYSTEMS AND ENVIRONMENTS - Errors that can be detected as a result of the mapping of transmission data from its physical form back to its logical form can be considered in addition to the errors detected by using an error detection technique (e.g., a conventional CRC technique), thereby allowing fewer error detection/recovery bits (error recovery data or bits) to be used as would be possible by using the error detection technique alone. In other words, less error recovery data would be needed to achieve a given level accuracy using conventional techniques. As a result, overhead associated with adding error detection/recovery bits can be reduced. | 2014-09-18 |
20140281781 | METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING DATA TRANSMISSION PARAMETERS AND CONTROLLING H-ARQ PROCESSES - A method and wireless transmit/receive unit (WTRU) for uplink data transmission is disclosed. Information indicating an allowed limit for uplink data transmission over an enhanced uplink channel is received. A hybrid automatic repeat request (H-ARQ) process to use for transmission of data over the enhanced uplink channel is identified. Data is selected for transmission over the enhanced uplink channel. A data transmission parameter is selected based on the received information indicating the allowed limit for uplink data transmission. The selected data is transmitted over the enhanced uplink channel using the identified H-ARQ process. An indication of the selected data transmission parameter is transmitted over an associated physical control channel. | 2014-09-18 |
20140281782 | DYNAMIC HARQ-ID RESERVATION - The method is used for detection and/or removal of errors in transmission systems which comprise a transmitter unit and at least one receiver unit. The transmitter unit transmits to the receiver unit on a semi-persistent transmission resource which provides an adjustable frequency range and an adjustable time period. Furthermore, the self-repeating, semi-persistent transmission resource repeating with the period T | 2014-09-18 |
20140281783 | REPLAY SUSPENSION IN A MEMORY SYSTEM - Embodiments relate to replay suspension in a memory system. One aspect is a system that includes a replay buffer coupled to a memory controller interface, and a replay control coupled to the replay buffer and a memory controller. The replay control is configured to receive an error indication associated with sending data from the memory controller interface to a memory subsystem as part of an operation. A replay pending signal is provided to the memory controller based on the error indication. Based on waiting for a period of time sufficient for the memory controller to provide remaining data associated with the operation to the replay buffer, a replay signal is asserted. | 2014-09-18 |
20140281784 | Systems and Methods for Data Repair - An embodiment method for data repair in a storage system includes determining, by a processor, a minimum number of missing data blocks needed to repair a corrupted object in a first portion of the storage system, wherein the missing data blocks are not available in the first portion of the storage system, retrieving only the minimum number of missing data blocks needed to repair the corrupted object from a second portion of the storage system, and repairing the corrupted object in the first portion of the storage system using erasure codes and the retrieved minimum number of missing data blocks. | 2014-09-18 |
20140281785 | ERROR-CORRECTION DECODING WITH CONDITIONAL LIMITING OF CHECK-NODE MESSAGES - An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method may include determining whether participating bits for a particular parity-check equation from the plurality of parity check equations satisfy the particular parity-check equation. The method may further include determining, based on whether the particular parity-check equation is satisfied, a magnitude of a reliability modification to one or more reliability values associated with at least one of the participating bits. The method may also include modifying the one or more reliability values by the magnitude of the reliability modification. | 2014-09-18 |
20140281786 | LAYERED DECODING ARCHITECTURE WITH REDUCED NUMBER OF HARDWARE BUFFERS FOR LDPC CODES - A layered decoding architecture with a reduced number of hardware buffers for low-density parity-check (LDPC) decoding by storing a variable-to-check message. When a check node begins a new operation, a variable-to-check message (Q) is added to a check-to-variable message (R) obtained in previous check-node operation to obtain an updated APP value. Then, the R value for the check node in the layer being processed is deducted from the APP value to obtain a variable-to-check message (Q). This variable-to-check message is stored in the memory and inserted into the check node equation to obtain a check-to-variable message. Finally the check-to-variable message obtained in this operation is stored to the check-to-variable message shift register to complete the updating operation for the check node and the variable node for the layer being processed. Improved hardware utilization and fewer buffers, thus achieving a smaller hardware area while retaining the converge speed, is obtained. | 2014-09-18 |
20140281787 | Min-Sum Based Hybrid Non-Binary Low Density Parity Check Decoder - Systems, methods, devices, circuits for a min-sum based hybrid non-binary low density parity check decoder. | 2014-09-18 |
20140281788 | SYSTEMS AND METHODS FOR DECODING USING PARTIAL RELIABILITY INFORMATION - Systems and methods are provided for decoding data. A decoder receives a plurality of variable node values for a plurality of variable nodes and processed reliability data for at least a subset of the plurality of variable nodes. Circuitry updates the variable node values based on the variable node values and the processed reliability data. The processed reliability data represents a version of the reliability data for at least the subset of the plurality of variable nodes. | 2014-09-18 |
20140281789 | ADAPTIVE MULTI-CORE, MULTI-DIRECTION TURBO DECODER AND RELATED DECODING METHOD THEREOF - A turbo decoder includes a plurality of decoder cores arranged for parallel decoding of a plurality of code segments of a code block in an iteration. Each of the decoder cores is arranged to decode a corresponding code segment according to a sliding window having a window size smaller than a length of the corresponding code segment in most cases, and sequentially generate a plurality of decoded soft outputs each derived from decoding an encoded soft input selected from the corresponding code segment by the sliding window. | 2014-09-18 |
20140281790 | Systems and Methods for Multi-Stage Encoding Of Concatenated Low Density Parity Check Codes - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for multi-stage encoding for concatenated low density parity check codes. | 2014-09-18 |
20140281791 | CODING ARCHITECTURE FOR MULTI-LEVEL NAND FLASH MEMORY WITH STUCK CELLS - Encoded least significant bit (LSB) values are generated for a cell based at least in part on a readback value for the cell. The encoded LSB values is decoded in order to obtain one or more decoded LSB values. Encoded most significant bit (MSB) values are generated for the cell based at least in part on (1) the readback value for the cell and (2) the decoded LSB values. The encoded MSB values are decoded in order to obtain one or more decoded MSB values, wherein the bit positions of the decoded LSB values do not overlap with the bit positions of the decoded MSB values. | 2014-09-18 |
20140281792 | Error Corrector Coding and Decoding - Methods and devices are provided for coding and decoding coded data including source data and redundancy data. The redundancy data is obtained by applying, upon coding, an error correction code to the source data, implementing a generating matrix. The generating matrix includes, in its systematic form, an identity matrix and an invertible matrix for switching from the source data to the redundancy data. The coding or decoding is based on a Tanner graph, which combines the graph of the error corrector code and the graph of the dual code of the error correction code by superimposing these graphs. | 2014-09-18 |
20140281793 | DATA DECODING ACROSS MULTIPLE TRACKS - Devices and/or methods may store a data unit across multiple data tracks. Each of the data tracks may have different signal-to-noise ratios (SNR). The SNR, or bit error rate, of the data unit may be diversified by being stored across multiple different tracks. | 2014-09-18 |
20140281794 | ERROR CORRECTION CIRCUIT - According to one embodiment, an error correction circuit includes a first memory module, a read-out module, a first arithmetic module, a detector, a second arithmetic module, and a transfer module. The first memory module stores logarithmic likelihood ratio (LLR) data to which low density parity check codes (LDPC) data has been converted. The read-out module reads out, from the first memory module, the LLR data of a plurality of variable nodes which are connected to a selected check node, based on a check matrix. The first and second arithmetic modules update the LLR data, based on the read-out LLR data and first and second reliability data. The transfer module transfers the updated LLR data to the first memory module. | 2014-09-18 |
20140281795 | METHOD AND APPARATUS FOR DECODING LDPC CODE - There are provided a method and apparatus for decoding an LDPC code. In this specification, a first result is calculated by performing the calculation of a check node having two inputs forward and recursively, a second result is calculated by performing the calculation of the check node having the two inputs backward and recursively, and the check node is calculated using the first result and the second result as the inputs. | 2014-09-18 |
20140281796 | STORAGE CONTROL APPARATUS AND STORAGE SYSTEM - A processor generates a parity from dummy data attached to a first piece of data of a plurality of pieces of data and a piece of data other than the first piece of data when writing the plurality of pieces of data into a first storage apparatus. Then, the processor stores the parity in a second storage apparatus. The processor performs a reading-out process in parallel with a restoration process when reading out the plurality of pieces of data from the first storage apparatus and writing them into the second storage apparatus. The reading-out process is a process to read out the first piece of data from the first storage apparatus and to write it into the second storage apparatus, and the restoration process is a process to restore a second piece of data among the plurality of pieces of data by using the dummy data and the parity. | 2014-09-18 |
20140281797 | PARALLEL LOW-DENSITY PARITY CHECK (LDPC) ACCUMULATION - Systems and methods for parallel accumulation of information bits as part of the generation of low-density parity-check codes are provided. Consecutive information bits can be accumulated through vector operations where the parity addresses used for accumulation can be made contiguous through a virtual to private parity address map. The method for accumulating a set of parity bits for an encoding operation may comprise the steps of performing an exclusive or (XOR) between a multi-bit vector containing information bits and a multi-bit vector of parity bits in an encoder, and storing results of the XOR as a set of parity bits. An encoder for accumulating the set of parity bits is also provided. | 2014-09-18 |
20140281798 | PERFORMING A CYCLIC REDUNDANCY CHECKSUM OPERATION RESPONSIVE TO A USER-LEVEL INSTRUCTION - In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed. | 2014-09-18 |
20140281799 | METHOD AND CONTROLLER FOR PROCESSING DATA MULTIPLICATION IN RAID SYSTEM - The invention discloses a method and controller for processing data multiplication in a RAID system. Map tables are generated for all values in a field, respectively. The length of an XOR operation unit is chosen to be appropriate w bits (e.g., 32 bits or 64 bits). One or several XOR operation units form a multiplication unit of a data sector. When computing on-line, data in a disk drive of a disk array are performed with XOR operations in accordance with one of the map tables using an XOR operation unit as one unit while computing on the multiplication unit to obtain a product of multiplication. | 2014-09-18 |
20140281800 | SYSTEM AND METHOD FOR HIGHER QUALITY LOG LIKELIHOOD RATIOS IN LDPC DECODING - A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword. | 2014-09-18 |
20140281801 | SELECTION OF REDUNDANT STORAGE CONFIGURATION BASED ON AVAILABLE MEMORY SPACE - A method includes, in a memory controller that controls a memory, evaluating an available memory space remaining in the memory to write data. A redundant storage configuration is selected in the memory controller depending on the available memory space. Redundancy information is calculated over the data using the selected redundant storage configuration. The data and the redundancy information are written to the available memory space in the memory. | 2014-09-18 |
20140281802 | MULTI-DIMENSIONAL ERROR DETECTION AND CORRECTION MEMORY AND COMPUTING ARCHITECTURE - Error correction and detection may be performed across multiple dimensions of memory storage, such as across two or more complete memory devices, as well as within individual pages of memory within a single memory device. Error correction and detection performed across two or more complete memory devices may mitigate single event functional interrupts that affect a complete memory device. Error detection and correction performed within individual pages of memory may be used to mitigate single event upset induced single and multiple bit flips within a page of a memory device. A parallel or serial block code, such as a parallel or serial block Reed-Solomon code or any other type of error correcting code, may be used for error correction and detection performed across two or more complete memory devices or within individual pages of memory within a single memory device. | 2014-09-18 |
20140281803 | MEMORY WITH ERROR CORRECTION CONFIGURED TO PREVENT OVERCORRECTION - A non-volatile memory array storing data and ECCs includes error correcting logic. A data set can be read by performing iterations including sensing data using a read bias, and producing an indication of errors in the sensed data. A first iteration uses a first read bias. In each iteration, if the indication in a current iteration is less than a threshold, then the data is output from the selected cells sensed in the present iteration. If the indication in the current iteration exceeds the threshold, then another iteration is performed using a moved read bias, unless the indication in the current iteration shows an increase in errors relative to a previous iteration, in which case then sensed data from the previous iteration is output. Double buffering logic can be used to store sensed data during a current and a previous iteration. | 2014-09-18 |
20140281804 | DISTRIBUTED STORAGE NETWORK FOR MODIFICATION OF A DATA OBJECT - In a dispersed storage network, data objects are dispersed storage error encoded into pluralities of sets of encoded data slices that are each stored in corresponding sets of storage units. To recover a data object, a read threshold number of encoded data slices from each set of encoded data slices of the plurality of sets of encoded data slices are required. Upon determining that an update is available for the storage units, a dispersed storage managing unit determines an updating sequence pattern that ensures that while one or more storage units are taken off line for the update, a sufficient number of storage units remain on line such that at least the read threshold number of encoded data slices are available for each set of encoded data slices. | 2014-09-18 |