38th week of 2012 patent applcation highlights part 44 |
Patent application number | Title | Published |
20120238037 | IMMUNOLOGICAL ASSAY AND IMMUNOLOGICAL ASSAY KIT - An antibody enabling a rapid measurement of HMGB1, for example a combination of antibodies to HMGB1, is elucidated and an immunological assay and an immunological assay kit are provided. It is intended to provide an immunological assay kit for determining the presence or absence, or the concentration, or both of HMGB1, including a first antibody and a second antibody, wherein the first antibody is immobilized on a carrier and the second antibody is modified with a labeling substance, and the first antibody and the second antibody are any of the following antibody (A), antibody (B), antibody (C), and antibody (D), and a permutation combination of the first antibody and the second antibody is any one of antibody (A) and antibody (B), antibody (A) and antibody (C), antibody (B) and antibody (A), antibody (B) and antibody (C), antibody (B) and antibody (D), and antibody (C) and antibody (B). | 2012-09-20 |
20120238038 | PEPTIDE BINDING TO METHYLATED DNA - The present invention aims to provide a tool etc. capable of detecting a methylated region of a DNA in a short time, in a labor-saving manner and without being limited by nucleotide sequences, and further capable of quantifying the methylation. The present invention provides a peptide containing a metal finger motif and a tyrosine derivative in a helix forming part of the motif, which recognizes and binds to a methylated region of a double stranded DNA. | 2012-09-20 |
20120238039 | NOVEL IMMOBILIZING FUSION PROTEIN FOR EFFECTIVE AND ORIENTED IMMOBILIZATION OF ANTIBODY ON SURFACES - The present invention relates to a novel fusion protein comprising Staphylococcal protein A and mussel adhesive protein, a biochip comprising a solid substrate to which the fusion protein is attached, and a method for detecting a target antigen in a biological sample using the biochip. Furthermore, the present invention relates to a polynucleotide encoding the fusion protein, a recombinant vector comprising the polynucleotide, a transformed cell comprising the recombinant vector, and a method of preparing the fusion protein by transformed cell comprising the recombinant vector. | 2012-09-20 |
20120238040 | PLASMA ETCHING APPARATUS AND PLASMA ETCHING METHOD - Disclosed is a technology that can obtain high in-plane uniformity of etching while etching a substrate using plasma. A proper temperature of a focus ring capable of performing etching having high in-plane uniformity is identified in advance for each of the multilayers formed on a wafer, the temperature is reflected to a processing recipe as a set temperature, and a heating mechanism and a cooling mechanism are controlled such that the temperature of the focus ring is within an appropriate temperature range including the set temperature thereof for each of the layers to be successively etched. Heat of the focus ring is radiated using a laser and is discharged to a supporting table without using a heater, to independently separate the heating mechanism and the cooling mechanism from each other. | 2012-09-20 |
20120238041 | COLOR CONTROL BY ALTERATION OF WAVELENGHT CONVERTING ELEMENT - A light emitting device is produced by depositing a layer of wavelength converting material over the light emitting device, testing the device to determine the wavelength spectrum produced and correcting the wavelength converting member to produce the desired wavelength spectrum. The wavelength converting member may be corrected by reducing or increasing the amount of wavelength converting material. In one embodiment, the amount of wavelength converting material in the wavelength converting member is reduced, e.g., through laser ablation or etching, to produce the desired wavelength spectrum. | 2012-09-20 |
20120238042 | Device for Releasably Receiving a Semiconductor Chip - A device is disclosed for releasably receiving a singulated semiconductor chip having a first main surface and a second main surface opposite the first main surface. The device includes a support structure. At least one elastic element is arranged on the support structure. Electrical contact elements are arranged on the at least one elastic element and adapted to be contacted to the first main surface of the semiconductor chip. A foil is adapted to be arranged over the second main surface of the semiconductor chip. | 2012-09-20 |
20120238043 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - With the stage kept in an as-heated state, the semiconductor wafer is placed over the stage (step S | 2012-09-20 |
20120238044 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND REINFORCING PLATE - According to one embodiment, in a method for manufacturing a semiconductor device, a semiconductor substrate having a plurality of first pads is covered with a bonding material. The semiconductor substrate is attached to a reinforcing plate having a plurality of first through-holes corresponding respectively to the first pads. The semiconductor substrate is removed until becoming a predetermined thickness. An electrode film is formed on the semiconductor substrate. A remover of the bonding material is injected into the first through-holes so as to expose the first pads. A probe is in contact with the exposed first pads through the first through-holes so as to measure a current flowing between the probe and the electrode film. The remover is injected into the first through-holes so as to separate the semiconductor substrate from the reinforcing plate. The semiconductor substrate is diced into a plurality of chips. | 2012-09-20 |
20120238045 | THREE DIMENSIONAL LIGHT EMITTING DIODE SYSTEMS, AND COMPOSITIONS AND METHODS RELATING THERETO - A flexible layered structure is disclosed having a flexible top conductive layer, a flexible bottom heat sink layer and a flexible dielectric middle layer. The combination has a longitudinal axis and a plurality of defined positions spaced along the longitudinal axis. The defined positions can be used for aligning a circuit and/or for the placement of LED lights. The flexible layered structure can be easily bent to form a LED substrate for shining light in more than one direction while efficiently removing heat arising from the LEDs. | 2012-09-20 |
20120238046 | LED MESA SIDEWALL ISOLATION BY ION IMPLANTATION - A method of LED manufacturing is disclosed. A coating is applied to a mesa. This coating may have different thicknesses on the sidewalls of the mesa compared to the top of the mesa. Ion implantation into the mesa will form implanted regions in the sidewalls in one embodiment. These implanted regions may be used for LED isolation or passivation. | 2012-09-20 |
20120238047 | LIGHT EMITTING DEVICE INCLUDING SEMICONDUCTOR NANOCRYSTALS - A light emitting device includes a semiconductor nanocrystal and a charge transporting layer that includes an inorganic material. The charge transporting layer can be a hole or electron transporting layer. The inorganic material can be an inorganic semiconductor. | 2012-09-20 |
20120238048 | METHOD OF MANUFACTURING A SOLAR CELL MODULE AND APPARATUS OF MANUFACTURING A SOLAR CELL MODULE - A method of manufacturing a solar cell, which includes an edge deletion step using a laser beam, and a manufacturing apparatus which is used in such a method, the method and the apparatus being capable of preventing a shunt and cracks from being generated are provided. By radiating a first laser beam to a multilayer body, which includes a transparent electrode layer, a photoelectric conversion layer, and a back electrode layer sequentially formed on a transparent substrate, from a side of the transparent substrate, the photoelectric conversion layer and the back electrode layer in a first region are removed, and by radiating a second laser beam into the region such that the second laser beam is spaced from a peripheral rim of the region, the transparent electrode layer in a second region is removed. | 2012-09-20 |
20120238049 | Method for Removing at least Sections of a Layer of a Layer Stack - In a method for removing at least sections of at least one semiconductor layer ( | 2012-09-20 |
20120238050 | Combinatorial Screening of Transparent Conductive Oxide Materials for Solar Applications - Embodiments of the current invention include methods of improving a process of forming a textured TCO film by combinatorial methods. The combinatorial method may include depositing a TCO by physical vapor deposition or sputtering, annealing the TCO, and etching the TCO where at least one of the depositing, the annealing, or the etching is performed combinatorially. Embodiments of the current invention also include improved methods of forming the TCO based on the results of combinatorial testing. | 2012-09-20 |
20120238051 | IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - The image sensor includes a substrate; a wiring structure formed on a front side of the substrate and including a plurality of wiring layers and a plurality of insulating films; a first well formed within the substrate and having a first conductivity type; and a first metal wiring layer directly contacting a backside of the substrate and configured to apply a first well bias to the first well. | 2012-09-20 |
20120238052 | METHOD OF PRODUCING A CRYSTALLINE SILICON SOLAR CELL - A method of producing a crystalline silicon solar cell, comprising: printing a conductive paste on a crystalline silicon substrate, and firing the conductive paste to form a light incident side electrode, wherein the conductive paste comprises conductive particles, glass frits, an organic binder and a solvent, the conductive particles comprise zinc particles and copper particles, and a weight ratio of the zinc particles and the copper particles is 2:1 to 2:3. | 2012-09-20 |
20120238053 | Chalcogenide Absorber Layers for Photovoltaic Applications and Methods of Manufacturing the Same - In one example embodiment, a method includes depositing one or more thin-film layers onto a substrate. More particularly, at least one of the thin-film layers comprises at least one electropositive material and at least one of the thin-film layers comprises at least one chalcogen material suitable for forming a chalcogenide material with the electropositive material. The method further includes annealing the one or more deposited thin-film layers at an average heating rate of or exceeding | 2012-09-20 |
20120238054 | SCREEN-PRINTABLE QUATERNARY CHALCOGENIDE COMPOSITIONS - The present invention relates to screen-printable quaternary chalcogenide compositions. The present invention also provides a process for creating an essentially pure crystalline layer of the quaternary chacogenide on a substrate. Such coated substrates contain p-type to semiconductors and are useful as the absorber layer in a solar cell. | 2012-09-20 |
20120238055 | METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT - An object of the present invention is to provide a method for manufacturing a variable resistance nonvolatile semiconductor memory element which can operate at a low voltage and high speed when initial breakdown is caused, and inhibit oxidization of a contact plug. The method for manufacturing the variable resistance nonvolatile semiconductor memory element, which includes a bottom electrode, a variable resistance layer, and a top electrode which are formed above a contact plug, includes oxidizing to insulate an end portion of the variable resistance layer prior to forming a bottom electrode by patterning a first conductive film. | 2012-09-20 |
20120238056 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The formation of a void is suppressed in the assembly of a semiconductor device. An MCU chip and an AFE chip are mounted over a die pad formed of a quadrangle having a pair of first sides and a pair of second sides. After wire bonding is carried out on the MCU chip and the AFE chip, resin is supplied from the side of one second side of the two second sides to the side of the other second side. The resin is thereby passed through the opening between a first pad group and a second pad group over the MCU chip to fill the area between the chips and thus the formation of a void is suppressed in the area between the chips. | 2012-09-20 |
20120238057 | Approach for Bonding Dies onto Interposers - A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs. | 2012-09-20 |
20120238058 | METHOD OF PACKAGING SEMICONDUCTOR DIE WITH CAP ELEMENT - A method of assembling semiconductor devices includes placing an array of semiconductor dies on a die support. A cap array structure is provided that has a corresponding array of caps supported by a cap frame structure. The cap array structure and the array of semiconductor dies on the die support are aligned, with the caps extending over corresponding semiconductor dies, in a mold chase. The array of semiconductor dies and the array of caps are encapsulated with a molding compound in the mold chase. The encapsulated units of the semiconductor dies with the corresponding caps are removed from the mold chase and singulated. Singulating the encapsulated units may include removing the cap frame structure from the encapsulated units. | 2012-09-20 |
20120238059 | SACRIFICIAL SUBSTRATE FILM FOR BALL LAND PROTECTION - A method of forming solder balls on package substrates includes attaching a semiconductor die to a frontside of a package substrate that includes a film over a bottomside of the package substrate including over a plurality of ball land areas configured to receive solder balls thereon, followed by forming an encapsulating mold layer over the semiconductor die. The film blocks contamination such as mold debris from reaching the ball land areas during die attachment and molding. The film is then removed from the bottomside of the package substrate after molding to expose the plurality of exposed ball land areas. Solder balls are dispensed onto the plurality of exposed ball land areas. | 2012-09-20 |
20120238060 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device, includes mounting a semiconductor chip on a wiring substrate such that one surface of the semiconductor chip is faced to one surface of the wiring substrate, and filling a first resin in a gap between the surface of the wiring substrate and the surface of the semiconductor chip such that part of the first resin protrudes from the gap. In the filling of the first resin, the first resin is injected into the gap by use of a first resin injection nozzle while the first resin injection nozzle is being moved along any one of sides of the semiconductor chip or along two sides of the semiconductor chip which are adjacent to each other. | 2012-09-20 |
20120238061 | Methods Of Forming Transistors, And Methods Of Forming Memory Arrays - Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed. | 2012-09-20 |
20120238062 | LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME - An LCD is manufactured to provide a wide viewing angle device and may reduce manufacturing costs according to an embodiment. The LCD includes a substrate, a gate line disposed on the substrate, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line contacting the semiconductor layer, a drain electrode contacting the semiconductor layer and separated from the data line, a pixel electrode contacting the drain electrode, a passivation layer disposed on the pixel electrode, and a common electrode disposed on the passivation layer and including a branch electrode overlapping the pixel electrode. In one embodiment, the pixel electrode contacts an end portion of a thin film transistor. The LCD manufacturing process may be shortened and may save manufacturing costs because the LCD process need not make contact holes to connect the pixel electrode and the TFT. | 2012-09-20 |
20120238063 | Termination and Contact Structures for a High Voltage Gan-Based Heterojunction Transistor - A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer. | 2012-09-20 |
20120238064 | ENHANCEMENT-MODE HIGH-ELECTRON-MOBILITY TRANSISTOR AND THE MANUFACTURING METHOD THEREOF - This invention discloses an enhancement-mode high-electron-mobility transistor and the manufacturing method thereof. The transistor comprises an epitaxial buffer layer on a substrate, a source and drain formed in the buffer layer, a PN-junction stack formed on the buffer layer and located between the source and drain, and a gate formed on the PN-junction stack, wherein the PN-junction stack is composed of alternating layers of a P-type semiconductor and an N-type semiconductor. | 2012-09-20 |
20120238065 | METHOD OF FABRICATING COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DEVICE - A method of fabricating a MOS device comprises steps as follows: An interfacial layer, a high-k dielectric layer and a cover layer on a substrate are sequentially formed. Then an in-situ wet etching step is performed by sequentially using a first etching solution to etch the cover layer and using a second etching solution to etch the high-k dielectric layer and the interfacial layer until the substrate is exposed, wherein the second etching solution is a mixed etching solution containing the first etching solution. | 2012-09-20 |
20120238066 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH SILICON-GERMANIUM CHANNELS INCLUDING HYDROGEN - A semiconductor device is fabricated by providing a substrate including a silicon channel layer and a silicon-germanium channel layer, forming gate structures disposed on the silicon channel layer and on the silicon-germanium channel layer, forming a first protection layer to cover the resultant structure including the gate structures, and injecting hydrogen and/or its isotopes into the silicon-germanium channel layer. The silicon and silicon-germanium channel layers may be oriented along a <100> direction. Related devices are also described. | 2012-09-20 |
20120238067 | Methods of Fabricating Semiconductor Devices Having Gate Trenches - Methods of fabricating semiconductor devices including providing a substrate having a channel region defined therein; forming an insulation layer on the substrate; forming a gate trench for forming a gate electrode having a sidewall portion, a bottom portion and an edge portion between the sidewall portion and the bottom portion on the insulation layer, the gate electrode trench overlapping the channel region; and forming a gate electrode in the gate electrode trench. Forming the gate electrode includes forming a first metal layer pattern in the gate electrode trench and forming a second metal layer pattern on the first metal layer pattern. | 2012-09-20 |
20120238068 | SEMICONDUCTOR DEVICE INCLUDING A STRESS FILM - A semiconductor device includes a first-type internal stress film formed of a silicon oxide film over source/drain regions of an nMISFET and a second-type internal stress film formed of a TEOS film over source/drain regions of a pMISFET. In a channel region of the nMISFET, a tensile stress is generated in the direction of movement of electrons due to the first-type internal stress film, so that the mobility of electrons is increased. In a channel region of the pMISFET, a compressive stress is generated in the direction of movement of holes due to the second-type internal stress film, so that the mobility of holes is increased. | 2012-09-20 |
20120238069 | ESD NETWORK CIRCUIT WITH A THROUGH WAFER VIA STRUCTURE AND A METHOD OF MANUFACTURE - A method includes forming an ESD active device on a substrate, forming a ground plane on a backside of the substrate and forming at least one through wafer via electrically connected to a negative power supply of the ESD active device and the ground plane to provide a low series resistance path to the substrate. | 2012-09-20 |
20120238070 | METHODS FOR PRODUCING SILICON ON INSULATOR STRUCTURES HAVING HIGH RESISTIVITY REGIONS IN THE HANDLE WAFER - Silicon on insulator structures having a high resistivity region in the handle wafer of the silicon on insulator structure are disclosed. Methods for producing such silicon on insulator structures are also provided. Exemplary methods involve creating a non-uniform thermal donor profile and/or modifying the dopant profile of the handle wafer to create a new resistivity profile in the handle wafer. Methods may involve one or more SOI manufacturing steps or electronic device (e.g., RF device) manufacturing steps. | 2012-09-20 |
20120238071 | SILICON LAYER TRANSFER SUBSTRATE AND METHOD OF MANUFACTURING SEMICONDUCTOR SUBSTRATE - A silicon layer transfer substrate includes a silicon substrate of a first substrate, a sacrificial layer, and a transfer silicon layer transferred to a second substrate, wherein the sacrificial layer has a silicon compound layer containing a compound of silicon and at least one element selected from a group consisting of germanium and carbon, and is provided on the silicon substrate of the first substrate, the silicon compound layer having a thickness equal to or smaller than a critical film thickness, the transfer silicon layer transferred to the second substrate is provided on the sacrificial layer, and at least either the silicon substrate or the silicon layer has a groove or a hole connected to the sacrificial layer. | 2012-09-20 |
20120238072 | HEAT TRANSFER FOR A HARD-DRIVE PRE-AMP - A substrate for mounting a preamp chip thereupon, fabricated using a stiffener layer made of a conductive material; an insulating layer provided over the circuitry area of the substrate; a circuitry made of a conductive material provided over the insulating layer; and a flap which is an extension of the stiffener layer having no insulating layer provided thereupon. The flap is fabricated to fold over the preamp chip to remove heat therefrom. | 2012-09-20 |
20120238073 | Method and Apparatus for Plasma Dicing a Semi-conductor Wafer - The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma. | 2012-09-20 |
20120238074 | METHODS AND APPARATUS FOR CONFORMAL DOPING - Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of doping a substrate may include forming a dopant region on a substrate by implanting one or more dopant elements into the dopant region of the substrate using a plasma doping process; forming a cap layer atop the dopant region; annealing the dopant region after forming the cap layer; and removing the cap layer after annealing the dopant region. | 2012-09-20 |
20120238075 | COATING APPARATUS AND COATING METHOD - A coating apparatus including a coating part which applies a liquid material containing an oxidizable metal and a solvent to a substrate; a chamber having a coating space in which the coating part applies the liquid material to the substrate and a transport space into which the substrate is transported; and a removal part which removes the liquid material from the atmosphere inside the chamber when a concentration of the solvent in the atmosphere inside the chamber exceeds a threshold value. | 2012-09-20 |
20120238076 | Method and Apparatus for Forming a III-V Family Layer - Provided is an apparatus. The apparatus includes: a first deposition component that is operable to form a compound over a semiconductor wafer, the compound including at least one of: a III-family element and a V-family element; a second deposition component that is operable to form a passivation layer over the compound; and a transfer component that is operable to move the semiconductor wafer between the first and second deposition components, the transfer component enclosing a space that contains substantially no oxygen and substantially no silicon; wherein the loading component, the first and second deposition components, and the transfer component are all integrated into a single fabrication tool. | 2012-09-20 |
20120238077 | Methods of Forming High Density Structures and Low Density Structures with a Single Photomask - Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask. | 2012-09-20 |
20120238078 | Method of Integrating Epitaxial Film Onto Assembly Substrate - A method of growing an epitaxial film and transferring it to an assembly substrate is disclosed. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications. | 2012-09-20 |
20120238079 | Method of Transferring Epitaxial Film - A method of growing an epitaxial film and transferring it to an assembly substrate is disclosed. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications. | 2012-09-20 |
20120238080 | Method of Forming Epitaxial Film - A method of growing an epitaxial film and transferring it to an assembly substrate is disclosed. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications. | 2012-09-20 |
20120238081 | Printed Material Constrained By Well Structures And Devices Including Same - A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g., an operative transistor. | 2012-09-20 |
20120238082 | NANO-WIRE FIELD EFFECT TRANSISTOR, METHOD FOR MANUFACTURING THE TRANSISTOR, AND INTEGRATED CIRCUIT INCLUDING THE TRANSISTOR - A manufacturing method of the nano-wire field effect transistor, comprising steps of preparing an SOI substrate having a (100) surface orientation; processing a silicon crystal layer comprising the SOI substrate into a standing plate-shaped member having a rectangular cross-section; processing the silicon crystal layer by orientation dependent wet etching and thermal oxidation into a shape where two triangular columnar members are arranged one above the other with a spacing from each other so as to face along the ridge lines of the triangular columnar members; and processing the two triangular columnar members into a circular columnar member configuring a nano-wire by hydrogen annealing or thermal oxidation. | 2012-09-20 |
20120238083 | Method of Forming Epitaxial Semiconductor Structure - A method of growing an epitaxial semiconductor structure is disclosed. The growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications. | 2012-09-20 |
20120238084 | Method of Forming Epitaxial Based Integrated Circuit - A method of growing an epitaxial semiconductor structure is disclosed. The growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications. | 2012-09-20 |
20120238085 | SEMICONDUCTOR ELEMENT, SEMICONDUCTOR DEVICE AND METHODS FOR MANUFACTURING THEREOF - The present invention provides a method of manufacturing a semiconductor element having a miniaturized structure and a semiconductor device in which the semiconductor element having a miniaturized structure is integrated highly, by overcoming reduction of the yield caused by alignment accuracy, accuracy of a processing technique by reduced projection exposure, a finished dimension of a resist mask, an etching technique and the like. An insulating film covering a gate electrode is formed, and a source region and a drain region are exposed, a conductive film is formed thereover, a resist having a different film thickness is formed by applying the resist over the conductive film, the entire surface of the resist is exposed to light and developed, or the entire surface of the resist is etched to form a resist mask, and the conductive film is etched by using the resist mask to form a source and drain electrode. | 2012-09-20 |
20120238086 | REDUCING EQUIVALENT THICKNESS OF HIGH-K DIELECTRICS IN FIELD EFFECT TRANSISTORS BY PERFORMING A LOW TEMPERATURE ANNEAL - When forming sophisticated high-k metal gate electrode structures, for instance on the basis of a replacement gate approach, superior interface characteristics may be obtained on the basis of using a thermally grown base material, wherein the electrically effective thickness may be reduced on the basis of a low temperature anneal process. Consequently, the superior interface characteristics of a thermally grown base material may be provided without requiring high temperature anneal processes, as are typically applied in conventional strategies using a very thin oxide layer formed on the basis of a wet oxidation chemistry. | 2012-09-20 |
20120238087 | NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory according to examples of the present invention comprises a memory cell and a peripheral transistor. The memory cell has a first intergate insulating film having a multilayer structure and provided on a floating gate electrode and an isolation insulating layer. The peripheral transistor has a second intergate insulating film having a multilayer structure and provided on a first gate electrode and a second isolation insulating layer. The first and second intergate insulating films have the same structure, and a lowermost insulating layer of the first intergate insulating film on the first isolation insulating layer is thinner than a lowermost insulating layer of the second intergate insulating film on the second isolation insulating layer. | 2012-09-20 |
20120238088 | FABRICATION METHOD OF METAL GATES FOR GATE-LAST PROCESS - A method for fabricating metal gates using a gate-last process, comprising: providing a substrate ( | 2012-09-20 |
20120238089 | METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR DEVICE - A semiconductor substrate having a main surface, first and second floating gates formed spaced apart from each other on the main surface of the semiconductor substrate, first and second control gates respectively located on the first and second floating gates, a first insulation film formed on the first control gate, a second insulation film formed on the second control gate to contact the first insulation film, and a gap portion formed at least between the first floating gate and the second floating gate by achieving contact between the first insulation film and the second insulation film are included. With this, a function of a nonvolatile semiconductor device can be ensured and a variation in a threshold voltage of a floating gate can be suppressed. | 2012-09-20 |
20120238090 | PRODUCTION METHOD FOR THICK FILM METAL ELECTRODE AND PRODUCTION METHOD FOR THICK FILM RESIST - One object of the present invention is to provide a method for producing a thick film metal electrode that is able to form a positive-negative reverse type resist, which has a thickness of 7 μm or more and excellent in-plane uniformity, on the circuit element formed on the silicon carbide substrate, and a method for producing a thick film resist, and the present invention provides a method for producing a thick film resist wherein a first positive-negative reverse type resist having a first viscosity is formed on an upper surface of a circuit element layer which is treated with HMDS, and a second positive-negative reverse type resist having a second viscosity, which is larger than the first viscosity, on the first positive-negative reverse type resist such that a total thickness of the first and second positive-negative reverse type resists constituting a thick film resist be 7 μm or more. | 2012-09-20 |
20120238091 | SEMICONDUCTOR HAVING A HIGH ASPECT RATIO VIA - The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a method for forming a via structure includes forming a via in a semiconductor substrate, wherein via sidewalls of the via are defined by the semiconductor substrate; forming a dielectric layer on the via sidewalls; removing the dielectric layer from a portion of the via sidewalls; and forming a conductive layer to fill the via, wherein the conductive layer is disposed over the dielectric layer and the portion of the via sidewalls. In an example, the dielectric layer is an oxide layer. | 2012-09-20 |
20120238092 | METHOD TO ALTER SILICIDE PROPERTIES USING GCIB TREATMENT - A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region. | 2012-09-20 |
20120238093 | Methods of Fabricating Semiconductor Devices - A method of fabricating a semiconductor device includes forming a stacked structure in which 2 | 2012-09-20 |
20120238094 | CMP POLISHING SOLUTION AND POLISHING METHOD - The CMP polishing liquid of the invention comprises a metal salt containing at least one type of metal selected from the group consisting of metals of Groups 8, 11, 12 and 13, 1,2,4-triazole, a phosphorus acid, an oxidizing agent and abrasive grains. The polishing method of the invention comprises a step of polishing at least a palladium layer with an abrasive cloth while supplying a CMP polishing liquid between the palladium layer of a substrate having the palladium layer and the abrasive cloth, wherein the CMP polishing liquid comprises a metal salt containing at least one type of metal selected from the group consisting of metals of Groups 8, 11, 12 and 13, 1,2,4-triazole, a phosphorus acid, an oxidizing agent and abrasive grains. | 2012-09-20 |
20120238095 | PATTERNING PROCESS AND COMPOSITION FOR FORMING SILICON-CONTAINING FILM USABLE THEREFOR - The invention provides a patterning process for forming a negative pattern by lithography, comprising at least the steps of: using a composition for forming silicon-containing film, containing specific silicon-containing compound (A) and an organic solvent (B), to form a silicon-containing film; using a silicon-free resist composition to form a photoresist film on the silicon-containing film; heat-treating the photoresist film, and subsequently exposing the photoresist film to a high energy beam; and using a developer comprising an organic solvent to dissolve an unexposed area of the photoresist film, thereby obtaining a negative pattern. There can be a patterning process, which is optimum as a patterning process of a negative resist to be formed by adopting organic solvent-based development, and a composition for forming silicon-containing film to be used in the process. | 2012-09-20 |
20120238096 | METHOD AND APPARATUS FOR INSPECTING A REFLECTIVE LITHOGRAPHIC MASK BLANK AND IMPROVING MASK QUALITY - An EUV integrated circuit fabrication method and system EUV that includes blank inspection, defect characterization, simulation, pattern compensation, modification of the mask writer database, inspection and simulation of patterned masks, and patterned mask repair. The system performs blank inspection to identify defects at multiple focal planes within the blank. The mask can be relocated on the blank and alterations to the pattern can be developed to compensate for the defects prior to prior to patterning the mask. Once the mask has been patterned, the reticle is inspected to identify any additional or remaining defects that were not picked up during blank inspection or fully mitigated through pattern compensation. The patterned reticle can then be repaired prior to integrated circuit fabrication. | 2012-09-20 |
20120238097 | METHOD FOR FABRICATING FINE LINE - Disclosed herein is a method for fabricating a fine line, which belongs to a field of ultra-large-scale integrated circuit manufacturing technology. In the invention, three trimming mask processes are performed to effectively improve a profile of the line and greatly reduce the LER (line edge roughness) of the line. At the same time, the invention is combined with a sidewall process, so that a nano-scaled fine line can be successfully fabricated and precisely controlled to 20 nm. Thus, a nano-scaled line with an optimized LER can be fabricated over the substrate. | 2012-09-20 |
20120238098 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device for forming a deep hole in a substrate by using a photoresist film formed on the substrate includes a positioning step of positioning a substrate inside an etching chamber, the substrate having a photoresist film including an opening part formed thereon, a first etching step of performing plasma etching on the substrate positioned inside the etching chamber by using a first mixed gas including at least SiF | 2012-09-20 |
20120238099 | METHOD OF MANUFACTURING ELECTRONIC PART - According to one embodiment, a process target above a substrate is processed in order to produce a wiring pattern including dense wirings and sparse wirings. Next, a sacrificial film filled between wirings is formed in a region where the dense wirings are formed, and then an insulation film is formed above the substrate. A mask is formed such that a part of the region where the dense wirings are formed is exposed and a region where the sparse wirings are formed is exposed, and the insulation film is etched using the mask. Then, the sacrificial film is removed through a part of the region where the dense wirings are formed. Thereafter, an embedded insulation film is formed above the substrate to fill a gap between adjacent wirings in the region where the sparse wirings are formed. | 2012-09-20 |
20120238100 | ETCHING METHOD, ETCHING APPARATUS, AND COMPUTER-READABLE RECORDING MEDIUM - Provided is an etching method capable of etching even a silicon film that is included in a multi-layered structure by using a resist film or an organic film as a mask, and also capable of integrally etching the silicon film and a silicon oxide film disposed under the silicon film. The etching method which etches the multi-layered structure including the silicon oxide film and the silicon film formed on the silicon oxide film, includes: integrally etching the silicon film and the silicon oxide film included in the multi-layered structure by using a resist film or an organic film as an etching mask and using an etching gas containing a CH | 2012-09-20 |
20120238101 | SELECTIVITY IN A XENON DIFLUORIDE ETCH PROCESS - A method and an apparatus for etching microstructures and the like that provides improved selectivity to surrounding materials when etching silicon using xenon difluoride (XeF2). Etch selectivity is greatly enhanced with the addition of hydrogen to the process chamber. | 2012-09-20 |
20120238102 | METHODS FOR ETCH OF SIN FILMS - A method of selectively etching silicon nitride from a substrate comprising a silicon nitride layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the silicon nitride layer at a higher etch rate than the reactive gas etches the silicon oxide layer. | 2012-09-20 |
20120238103 | METHODS FOR ETCH OF METAL AND METAL-OXIDE FILMS - A method of selectively etching a metal-containing film from a substrate comprising a metal-containing layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber, and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions, and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the metal-containing layer at a higher etch rate than the reactive gas etches the silicon oxide layer. | 2012-09-20 |
20120238104 | ETCHING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND ETCHING DEVICE - An etching method includes: applying a radiation to an etching aqueous solution; and etching a material to be etched by using the etching aqueous solution irradiated with the radiation. | 2012-09-20 |
20120238105 | FORMULATIONS FOR THE PRODUCTION OF ELECTRONIC DEVICES - The present invention relates to formula, comprising at least one solvent, and at least one functional composition of the general formula (I), wherein A is a functional structural element, B is a solvent-providing structural element, and k is an integer in the range of 1 to 20. The molecular weight of the functional composition is at least 550 g/mol, and the solvent-providing structural element B corresponds to the general formula ((L-I). Ar1, Ar2 JeWeUs, independently of each other, signify an aryl or heteroaryl group, which can be substituted with one or several discretionary residues R. Each X is, independently of one another, N or CR | 2012-09-20 |
20120238106 | COATING METHOD AND COATING APPARATUS - A coating method for coating a treatment liquid having a viscosity of 5 cp or less on a substrate includes rotating the substrate, increasing a rotation speed of the substrate while discharging the treatment liquid on the substrate from a nozzle, and repeating at least twice increasing and decreasing the rotation speed of the substrate while discharging the treatment liquid on the substrate from the nozzle. | 2012-09-20 |
20120238107 | PROCESSING METHOD FOR FORMING STRUCTURE INCLUDING AMORPHOUS CARBON FILM - A processing method for forming a structure including an amorphous carbon film includes performing a preliminary treatment of removing water from a surface of the underlying layer by heating the inside of the reaction chamber at a preliminary treatment temperature of 800 to 950° C. and supplying a preliminary treatment gas selected from the group consisting of nitrogen gas and ammonia gas into the reaction chamber while exhausting gas from inside the reaction chamber; and, then performing main CVD of forming an amorphous carbon film on the underlying layer by heating the inside of the reaction chamber at a main process temperature and supplying a hydrocarbon gas into the reaction chamber while exhausting gas from inside the reaction chamber. | 2012-09-20 |
20120238108 | TWO-STAGE OZONE CURE FOR DIELECTRIC FILMS - A method of forming a silicon oxide layer is described. The method increases the oxygen content of a dielectric layer by curing the layer in a two-step ozone cure. The first step involves exposing the dielectric layer to ozone while the second step involves exposing the dielectric layer to ozone excited by a local plasma. This sequence can reduce or eliminate the need for a subsequent anneal following the cure step. The two-step ozone cures may be applied to silicon-and-nitrogen-containing film to convert the films to silicon oxide. | 2012-09-20 |
20120238109 | METHOD OF FORMING PATTERN - According to one embodiment, a method of forming a pattern includes forming a monolayer on a substrate, selectively exposing the monolayer to an energy beam and selectively modifying exposed portions thereof to form patterns of exposed and unexposed portions, forming a block copolymer layer includes first and second block chains on the monolayer, and causing the block copolymer layer to be phase-separated to form patterns of the first and second block chains of the block copolymer layer based on the patterns of the exposed and unexposed portions of the monolayer. | 2012-09-20 |
20120238110 | HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS FOR HEATING SUBSTRATE BY IRRADIATING SUBSTRATE WITH FLASH OF LIGHT - The first flash irradiation is performed on a semiconductor wafer preheated to 500° C. to heat a front surface of the semiconductor wafer. Thereafter, the second flash irradiation is performed to reheat the front surface of the semiconductor wafer before the temperature of the front surface of the semiconductor wafer becomes equal to the temperature of a back surface of the semiconductor wafer. Thus, the second flash irradiation is performed before the temperature of the front surface of the semiconductor wafer falls. Even if less energy is consumable by the second flash irradiation, the efficiency of heating of the front surface of the semiconductor wafer resulting from each iteration of the flash irradiation is improved. | 2012-09-20 |
20120238111 | ANNEALING APPARATUS USING TWO WAVELENGTHS OF CONTINUOUS WAVE LASER RADIATION - A thermal processing apparatus and method in which a first laser source, for example, a CO | 2012-09-20 |
20120238112 | ROTARY CONNECTOR - After a lead block, where a required number of pin terminals are fitted to and assembled with an insulating support member, is connected to an end portion of a flat cable, the lead block is assembled with a lower connector holder of a rotary connector. The lower connector holder includes lower protruding portions of a lower cover and an outer cylindrical portion that are snap-fitted to each other. The lower protruding portion includes a receiving recess and the lower protruding portion includes a holding wall portion. Leading end portions of pin terminals are inserted into insertion holes of the holding wall portion, so that the lead block is assembled. While stopper portions of the pin terminals are interposed between the holding wall portion and the outer wall of the support member, the support member is positioned and held in the receiving recess. | 2012-09-20 |
20120238113 | Locking Mechanisms and Locking Caps for USB Connectors - According to various embodiments, an exemplary locking mechanism for a USB connector comprises a hook, a hook bracket at least partially inserted within the hook to form a first assembly, a holder, the holder enclosing at least a portion of the first assembly to form a second assembly, and a button, the button enclosing at least a portion of the second assembly to form the locking mechanism. The locking mechanism may further comprise a spring fitted around a protruding portion of the hook bracket, the protruding portion extending outward from the first assembly. The locking mechanism may further comprise one or more screws attaching the first assembly to the holder to form the second assembly. The locking mechanism may include a cap enclosing at least a portion of the button to form a locking cap. | 2012-09-20 |
20120238114 | Card Connector - A card connector for receiving a card that is small and includes a card guide for guiding the card that will not deteriorate, even if the card is pulled out of or inserted into a card receiving space at a large tilt angle with respect to the card receiving space. The card connector having a housing, a plurality of contacts, a shell, and the card guide. The plurality of contacts arranged along the housing, while the shell covers the housing and provides a card receiving space between the housing and the shell. The card guide extends extending obliquely into the card receiving space from a top wall of the shell and is inclined at an acute angle with respect to the top wall. | 2012-09-20 |
20120238115 | Lighting Connector Devices and Uses Thereof - A lighting connector which includes (a) an upper housing having plural connector pins, and one or more interlocking grooves; and (b) a lower housing, the lower housing having a plurality of connector pin guide holes, and one or more interlocking tongue portions. The lower housing is connectable with the upper housing to form the lighting connector by coupling at least one of the one or more interlocking grooves with at least one of the one or more interlocking tongue portions, and by coupling at least one of the plural connector pins with at least one of the connector pin guide holes. | 2012-09-20 |
20120238116 | Lighting Connector Devices and Uses Thereof - A lighting connector which includes first and second upper housings, each upper housing having plural connector pins, and one or more interlocking grooves; first and second lower housings, each the lower housing having a plurality of connector pin guide holes, and one or more interlocking tongue portions; and a flexible connector electrically connecting an inner side of the first lower housing with an inner side of the second lower housing, the first lower housing being connectable with the first upper housing, and the second lower housing being connectable with the second upper housing, to form the lighting connector by coupling at least one of the one or more interlocking grooves with at least one of the one or more interlocking tongue portions, and by coupling at least one of the plural connector pins with at least one of the connector pin guide holes. | 2012-09-20 |
20120238117 | Lighting Connector Devices and Uses Thereof - A lighting connector which includes an upper housing having plural connector pins, and one or more interlocking grooves; a lower housing, the lower housing having a plurality of connector pin guide holes, and one or more interlocking tongue portions; a power supply plug; and a flexible connector electrically connecting an inner side of the lower housing with an inner side of the power supply plug, the lower housing being connectable with the upper housing to form the lighting connector by coupling at least one of the one or more interlocking grooves with at least one of the one or more interlocking tongue portions, and by coupling at least one of the plural connector pins with at least one of the connector pin guide holes. | 2012-09-20 |
20120238118 | CONNECTOR - A connecting terminal for a connector has a fixed portion configured to be connected to an electrode portion provided in a member for mounting the connector, and a contact configured to electrically come in contact with a contact portion of a connected portion to be connected to the connector. At least one concave portion is provided along a whole outer peripheral surface of the connector terminal. | 2012-09-20 |
20120238119 | HAND TOOL MODULE - A hand tool module having an interconnection device, which has an interface. The interconnection device has, in addition to the interface, at least one auxiliary interface, which is provided to bidirectionally exchange at least power at least with one additional hand tool module and/or a hand tool. | 2012-09-20 |
20120238120 | ALL-IN-ONE CONVERTER STRUCTURE - The present invention provides an all-in-one converter structure, which has a plurality of plugs each having a different type of connector. A user can choose an appropriate connector from the plurality of plugs. The plurality of plugs are connected with each other via at least a flexible connecting member. Thereby, no loss problem of plug will occur. In addition, the flexible connecting member are more damage-resistant than rigid connecting members. | 2012-09-20 |
20120238121 | POWER PLUG LOCKING DEVICE - A power plug locking device includes a lock unit that restricts movement of an operation arm arranged on a power plug. The lock unit includes a first member, which is moved between a lock position and an unlock position, and a second member, of which movement is restricted in accordance with the movement of the first member. The second member restricts the movement of the operation arm in cooperation with the first member that is moved to the lock position. The first member includes a first contact surface. The second member includes a second contact surface that is able to contact the first member that is moved to the lock position. At least one of the first contact surface and the second contact surface includes a stepped shape. | 2012-09-20 |
20120238122 | POWER PLUG LOCKING DEVICE - A power plug locking device that prevents unauthorized removal of a power plug from an inlet includes a lock member pivoted about its axis. The lock member is pivoted between a lock position, at which the lock member locks the power plug to the inlet, and an unlock position, at which the lock member releases the power plug from a state locked to the inlet. A manual operation unit is manually operated to pivot the lock member from the unlock position to the lock position. A position holding unit is formed to hold the lock member at the lock position and maintain the power plug in a locked state with the lock member. | 2012-09-20 |
20120238123 | PLUG-AND-SOCKET CONNECTOR ARRANGEMENT WITH FIRST AND SECOND PLUGS AND MATING PLUG - The invention relates to a plug ( | 2012-09-20 |
20120238124 | High Voltage Connector Assembly - A connector assembly includes an electrical connector having a housing that includes a mating end with an exterior profile being generally D-shaped. The housing has a pair of corners. The electrical connector further includes an insert held within the housing having a mating end. A high voltage interlock (HVIL) conductor is located in at least one of the corners of the housing. The HVIL conductor is configured to be electrically connected to a corresponding HVIL conductor of a second electrical connector when the electrical connector and the second electrical connector are coupled together. An interfacial seal is positioned forward of a locking finger of the electrical connector. The HVIL conductors are either in-line or shunted. The HVIL conductors may extend through the insert. | 2012-09-20 |
20120238125 | ELECTRIC CONNECTOR - To allow a quick and reliable check with a simple structure as to whether a signal transmission medium has been inserted up to a predetermined position or whether a lock operation has been completed, an insulating housing is provided with lock checking device allowing a displaced state or an engaged state of a lock member to be visually checked. With this, the displaced state of the lock member or a state in which the signal transmission medium has fallen in an engagement positioning part when the signal transmission medium is inserted up to the predetermined position can be visually checked through the lock checking device, thereby allowing the quality of an insertion state of the signal transmission medium to be immediately determined. | 2012-09-20 |
20120238126 | CONTACT ASSEMBLY FOR ELECTRICAL CONNECTOR - A contact assembly includes a contact organizer having a central axis. A plurality contacts are secured to the contact organizer. The contacts are arranged as differential pairs. The contacts have mating segments and termination segments extending from the mating segments. The mating segments extend along the central axis. The termination segments are configured to terminate to corresponding wires. The mating segments of each differential pair of contacts are radially offset from the central axis of the contact organizer. Wire holders are coupled to the contact organizer. The wire holders have openings extending therethrough and are configured to receive wires. The wire holders are configured to terminate the wires to the termination segments of the contacts when the wire holders are coupled to the contact organizer. | 2012-09-20 |
20120238127 | CAPPED INSULATION DISPLACEMENT CONNECTOR (IDC) - An electrical insulation displacement connector (IDC) assembly includes a body having at least one channel with an open top side for receipt of an insulated conductive core wire. A contact element is fixed in the body with a first insulation displacement end defined by opposed blades oriented across the channel, and a second end extending from a bottom surface of the body for electrical contact with a PCB. The IDC assembly includes a cap having a size and configuration to engage over the body, with the cap including a recess with an open bottom that is aligned with the body channel in a fitted configuration of the cap on the body. The wires may be initially received in the cap recesses wherein upon pressing engagement of the cap onto the body, the insulated conductive core wire is pressed into the body channel between the contact element. | 2012-09-20 |
20120238128 | Lighting Connector Devices and Uses Thereof - A lighting connector which includes (a) an upper housing having plural connector pins, and one or more interlocking grooves; and (b) a lower housing, the lower housing having a plurality of connector pin guide holes, and one or more interlocking tongue portions. The lower housing is connectable with the upper housing to form the lighting connector by coupling at least one of the one or more interlocking grooves with at least one of the one or more interlocking tongue portions, and by coupling at least one of the plural connector pins with at least one of the connector pin guide holes. | 2012-09-20 |
20120238129 | Lighting Connector Devices and Uses Thereof - A lighting connector which includes (a) an upper housing having plural connector pins, and one or more interlocking grooves; and (b) a lower housing, the lower housing having a plurality of connector pin guide holes, and one or more interlocking tongue portions. The lower housing is connectable with the upper housing to form the lighting connector by coupling at least one of the one or more interlocking grooves with at least one of the one or more interlocking tongue portions, and by coupling at least one of the plural connector pins with at least one of the connector pin guide holes. | 2012-09-20 |
20120238130 | WIRE HOLDER AND CHARGING CONNECTOR PROVIDED THEREWITH | 2012-09-20 |
20120238131 | CHARGING CONNECTOR - A charging connector ( | 2012-09-20 |
20120238132 | PORTABLE UNIVERSAL SERIAL BUS (USB) CABLE KEYCHAIN ASSEMBLY WITH CARABINER CLIP - A cable assembly for connecting a portable electronic device to a host device includes an upstream connector section comprising a upstream connector housing, an upstream connector secured to the upstream connector housing, and a downstream connector section comprising a downstream connector housing, a first downstream connector secured to the downstream connector housing, and a second downstream connector secured to the downstream connector housing. The cable assembly further includes a main body section having an attachment mechanism comprising a through hole formed in the main body, the through hole including on one side a carabiner clip comprising a spring-loaded hinged inwardly movable outer portion completing the through hole. | 2012-09-20 |
20120238133 | CONNECTOR MOUNTING APPARATUS WITH EMI SHIELDING CLIP - A connector mounting apparatus includes a mounting bracket and a receiving member. A receiving space is defined in the mounting bracket. The receiving member includes a main body, a first resilient resisting tab extending outward from a base panel of the main body, and a first resilient contacting tab extending inward from the base panel to resiliently abut a connector interface received inside the main body. The main body is received in the receiving space and the first resisting tab resiliently abuts an inner surface of the receiving space. | 2012-09-20 |
20120238134 | DEVICE CONNECTOR AND METHOD OF PRODUCING IT - A terminal block includes a metal plate ( | 2012-09-20 |
20120238135 | DUMMY PLUG - A dummy plug ( | 2012-09-20 |
20120238136 | SPRING CONTACT AND A SOCKET EMBEDDED WITH SPRING CONTACTS - The present invention relates to a spring contact and a socket embedded with spring contacts. The spring contact comprises: an upper contact pin, which includes a contact portion of a predetermined shape intended to be in contact with the lead of a separate semiconductor IC to be inspected, two spring-fixed protrusions and a body; a lower contact two spring-fixed protrusions and a body; a lower contact pin coupled orthogonally to the upper contact pin; and a spring to be inserted between the upper contact pin and the lower contact pin, wherein the body has an oblique end surface with a locking protrusion formed thereon and two symmetric elastic portions, and wherein the two elastic portions form inside thereof an escape groove to provide a flow space when coupled with the lower contact pin and a flow groove to receive the locking protrusion of the lower contact pin and allow it to flow therein, the flow groove being intended to have an electric contact with the locking protrusion of the lower contact pin and with a side contact portion. Further, the present invention provides a variety of structure, such as a structure for minimizing a compressed length of a contact, a structure for an in-line fine pitch spring contact and socket or a structure for a soldered spring contact and socket. | 2012-09-20 |