39th week of 2008 patent applcation highlights part 14 |
Patent application number | Title | Published |
20080230773 | Polymer Composition for Preparing Electronic Devices by Microcontact Printing Processes and Products Prepared by the Processes - The present invention is directed to methods for patterning substrates using contact printing processes and inks comprising an organic semiconductive or semiconductive polymer, inks for use with the processes, and products formed by the processes. | 2008-09-25 |
20080230774 | ORGANIC THIN-FILM TRANSISTOR MANUFACTURING METHOD, ORGANIC THIN-FILM TRANSISTOR, AND ORGANIC THIN-FILM TRANSISTOR SHEET - An organic thin-film transistor manufacturing method and an organic thin-film transistor manufactured by the method are disclosed, the method comprising the steps of a) forming a gate electrode on a substrate, b) forming a gate insulating layer on the substrate, c) forming an organic semiconductor layer on the substrate, d) forming an organic semiconductor layer protective layer on the organic semiconductor layer, e) removing a part of the organic semiconductor layer protective layer, and f) forming a source electrode and a drain electrode at portions where the organic semiconductor layer protective layer has been removed, so that the source electrode and drain electrode contacts the organic semiconductor layer. | 2008-09-25 |
20080230775 | Organic light emitting display device and method for manufacturing the same - An organic light emitting display device and a method for manufacturing the same are disclosed. The method for manufacturing the organic light emitting display device includes forming a switching element and a silicon nitride layer over a substrate, patterning and removing a portion of the silicon nitride layer formed on a light emitting region through which light is transmitted, forming an overcoat layer formed on the silicon nitride layer, wherein a portion of the overcoat layer corresponding to the light emitting region has a thickness of about 1.1 μm to about 2.1 μm, forming a first electrode electrically connected to the switching element over the light emitting region, and sequentially forming an organic light emitting layer and a second electrode on the first electrode. | 2008-09-25 |
20080230776 | Organic semiconductor material and organic transistor using the same - The invention relates to an organic semiconductor material with a high carrier mobility, which is capable of obtaining favorable semiconductor characteristics when used in an organic semiconductor device, and an organic transistor using the same. More specifically, the present invention has a following structure including an oligothiophene part and a connecting part G; | 2008-09-25 |
20080230777 | METHOD OF MAKING AN ORGANIC LIGHT EMITTING DEVICE - The invention relates to a method of making an organic electronic device and articles. | 2008-09-25 |
20080230778 | Method for manufacturing an organic semiconductor device, as well as organic semiconductor device, electronic device, and electronic apparatus - An organic semiconductor device having a gate electrode, a source electrode, a drain electrode, an organic semiconductor layer, a gate insulation layer, and a substrate. The substrate of the semiconductor device having an underlayer including an organic polymer material having a liquid crystal core. The underlayer is oriented in a specific direction formed between the substrate and the organic semiconductor layer so as to orient the organic semiconductor layer along the orientation of the underlayer. | 2008-09-25 |
20080230779 | [100] Or [110] aligned, semiconductor-based, large-area, flexible, electronic devices - Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices. | 2008-09-25 |
20080230780 | Group III Nitride Semiconductor Multilayer Structure - An object of the present invention is to provide a Group III nitride semiconductor multilayer structure having a smooth surface and exhibiting excellent crystallinity, which multilayer structure employs a low-cost substrate that can be easily processed. Another object is to provide a Group III nitride semiconductor light-emitting device comprising the multilayer structure. | 2008-09-25 |
20080230781 | Method of forming an oxygen- or nitrogen-terminated silicon nanocrystalline structure and an oxygen- or nitrogen-terminated silicon nanocrystalline structure formed by the method - A substrate is set at a predetermined temperature in a plasma treatment chamber, then the inside of the plasma treatment chamber is regulated at a reduced pressure containing at least a silicon hydride gas and a hydrogen gas, a high-frequency electric field is applied to form a silicon film of nanometer scale thickness composed of fine silicon crystals and amorphous silicon on the substrate. Thereafter, application of the high-frequency electric field is terminated, then the inside of the plasma treatment chamber is replaced by an oxidizing or nitriding gas, and a high-frequency electric field is applied again for plasma oxidizing treatment or plasma nitriding treatment of the silicon film formed on the substrate. | 2008-09-25 |
20080230782 | PHOTOCONDUCTIVE DEVICES WITH ENHANCED EFFICIENCY FROM GROUP IV NANOPARTICLE MATERIALS AND METHODS THEREOF - A device for generating a plurality of electron-hole pairs from a photon is disclosed. The device includes a substrate, a first electrode formed above the substrate, and a first doped Group IV nanoparticle thin film deposited on the first electrode. The device further includes an intrinsic layer deposited on the first doped Group IV nanoparticle thin film, wherein the intrinsic layer includes a matrix material with a melting temperature T | 2008-09-25 |
20080230783 | Image Sensor and Method for Manufacturing the Same - An image sensor and a method for manufacturing the same are provided. The image sensor can include: a semiconductor substrate including a circuit area; a metal interconnection layer including a metal interconnection and a an interlayer dielectric layer on the semiconductor substrate; a first conductive-type pattern on the metal interconnection layer; an intrinsic layer pattern having a dome-like shape on the first conductive-type pattern; and a second conductive-type conductive layer on the metal interconnection layer including the intrinsic layer pattern. | 2008-09-25 |
20080230784 | Cascode circuit employing a depletion-mode, GaN-based fet - A circuit includes an input drain, source and gate nodes. The circuit also includes a group III nitride depletion mode FET having a source, drain and gate, wherein the gate of the depletion mode FET is coupled to a potential that maintains the depletion mode FET in its on-state. In addition, the circuit further includes an enhancement mode FET having a source, drain and gate. The source of the depletion mode FET is serially coupled to the drain of the enhancement mode FET. The drain of the depletion mode FET serves as the input drain node, the source of the enhancement mode FET serves as the input source node and the gate of the enhancement mode FET serves as the input gate node. | 2008-09-25 |
20080230785 | Termination and contact structures for a high voltage GaN-based heterojunction transistor - A semiconductor device is provided that includes a substrate, a first active layer disposed over the substrate, and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A termination layer, which is disposed on the second active layer, includes InGaN. Source, gate and drain contacts are disposed on the termination layer. | 2008-09-25 |
20080230786 | High temperature performance capable gallium nitride transistor - A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device. | 2008-09-25 |
20080230787 | Silicon carbide semiconductor device, and method of manufacturing the same - The silicon carbide semiconductor device includes a trench formed from a surface of a drift layer of a first conductivity type formed on a substrate of the first conductivity type, and a deep layer of a second conductivity type located at a position in the drift layer beneath the bottom portion of the trench. The deep layer is formed at a certain distance from base regions of the second conductivity type formed on the drift layer so as to have a width wider than the width of the bottom portion of the trench, and surround both the corner portions of the bottom portion of the trench. | 2008-09-25 |
20080230788 | LIQUID CRYSTAL DISPLAY PANEL - A liquid crystal display (LCD) panel is provided. The LCD panel includes an active device array substrate, an opposite substrate, and a liquid crystal layer. The active device array substrate includes a plurality of pixel units, and each of the pixel units has a reflective area and a transmissive area. The opposite substrate is disposed above the active device array substrate and has a plurality of first alignment protrusions corresponding to the reflective area and a plurality of second alignment protrusions corresponding to the transmissive area. The first and the second alignment protrusions are positioned between the opposite substrate and the active device array substrate. Additionally, a height of the first alignment protrusions is greater than a height of the second alignment protrusions. The liquid crystal layer is disposed between the opposite substrate and the active device array substrate. The LCD panel has a high aperture ratio. | 2008-09-25 |
20080230789 | Light emitting device, method of manufacturing the same and monolithic light emitting diode array - A light emitting device including: at least one light emitting stack including first and second conductivity type semiconductor layers and an active layer disposed there between, the light emitting stack having first and second surfaces and side surfaces interposed between the first and second surfaces; first and second contacts formed on the first and second surface of the light emitting stack, respectively; a first insulating layer formed on the second surface and the side surfaces of the light emitting stack; a conductive layer connected to the second contact and extended along one of the side surfaces of the light emitting stack to have an extension portion adjacent to the first surface; and a substrate structure formed to surround the side surfaces and the second surface of the light emitting stack. | 2008-09-25 |
20080230790 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device has an outer lead disposed along an outer wall of a mold resin portion perpendicular to a light-emitting plane of a light emitting diode. An outer lead is also disposed at an outer wall of the mold resin portion parallel to and opposite to the light-emitting plane. The outer wall of the resin mold where the outer lead is disposed is taken as a mount face. Each outer wall of the mold resin portion constituting a mount face includes at least one outer lead for an anode and a cathode. According to the present configuration, there is provided a semiconductor light emitting device that allows selection of side-emission mounting or top-emission mounting with the same components on a mount substrate. | 2008-09-25 |
20080230791 | Optoelectronic device - An optoelectronic device such as a light-emitting diode chip is disclosed. It includes a substrate, a multi-layer epitaxial structure, a first metal electrode layer, a second metal electrode layer, a first bonding pad and a second bonding pad. The multi-layer epitaxial structure on the transparent substrate comprises a semiconductor layer of a first conductive type, an active layer, and a semiconductor layer of a second conductive type. The first bonding pad and the second bonding pad are on the same level. Furthermore, the first metal electrode layer can be patterned so the current is spread to the light-emitting diode chip uniformly. | 2008-09-25 |
20080230792 | Semiconductor Light-Emitting Device with Electrode for N-Polar Ingaain Surface - One embodiment of the present invention provides a semiconductor light-emitting device, which comprises: an upper cladding layer; a lower cladding layer; an active layer between the upper and lower cladding layers; an upper ohmic-contact layer forming a conductive path to the upper cladding layer; and a lower ohmic-contact layer forming a conductive path the lower cladding layer. The lower ohmic-contact layer has a shape substantially different from the shape of the upper ohmic-contact layer, thereby diverting a carrier flow away from a portion of the active layer which is substantially below the upper ohmic-contact layer when a voltage is applied to the upper and lower ohmic-contact layers. | 2008-09-25 |
20080230793 | Patterned Substrate For Light Emitting Diode and Light Emitting Diode Employing the Same - Disclosed herein are a patterned substrate for a light emitting diode and a light emitting diode employing the patterned substrate. The substrate has top and bottom surfaces. Protrusion patterns are arranged on the top surface of the substrate. Furthermore, recessed regions surround the protrusion patterns. The recessed regions have irregular bottoms. Thus, the protrusion patterns and the recessed regions can prevent light emitted from a light emitting diode from being lost due to the total reflection to thereby improve light extraction efficiency. | 2008-09-25 |
20080230794 | Pn Junction Type Group III Nitride Semiconductor Light-Emitting Device - A pn junction type Group III nitride semiconductor light-emitting device | 2008-09-25 |
20080230795 | LIGHT EMITTING DIODE - A light emitting diode and a method of producing white light from the light emitting diode with an active region producing an emission falling in a primary wavelength range. A first part of the active region covered with a first conversion element for converting the emission falling in the primary wavelength range to an emission falling in a second wavelength range. A remaining second part of the active region covered with a second conversion element for converting the emission falling in the primary wavelength rage to an emission falling in a third wavelength range. The light emitting diode is configured to control the intensity of the emission falling in the primary wavelength range to control the color point of the white light generated by mixing the emissions falling the second wavelength range and the third wavelength range. The LED | 2008-09-25 |
20080230796 | Surface mount type light-emitting diode package device and light-emitting element package device - The present invention discloses a surface mount type light-emitting diode package device and a light-emitting element package device. In the device, the encapsulation layer comprises an encapsulation material and at least one material having a refraction index different from the encapsulation material distributed therein. The distribution of the material having a refraction index different from the encapsulation material is in a way such that the refraction index of the encapsulation layer is gradually reduced from the bottom portion upward to the top portion or the inner portion outward to the outer portion of the encapsulation layer. Accordingly, a difference between the refraction indexes of two adjoining media can be reduced to eliminate a total reflection and the Fresnel loss and enhance light extraction efficiency. | 2008-09-25 |
20080230797 | LED module and manufacturing method thereof - An LED module and a manufacturing method thereof are disclosed. The LED module includes a PCB and an LED chip connected with the PCB and a light congregating cup mounted on the PCB. Two ends of the light congregating cup define two hatches, the two hatches run-through each other and form a chip containing space within the light congregating cup. The LED chip is contained in the chip containing space and packaged therein by a packaging colloid. Because the light congregating cup is assembled with the PCB, the operating time of the production machine can be lowered. The defect rate, caused by traditional methods of setting the LED chip in a slantwise concave, can also be reduced. Moreover, the invention also provides a manufacturing method for the LED module. | 2008-09-25 |
20080230798 | ACTIVE MATRIX ORGANIC ELECTROLUMINESCENT SUBSTRATE AND METHOD OF MAKING THE SAME - An active matrix organic electroluminescent substrate includes a substrate having a controlling element region and a luminescent region, a thin film transistor, a first passivation layer, a conductive layer electrically connected to the thin film transistor, and a second passivation layer disposed on the first passivation layer and the conductive layer. The second passivation layer has an opening partially exposing the conductive layer, and a step-shaped structure located between the controlling element region and the luminescent region. | 2008-09-25 |
20080230799 | Semiconductor Light-Emitting Device with Electrode for N-Polar Ingaain Surface - One embodiment of the present invention provides a semiconductor light-emitting device. The semiconductor light-emitting device includes a substrate, a p-type doped InGaAIN layer, an n-type doped InGaAIN layer, and an active layer situated between the p-type doped and n-type doped InGaAIN layers. The semiconductor light-emitting device further includes an n-side Ohmic-contact layer coupled to an N-polar surface of the n-type doped InGaAIN layer. The Ohmic-contact layer comprises at least one of Au, Ni, and Pt, and at least one of group IV elements. | 2008-09-25 |
20080230800 | N-Type Group III Nitride Semiconductor Layered Structure - An object of the present invention is to provide a low-resistance n-type Group III nitride semiconductor layered structure having excellent flatness and few pits. The inventive n-type group III nitride semiconductor layered structure comprises a substrate and, stacked on the substrate, an n-type impurity concentration periodic variation layer comprising an n-type impurity atom higher concentration layer and an n-type impurity atom lower concentration layer, said lower concentration layer being stacked on said higher concentration layer. | 2008-09-25 |
20080230801 | TRENCH TYPE POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a trench type power semiconductor device is provided. The method includes: forming a first silicon oxide film on a silicon substrate; forming a thermal oxidation-resistant film on the first silicon oxide film; forming an opening in the first silicon oxide film and the thermal oxidation-resistant film; forming a sidewall on an inner side surface of the opening; forming a trench in the silicon substrate by etching the silicon substrate using the first silicon oxide film, the thermal oxidation-resistant film, and the sidewall as a mask; removing the sidewall; forming a second silicon oxide film thicker than the first silicon oxide film on an inner surface of the trench by applying thermal oxidation to the silicon substrate; burying a trench gate electrode in the trench; removing the thermal oxidation-resistant film; and introducing impurities into at least part of a region of the silicon substrate between the trenches. | 2008-09-25 |
20080230802 | Semiconductor Device Comprising a Heterojunction - A semiconductor device with a heterojunction. The device comprises a substrate and at least one nanostructure. The substrate and nanostructure is of different materials. The substrate may e.g. be of a group IV semiconductor material, whereas the nanostructure may be of a group III-V semiconductor material. The nanostructure is supported by and in epitaxial relationship with the substrate. A nanostructure may be the functional component of an electronic device such as a gate-around-transistor device. In an embodiment of a gate-around-transistor, a nanowire ( | 2008-09-25 |
20080230803 | Integrated Contact Interface Layer - A semiconductor device that is fabricated by metamorphic epitaxial growth processes, and includes a combined graded base and active layer having a thickness less than 5000 Å. In one non-limiting embodiment, the semiconductor device is an HBT device that includes a combined doped graded buffer and sub-collector layer having a thickness less than 5000 Å, and a concentration of indium of about 86% at a top of the combined layer. | 2008-09-25 |
20080230804 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF SAME - A semiconductor device having an electrode with reduced electrical contact resistance even where either electrons or holes are majority carriers is disclosed. This device has an n-type diffusion layer and a p-type diffusion layer in a top surface of a semiconductor substrate. The device also has first and second metal wires patterned to overlie the n-type and p-type diffusion layers, respectively, with a dielectric layer interposed therebetween, a first contact electrode for electrical connection between the n-type diffusion layer and the first metal wire, and a second contact electrode for connection between the p-type diffusion layer and the second metal wire. The first contact electrode's portion in contact with the n-type diffusion layer and the second contact electrode's portion contacted with the p-type diffusion layer are each formed of a first conductor that contains a metal and a second conductor containing a rare earth metal. | 2008-09-25 |
20080230805 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device may include a Si substrate, a gate electrode provided on the semiconductor via a gate dielectric layer, a first epitaxially grown layer provided on the Si substrate, a channel region provided in the Si substrate below the gate electrode, a source/drain region provided in the first epitaxially grown layer sandwiching the channel region, and having a first conductivity type impurity, a second epitaxially grown layer provided between the channel region and the first epitaxially grown layer, and provided below the gate electrode, and having a second conductivity type impurity opposite to the first conductivity type. | 2008-09-25 |
20080230806 | HBT and field effect transistor integration - Methods and systems for fabricating an integrated BiFET using two separate growth procedures are disclosed. Performance of the method fabricates the FET portion of the BIFET in a first fabrication environment. Performance of the method fabricates the HBT portion of the BiFET in a second fabrication environment. By separating the fabrication of the FET portion and the HBT portion in two or more separate reactors, the optimum device performance can be achieved for both devices. | 2008-09-25 |
20080230807 | Semiconductor Device - A semiconductor device having sufficiently high heat dissipation performance while inhibiting an increase in the area of a chip is provided. In semiconductor device | 2008-09-25 |
20080230808 | HETEROJUNCTION BIPOLAR TRANSISTOR - A base layer made of SiGe mixed crystal includes a spacer layer formed in contact with a collector layer with no base impurities diffused therein and an intrinsic base layer formed in contact with an emitter layer with base impurities diffused therein. The spacer layer contains C at a low concentration. The intrinsic base layer has a first region containing C at a low concentration on the collector side and a second region containing C at a high concentration on the emitter side. | 2008-09-25 |
20080230809 | Semiconductor device and method of fabricating the same - A sophisticated semiconductor device capable of being fabricated without introducing a high-precision exposure apparatus is obtained. This semiconductor device includes a conductive layer formed on a first conductivity type collector layer, a first conductivity type emitter electrode formed on the conductive layer and a protruding portion protruding from an outer side toward an inner side of the emitter electrode along an interface between the emitter electrode and the conductive layer. The conductive layer has a first conductivity type emitter diffusion layer in contact with the emitter electrode through the protruding portion and a second conductivity type base layer. | 2008-09-25 |
20080230810 | INSULATED GATE SEMICONDUCTOR DEVICE - An isolation region is provided around a sense part. The isolation region is provided to have a depth that suppresses spread of a region with an uneven current distribution, which occurs at a peripheral edge of the sense part. Thus, in the sense part, an influence of the region with the uneven current distribution can be suppressed. Since the current distribution can be set more even throughout the sense part, the on-resistance in the sense part can be set closer to its designed value. Thus, a current ratio corresponding to a cell ratio can be obtained as designed. Consequently, current detection accuracy is improved. | 2008-09-25 |
20080230811 | Semiconductor Structure - The invention relates to a semiconductor structure, especially for use in a semiconductor detector. The semiconductor structure includes a weakly doped semiconductor substrate (HK) of a first or second doping type, a highly doped drain region (D) of a second doping type, located on a first surface of the semiconductor substrate (HK), a highly doped source region (S) of the second doping type, located on the first surface of the semiconductor substrate (HK), a duct (K) extending between the source region (S) and the drain region (D), a doped inner gate region (IG) of the first doping type, which is at least partially located below the duct (K), and a blow-out contact (CL) for removing charge carriers from the inner gate region (IG). According to the invention, the inner gate region (IG) extends in the semiconductor substrate (HK) at least partially up to the blow-out contact (CL) and the blow-out contact (CL) is located on the drain end relative to the source region (S). | 2008-09-25 |
20080230812 | Isolated junction field-effect transistor - Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described. | 2008-09-25 |
20080230813 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR | 2008-09-25 |
20080230814 | Methods for fabricating a semiconductor device - A method for fabricating a semiconductor device comprises providing a silicon-containing substrate with first, second, and third regions. First, second, and third gate stacks respectively overlie a portion of the silicon-containing substrate in the first, second, and third regions. A spacer is formed on opposing sidewalls of each of the first, second, and third gate stacks, the spacer overlying a portion of the silicon-containing substrate in the first, second, and third regions, respectively. A source/drain region is formed in a portion of the silicon-containing substrate in the first, second, and third regions, with the source/drain region adjacent to the first, second, and third gate stacks, respectively. The first, second, and third gate stacks have first, second, and third gate dielectric layers of various thicknesses and at least one thereof with a relatively thin thickness is treated by NH | 2008-09-25 |
20080230815 | Mitigation of gate to contact capacitance in CMOS flow - Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics. | 2008-09-25 |
20080230816 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device has forming a first silicon film over the first insulating film, forming a second silicon film over the first silicon film, a first etching the second silicon film in a depth, which the first silicon film is not exposed, in first condition, a second etching a remaining portion of the second silicon film and the first silicon film in a depth, which the first insulating film is not exposed, in second condition which gives a higher vertical etching component ratio than the first condition; and a third etching a remaining portion of the first silicon film in third condition which an etching rate for the first silicon film is larger than an etching rate for the first insulating film as compared to the second condition, wherein an impurity concentration of a first conductivity type of the first silicon film is higher than an impurity concentration of first conductivity type of the second silicon film. | 2008-09-25 |
20080230817 | SEMICONDUCTOR PHOTODETECTOR DEVICE - A semiconductor photodetector device includes a light receiving operation section converting incident light to an electric signal and a current amplifying operation section amplifying the electric signal. The light receiving operation section includes: a first conductivity type semiconductor layer a formed on a first conductivity type semiconductor substrate; a second conductivity type first semiconductor region formed on the semiconductor layer; and a first conductivity type second semiconductor region formed on the semiconductor layer and separated from the first semiconductor region. The current amplifying operation section includes: the second semiconductor region; a second conductivity type third semiconductor region formed in the semiconductor substrate; a second conductivity type fourth semiconductor region formed on the third semiconductor region and separated from the second semiconductor region. | 2008-09-25 |
20080230818 | NON-VOLATILE MEMORY DEVICE - According to an aspect of the present invention, there is provided a non-volatile memory including: a transistor formed on a semiconductor substrate, the transistor including: two diffusion layers and a gate therebetween; a first insulating film formed on a top and a side surfaces of the gate; a first and a second contact plugs formed on corresponding one of the diffusion layers to contact the first insulating film; a ferroelectric capacitor formed on the first contact plug and on the first insulating film, the ferroelectric capacitor including: a first and a second electrodes and a ferroelectric film therebetween; a third contact plug formed on the second electrode; and a fourth contact plug formed on the second contact plug. | 2008-09-25 |
20080230819 | SPIN TRANSFER MAGNETIC ELEMENT WITH FREE LAYERS HAVING HIGH PERPENDICULAR ANISOTROPY AND IN-PLAN EQUILIBRIUM MAGNETIZATION - A method and system for providing a magnetic element that can be used in a magnetic memory is disclosed. The magnetic element includes pinned, nonmagnetic spacer, and free layers. The spacer layer resides between the pinned and free layers. The free layer can be switched using spin transfer when a write current is passed through the magnetic element. The free layer includes a first ferromagnetic layer and a second ferromagnetic layer. The second ferromagnetic layer has a very high perpendicular anisotropy and an out-of-plane demagnetization energy. The very high perpendicular anisotropy energy is greater than the out-of-plane demagnetization energy of the second layer. | 2008-09-25 |
20080230820 | SEMICONDUCTOR DEVICE - Coexistence of the realization of high-capacity of a capacitive element and the area reduction of a semiconductor device is aimed at. A plurality of capacitive elements from which a kind differs mutually are accumulated and arranged on a semiconductor substrate, and they are connected in parallel. These capacitive elements are arranged to the same plane region, and make a plane size almost the same. A lower capacitive element is an MOS type capacitive element which uses as both electrodes the n-type semiconductor region formed in the semiconductor substrate, and the upper electrode formed via the insulation film on the n-type semiconductor region. The MIM type capacitive element formed with the pattern of the comb-type of a wiring is arranged in the upper part of a lower capacitive element, and this is connected with a lower capacitive element in parallel. | 2008-09-25 |
20080230821 | Semiconductor device - In a semiconductor device which can perform data communication through wireless communication, to suppress transmission and the like of an AC signal, the semiconductor device includes an input circuit to which a radio signal is input, a first circuit, which generates a constant voltage, such as a constant voltage circuit or a limiter circuit, a second circuit to which the generated constant voltage is input and which can change impedance of the semiconductor device, and a filter provided between the first circuit and the second circuit. Transmission of an AC signal is suppressed by the filter, and malfunctions or operation defects such as complete inoperative due to variation in the constant voltage is prevented. | 2008-09-25 |
20080230822 | VERTICAL TRENCH MEMORY CELL WITH INSULATING RING - A method of forming a vertical transistor trench memory cell having an insulating ring is provided. The method includes forming a semiconductor material region in an etched portion of a semiconductor substrate; partially etching the semiconductor material region to form a deep trench, where the deep trench extends beyond the semiconductor material region, and where the remaining of the partially etched semiconductor material region defines an insulating ring. A vertical transistor is then formed in the deep trench, such that the vertical transistor is isolated by the insulating ring. A semiconductor structure is also provided. The semiconductor structure includes a first and a second trench memory cells formed on a semiconductor substrate; and an insulating ring surrounding each of the first and second trench memory cells. The insulating ring is configured for significantly enclosing outdiffusions from the trench memory cells. | 2008-09-25 |
20080230823 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device having an active element and an MIM capacitor and a structure capable of reducing the number of the manufacturing steps thereof and a manufacturing method therefor are provided. The semiconductor device has a structure that the active element having an ohmic electrode and the MIM capacitor having a dielectric layer arranged between a lower electrode and an upper electrode are formed on a semiconductor substrate, wherein the lower electrode and ohmic electrode have the same structure. | 2008-09-25 |
20080230824 | Double Gate Non-Volatile Memory Device and Method of Manufacturing - The present invention relates to a non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin-shaped channel; the control gate being in contact with the charge storage stack, wherein—an access gate is provided adjacent to one sidewall portion and separated therefrom by an intermediate gate oxide layer, and—the charge storage stack contacts the fin-shaped channel on the other sidewall portion and is separated from the channel by the intermediate gate oxide layer. | 2008-09-25 |
20080230825 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer, a first gate electrode, a second insulating layer, and a second gate electrode which are layered over the semiconductor layer in that order. Part or all of the source and drain regions is formed using a metal silicide layer. The first gate electrode contains a noble gas element. | 2008-09-25 |
20080230826 | Construction of flash memory chips and circuits from ordered nanoparticles - Methods, apparatus and systems form memory structures, such as flash memory structures from nanoparticles by providing a source of nanoparticles as a conductive layer. The particles are moved by application of a field, such as an electrical field, magnetic field and even electromagnetic radiation. The nanoparticles are deposited onto an insulating surface over a transistor in a first distribution of the nanoparticles. A field is applied to the nanoparticles on the surface that applies a force to the particles, rearranging the nanoparticles on the surface by the force from the field to form a second distribution of nanoparticles on the surface. A protective and enclosing insulating layer is deposited on the nanoparticle second distribution. The addition of a top conductive layer completes a basic flash memory structure. | 2008-09-25 |
20080230827 | SCALABLE FLASH/NV STRUCTURES AND DEVICES WITH EXTENDED ENDURANCE - Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an injector medium. The high K charge blocking and charge storing medium is disposed on the tunnel medium. The injector medium is operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling. According to one embodiment, the injector medium is disposed on the high K charge blocking and charge storing medium. According to one embodiment, the tunnel medium is disposed on the injector medium. Other aspects and embodiments are provided herein. | 2008-09-25 |
20080230828 | GATE STRUCTURE OF A NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING SAME - A non-volatile memory device includes a substrate that is divided into a field region and an active region by isolation layer patterns. The active region has an active trench for increasing an effective area of the active region. A tunnel oxide layer is formed on the active region. A floating gate pattern is formed on the tunnel oxide layer to fill up the active trench. A dielectric layer pattern is formed on the floating gate pattern. A control gate pattern is formed on the dielectric layer pattern. Thus, the non-volatile memory device has an increased effective area of the active region so that the non-volatile memory device may have improved operational characteristics. | 2008-09-25 |
20080230829 | Memory device and method of fabricating the same - A memory device and a method of fabricating the same. The memory device includes a substrate and a first gate electrode overlying the substrate. Overlying a top surface of the first gate electrode, a second gate electrode comprises end portions extending to spaces adjacent to the substrate and sidewalls of the first gate electrode. Further, a dielectric layer comprises a first portion sandwiched between the first gate electrode and the second gate electrode, and second portions extending from the first portion, sandwiched between the substrate and the end portions of the second gate electrode. | 2008-09-25 |
20080230830 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer. | 2008-09-25 |
20080230831 | Semiconductor device and manufacturing method thereof - A charge retention characteristic of a nonvolatile memory transistor is improved. A first insulating film that functions as a tunnel insulating film, a charge storage layer, and a second insulating film are sandwiched between a semiconductor substrate and a conductive film. The charge storage layer is formed of two silicon nitride films. A silicon nitride film which is a lower layer is formed using NH | 2008-09-25 |
20080230832 | TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device to enlarge a channel region is provided. The channel region is enlarged due to having pillar shaped sidewalls of a transistor. The transistor includes a fin active region vertically protruding on a substrate, an isolation layer enclosing a lower portion of the fin active region, and a gate electrode crossing the fin active region and covering a portion of the fin active region. An isolation layer is formed enclosing a lower portion of the fin active region and the isolation layer under the spacers is partially removed to expose a portion of the sidewalls of the fin active region. Subsequently, dry etching is performed to form the sidewalls having a pillar/neck. | 2008-09-25 |
20080230833 | SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT - A semiconductor component having a semiconductor body having first and second semiconductor regions of a first conduction type, and a third semiconductor region of a second conduction type, which is complementary to the first conduction type. The second semiconductor region is arranged between the first and third semiconductor region and together with the first semiconductor region forms a first junction region and together with the third semiconductor region forms a second junction region. In the second semiconductor region the dopant concentration is lower than the dopant concentration in the first semiconductor region. The dopant concentration in the second semiconductor region along a straight connecting line between the first and third semiconductor regions is inhomogeneous and has at least one minimum between the first and second junction regions, wherein the minimum is at a distance from the first and second junction regions. | 2008-09-25 |
20080230834 | Semiconductor apparatus having lateral type MIS transistor - A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor includes: a line coupled with a gate of the lateral type MIS transistor; a polycrystalline silicon resistor that is provided in the line, and that has a conductivity type opposite to a drain of the lateral type MIS transistor; and an insulating layer through which a drain voltage of the lateral type MIS transistor is applied to the polycrystalline silicon resistor. | 2008-09-25 |
20080230835 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object to provide an element structure of a semiconductor device for having a sufficient contact area between an electrode in contact with a source region or a drain region and the source region or the drain region, and a method for manufacturing the semiconductor device with the element structure. An upper electrode is formed over a high-concentration impurity region (the source region or the drain region). A contact hole passing through an interlayer insulating film is formed overlapping with a region where the upper electrode and the high-concentration impurity region are stacked. | 2008-09-25 |
20080230836 | Semiconductor device and boost circuit - A semiconductor device includes a transistor that is used for a charge pump circuit, being configured with a fully depleted silicon-on-insulator transistor. | 2008-09-25 |
20080230837 | RADIATION-HARDENED SILICON-ON-INSULATOR CMOS DEVICE, AND METHOD OF MAKING THE SAME - A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity concentration in the ultrathin silicon layer. | 2008-09-25 |
20080230838 | Semiconductor memory device and manufacturing process therefore - An objective of this invention is to solve the problem caused by a difference in a silicon layer film thickness between a memory cell region and a region other than the memory cell region. | 2008-09-25 |
20080230839 | Method of producing a semiconductor structure - The invention is related to a method of producing a semiconductor structure comprising the steps of: fabricating a gate stack structure and oxidizing at least a portion of the gate stack structure's sidewalls, wherein the step of oxidizing is carried out at a temperature below 500° C. using a process gas which comprises oxygen radicals. | 2008-09-25 |
20080230840 | ULTRA SHALLOW JUNCTION FORMATION BY EPITAXIAL INTERFACE LIMITED DIFFUSION - A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate. | 2008-09-25 |
20080230841 | INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS MEMORIZATION TRANSFER - An integrated circuit system that includes: providing a gate and a spacer formed over a substrate; performing an implant that amorphizes the gate and a source/drain region defined by the spacer; removing the spacer; depositing a stress memorization layer over the integrated circuit system; and transferring a stress from the stress memorization layer to the gate and the source/drain region. | 2008-09-25 |
20080230842 | Semiconductor Device Having High-K Gate Dielectric Layer and Method For Manufacturing the Same - A semiconductor device having a high-K gate dielectric layer includes a p-type well that is formed in an upper layer of a silicon substrate. Arsenic ions are implanted into an extreme surface layer of the p-type well and a heat treatment is performed to form a p-type low-concentration layer. A HfAlOx film and a polycrystalline silicon layer are laminated on the substrate. A gate electrode is formed by patterning the polycrystalline silicon layer. After a n-type extension region is formed by implanting arsenic ions by using the gate electrode as a mask, sidewall spacers are formed on sides of the gate electrode. Arsenic ions are implanted by using the sidewall spacers and the gate electrode as masks, whereby n-type source/drain regions are formed. | 2008-09-25 |
20080230843 | Isolation Structure for MOS Transistor and Method for Forming the Same - A method for forming isolation structure for MOS transistor is disclosed, which includes forming a first photoresist layer over a sacrificed oxide layer of a semiconductor substrate, patterning the first photoresist layer to define a PMOS active region and a PMOS isolation region; implanting nitrogen ions into the PMOS isolation region through the sacrificed oxide layer by using the first photoresist layer as a mask; removing the first photoresist layer; forming a second photoresist layer over the sacrificed oxide layer, patterning the second photoresist layer to define a NMOS active region and a NMOS isolation region; implanting oxygen ions into the NMOS isolation region through the sacrificed oxide layer by using the second photoresist layer as a mask; removing the second photoresist layer and the sacrificed oxide layer; and annealing the semiconductor substrate to form isolation structures of PMOS and NMOS, respectively. | 2008-09-25 |
20080230844 | Semiconductor Device with Multiple Silicide Regions - A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transistor) into the source/drain extensions after silicide contacts have been formed. An anneal is then performed to create a second silicide region within the source/drain extension. Optionally, a second anneal could be performed on the second silicide region to force a further reaction. This process could be performed to multiple semiconductor devices on the same substrate. | 2008-09-25 |
20080230845 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silicon diffusion layer. The diffusion barrier layer prevents a diffusion of at least one of silicon-interstitial and silicon-vacancy between the single crystal silicon diffusion layer and the polycrystal silicon conductor. | 2008-09-25 |
20080230846 | METHOD OF MANUFACTURING METAL SILICIDE CONTACTS - A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts. | 2008-09-25 |
20080230847 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films | 2008-09-25 |
20080230848 | STRUCTURE HAVING DUAL SILICIDE REGION AND RELATED METHOD - A structure including a dual silicide region and a related method are disclosed. The structure may include a doped silicon, and a dual silicide region in the doped silicon, the dual silicide region including a first silicide region including a mid band gap metal, and a second silicide region including a near band gap metal, wherein the second silicide region is immediately adjacent to the doped silicon. The method may include forming a first silicide portion in a doped silicon by depositing a first metal over the doped silicon, annealing and removing unreacted first metal; ion implanting a second metal into the doped silicon; and annealing to form a second silicide portion from the second metal, wherein the first metal is different than the second metal. | 2008-09-25 |
20080230849 | DEVICE COMPRISING DOPED NANO-COMPONENT AND METHOD OF FORMING THE DEVICE - A device comprising a doped semiconductor nano-component and a method of forming the device are disclosed. The nano-component is one of a nanotube, nanowire or a nanocrystal film, which may be doped by exposure to an organic amine-containing dopant. Illustrative examples are given for field effect transistors with channels comprising a lead selenide nanowire or nanocrystal film and methods of forming these devices. | 2008-09-25 |
20080230850 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device has forming a first mask pattern exposing a region for forming a first transistor and a region for forming a second transistor, performing a first ion implantation using the first mask pattern, performing a second ion implantation using the first mask pattern, removing the first mask pattern and forming a second mask pattern in which the first transistor forming region is covered and the second transistor forming region is opened, and performing a third ion implantation using the second mask pattern. | 2008-09-25 |
20080230851 | METAL OXIDE SEMICONDUCTOR (MOS) TYPE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors. | 2008-09-25 |
20080230852 | Fabrication of FinFETs with multiple fin heights - A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the first semiconductor strip, wherein the first insulating region has a first top surface lower than a top surface of the first semiconductor strip. A second semiconductor strip extends from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the second semiconductor strip has a second height greater than the first height. A second insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the second semiconductor strip, wherein the second insulating region has a second top surface lower than the first top surface, and wherein the first and the second insulating regions have substantially same thicknesses. | 2008-09-25 |
20080230853 | Transistor and method of manufacturing the same - In a transistor and a method of manufacturing the same, the transistor includes a channel layer arranged on a substrate, a source electrode and a drain electrode formed on the substrate so as to contact respective ends of the channel layer, a gate insulating layer surrounding the channel layer between the source electrode and the drain electrode, and a gate electrode surrounding the gate insulating layer. | 2008-09-25 |
20080230854 | SEMICONDUCTOR DEVICE CONTAINING CRYSTALLOGRAPHICALLY STABILIZED DOPED HAFNIUM ZIRCONIUM BASED MATERIALS - A semiconductor device, such as a transistor or capacitor is provided. The device includes a substrate, a gate dielectric over the substrate, and a conductive gate dielectric film over the gate dielectric. The gate dielectric includes a doped hafnium zirconium oxide containing one or more dopant elements selected from Group II, Group XIII, silicon, and rare earth elements of the Periodic Table. According to one embodiment, the conductive gate dielectric can contain doped hafnium zirconium nitride or doped hafnium zirconium oxynitride. | 2008-09-25 |
20080230855 | Gate strip with reduced thickness - A semiconductor structure with reduced inter-diffusion is provided. The semiconductor structure includes a semiconductor substrate; a first well region in the semiconductor substrate; a second well region in the semiconductor substrate; an insulating region between and adjoining the first and the second well regions; a gate dielectric layer on the first and the second well regions; and a gate electrode strip on the gate dielectric and extending from over the first well region to over the second well region. The gate electrode strip includes a first portion over the first well region, a second portion over the second well region, and a third portion over the insulating region. A thickness of the third portion is substantially less than the thicknesses of the first and the second portions. | 2008-09-25 |
20080230856 | INTERMEDIATE PROBE STRUCTURES FOR ATOMIC FORCE MICROSCOPY - An intermediate probe structure for atomic force microscopy is disclosed. The probe structure comprises a semiconductor substrate with one or more moulds formed on a surface of one side of the substrate. The probe structure further comprises one or more probe configurations formed on the one side of the semiconductor substrate, wherein each probe configuration comprises a contact region and at least one set of a probe tip and a cantilever. The probe structure further comprises one or more holders attached to each of the contact regions, wherein the surface area of each contact region is smaller in size than the surface area of the holder which is attached to the contact region. | 2008-09-25 |
20080230857 | SENSOR CHIP AND SUBSTRATE ASSEMBLY FOR MEMS DEVICE - A sensor chip and substrate assembly for use in a MEMS device includes a substrate and a sensor chip. The substrate has a top surface, a bottom surface opposite to the top surface, and a passage obliquely penetrating through the top surface and the bottom surface. The sensor chip is mounted on the top surface of the substrate and provided with a sensing zone facing the passage of the substrate. The oblique passage provides a buffering effect to prevent damage to the sensor chip when the quantity of the physical property sending from the detected object increases sharply. | 2008-09-25 |
20080230858 | Multi-layer Package Structure for an Acoustic Microsensor - A multi-layer package structure for an acoustic microsensor, the package structure mainly utilizes a stack of multiple substrates for housing and protecting circuit elements such that integrated circuit element and acoustic microsensor arranged in recessions of a substrate can reduce volume of the package structure. By adding various sound hole designs, the problem of larger package volume can be effectively solved and sensing frequency of the acoustic microsensor can be increased simultaneously. | 2008-09-25 |
20080230859 | SAW DEVICES, PROCESSES FOR MAKING THEM, AND METHODS OF USE - The design, fabrication, post-processing and characterization of a novel SAW (Surface Acoustic Wave) based bio/chemical sensor in CMOS technology is introduced. The sensors are designed in AMI 1.5 μm 2 metal, 2 poly process. A unique maskless post processing sequence is designed and completed. The three post-processing steps are fully compatible with any CMOS technology. This allows any signal control/processing circuitry to be easily integrated on the same chip. ZnO is used as the piezoelectric material for the SAW generation. A thorough characterization and patterning optimization of the sputtered ZnO was carried out. The major novelties that are introduced in the SAW delay line features are: The embedded heater elements for temperature control, compensation and acoustic absorbers that are designed to eliminate edge reflections and minimize triple transit interference. Both of these attributes are designed by using the CMOS layers without disturbing the SAW performance. | 2008-09-25 |
20080230860 | Integrated cirucit package and method for fabrication thereof - The invention provides an integrated circuit package and method of fabrication thereof. The integrated circuit package comprises an integrated circuit chip having a photosensitive device thereon; a bonding pad formed on an upper surface of the integrated circuit chip and electrically connected to the photosensitive device, a barrier formed between the bonding pad and the photosensitive device; and a conductive layer formed on a sidewall of the integrated circuit chip and electrically connected to the bonding pad. The barrier layer blocks overflow of the adhesive layer into a region, on which the photosensitive device is formed, to improve yield for fabricating the integrated circuit package. | 2008-09-25 |
20080230861 | CMOS front end process compatible low stress light shield - An improved imaging device having a pixel arrangement featuring a multilayer light shield. The multilayer light shield includes stacked layers of light-shielding and light-transparent material. The light-transparent material, such as a dielectric, is selected to have a stress, such as a tensile stress, that offsets the stress, such as a compressive stress, of the light shielding material. Without the stress offset, the high compressive stress of the refractory metal could damage the integrity of the nearby silicon. The refractory metal is capable of withstanding the high temperatures associated with front end CMOS processing. The laminate structure allows the light shield to be placed close to the pixel surface. The light-transparent material has a thickness equal to about one-quarter wavelength of the light to be blocked, to act as an anti-reflective coating. An aperture in the light shield exposes the active region of the pixel's photoconversion device. | 2008-09-25 |
20080230862 | Method, Apparatus, Material, and System of Using a High Gain Avalanche Photodetector Transistor - Here, we demonstrate new material/structures for the photodetectors, using semiconductor material. For example, we present the Tunable Avalanche Wide Base Transistor as a photodetector. Particularly, SiC, GaN, AlN, Si and Diamond materials are given as examples. The desired properties of an optimum photodetector is achieved. Different variations are discussed, both in terms of structure and material. | 2008-09-25 |
20080230863 | Methods and apparatus for manufacturing semiconductor devices - In accordance with the teachings of the present disclosure, methods and apparatus are provided for a semiconductor device having thin anti-reflective layer(s) operable to absorb radiation that may otherwise reflect off surfaces disposed inwardly from the anti-reflective layer(s). In a method embodiment, a method for manufacturing a semiconductor device includes forming a support structure outwardly from a substrate. The support structure has a first thickness and a first outer sidewall surface that is not parallel with the substrate. The first outer sidewall surface has a first minimum refractive index. The method further includes forming an anti-reflective layer outwardly from the first outer sidewall surface. The anti-reflective layer has: a second outer sidewall surface that is not parallel with the substrate, a second refractive index that is greater than the first minimum refractive index, and a second thickness that is less than the first thickness. | 2008-09-25 |
20080230864 | Image Sensor and Method for Manufacturing the Same - Disclosed is an image sensor which includes a plurality of pixel patterns formed on corresponding metal interconnections of an interlayer dielectric and a dummy pixel pattern formed between adjacent pixel patterns of the plurality of the pixel patterns. The dummy pixel patterns are not formed connected to the metal interconnections. The dummy pixel patterns can be formed spaced a distance apart from the plurality of pixel patterns such that air gaps form between the dummy pixel patterns and the pixel patterns in an intrinsic layer that is formed on the dummy pixel pattern and the plurality of pixel patterns. | 2008-09-25 |
20080230865 | Image Sensor and Method for Manufacturing the Same - An image sensor and method of manufacturing the same are provided. According to an embodiment, the image sensor comprises: a circuit including an interconnection on a substrate; a lower electrode on the interconnection; a separated intrinsic layer on the lower electrode; a second conductive type conduction layer on the separated intrinsic layer; and an upper electrode on the second conductive type conduction layer. The separated intrinsic layer can have an inwardly sloping sidewall to focus light incident the photodiode for the unit pixel. | 2008-09-25 |
20080230866 | RFID TEMPERATURE SENSING WAFER, SYSTEM AND METHOD - A system and method for manufacturing semiconductor wafers comprising an RFID temperature sensor and generally described herein. Other embodiments may be described and claimed. | 2008-09-25 |
20080230867 | Method of forming ohmic contact to a semiconductor body - A process for forming an ohmic contact on the back surface of a semiconductor body includes depositing a donor layer on the back surface of the semiconductor body followed by a sintering step to form a shallow intermetallic region capable of forming a low resistance contact with a contact metal. | 2008-09-25 |
20080230868 | PATTERN ENHANCEMENT BY CRYSTALLOGRAPHIC ETCHING - A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners. | 2008-09-25 |
20080230869 | ULTRA-THIN SOI VERTICAL BIPOLAR TRANSISTORS WITH AN INVERSION COLLECTOR ON THIN-BURIED OXIDE (BOX) FOR LOW SUBSTRATE-BIAS OPERATION AND METHODS THEREOF - The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. | 2008-09-25 |
20080230870 | INPUT PROTECTION CIRCUIT PREVENTING ELECTROSTATIC DISCHARGE DAMAGE OF SEMICONDUCTOR INTEGRATED CIRCUIT - An input protection circuit comprises a semiconductor chip, an internal circuit disposed on the semiconductor chip, a first input/output terminal which is disposed on the semiconductor chip and connected to the internal circuit, a second input/output terminal which is disposed on the semiconductor chip, connected to the internal circuit and disposed at a position adjacent to the first input/output terminal, and a fusing part which is disposed on the semiconductor chip and connected between the first and second input/output terminals. | 2008-09-25 |
20080230871 | SEMICONDUCTOR DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT. | 2008-09-25 |
20080230872 | BIPOLAR TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A bipolar transistor and a method for manufacturing the same. The bipolar transistor can include a collector region formed in a substrate, an epitaxial layer formed over the substrate including the collector region, a base region formed in the epitaxial layer, an emitter region formed in the base region, an oxide layer formed on sidewalls of a trench extending through the emitter region, the base region, the epitaxial layer and in the collector region, and a polysilicon layer formed in the trench. | 2008-09-25 |