39th week of 2008 patent applcation highlights part 19 |
Patent application number | Title | Published |
20080231276 | MAGNETIC RESONANCE SYSTEM WITH RADIO-FREQUENCY SHIELD WITH FREQUENCY-DEPENDENT SHIELDING EFFECT - A magnetic resonance system has a basic magnet that generates a static basic magnetic field in an examination volume, and a whole-body antenna that emits a homogeneous radio-frequency field in the examination volume, the homogeneous radio-frequency field exhibiting an excitation frequency so that nuclei in an examination subject in the examination volume are excited to emit magnetic resonance signals, and a radio-frequency shield. The radio-frequency shield is arranged between the whole-body antenna and the basic magnet. The whole-body antenna is arranged between the radio-frequency shield and the examination volume. The radio-frequency shield is fashioned to exhibit a high shielding effect in a shielding frequency range that encompasses the excitation frequency. The shielding effect drops to a significantly lower shielding effect on both sides at side bands adjoining the shielding frequency range. The shielding frequency range and the side bands exhibit bandwidths that are significantly smaller than the excitation frequency. | 2008-09-25 |
20080231277 | NMR spectrometer - The present invention provides a highly-sensitive nuclear magnetic resonance (NMR) spectrometer which achieves a high Q factor using a superconductor, and concurrently which is provided with a probe antenna maintaining the magnetic homogeneity of the static magnetic field in a sample space. An antenna coil is fabricated by using a wire having a superconducting layer formed on the surface of a metal wire. | 2008-09-25 |
20080231278 | RADIO-FREQUENCY COIL AND MAGNETIC RESONANCE IMAGING APPARATUS - A radio-frequency coil has a first element and a second element both being adjacently arranged so as to nip a division/join portion. The first element has a first main loop portion provided along an arrangement plain surface and a first sub-loop portion provided along a surface substantially perpendicular to the arrangement plain surface. The second element has a second main loop portion provided along the arrangement plain surface and a second sub-loop portion provided facing the first sub-loop. The first sub-loop portion and the second sub-loop portion generate an induced electromotive force such that, among magnetic fields generated when a current flows in one coil, a summation of the magnetic fields, which interlink with the other coil, becomes zero. | 2008-09-25 |
20080231279 | RF COIL AND MAGNETIC RESONANCE IMAGING APPARATUS - An RF coil includes: a first loop coil element including a first plane closed by a first coil line; and a second loop coil element including a second plane closed by a second coil line, in which part of said first plane and part of said second plane face each other, wherein: said first loop coil element and said second loop coil element so move while maintaining the facing state as to vary the square measure of the facing area in which said first coil plane and said second coil plane face each other; said first loop coil element includes: a first spreading part having a first coil line so disposed that the distance of opposing by said first coil line parallel to a first moving direction, widens in said first moving direction, in a direction normal to said first moving direction in which the movement so takes place that the square measure of said facing area increases relative to said second loop coil element in a direction parallel to said first plane; and a first coil crossing part in which a first coil line is so disposed as to cross a second spreading part, in an arrangement in which said first loop coil element and said second loop coil element are electromagnetically decoupled and the square measure of said facing area is at the minimum thereof; said second loop coil element includes: a second spreading part having a second coil line so disposed that the distance of opposing by said second coil line parallel to a second moving direction, widens in said second moving direction, in a direction normal to said second moving direction in which the movement so takes place that the square measure of said facing area increases relative to said first loop coil element in a direction parallel to said second plane. | 2008-09-25 |
20080231280 | MAGNETIC RESONANCE APPARATUS, METHOD AND AUXILLIARY COIL ELEMENT FOR MANIPULATION OF THE B1 FIELD - In a method and arrangement for local manipulation of a B | 2008-09-25 |
20080231281 | RF COIL ASSEMBLY AND METHOD FOR PRACTICING MAGNETIZATION TRANSFER ON MAGNETIC RESONANCE IMAGING AND SPECTROSCOPY SYSTEMS - An RF coil assembly for an MRI system includes a resonator formed by a cylindrical shield and pairs of opposing conductive legs disposed symmetrically around a central axis and extending the axial length of the shield. One set of conductive leg pairs is tuned to operate at the Larmor frequency of | 2008-09-25 |
20080231282 | On-coil switched mode amplifier for parallel transmission in MRI - Example systems, apparatus, circuits, and so on described herein concern parallel transmission in MRI. One example apparatus includes at least two field effect transistors (FETs) that are connected by a coil that includes an LC (inductance-capacitance) leg. The apparatus includes a controller that inputs a digital signal to the FETs to control the production of an output analog radio frequency (RF) signal. The LC leg is to selectively alter the output analog RF signal and the analog RF signal is used in parallel magnetic resonance imaging (MRI) transmission. | 2008-09-25 |
20080231283 | Multi-Frequency Cancellation of Dielectric Effect - Measurements made with an induction logging tool are responsive to formation conductivity and permittivity. The effect of permittivity can be substantially removed by multifrequency focusing. | 2008-09-25 |
20080231284 | Method and Device for Detdermining the Ageing of a Battery - Disclosed is a method for determining the ageing (SoH) of a battery ( | 2008-09-25 |
20080231285 | Trailer Lighting, Control and Signaling Circuits Tester - An electronic circuit tester is disclosed which is utilized for the testing and troubleshooting of the various lighting, control and signaling circuits required in the towing of a trailer, vehicle or other conveyance. The tester generally comprises an enclosure, which may be included as a part of a wiring harness connector, or separately attached to a wiring harness connector by means of electrical wiring. The testing circuit includes a plurality of input lines, logic means, and an alerting means. The testing circuits cause a distinct alert to be produced in response to each distinct test of the trailer device driving circuits of the vehicle. | 2008-09-25 |
20080231286 | WIRE ABNORMALITY DETECTING DEVICE - A sensor switch | 2008-09-25 |
20080231287 | EVALUATION BOARD AND FAILURE LOCATION DETECTION METHOD - An evaluation board, on which is mounted a chip to be evaluated is provided. Particularly, the evaluation board includes a monitoring window for monitoring a power supply part, a ground part, and a surface of the chip, a first signal input part for inputting signals to the chip, and a second signal input part for inputting signals to the chip, wherein the second signal input part is placed as to sandwich said monitoring window between itself and the first signal input part. | 2008-09-25 |
20080231288 | Semiconductor package having projected substrate - A semiconductor package includes a bare chip which has a plurality of external electrodes, a land grid array substrate having an edge, a first surface and a second surface. The first surface includes a first portion apart from the edge and a second portion adjacent to the edge. The first portion of the first surface mounts the bare chip and is covered with a resin to seal the bare chip with the resin. The first portion of the first surface and the second surface includes a non-sealed region which is not covered with the resin. A plurality of first electrodes are arranged on the non-sealed region and connected to the external electrodes and a plurality of second electrodes are arranged on the second surface and connected to the external electrodes. | 2008-09-25 |
20080231289 | CLAMPING APPARATUS AND A SYSTEM AND METHOD FOR DETECTING DEFECTS IN ELECTRICAL WIRING - A wire diagnostic clamp including a clamp body configured to receive multiple electrical wires is provided. The wire diagnostic clamp also includes a sensor disposed within the clamp body and being configured to detect a defect in the multiple electrical wires. The wire diagnostic clamp further includes a mounting component configured to mount the wire diagnostic clamp to a substrate. | 2008-09-25 |
20080231290 | Capacitive Position Sensor - A capacitive position sensor has a periodic array of electrodes which form capacitors between pairs of the electrodes. The location of a dielectric inhomogeneity in the vicinity of the sensor is determined by comparison of the relative change in the capacitance of the capacitors. The comparison may be carried out using a capacitive Wheatstone Bridge arrangement. The sensor configuration has the advantage that it is independent of the absolute value of the dielectric constant of the environment in which the sensor is located. | 2008-09-25 |
20080231291 | Capacitive Distance Sensing In Semiconductor Processing Tools - A sensor for sensing a gap between the sensor and an object of interest within a semiconductor processing chamber is provided. The sensor includes a housing, a power source inside the housing, wireless communication circuitry, a controller, measurement circuitry and a plurality of capacitive plate pairs. The controller and wireless communication circuitry are coupled to each other, and to the power source. The plurality of capacitive plate pairs are configured to form capacitors having a capacitance that varies with the gap. Measurement circuitry is coupled to the controller and to the plurality of capacitive plate pairs. The measurement circuitry is configured to measure the capacitance of the capacitive plate pairs and provide indications thereof to the controller. The controller is configured to provide an indication relative to the gap based, at least in part, upon the measured capacitances. | 2008-09-25 |
20080231292 | Device and Method for Capacitive Measurement by a Floating Bridge - A device for capacitive measurement by a floating bridge, including: a sensor module including at least one measuring electrode and at least one guard electrode arranged close to a target connected to a general earth, at least one integrated circuit for capacitive measurement, provided with a guard to which the guard electrode is connected, having an input connected to the measuring electrode, a guard connected to the reference earth of the integrated circuit, an excitation output connected to the general earth, a measurement output, and structure for supplying the integrated circuit for capacitive measurement in floating mode. | 2008-09-25 |
20080231293 | DEVICE AND METHOD FOR ELECTRICAL CONTACTING FOR TESTING SEMICONDUCTOR DEVICES - A device and method for electrical contacting for the testing of semiconductor devices is disclosed. One embodiment provides for the electrical connection of the semiconductor device with a test system, including devices for the contacting of connection pins or contact pads of the semiconductor device to be tested. The devices for the contacting of the connection pins or the contact pads of the semiconductor device to be tested include contact holders with at least one exchangeable contact tip. | 2008-09-25 |
20080231294 | STRUCTURAL HEALTH MONITORING CIRCUIT - A structural health monitoring circuit apparatus and method are based on electrical impedance variations of a piezoelectric patch, which is attached to a structure to be monitored. The circuit compares a known good sweep of frequency-impedance pairs with a contemporaneous sweep to generate an alarm when an error bound is exceeded. The impedance of the piezoelectric patch is determined though adjustment of a variable reactance in a bridge configuration. By suitable design of the bridge elements, the electrical impedance of the piezoelectric patch may be directly measured. A microprocessor controlled version of this device consumes less than 2 W of power, which may be further reduced by further large scale integration or reduction to a state machine on a programmable gate array. Ultimately, this device may give personnel warnings to aircraft, automobiles, bridges, elevated roads, buildings, or home structural failures. | 2008-09-25 |
20080231295 | DEVICE AND METHOD FOR ELECTRICAL CONTACTING SEMICONDUCTOR DEVICES FOR TESTING - A device and method are disclosed for electrical contacting of semiconductor devices for testing. One embodiment provides for testing semiconductor devices or integrated circuits, including a probe card with contact tips for the electrical contacting of the semiconductor devices. The electrical connection of at least one contact tip to the test system is adapted to be switched via a resistively switching memory cell. A resistively switching memory cell in the form of a nano switch is integrated in the electrical connection of the contact tip. | 2008-09-25 |
20080231296 | Test Apparatus for the Testing of Electronic Components - In the case of a test apparatus for testing electronic components which are present in an assembly, in particular in the form of strips, a slide-like contacting board supporting device ( | 2008-09-25 |
20080231297 | Method for calibrating semiconductor device tester - A method for calibrating a semiconductor device tester is disclosed. In accordance with method of the present invention, a timing is calibrated using a programmable delay device and calibration boards so as to remove a timing difference between channels and compensate a linearity of the programmable delay device for an adjustment of a timing by building and using a database of the round trip delay actually generated during the test. | 2008-09-25 |
20080231298 | INSPECTION APPARATUS AND METHOD - An inspection apparatus for inspecting electrical characteristics of an inspection target object includes a movable mounting table for mounting the inspection target object thereon, a probe card disposed above the mounting table, and one or more displacement sensors, provided at one or more location of the mounting table, each of the sensors measuring a distance between the mounting table and the probe card or a vicinity thereof. The inspection target object is brought into electrical contact with the probe card by overdriving the mounting table. | 2008-09-25 |
20080231299 | Vacuum chamber with two-stage longitudinal translation for circuit board testing - A circuit board tester that uses a dual-stage translation to bring a unit under test (UUT) into physical and electric contact first with a series of tall probes, then with a series of short probes. Initially, the UUT is mounted on a support plate, and spaced apart from both the tall and short probes. First, in order to perform a functional test on the UUT, a first vacuum stage is engaged, and atmospheric pressure translates the UUT longitudinally until contact is made with a first hard stop, defining a first position. At this first position, the UUT is in contact with a series of tall probes, and is spaced apart from a series of short probes. After a function test is performed, a second vacuum stage is engaged in addition to, and independent of, the first vacuum stage. Atmospheric pressure translates the UUT longitudinally until contact is made with a second hard stop, defining a second position. | 2008-09-25 |
20080231300 | METHOD FOR DETECTING TIP POSITION OF PROBE, ALIGNMENT METHOD, APPARATUS FOR DETECTING TIP POSITION OF PROBE AND PROBE APPARATUS - An probe tip position detecting method detects tip positions of a plurality of probes by using a tip position detecting device including a sensor unit for detecting tips of the probes and a movable contact body belonging to the sensor unit, the method used in inspecting electrical characteristics of an object to be inspected by bringing the object supported on a movable mounting table into electrical contact with the probes. The method includes a first step for moving the tip position detecting device by using the mounting table to thereby bring the contact the object into contact with the tips of the probes; a second step for further moving the mounting table to thereby move the contact body toward the sensor unit without causing elastic deformation to the probes; and a third step of determining a movement starting position of the contact body as the tip positions of the probes. | 2008-09-25 |
20080231301 | INSPECTION APPARATUS - An inspection apparatus includes a mounting table movable in X and Y directions and an alignment mechanism which performs an alignment of a target object placed on the mounting table. Further, the alignment mechanism includes an image pickup device which is movable in either one of the X and Y directions and is capable of being stopped at a desired position and a controller for performing a preliminary alignment of the target object by moving the image pickup device and the mounting table in respectively movable directions. | 2008-09-25 |
20080231302 | Wafer translator having metallization pattern providing high density interdigitated contact pads for component - A metallization pattern for a wafer translator provides a high density layout of interdigitated contact pads, suitable for component placement, along with larger contact pads suitable for connection to external equipment terminals. In another aspect, electrically conductive material may be added to, or removed from, the high density layout of interdigitated contact pads and larger contact pads to modify, or reconfigure, the electrical pathways of the wafer translator. | 2008-09-25 |
20080231303 | SEMICONDUCTOR DEVICE FOR ELECTRICAL CONTACTING SEMICONDUCTOR DEVICES - A semiconductor device with a number of contact pads for the electrical contacting of the semiconductor device is disclosed. A padding layer, which is manufactured of a hard material, is provided at least partially below an upper layer of the contact pads. | 2008-09-25 |
20080231304 | Apparatus and method for controlling temperature in a chuck system - An apparatus and method of controlling the temperature of a thermal chuck system are disclosed. The system includes a temperature controller which controls a temperature transition in a thermal chuck. The temperature controller comprises inputs that receive air and fluid from an air source and water source, respectively, and an output for alternately transferring the air and fluid in proportions to the thermal chuck. A time proportional controller generates the proportions by computing a proportion band in each of a plurality of control regions. The proportion bands are used by the temperature controller to manage the flow of air and fluid to the chuck such that a minimum undershoot of the temperature transition is realized. | 2008-09-25 |
20080231305 | CONTACT CARRIERS (TILES) FOR POPULATING LARGER SUBSTRATES WITH SPRING CONTACTS - An interconnection apparatus and a method of forming an interconnection apparatus. Contact structures are attached to or formed on a first substrate. The first substrate is attached to a second substrate, which is larger than the first substrate. Multiple such first substrates may be attached to the second substrate in order to create an array of contact structures. Each contact structure may be elongate and resilient and may comprise a core that is over coated with a material that imparts desired structural properties to the contact structure. | 2008-09-25 |
20080231306 | INTEGRATED CIRCUIT BURN-IN TEST SYSTEM AND ASSOCIATED METHODS - An integrated circuit burn-in test system includes an integrated circuit and a tester. The integrated circuit includes operating circuitry, a heater for heating the operating circuitry, and burn-in test circuitry for testing the operating circuitry while being heated. A package surrounds the operating circuitry, the heater and the burn-in test circuitry. The burn-in test circuitry causes the operating circuitry to operate and generate data related thereto. The tester receives data from the burn-in test circuitry. The heater may be configured within the package to heat at least one predetermined portion of the operating circuitry. | 2008-09-25 |
20080231307 | TESTING METHOD USING A SCALABLE PARAMETRIC MEASUREMENT MACRO - Disclosed are testing method embodiments in which, during post-manufacture testing, parametric measurements are taken from on-chip parametric measurement elements and used to optimize manufacturing in-line parametric control learning and/or to optimize product screening processes. Specifically, these post-manufacture parametric measurements can be used to disposition chips without shipping out non-conforming products, without discarding conforming products, and without requiring high cost functional tests. They can also be used to identify yield sensitivities to parametric variations from design and to provide feedback for manufacturing line improvements based on the yield sensitivities. Additionally, a historical database regarding the key parameters that are monitored at both the fabrication and post-fabrication levels can be used to predict future yield and, thereby, to preemptively improve the manufacturing line and/or also to update supply chain forecasts. | 2008-09-25 |
20080231308 | Sub-Sampling of Weakly-Driven Nodes - A method and apparatus for performing on-chip voltage sampling of a weakly-driven node of a semiconductor device are disclosed. In some embodiments, the node is a floating node or is capacitively-driven. In some embodiments, it is involved in proximity-based communication. Sampling the node may include isolating the signal to be sampled using a source-follower amplifier before passing it to the sampling circuit. Sampling the node may include biasing the node to a desired voltage using a leaky transistor or other biasing circuit. In some embodiments, the biasing circuit may also be used to calibrate the sampler by coupling one or more calibration voltages to the node in place of a biasing voltage and measuring the sampler output. The sampler may be suitable for sub-sampling high frequency signals to produce a time-expanded, lower frequency version of the signals. The output of the sampler may be a current communicated off-chip for testing. | 2008-09-25 |
20080231309 | PERFORMANCE BOARD AND COVER MEMBER - A performance board which is attached to a semiconductor test apparatus and on which devices under test are mounted is provided. The performance board includes: a substrate; sockets which are attached to the surface of the substrate and on which devices under test are mounted; and an adiathermic cover member attached to the rear surface of a region of the substrate on which the sockets are mounted. | 2008-09-25 |
20080231310 | FLEXIBLE ON CHIP TESTING CIRCUIT FOR I/O'S CHARACTERIZATION - The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules. | 2008-09-25 |
20080231311 | PHYSICALLY HIGHLY SECURE MULTI-CHIP ASSEMBLY - A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts. | 2008-09-25 |
20080231312 | Structure for modeling stress-induced degradation of conductive interconnects - A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via. | 2008-09-25 |
20080231313 | Semiconductor device - A semiconductor device according to the present invention includes an internal circuit executing a predetermined processing based on signal input from an external device, an output buffer driving line connected to an output terminal based on signal output from the internal circuit, a feedback line branched off from signal line in buffer transmitting data signal to an output stage circuit of the output buffer, and a delay test circuit connected to the feedback line. | 2008-09-25 |
20080231314 | Configurable IC Having A Routing Fabric With Storage Elements - Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC. | 2008-09-25 |
20080231315 | Configurable IC Having A Routing Fabric With Storage Elements - Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC. | 2008-09-25 |
20080231316 | Distributed memory in field-programmable gate array integrated circuit devices - Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA. | 2008-09-25 |
20080231317 | Staggered logic array block architecture - A staggered logic array block (LAB) architecture can be provided. An integrated circuit (IC) device can include a first group of LABs substantially aligned with each other, and a second group of LABs substantially aligned with each other and coupled to the first group of LABs by a plurality of horizontal and vertical conductors. The first group of LABs can be substantially offset from the second group of LABs in the IC layout. In an embodiment of the invention, the first and second groups of LABs can be columns of LABs, and the columns can be vertically offset from each other (e.g., by half the number of logic elements in each LAB). The offsetting can advantageously allow more LABs to be reached using a single routing channel, or without using any routing channel, thereby reducing communication latency and improving overall IC performance. | 2008-09-25 |
20080231318 | CONFIGURABLE IC HAVING A ROUTING FABRIC WITH STORAGE ELEMENTS - Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC. | 2008-09-25 |
20080231319 | DEDICATED INPUT/OUTPUT FIRST IN/FIRST OUT MODULE FOR A FIELD PROGRAMMABLE GATE ARRAY - A field programmable gate array architecture having a plurality of input/output pads. The architecture comprising: a plurality of logic clusters; a plurality of input/output clusters; a plurality of input/output buffers; a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; an input/output block controller programmably coupled to the plurality of dedicated input/output first-in/first-out memory blocks; and a routing interconnect architecture programmably coupling the logic clusters, input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters. | 2008-09-25 |
20080231320 | TRI-STATE CIRCUIT USING NANOTUBE SWITCHING ELEMENTS - Nanotube-based logic circuitry is disclosed. Tri-stating elements add an enable/disable function to the circuitry. The tri-stating elements may be provided by nanotube-based switching devices. In the disabled state, the outputs present a high impedance, i.e., are tri-stated, which state allows interconnection to a common bus or other shared communication lines. In embodiments wherein the components are non-volatile, the inverter state and the control state are maintained in the absence of power. Such an inverter may be used in conjunction with and in the absence of diodes, resistors and transistors or as part of or as a replacement to CMOS, biCMOS, bipolar and other transistor level technologies. | 2008-09-25 |
20080231321 | Drive circuit with a TOP level shifter for transmission of an input signal, and method for transmission - A TOP level switch for use in a drive circuit in power-electronic systems having a half-bridge circuit formed by two power switches, a first so-called TOP switch and a second so-called BOT switch, which are arranged connected in series. The TOP level shifter transmits an input signal from drive logic to a TOP driver. In this case, the TOP level shifter is designed as an arrangement of an UP and a DOWN level shifter path, as well as a downstream signal evaluation circuit. In the associated method for transmission of this input signal, the signal evaluation circuit passes an output signal to the TOP driver when either the UP or the DOWN, or both, level shifter paths emit a signal to the respectively associated input of the signal evaluation circuit. | 2008-09-25 |
20080231322 | Circuit Device and Method of Controlling a Voltage Swing - In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device including a capacitive node. The method also includes selectively activating a voltage level adjustment element to regulate an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node. In a particular illustrative embodiment, the received signal may be a clock signal. | 2008-09-25 |
20080231323 | INTEGRATED CIRCUIT CHIP WITH IMPROVED ARRAY STABILITY - A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage. | 2008-09-25 |
20080231324 | PHASE FREQUENCY DETECTOR AND PHASE-LOCKED LOOP - A phase frequency detector with two different delays is disclosed herein. The phase detector comprises a first D flip-flop, a second D flip-flop, a first delay unit and a second delay unit. The first D flip-flop receives a reference signal to output an up signal. The second D flip-flop receives a clock signal to output a down signal. The first delay unit delays the received signal with a first delay. The second delay unit delays the received signal with a second delay. When the reference signal synchronizes with the clock signal and the charge pump currents are calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the first delay, and when the reference signal does not synchronize with the clock signal and the charge pump currents are not calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the second delay. | 2008-09-25 |
20080231325 | METHOD FOR CHECKING THE INTEGRITY OF A CLOCK TREE - A method and device detect synchronization errors between logic signals of a group of logic signals. A control word is loaded into a shift register arranged in loop and clocked by resulting logic signals equal to the result of the OR logic function and to the result of the AND logic function applied to the logic signals of the group of logic signals. The value of the control word is monitored as it propagates in the shift register, and a synchronization error signal is sent if the control word changes value. Application in particular for checking the integrity of a clock tree in an integrated circuit. | 2008-09-25 |
20080231326 | SIGNAL CONDITIONING FOR AN OPTICAL ENCODER - An encoder with signal conditioning of an emitter drive signal is described. In one embodiment, the encoder includes a peak comparator, a pulse generator, a threshold comparator, and digital circuitry. The peak comparator outputs a peak comparator signal based on a comparison of an input sinusoidal signal stored at a first time with the input sinusoidal signal stored at a second time. The pulse generator determines a peak of the input sinusoidal signal based on the peak comparator signal. The threshold comparator compares a differential signal amplitude with a differential signal amplitude window at approximately the peak of the input sinusoidal signal. The differential signal amplitude is associated with the input sinusoidal signal. The digital circuitry generates an emitter modification signal in response to a determination that the differential signal amplitude is outside of the differential signal amplitude window. | 2008-09-25 |
20080231327 | SIGNAL TRANSFER SYSTEMS AND METHODS - A signal transfer system. A first device operates with a first voltage and outputs a first signal and a second signal. A protection circuit receives the first and second signals and outputs the first and second signals when the first voltage is greater than or equal to a predetermined voltage, and provides a third signal and a fourth signal when the first voltage is smaller than the predetermined voltage. A delay circuit delays the second and fourth signals to generate a first delay signal and a second delay signal, respectively. A second device operates with the first signal and the first delay signal when the first voltage is greater than or equal to the predetermined voltage, and operates with the third signal and the second delay signal when the first voltage is smaller than the predetermined voltage. | 2008-09-25 |
20080231328 | Method and Circuit for Local Clock Generation and Smartcard Including it Thereon - One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal φ( | 2008-09-25 |
20080231329 | DIFFERENTIAL SIGNAL OUTPUT CIRCUIT FOR TIMING CONTROLLER OF DISPLAY DEVICE - A differential-signal output circuit for a timing controller of a display device includes a conversion circuit, a pre-charging circuit and a timing generator. The conversion circuit is used for receiving a differential signal and outputting a current to a load circuit according to polarity of the differential signal. The pre-charging circuit is coupled to a first output end and a second output end of the conversion circuit or is coupled to a first power driving end and a power second driving end of the conversion circuit. The pre-charging circuit is used for pre-charging the load according to a control signal. The timing generator is used for generating the differential signal and a control signal according to display data. | 2008-09-25 |
20080231330 | RAMP GENERATOR AND CIRCUIT PATTERN INSPECTION APPARATUS USING THE SAME RAMP GENERATOR - The present invention provides a ramp generator capable of appropriately setting a rise starting point of an output voltage of a ramp waveform and an output voltage at the time of stable output. A current adjustment unit including a differential pair of transistors and an amplifier constitute a feedback circuit. By controlling the charging/discharging of an integration capacitor by ON/OFF of a discharge current source connected to a common emitter terminal of the current adjustment unit, an output of the ramp waveform outputted from an output terminal disposed at the connection end of the integration capacitor is controlled. | 2008-09-25 |
20080231331 | Spread spectrum clock generator - Disclosed are embodiments of methods and circuits to generate spread spectrum clocks. | 2008-09-25 |
20080231332 | Clock Signal Generation Device, Semiconductor Integrated Circuit, and Data Reproduction Method - The present invention improves a lead-in time of the PLL with a phase error detector having an enlarged range of phase error detection and gain control based on the PLL synchronous state. The phase error detection range is enlarged by correcting the phase error detection point in a case where the phase error increases. A locked state of the PLL is determined based on a standard deviation of the smoothed phase error values and the gains are switched between a lead-in transient state and a stationary state. As a result, it is possible to shorten and stabilize the lead-in time of the PLL. | 2008-09-25 |
20080231333 | Spread Spectrum Clock Generator - A spread spectrum clock generator is disclosed. The spread spectrum clock generator (SSCG) bases on the structure of the phase-lock loop. The SSCG uses the voltage control oscillator with multi-phase output function for outputting clock signals of different phases. The clock signals of different phases are selectively fed back to the phase frequency detector. In this way, the frequency of the output signal is changed, which achieves spreading spectrum. | 2008-09-25 |
20080231334 | CLOCK SIGNAL TRANSMISSION CIRCUIT - A clock signal transmission circuit having a variable initial value for a wait time that is required until a clock signal stabilizes. The clock signal is generated from an original clock signal. The wait time setting unit generates a plurality of wait time signals to wait until the original clock signal stabilizes before providing the clock signal to the internal circuit. A wait time determination unit selects one of the wait time signals and provides the selected wait time signal to a clock control unit. The wait time determination unit includes a data holding circuit which generates a selection signal in accordance with the initial value, a selection circuit which selects one of the wait time signals based on the selection circuit, and an initial value setting circuit enabling the initial value to be varied. | 2008-09-25 |
20080231335 | CIRCUIT TO REDUCE DUTY CYCLE DISTORTION - A method and a circuit for correcting duty cycle distortion. A delay insertion gate corrects data dependent delay distortion that is generated by CMOS flip-flop circuits. The delay insertion gate includes two field effect transistors and a current mirror. The two transistors each respectively receive an input signal from an upstream circuit. At least one of the transistors is coupled to an output node. The output node temporarily holds a voltage state within the delay insertion gate, correcting any distortion in the duty cycle of the input signals. | 2008-09-25 |
20080231336 | SCAN FLIP-FLOP CIRCUIT WITH EXTRA HOLD TIME MARGIN - The present invention is a scan flip-flop circuit with extra hold time margin. The scan flip-flop circuit includes a multiplexer, a sense amplifier and a latch. The latch includes a generation unit for generating an output signal in response to a first signal and a second signal outputted from the sense amplifier, and a storage unit receives the second signal and the output signal and maintains the output signal of the latch when the first signal and the second signal are non-activated. | 2008-09-25 |
20080231337 | Compact subnanosecond high voltage pulse generation system for cell electro-manipulation - Disclosed are methods and systems for subnanosecond rise time high voltage (HV) electric pulse delivery to biological loads. The system includes an imaging device and monitoring apparatus used for bio-photonic studies of pulse induced intracellular effects. The system further features custom fabricated microscope slide having micro-machined electrodes. A printed circuit board to interface the pulse generator to the micro-machined glass slide having the cell solution. An low-parasitic electronic setup to interface with avalanche transistor-switched pulse generation system. The pc-board and the slide are configured to match the output impedance of the pulse generator which minimizes reflection back into the pulse generator, and minimizes distortion of the pulse shape and pulse parameters. The pc-board further includes a high bandwidth voltage divider for real-time monitoring of pulses delivered to the cell solutions. | 2008-09-25 |
20080231338 | Converter systems having reduced-jitter, selectively-skewed interleaved clocks - Converter systems are disclosed that use particular combinations of fixed and variable clock skewers to generate interleaved clock signals for the systems. These combinations have been found effective in accurately generating selectively-skewed clocks while simultaneously restricting the jitter that generally accompanies the skewing process. | 2008-09-25 |
20080231339 | Double quench circuit for an avalanche current device - A double quench circuit for an avalanche current device is provided in which the circuit includes an avalanche current device having a first terminal responsive to a bias voltage to reverse bias the avalanche current device above its avalanche breakdown voltage. A first quench circuit is responsive to the bias voltage and coupled to the first terminal of the avalanche device for reducing the amount of the avalanche current passing through the avalanche device. A second quench circuit is coupled to a second terminal of the avalanche device for reducing the amount of the avalanche current passing through the avalanche device. | 2008-09-25 |
20080231340 | Level shift circuit - A level shift circuit includes a first capacitor circuit including capacitors connected in series between a ground and a predetermined potential, a first trigger circuit coupled to the predetermined potential side of the first capacitor circuit, an input terminal coupled to the ground side of the first capacitor circuit, a second capacitor circuit including capacitors connected in series between the ground and the predetermined potential, a second trigger circuit coupled to the predetermined potential side of the second capacitor circuit, an inverter coupled between the input terminal and the ground potential side of the second capacitor circuit, and a SR latch circuit having a first input coupled to an output of the first trigger circuit and a second input coupled to an output of the second trigger circuit. | 2008-09-25 |
20080231341 | OVER-VOLTAGE TOLERANT PASS-GATE - A pass-gate having a single or parallel opposite polarity FETs is disclosed. The wells of the primary transistor switches are driven from circuitry that reduces over-voltage leakage and other malfunctions. A circuit that drives the wells is also used to power enable circuits that drive the gates of the pass transistors. The use of separate circuits to the gate and the wells further reduces leakage. In the condition of power supply voltage and signal levels that are near the thresholds of the FETs involved, one or more Schottky diodes may be used across pn junctions in the FETs that will prevent turning on the pn junctions. | 2008-09-25 |
20080231342 | PROGRAMMABLE CALIBRATION CIRCUIT FOR POWER SUPPLY CURRENT SENSING AND DROOP LOSS COMPENSATION - A circuit for regulating power is disclosed. The present invention provides circuits and methods for current sensing variations, static droop settings, mismatched phase outputs, and temperature variations in a multiphase power regulator. The circuits may include a calibration controller that senses and regulates both a current sensing circuit and the droop in a power regulator over a range of temperatures thus equalizing phase outputs. The present invention includes the schematic organization and implementation of the circuit, the circuit's calibration, its use, and implementation. This invention advantageously provides circuits and methods to properly power a processor or IC chip according to the unique power specifications of the processor or chip. | 2008-09-25 |
20080231343 | Method and System for Vibration Sensing Power Management - The invention provides in one aspect a method for vibration sensing. The method comprises powering down at least one electronic component required for recording vibration data; powering down a processor used to carry out one or more steps of the method; measuring the vibration level of a machine in a frequency band of interest; comparing the measured vibration level with a user-selected reference vibration level; and powering up the processor if the measured vibration level is greater than or equal to the reference vibration level. In another aspect the invention provides a system for vibration sensing. | 2008-09-25 |
20080231344 | Power-diode driver having expansible isolated sub-drivers using single power source - A power-diode-driver uses a single power source to supply power to the sub-drivers inside. The sub-drivers are well isolated so that they can be safely and easily expanded by connecting to other device or driver. Thus, the power-diode driver has a changeable turn-on time and a highly modulated assembly. And, hence, the present invention is suitable for mass producing reliable power-diode drivers. | 2008-09-25 |
20080231345 | Silicon Wafer For Semiconductor With Powersupply System on the Backside of Wafer - Disclosed is a semiconductor silicon wafer having an electric power supply affixed to the backside of the wafer. By fabricating the electric power supply onto the backside of the wafer that has been left unused, the semiconductor chip can have a self-supplied power, realizing the self-powered semiconductor chip with an increased efficiency. Further, since the electric power supply is installed on the wafer, not the semiconductor chip, the fabrication procedure becomes very simple, and the battery can be mounted on any type of chip. | 2008-09-25 |
20080231346 | CHARGE PUMP CIRCUIT WITH DYNAMIC CURENT BIASING FOR PHASE LOCKED LOOP - A charge pump circuit includes a first PMOS transistor, a first NMOS transistor connected with the first PMOS transistor at a CPOUT node that is configured to provide an output signal from the charge pump circuit, and a second PMOS transistor connected between a high-voltage supply terminal (VDD) and the first PMOS transistor. The second PMOS transistor can provide a current IUP to the first PMOS transistor. A capacitor is connected to VDD and the gate of the second PMOS transistor. The charge pump circuit also includes an operational amplifier having its negative input and its output connected to the gate of the second PMOS transistor, and its positive input connected to the CPOUT node. | 2008-09-25 |
20080231347 | CHARGE PUMP CIRCUIT - A charge pump circuit including a plurality of switches and a switch control circuit is provided. The charge pump circuit is suitable for a display panel. The switches switch from “off” state to “on” state in an enable transition, and switch from “on” state to “off” state in a disable transition. The switch control circuit is coupled to the switches for controlling the on/off states of the switches and allowing the charge pump circuit to provide an output voltage that is different from an input voltage. The switch control circuit prolongs the time required for enable transition of the switches to be longer than the time for disable transition thereof. The equivalent impedances of the switches change from high values to low values when the switches are at the enable transition. | 2008-09-25 |
20080231348 | Circuit for fixing peak current of an inductor and method thereof - The circuit for fixing the peak current of an inductor includes an operating current, a ramp-type boost converter and a comparator. The magnitude of the operating current is proportional to that of the voltage source of the inductor. The ramp-type boost converter is connected to the operating current. One input end of the comparator is connected to a reference voltage, and the other end is connected to the output of the ramp-type boost converter. The output of the comparator is connected to the gate of a power transistor, which controls the turn-on time of the inductor. | 2008-09-25 |
20080231349 | SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR APPARATUS INTEGRALLY HAVING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a first power supply whose potential is controlled under control operation from an external control circuit, a second power supply whose potential is controlled under control operation from the external control circuit, and whose potential can be set independently of the first power supply, a first power-supply system comprising a circuit driven by the first power supply, a second power-supply system comprising a circuit driven by the second power supply, and a connecting circuit that performs connecting operation between a first high-potential line of the first power-supply system and a second high-potential line of the second power-supply system in response to a potential-matching signal indicating that the first power-supply system and the second power-supply system are operated by the same potential from the external control circuit. | 2008-09-25 |
20080231350 | Internal voltage generating circuit for use in a semiconductor device - An internal voltage generating circuit for use in a semiconductor memory device includes a reference voltage input terminal to receive a reference voltage, a comparison unit to output a first internal voltage, the first internal voltage having a voltage level based at least in part on the reference voltage, a first feedback unit to receive the first internal voltage and an external voltage and to provide a first feedback internal voltage to the comparison unit, a loading circuit to output a second internal voltage, and a second feedback unit to receive the second internal voltage from the loading circuit and to provide a second feedback internal voltage to the comparison unit. | 2008-09-25 |
20080231351 | VOLTAGE STEP-DOWN CIRCUIT - According to an aspect of the present invention, there is provided a voltage step-down circuit including: a first NMOS connected between an external and an internal power-supply voltages through a PMOS turned ON during an active state and turned OFF during a standby state; a second NMOS connected between the external and the internal power-supply voltages; and a current control circuit that sinks a current from the internal power-supply voltage to a ground level for a certain period of time after an operation state is switched from the active state to the standby state. | 2008-09-25 |
20080231352 | Adjusting PLL/analog supply to track CPU core supply through a voltage regulator - A processing device includes a Phase Locked Loop (PLL) system with an adjustable power supply designed to track the power supply provided to one or more of the cores in the processor device. The PLL no longer operates at a fixed voltage level that is held constant and independent from the requested core frequency or the core digital voltage, but rather the power supply to the phase locked loop is adjusted along with the main power supply to the processor core. | 2008-09-25 |
20080231353 | Ultra fast circuitry for digital filtering - The invention includes a novel differentiator cell, a novel resample unit cell, and precision synchronization circuitry to ensure proper timing of the circuits and systems at the anticipated ultra-high speed of operation. The novel differentiator cell includes circuitry for combining a carry input signal, a data bit signal and the output signal of a NOT cell and applying the signals as distinct and separate pulses to the input of a toggle flip-flop (TFF) for producing an asynchronous carry output and a clocked data output. The novel differentiator cells can be interconnected to form a multi-bit differentiator circuit using appropriate delay and synchronization circuitry to compensate for delays in producing the carry output of each cell which is applied to a succeeding cell. The novel resample cell includes a non-destructive reset-set flip-flop (RSN) designed to receive a data bit, at its set input, at a slow clock rate, which data is repeatedly read out of the RSN at a fast clock rate, until the RSN is reset. The novel differentiator and resampler cells can be interconnected, for example, to form the differentiator and up-sampling sections of a digital interpolation filter (DIF). Also, the relative clocking of bit slices (columns) in such a DIF may be achieved by using the fast clock signal to synchronize the slow clock which controls data entry. The circuits of the invention can be advantageously implemented with Josephson Junctions in rapid-single-flux-quantum (RSFQ) logic. | 2008-09-25 |
20080231354 | Semiconductor Device - The invention provides a semiconductor device that power is stabilized by suppressing power consumption as much as possible. The semiconductor device of the invention includes a logic portion and a memory portion each including a plurality of transistors, a detecting portion for detecting one or both of operation frequencies of the logic portion and the memory portion, a Vth control for supplying a Vth control signal to one or both of the logic portion and the memory portion, and an antenna. Each of the plurality of transistors has a first gate electrode which is input with a logic signal, a second gate electrode which is input with the Vth control signal, and a semiconductor film such that the second gate electrode, the semiconductor film, and the first gate electrode are provided in this order from the bottom. | 2008-09-25 |
20080231355 | Tuner and Demodulating Unit Thereof - A tuner and a demodulating unit thereof are provided. A trap filter for a specific frequency is installed in the IF demodulating unit so as to eliminate a frequency signal acting as a beat component. | 2008-09-25 |
20080231356 | Voltage margining with a low power, high speed, input offset cancelling equalizer - A switched-capacitor circuit that may be used for equalization, but configurable for voltage margining. The switched-capacitor circuit cancels the offset voltage inherent in an amplifier and sets the common mode of an input signal at half the rail voltage. Two capacitors level shift an input signal before being applied to the two input ports of an amplifier. When used for voltage margining, the input voltage swing is reduced at the input ports of the amplifier by connecting a digital-to-analog controlled voltage source to the two capacitors. | 2008-09-25 |
20080231357 | METHOD AND SYSTEM FOR GAIN CONTROL AND POWER SAVING IN BROADBAND FEEDBACK LOW-NOISE AMPLIFIERS - Methods and systems for gain control and power saving in broadband feedback low-noise amplifiers are disclosed and may include controlling gain, power and/or a noise figure by selectively enabling one or more of a plurality of gain stages by activating one or more of a plurality of pairs of switching transistors. Each of the gain stages may comprise complementary inverter pairs, with the gain of each of the gain stages binary weighted and stored in a lookup table. A feedback resistance coupled across the gain stages may be adjusted, and may comprise a plurality of individually addressable resistors, with the resistance binary weighted and stored in a lookup table. The adjusting of the feedback resistance may comprise switching one or more of a plurality of switching transistors, each connected in parallel with one of the individually addressable resistors, which may shunt one or more of the individually addressable resistors. | 2008-09-25 |
20080231358 | POWER AMPLIFIER CIRCUIT - In a third operation in an amplifier, in which first and second amplifier circuits amplify a input signal, a distribution circuit adjusts the power of the signal supplied to the first amplifier circuit to within a range in which the input power to the first amplifier circuit and the output power from the first amplifier are proportional to each other. In a linear operation, the power of the signal from the first amplifier circuit and input to the comparison circuit and the power of the signal from the second amplifier circuit and input to the comparison circuit are equal. The comparison circuit adjusts the gain or the saturated power of the second amplifier circuit on the basis of the difference between the signals from the first and second amplifier circuits and input to the comparison circuit, so that the input power to the second amplifier circuit and the output power from the second amplifier circuit are proportional to each other. | 2008-09-25 |
20080231359 | POWER DIVIDER/COMBINER AND POWER DIVIDING/COMBINING METHOD USING THE SAME - A power divider/combiner include a power n-dividing unit for dividing a power of an input signal to n divided signals (n: positive integer not less than 2); n phase adjustment units for adjusting a phase of each of said n divided signals; n amplifiers for amplifying each of said n divided signals after phase adjustment by said n phase adjustment units; and power combining units for combining said n divided signals amplified by said n amplifiers and outputting a power combined signal. | 2008-09-25 |
20080231360 | ARRANGEMENT OF SIGNAL LINE PAIRS AND AMPLIFIERS - An arrangement of signal line pairs and amplifiers is disclosed. One embodiment provides each signal line pair of a group of signal line pairs that are directly adjacent and run parallel to one another is respectively assigned an amplifier from a group of amplifiers arranged successively in a signal line direction. Each signal line pair includes a first and a second signal line, between which the amplifier assigned to the respective signal line pair is arranged. The position of an amplifier is assigned to a specific signal line pair in the amplifier group along the signal line direction is chosen in such a way that a first coupling section which forms the first signal line assigned to the respective amplifier together with its adjacent lines along the amplifier group, and a second coupling section, which forms the second signal line assigned to the respective amplifier together with its adjacent lines along the amplifier group, substantially have the same coupling properties. | 2008-09-25 |
20080231361 | MOLECULAR TRANSISTOR CIRCUITS COMPATIBLE WITH CARBON NANOTUBE SENSORS AND TRANSDUCERS - Small-signal and other circuit design techniques realized by carbon nanotube field-effect transistors (CNFETs) to create analog electronics for analog signal handling, analog signal processing, and conversions between analog signals and digital signals. As the CNFETs exist and operate at nanoscale, they can be readily collocated or integrated into carbon nanotube sensing and transducing systems. Such collocation and integration is at, or adequately near, nanoscale. | 2008-09-25 |
20080231362 | LINEAR TRANSCONDUCTOR FOR RF COMMUNICATIONS - The present patent application comprises a linear transconductor having at least one input and at least one output, comprising a differential amplifier having a plurality of transistors and a plurality of inputs, wherein a difference of input signals is amplified, a cascode circuit having a plurality of transistors, wherein the transistors are operably connected to the differential amplifier, wherein reverse isolation between an input and an output of the linear transconductor is improved by decoupling the input and the output of the linear transconductor by mounting at least one transistor of the plurality of transistors of the cascode circuit as a common-gate stacked on the at least one transistor of the differential amplifier, an active load having a plurality of transistors operably connected between the cascode circuit and supply voltage, and an auxiliary device operably connected to the connection between the active load, the cascode device and ground. | 2008-09-25 |
20080231363 | Temperature compensation of small signal gain of an amplifier stage - The invention relates to an differential amplifier circuit comprising an amplifier stage comprising a first and a second transistor, the gates of which are connected to differential input terminals of the amplifier stage. The differential amplifier further comprises a temperature compensation circuit comprising a third and fourth transistor. The third transistor is connected to the source of the first transistor and the fourth transistor is connected to the source of the second transistor. Further, the temperature compensation circuit comprises a constant current source connected to the respective sources of the third and fourth transistors. Thereby the temperature compensation circuit is arranged to provide a feedback resistance in dependence on the operating temperature so as to compensate for variations of the resistance of the first and second transistors. | 2008-09-25 |
20080231364 | AMPLIFYING CIRCUIT HAVING A PULL-UP CIRCUIT AND A PULL-DOWN CIRCUIT FOR INCREASING SLEW RATE - An amplifying circuit includes an operational amplifier, a pull-up circuit and a pull-down circuit. The operational amplifier generates a first pull-up signal, a first pull-down signal and an output signal, wherein the phases of the first pull-up signal and the first pull-down signal are out of phase with the output signal. The pull-up circuit includes a first controlling module for outputting a second pull-up signal according to the first pull-up signal, and a first adjusting module for adjusting the output signal according to the second pull-up signal. The pull-down circuit includes a second controlling module for outputting a second pull-down signal according to the first pull-down signal, and a second adjusting module for adjusting the output signal according to the second pull-down signal. | 2008-09-25 |
20080231365 | OPERATIONAL AMPLIFIER - An operational amplifier including an input amplifier configured to amplify at least one differential input signal, a first common mode feedback amplifier configured to amplify a first common mode voltage, a cascode amplifier configured to cascode-amplify output signals from the input amplifier and the first common mode feedback amplifier, a first common mode voltage generator configured to generate a central voltage of the output signal from the cascode amplifier and input the central voltage to the first common mode feedback amplifier, and a frequency compensator configured to feedback the output signal of the cascode amplifier to the first common mode feedback amplifier so as to compensate a frequency of the first common mode feedback amplifier. | 2008-09-25 |
20080231366 | Method and System for a Low Noise Amplifier with Tolerance to Large Inputs - Methods and systems for a low noise amplifier with tolerance to large inputs are disclosed. Aspects of one method may include providing an individual current source for each input transistor to a low noise amplifier (LNA), wherein the individual current sources may be isolated from each other when the LNA is turned off. The individual current sources may also form a common current source for the input transistors when the LNA is turned on. Accordingly, the input transistors to the LNA may float when the LNA is turned off, thereby coupling the input signal voltage to the source and drain terminals. The individual current sources may be isolated from each other by a coupling transistor that is turned off. When the LNA is turned on, the coupling transistor may be turned on to couple the individual current sources to each other to form the common current source for the input transistors. | 2008-09-25 |
20080231367 | Amplifier - An amplifier according to the present invention includes an amplifying transistor, and an impedance converter circuit coupled to an output unit of the amplifying transistor and including a plurality of impedance converting transistors different in input impedance, which are series-connected. | 2008-09-25 |
20080231368 | WIRELESS FREQUENCY POWER AMPLIFIER, SEMICONDUCTOR DEVICE, AND WIRELESS FREQUENCY POWER AMPLIFICATION METHOD - A differential amplifier circuit is connected to the input node and the output node of the final amplification stage through detection circuits. The signal level difference output from the differential amplifier circuit does not change even if the input power varies. Because a change in the power gain at the output node does not travel back to the input node when the load impedance of the wireless frequency power amplifier varies, it is possible to detect only the change in the load impedance. Damage to the final stage can be prevented by controlling the operating current of the final stage and the gain of the drive stage according to the detected load variation. Nonlinear distortion in the wireless frequency power amplifier output can also be reduced by detecting and canceling the change in the gain of the drive stage by changing the gain of the adjustment stage. | 2008-09-25 |
20080231369 | VARIABLE-GAIN LOW-NOISE AMPLIFIER - A variable-gain low-noise amplifier is provided. The variable-gain low-noise amplifier includes a first load, a second load, an input transistor, a pole/zero control circuit, and a gain control circuit. A first terminal of the first load is connected to a power-source voltage, and a second terminal thereof is connected to an output terminal. The second load is operated in response to a bias voltage, and a first terminal thereof is connected to the output terminal. A first terminal of the input transistor is connected to the second terminal of the second load, and a gate thereof is connected to an input terminal. The pole/zero control circuit adjusts frequency characteristics and a gain in response to at least one pole/zero control signal. A first terminal of the pole/zero control circuit is connected to the input terminal, and a second terminal thereof is connected to the output terminal. The gain control circuit adjusts the gain in response to at least one gain control signal. A first terminal of the gain control circuit is connected to a common terminal of the second load and the input transistor, and a second terminal thereof is connected to the input terminal, and a third terminal thereof of is connected to a ground voltage. | 2008-09-25 |
20080231370 | Apparatus and methods for amplifiers - Circuits and methods for reducing distortion in an amplified signal are disclosed. The circuits and methods may use multiple single-ended gain stages to produce multiple amplified signals. The amplified signals may be processed in combination to produce a resulting output signal having little, or no, distortion. The circuits may be implemented on a single chip as integrated circuits. | 2008-09-25 |
20080231371 | Amplifier Circuit With Adjustable Amplification - An amplifier circuit has an amplifier element having an amplifier element input and an amplifier element input impedance, an amplification adjuster adapted to adjust an amplification of the amplifier element, an amplifier circuit input coupled to the amplifier element input, an impedance element having a alterable impedance value and being coupled to the amplifier circuit input, and an impedance adjuster adapted to adjust the impedance value of the impedance element as a function of the amplification of the amplifier element. | 2008-09-25 |
20080231372 | DYNAMIC BIASING AMPLIFIER APPARATUS, DYNAMIC BIASING APPARATUS AND METHOD - A dynamic biasing amplifier apparatus, and dynamic biasing apparatus, and method are disclosed. The dynamic biasing amplifier apparatus includes a comparator unit, a dynamic bias generator unit, and an amplifier unit. The amplifier unit receives an input signal and output an output signal based on at least a bias voltage. The comparator unit compares the positive and negative input signals of the amplifier unit. The dynamic bias generator unit generates and adjusts the bias voltage in accordance with the comparing result of the comparator unit. Therefore, the dynamic bias generator unit controls the amplifier unit to operate in a low static current mode when the input signal is in steady state; and the dynamic bias generator unit controls the amplifier unit to operate in a high dynamic current mode when the input signal is in transition state. | 2008-09-25 |
20080231373 | Output Circuit - One embodiment of the invention provides an output circuit for a transistor. The output circuit includes a first capacitor coupled between ground and a drain electrode of the transistor via a first bond wire and a second bond wire coupling which couples a node between said first bond wire coupling and said first capacitor with ground via a second capacitor. | 2008-09-25 |
20080231374 | POWER EFFICIENT MULTISTAGE AMPLIFIER AND DESIGN METHOD - A multistage amplifier and design method are disclosed. The multistage amplifier has a plurality of amplifier stages, each stage having an amplifier designed and biased to operate at or near the amplifier's power added efficiency (PAE) peak. The PAE peak of each of the amplifier is at or near the amplifiers linear-compression transition region, providing a multistage power amplifier that is power efficient and has desirable amplitude to amplitude and amplitude to phase power transfer characteristics. The amplifier is designed by matching the output impedance of a final stage with a load. Amplifier stages are iteratively designed from the last stage to the first. At each stage, an amplifier and drive circuit are designed. The drive circuit and amplifier are designed to provide each stage with output impedance matched to the input impedance of the following stage and to operate at or near the PAE peak of the amplifier. | 2008-09-25 |
20080231375 | METHOD AND SYSTEM FOR USING A FREQUENCY LOCKED LOOP LOGEN IN OSCILLATOR SYSTEMS - Aspects of a method and system for using a frequency locked loop LOGEN in oscillator systems may include generating an oscillating signal via one or more circuits comprising a feedback loop. The generation may be controlled by enabling or disabling the feedback loop, based on the generated oscillating signal. The one or more circuits may comprise a frequency-locked loop (FLL) that may enable the generation of the oscillating signal. The frequency-locked loop may comprise a voltage-controlled oscillator. The feedback loop may be disabled when an estimated frequency difference between a reference signal and a feedback signal may be less than or equal to a specified threshold. The feedback loop may be enabled when an estimated frequency difference between a reference signal and a feedback signal may be greater than a particular threshold. | 2008-09-25 |