39th week of 2008 patent applcation highlights part 60 |
Patent application number | Title | Published |
20080235381 | MESSAGE RELAYING APPARATUS, COMMUNICATION ESTABLISHING METHOD, AND COMPUTER PROGRAM PRODUCT - A storage unit of a relaying apparatus stores first identification information that identifies an SIP terminal and second identification that identifies other SIP terminal which is forecast as a transfer destination of a message. A transmitting-and-receiving unit receives from the SIP terminal a request message that is received before a transfer message to be transferred to other SIP terminal and that includes a processing request concerning communications and the first identification information. An obtaining unit obtains from a storage unit the second identification information corresponding to the first identification information included in the received request message. A connection establishing unit establishes communications between the other SIP terminal of the obtained second identification information and the relaying apparatus. | 2008-09-25 |
20080235382 | FAULT TOLERANT TCP SPLICE SYSTEMS AND METHODS - Computer architecture and method splice a new TCP connection. A proxy group for the new TCP connection is determined and, at one of the proxies, the new TCP connection is accepted. At the one proxy, a client request is received from a client of the new TCP connection and an appropriate backend server to handle the client request is determined. At the one proxy, the client request is spliced and sent to the appropriate backend server. Splicing state information of the new TCP connection is sent from the one proxy to other proxies of the proxy group. Each subsequent TCP segment of the new TCP connection is spliced and sent to the appropriate backend server at any one proxy of the proxy group. | 2008-09-25 |
20080235383 | Methods, Systems, Products, And Devices For Generating And Processing DNS Friendly Identifiers - When a request having a keyword is received, a domain name having the keyword can be generated and a network resource corresponding to the domain name can be requested wherein the network resource is adapted to extract the keyword from the domain name. In turn, when a request having a first domain name is received, a second domain name having the first domain name can be generated and a network resource corresponding to the second domain name can be requested wherein the network resource is adapted to extract the first domain name from the second domain name. | 2008-09-25 |
20080235384 | Web service for coordinating actions of clients - Architecture for providing communications resources of a network for client intercommunications. A client that desires to communicate makes a request to an arbitrary communications server node by the announcing of identifying information. The web service “parks” the request until the identifying information is ready. A second client can ultimately interact with the first client by sending identifying information and following the same lookup path to find the location at which the first client request is “parked”. A continuous hash is employed that enables a client to negotiate services of a resource and via which resource multiple clients can rendezvous for communications. The continuous hash minimizes the disruption to clients already accessing network resources. A resource is brought online or taken offline without dramatically impacting ongoing use of currently operational resources. In the event a hosting resource fails, the clients repeat the lookup process and re-converge on a new server. | 2008-09-25 |
20080235385 | Selective use of anonymous proxies - A method and apparatus for selectively using an anonymous proxy. A user request for content is received. A determination is made as to whether the user request satisfies context criteria. When the user request satisfies the context criteria, the user request is forwarded to an anonymous proxy. When the user request does not satisfy the context criteria, the request is sent directly to a content provider. | 2008-09-25 |
20080235386 | Techniques for Updating Security-Related Parameters for Mobile Stations - A method is performed on a first server for communicating with a mobile station in order for the mobile station to update a security-related parameter. The method includes determining that a request expressed in a first protocol has been made by a second server for updating the security-related parameter on the mobile station. In response to the determination, the request is packaged in a message expressed in a second protocol and is communicated to the mobile station. Another method is disclosed that is performed on a mobile station for updating a security-related parameter. The method includes receiving a message that is expressed in a first protocol from a server and that includes a request for the mobile station to update the security-related parameter. The request is expressed in a second protocol. In response to the message, at least one operation is performed in order to update the security-related parameter. | 2008-09-25 |
20080235387 | Method and Apparatus for the Dynamic Introduction of New Attributes into Policies - In one aspect this invention provides a computer program embodied on a computer readable medium that is executed by at least one data processor of a policy management system. The computer program includes first computer program instructions for implementing a user interface and second computer program instructions for implementing a policy manager that is coupled to the user interface via a policy repository for introducing a new attribute, using the first computer program instructions, into a policy for a policy-managed system, without requiring a change to (e.g., without having to re-write or re-compile) the second computer program instructions. | 2008-09-25 |
20080235388 | METHOD AND APPARATUS TO DETERMINE HARDWARE AND SOFTWARE COMPATIBILITY RELATED TO MOBILITY OF VIRTUAL SERVERS - A method and system for determining hardware and software compatibility related to mobility of virtual servers. Upon receiving an inventory of properties of a managed server which are relevant for compatibility testing, mandatory and optional properties available for use in a compatibility policy for a WPAR instance running on the managed server are defined. Mandatory compatibility tests are selected based on the mandatory properties in the compatibility policy for the WPAR instance. Optional compatibility tests are selected based on the optional properties in the compatibility policy for the WPAR instance. The selected mandatory and optional compatibility tests are associated with the compatibility policy, wherein the selected tests are executed to compare a profile of a potential target system with the WPAR instance and to determine compatibility of the potential target system with the WPAR instance prior to performing a mobility operation of the WPAR instance. | 2008-09-25 |
20080235389 | Method of transmitting data in a communication system - A method of transmitting data from a first node to a second node in a communication network includes receiving a signal; dividing the signal into data elements arranged in a first data stream comprising active and inactive data elements; analysing at least one characteristic of the signal to determine if the signal is stable; dropping at least one active data element from a plurality of data elements of the first data stream if it is determined that the portion of the signal included in the plurality of data elements is stable; inputting the data elements that are not dropped from the first data stream into a core stream; and transmitting the core stream from the first node to the second node. | 2008-09-25 |
20080235390 | Moving Image Displaying Method and System - In order to overcome a difficulty in which, when a moving image played back by an operated-side computer is displayed on an operating-side computer through a network, a smooth moving image cannot be displayed because of being adversely influenced by the variation of a transfer data amount or a network bandwidth, a moving image displaying method and system are arranged to capture moving image playback event information being remotely operated and convey the information about the playback of the moving image on the operated-side computer to the operating-side computer. The operating-side computer provides a function of obtaining and receiving the moving image data played back on the event information, playing back the display image from the obtained moving image data, and overlapping the display image with the remote operation view. | 2008-09-25 |
20080235391 | Method and apparatus for transferring files to clients using a peer-to-peer file transfer model and a client-server transfer model - A method and apparatus is provided for delivering a content file to a client over a packet-switched network. The method begins by determining a suitable throughput required to deliver the content file to the client. Next, the throughput available in a peer-to-peer network for delivering the content file to the client is determined. The required throughput is compared to the available throughput. If the available throughput is less than the required throughput, the available throughput is supplemented with additional throughput. The content is then delivered to the client over the packet-switched network using the available throughput of the peer-to-peer network and the additional throughput. | 2008-09-25 |
20080235392 | Network file system - A method in one embodiment is performed at least in part at a server in a network file system that includes said server and a plurality of clients connected by a network, the method comprising: receiving a data write request from one client; selecting a client as a write object of said data from the other clients according to a condition of said one client stored in advance and/or conditions of said other clients; and transmitting said data write request to the client selected as a write object. Additional systems, methods and computer program products are also presented. | 2008-09-25 |
20080235393 | Framework for corrrelating content on a local network with information on an external network - A correlation system and method implement a framework for correlating content available from a local network with information on an external network. The system identifies information related to content available on the local network of interest to the user and also identifies one or more external sources that contain such related information. Then the system extracts data related to the identified information from the external sources, and determines correlations between the identified information and the data extracted from the external network. | 2008-09-25 |
20080235394 | Secure Document Management System - A method of uploading documents to a secure electronic document storage system includes receiving a request from a user for an upload of at least one document to a secure electronic document storage system. A routing document is generated including routing information related to the secure electronic document storage system. The routing document is transmitted to the user. The secure electronic document storage system receives a facsimile transmission from the user, wherein the facsimile transmission includes the routing document and at least one other document. The at least one document is routed to the secure electronic document storage system, based on the routing information contained in the routing document. | 2008-09-25 |
20080235395 | MEDICAL IMAGE TRANSFER CONTROL APPARATUS AND METHOD, AND MEDICAL IMAGE TRANSFER SYSTEM - A medical image transfer system consists of a plurality of transfer servers for transferring individually a medical image from a modality to an image server, and a control server for controlling the transfer servers. The transfer server sends information tagged to the medical image to the control server, to inquire about a destination of the medical image and an editorial process to be executed on the tagged information to adapt it to the destination. The control sever determines one of the image servers as the destination on the basis of the tagged information as received from the transfer server, and notifies of the destination and the editorial process necessary for the destination as a response to the inquiry. The transfer server executes the assigned editorial process on the tagged information and then transfers the medical image with the processed tagged information to the assigned destination. | 2008-09-25 |
20080235396 | Method and system for processing a service request associated with a particular priority level of service in a network data processing system using parallel proxies - A proxy server is provided with a plurality of prioritized proxies configured in parallel. The proxy server can include 1-to-n proxy subunits, where “n” can vary depending on the total priority levels available for any given system. Each service (e.g., document-handling) request made to the proxy server is prioritized according to the prioritized proxy subunit that is configured to service the request, which increases the request handling response times for the higher priority requests, and thus, improves the overall performance of the proxy server involved. | 2008-09-25 |
20080235397 | Systems and Methods for Content-Aware Load Balancing - Improved load balancing techniques are disclosed. For example, in one illustrative aspect of the invention, a method of satisfying requests in a system comprised of a plurality of servers comprises the following steps. At least one load balancer is provided for routing requests to the plurality of servers. At the at least one load balancer, a request sent from a client is obtained. At the at least one load balancer, the request is examined. Costs of satisfying the request by at least two of the plurality of servers are estimated. The estimation is based on at least one of a number and a cost of at least one remote access for satisfying the request. The request is routed to a server of the plurality of servers with a low estimated cost of satisfying the request. | 2008-09-25 |
20080235398 | Method For Coordination of Concurrent Processes or for Control of the Transport of Mobile Units Within a Network - A method for coordination of concurrent processes or for control of the transport of mobile units within a network, wherein a) the control of the network occurs in a decentralized and self-organizing manner in the controllers of node points or local defined sub-networks, whereby the control units of adjacent node points or sub-networks are connected to each other for data exchange of, b1) data from prediction models for local process sequences at each node and/or data from prediction models for the local process sequences of adjacent nodes and/or b2) data from data recording elements of each node or the boundaries associated therewith and/or data from data recording elements of adjacent nodes or the boundaries associated therewith, c) local simulation and optimization of switching the controller to establish the performance of the nodes or sub-networks with regard to the buffer capacity of the boundaries based on models for short-term predictions with fixed switch states for adjacent nodes, are applied. | 2008-09-25 |
20080235399 | Information Processing Device, Server, Communication System, Address Decision Method, Address Modification Method, and Program - A first information processing device ( | 2008-09-25 |
20080235400 | CONTENT REQUEST ROUTING AND LOAD BALANCING FOR CONTENT DISTRIBUTION NETWORKS - A content distribution mechanism that distributes content of a content provider at various sites across a network and selects the site that is nearest a content requestor using an anycast address that resides at each of the sites. The sites are configured as nodes (or clusters) and each node includes a content server and a DNS server. The DNS servers are so associated with the content servers at their respective nodes as to resolve the name of the content provider to the IP address of the content servers at the nodes. The DNS servers each are assigned the anycast address in addition to a unique address, and the anycast address is advertised to the network (in particular, the network routing infrastructure) using Border Gateway Protocol (BGP). Node selection occurs when the network routing infrastructure selects a shortest path to the anycast address during DNS name resolution. | 2008-09-25 |
20080235401 | Method of storing media data delivered through a network - There are various methods to stream media data, particularly video data, through a network for playing on a client workstation, for example, WMV™, Real™ Video, and so on. If multiple formats are involved, it is difficult to store the media data, and streaming the stored data whenever required. Further, existing devices are not able to record digital AV content from IP network, DVB, or AV encoder. The current invention provides a method of storing media data delivered to a client, for example via the internet. The media data can be encoded more than one format. The format of the media data is first identified when the media data is received by the client, and then analyzed to extract unit attributes from the media data. The unit attributes are stored in a media attribute file. The media data is then stored to a media storage file according to the sequence of the media data sent to the client. The media data stored by the methods of this invention can then be played by a player software. | 2008-09-25 |
20080235402 | System and Method for Bi-Directional Synchronized Conversion of Electronic Mail Data - A portable storage device is connected to a first computer and the email data is synchronized between the first computer and the device. The portable storage device can then be connected to a second computer that has an email program that is incompatible with the first computer's email program. The second computer is personalized with the email data retrieved from the portable device. The user is allowed to use the second computer to send or receive emails and otherwise alter the email data. Upon logging out of the second computer, any changes made thereon can be recorded to the portable storage device. The device can then be re-connected to the first computer and the data can once again be re-synchronized. The universal format database enables bidirectional synchronization and conversion of email data between multiple incompatible format email programs. | 2008-09-25 |
20080235403 | System, method, and device to wirelessly communicate multimedia timeline data - Systems, methods, and devices to provide to wirelessly communicate multimedia timeline data are disclosed. A first wireless network may be provided to communicate data associated with a multimedia timeline between a multimedia device and a second network. A request that identifies a multimedia timeline may be received from the multimedia device via the first wireless network. The request may be sent to a timeline server via the second network. | 2008-09-25 |
20080235404 | STORAGE APPARATUS AND DATA TRANSFER METHOD THEREOF - A storage apparatus automates a mapping operation and can automatically perform online data transfer from a storage unit of a data transfer source between a plurality of storage units. It includes a data transfer means for acquiring the construction information of the second storage in a first storage apparatus before a second storage unit is connected to a communication port for external connection, providing a storage device for performing data migrates from the second storage unit to a first storage control unit on the basis of the acquired construction information of the second storage unit, and performing mapping of the storage device in the second storage unit and data transfer from the second storage unit to the first storage control unit, with respect to an external connection function and an online data transfer function, after the second storage unit is connected to the external connection port. | 2008-09-25 |
20080235405 | USB controller and a testing method of the USB controller - A USB controller and a testing method of the USB controller are disclosed. The USB controller includes | 2008-09-25 |
20080235406 | System and method for upgrading the functionality of a controlling device in a secure manner - Secure access to a database of upgrade data is provided by storing an encryption key value in a cable used to interconnect a first device and a second device that is associated with the database of upgrade data. The second device allows access to the database of upgrade data via the cable only when the cable is first positively authenticated by the second device through use of the encryption key value stored in the cable. | 2008-09-25 |
20080235407 | SYSTEM FOR AUTOMATICALLY DETERMINING I/O CONNECTOR CONFIGURATION - A system for automatically determining a configuration of an I/O connector panel is disclosed. The system provides information about the capabilities of the connector card to a memory within the connector card, examining the information in the memory. The system further downloads at least one driver to a system coupled to the I/O connector panel based upon the examined information. The I/O capabilities of a platform (as determined by an I/O panel or other hardware that contains some identification mechanism that defines the I/O capabilities) is within the connector card. This mechanism is then used to determine what software to “preload” into a system so that as new I/O devices are added in the field, the required software for these devices has already been preloaded. | 2008-09-25 |
20080235408 | Computer Readable Medium Recording an Information Providing Program, Information Providing Device, and Method for Providing Information - The present invention provides a computer readable medium recording a program for providing information relating to an optional device installable on an apparatus such as a printer, the program being an information providing program for providing information, to a user in an easily understandable form, related to an installable optional device that is presently uninstalled. In the information providing program for causing an information providing device to execute a processing of providing information relating to an optional device installable on a target apparatus, the information providing device is caused to execute: acquiring information relating to the installation status of the optional device on the target apparatus and determining an uninstalled optional device, which is an installable optional device that has not been installed; and displaying an image representing the determined uninstalled optional device to a user. | 2008-09-25 |
20080235409 | Multiple Phase Buffer Enlargement for Rdma Data Transfer Related Applications - Methods of provisioning remote direct memory access (RDMA) buffers are disclosed. In one aspect, a method may include determining that a pre-registered RDMA buffer has insufficient size to transfer a particular data. A larger RDMA buffer, which is larger than the pre-registered RDMA buffer, may then be provisioned. Then, the data may be transferred to a potentially remote node over a network using the provisioned larger RDMA buffer. Other methods, including methods of receiving data, are also disclosed. Apparatus and system to implement such methods are also disclosed. | 2008-09-25 |
20080235410 | Usb-Sd Memory Device Having Dma Channels and Method of Storing Data in Usb-Sd Memory Device - Disclosed is a memory device having Universal Serial Bus (USB) interface and Secure Digital (SD) card interface, including: a plurality of flash memory units; a plurality of flash memory controllers each controlling reading and writing data on the flash memory unit; a Direct Memory Access (DMA) controller including a plurality of DMA channels each transmitting/receiving data to/from the flash memory unit in DMA mode; a Micom dividing a signal received from the USB interface and the SD card interface into data and an address and transmitting the data to the DMA controller; and an address decoder calculating positions of the received data to be written or read on the flash memory unit according to the address. | 2008-09-25 |
20080235411 | Peripheral Interface, Receiving Apparatus and Data Communication Method Using the Same - Peripheral interface(s), a receiving apparatus and a data communication method using the same are disclosed. According to an embodiment of the present invention, a peripheral interface comprises one or more pins for multiplexing at least two types of interfaces, wherein the pins transmit interface signals corresponding to an interface type and type-associated operating mode which are selected from those multiplexed by the pins. According to another embodiment, a receiving apparatus comprises: a peripheral interface for multiplexing at least two types of interfaces; a receiving module for receiving an instruction signal; a selecting module for selecting an interface type and type-associated operating mode which corresponds to an external device to be connected, based on the instruction signal; a controlling module for controlling the peripheral interface to communicate with the external device via at least one interface signal corresponding to the selected interface type and type-associated operating mode. | 2008-09-25 |
20080235412 | MEMORY CONTROLLER WITH BI-DIRECTIONAL BUFFER FOR ACHIEVING HIGH SPEED CAPABILITY AND RELATED METHOD THEREOF - A memory controller for accessing a serial Flash memory is disclosed. The memory controller includes a logic circuit; a bi-directional buffer, coupled to the logic circuit, for selectively reversing the direction of data flow according to a control signal generated from the logic circuit, the bi-directional buffer comprising: an input port, coupled to a data output port of the logic circuit; a control port, coupled to the logic circuit, for receiving the control signal; and an output port, coupled to a data input port of the logic circuit, the output port being utilized for coupling both an input data port and an output data port of the serial Flash memory. | 2008-09-25 |
20080235413 | Apparatus and Method to Maximize Buffer Utilization in an I/O Controller - An apparatus and method for maximizing buffer utilization in an I/O controller using credit management logic contained within the I/O controller. The credit management logic keeps track of the number of memory credits available in the I/O controller and communicates to a chipset connected to the I/O controller the amount of available memory credits. The chipset may then send an amount of data to the I/O controller equivalent to or less than the communicated available amount of memory credits to reduce the occurrence of a “retry” event. The amount of available memory credits is determined by comparing the available memory in each buffer within the I/O controller and designating that the “available” amount of memory for the I/O controller is an amount equivalent to the amount of memory contained in the buffer with the least amount of available memory. This “available” amount of I/O controller memory may then be converted into memory credits and communicated to the chipset. | 2008-09-25 |
20080235414 | RETRACTABLE MEMORY DRIVE - A retractable memory drive in accordance with the present invention comprises a top casing, a middle carrier, an electronic device such as a USB thumb drive, and a bottom casing. A positioning device on the middle carrier has a portion that protrudes outside the casing and operates like a button. The location of the positioning device where the button is located has two key attributes. First, there is a protrusion that acts as a lock with the casing. Second, the area below the button is not rigid and so it gives way when pressure is applied to the button. The top and bottom casings provide a casing structure which includes two detents. One detent is for locking the device with the connector in the extended position, and one detent for locking the device with the connector retracted in the in position. This allows for just one press of the extended portion of the positioning device to unlock it from its present position. When the device reaches its new position it will automatically lock. There are also guide rails that allow the middle carrier to remain in an appropriate position. | 2008-09-25 |
20080235415 | Method and System for Modeling a Bus for a System Design Incorporating One or More Programmable Processors - Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload. | 2008-09-25 |
20080235416 | UART INTERFACE COMMUNICATION CIRCUIT - A UART interface communication circuit includes a plurality of communication devices, and each includes a UART interface, a selecting apparatus, a CPU, and a multiplexer (MUX). The communication devices connect with each other via the UART interfaces thereof. The selecting apparatus is connected to the CPU for defining one of the communication devices as a master communication device and the rest as slave communication devices. The MUX is connected between the UART interface and the CPU. When the master communication device transmits data carrying an ID to the slave communication devices, a slave communication device corresponding to the ID receives and processes the data, and transmits return data to the master communication device, and then the MUX receives the return data from the slave communication device and passes it to the CPU of the master communication device for processing. | 2008-09-25 |
20080235417 | METHOD AND APPARATUS FOR BUS ENCODING AND DECODING - A method and an apparatus for bus encoding and a method and an apparatus for bus decoding are provided. The methods and apparatuses for bus encoding/decoding use a discontinuous pattern table (DPT) to store discontinuous pattern pairs. The tables are kept synchronous in both transmitter and receiver ends. After transmitting the first data in a discontinuous pattern pair, the second data may be transmitted by merely informing the receiver end through a control line instead of transmitting the second data by the bus. | 2008-09-25 |
20080235418 | Optical Data Link - The invention provides an optically powered device interface module for operating an external device, and an optically powered data link comprising the same. In one embodiment the device interface module includes an optical interface for receiving optical power and data signals, an electrical USB interface for providing USB compliant electrical data signals and a 5V electrical power signal to an external USB device, a transducer coupled to a signal processor for converting the optical power and data signals into the 5V electrical power signal and the USB-compliant electrical data signals, and a power distribution circuit for providing electrical power obtained from the optical power signal to the device interface module circuitry. The transducer may be embodied using a single photovoltaic power converter for receiving the optical power and for receiving and transmitting optical data signals. | 2008-09-25 |
20080235419 | Integrated Circuit and Method of Securing Access to an On-Chip Memory - The integrated circuit comprises: —an on-chip access right manager ( | 2008-09-25 |
20080235420 | METHOD OF DETECTING MASTER/SLAVE RESPONSE TIME-OUT UNDER CONTINUOUS PACKET FORMAT COMMUNICATIONS PROTOCOL - A method of detecting master/slave response time-out under continuous packet format communications protocol, which calculates the time required for the slave device to respond to a Modbus request subject to Modbus TCP/UDP protocol. The method is to continuously send Modbus requests to a slave device through a detection device and to record each Modbus request sent time, and to have the slave device provide to the detection device a response for each Modbus request. By means of calculating the precise response time-out from the response time-outs which are gotten from the slave device responds to a predetermined number of Modbus requests, the user or manager can determine the response time-out required for the slave device precisely so as to give an EXECUTE instruction or command at the accurate time point. | 2008-09-25 |
20080235421 | Technique and apparatus to optimize inter-port memory transaction sequencing on a multi-ported memory controller unit - An apparatus that includes a multi-ported memory controller unit to control access to a memory external to the memory controller and comprising port interfaces coupled to the masters. Each master is capable of generating a transaction request with the memory. The apparatus also includes a transaction sequence logic to communicate with the masters using sideband signals to receive the transaction request and apply rules to control access to the memory by the masters | 2008-09-25 |
20080235422 | DOWNSTREAM CYCLE-AWARE DYNAMIC INTERCONNECT ISOLATION - A device, method, and system are disclosed. In one embodiment, the device includes a data reception unit that receives data from an interconnect, and a data suppression unit that receives a target address from the interconnect, determines if the target address is local to the device, and, if the target address is not local to the device, the data suppression unit suppresses the interconnect from switching at the interconnect entry point into the data reception unit. | 2008-09-25 |
20080235423 | Data processing apparatus and method for arbitrating between messages routed over a communication channel - A data processing apparatus and method are provided for arbitrating between messages routed over a communication channel. The data processing apparatus has a plurality of processing elements, each processing element executing a process requiring messages to be issued to recipient elements, and a communication channel shared amongst those processing elements over which the messages are routed. Arbitration circuitry performs an arbitration process to arbitrate between multiple messages routed over the communication channel. Each processing element issues progress data for the process executing on that processing element, the progress data indicating latency implications for the process. Arbitration control circuitry is then responsive to the progress data from each processing element to perform a priority ordering process taking into account the latency implications of each process as indicated by the progress data in order to generate priority ordering data. That priority ordering data is then output to the arbitration circuitry in order to control the arbitration process. This enables quality of service to be determined and allocated automatically between the various processes, without the need to know the requirements of the processes in advance, and the prioritisation mechanism adapts dynamically to changes in communication between the processes. | 2008-09-25 |
20080235424 | Method and apparatus for performing interrupt coalescing - In one embodiment, the invention includes a controller that interrupts a CPU based on a counter that uses a decrement step which may increase as high priority data packets are received by the controller. | 2008-09-25 |
20080235425 | MANAGING INPUT/OUTPUT INTERRUPTIONS IN NON-DEDICATED INTERRUPTION HARDWARE ENVIRONMENTS - Input/output interruptions are managed in computing environments that do not use dedicated per-guest interruption hardware to present interruptions. Dispatchable guest programs in the environment receive I/O interruptions directly without hypervisor intervention. This is facilitated by using one or more interruption controls stored in memory and associated with each guest program. For those guest programs that are not currently dispatchable, interruptions can be posted for the guests and notifications to the hypervisor can be aggregated. The hypervisor can then process a plurality of notifications for the plurality of guests in a single invocation. | 2008-09-25 |
20080235426 | Handling shared interrupts in bios under a virtualization technology environment - A custom interrupt service routine may be developed to handle interrupt requests that would not be appropriately handled by either of two operating system guests in a virtualization technology (VT) environment. In some embodiments, the custom interrupt service routine does not in any way interfere with the operation of the interrupt handling in a non-VT environment. | 2008-09-25 |
20080235427 | Electronic device with card interface - When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode. | 2008-09-25 |
20080235428 | METHOD AND SYSTEM FOR DYNAMIC SWITCHING BETWEEN MULTIPLEXED INTERFACES - A bridge is disclosed. The bridge comprises a first interface having at least one multiplexed clock signal line. The multiplexed clock signal line outputs first and second control signals for respectively controlling the access to first and second devices coupled to the bridge. The bridge selectively outputs the first clock signal or the second clock signal to the multiplexed clock signal line to access the first device or the second device respectively. | 2008-09-25 |
20080235429 | Operating PCI Express Resources in a Logically Partitioned Computing System - Methods, systems, and products are disclosed for operating Peripheral Component Interconnect (‘PCI’) Express resources in a logically partitioned computing system that include: allocating, by a hypervisor installed on the computing system, a PCI Express adapter installed in the computing system to a logical partition of the computing system, including establishing a data communication path between a processor of the computing system and the PCI Express adapter, the data communication path including a link between a PCI Express root complex and the PCI Express adapter; and administering, by the hypervisor for the logical partition, the PCI Express root complex and the link between the PCI Express root complex and the PCI Express adapter. | 2008-09-25 |
20080235430 | Creation and Management of Routing Table for PCI Bus Address Based Routing with Integrated DID - A method is provided for creating and managing tables for routing packets through an environment that includes multiple hosts and shared PCI switches and adapters. A Destination Identification (DID) field in the PBA is appended to a transaction packet dispatched through the PCI switches, wherein a particular DID is associated with a particular host or system image, and thus identifies the physical or virtual end point of its packet. In one embodiment, packets are routed through PCI switches in a distributed computer system comprising multiple root nodes, wherein each root node includes one or more hosts. The embodiment includes the step of creating a table or like data structure in a specified one of the switches. When a particular host of one of the root nodes becomes connected to the specified switch, a PCI Configuration Master (PCM), residing in one of the root nodes, is operated to enter a destination identifier or DID into the table. The DID is then appended as an address component, to packets directed through the specified switch from the particular host to one of the adapters. The destination identifier is also used to determine that a PCI packet, routed through the specified switch from one of the adapters, is intended for the particular root node. | 2008-09-25 |
20080235431 | Method Using a Master Node to Control I/O Fabric Configuration in a Multi-Host Environment - A method is directed to use of a master root node, in a distributed computer system provided with multiple root nodes, to control the configuration of routings through an I/O switched-fabric. One of the root nodes is designated as the master root node or PCI Configuration Manager (PCM), and is operable to carry out the configuration while each of the other root nodes remains in a quiescent or inactive state. In one useful embodiment pertaining to a system of the above type, that includes multiple root nodes, PCI switches, and PCI adapters available for sharing by different root nodes, a method is provided wherein the master root node is operated to configure routings through the PCI switches. Respective routings are configured between respective root nodes and the PCI adapters, wherein each of the configured routings corresponds to only one of the root nodes. A particular root node is enabled to access each of the PCI adapters that are included in any configured routing that corresponds to the particular root node. At the same time, the master root node writes into a particular root node only the configured routings that correspond to the particular root node. Thus, the particular root node is prevented from accessing an adapter that is not included in its corresponding routings. | 2008-09-25 |
20080235432 | MEMORY SYSTEM HAVING HYBRID DENSITY MEMORY AND METHODS FOR WEAR-LEVELING MANAGEMENT AND FILE DISTRIBUTION MANAGEMENT THEREOF - The present invention discloses a memory system having a hybrid density memory. The memory system includes a plurality of storage spaces whereby the storage spaces have respective levels of endurance and each storage space has a plurality of blocks and pre-determined weighting factors corresponding to the levels of endurance of the storage spaces. After executing a command of erasing a specific block, the system records the erase in accordance with the weighting factor of the storage space to which the specific block belongs. Whereby, the erase counts of all the blocks of different storage spaces are able to reach respective levels of endurance as simultaneously as possible. | 2008-09-25 |
20080235433 | HYBRID DENSITY MEMORY STORAGE DEVICE AND CONTROL METHOD THEREOF - The present invention discloses a control method for a hybrid density memory storage device. The method arranges physical locations for a file system stored in the storage device. The storage device includes a high density storage space, a low density storage space and a hot list capable of recording a plurality of logical locations. The method includes the following steps: receiving a command; verifying whether the logical location of the command belongs to the logical locations recorded in the hot list; and according to the verification, assigning a physical location of the high density storage space or a physical location of the low density storage space as the physical location corresponding to the logical location of the command. | 2008-09-25 |
20080235434 | Information processing method, and information processing system - A user-information managing unit controls reading of information stored in a user-information DB and a rule DB and writing of information to these databases. A customization processing unit receives a request for customizing rule information stored in the rule DB and, according to the request, customizes the rule information stored in the rule DB via the user-information managing unit. | 2008-09-25 |
20080235435 | USE OF A SHUTDOWN OBJECT TO IMPROVE INITIALIZATION PERFORMANCE - According to some embodiments, use of a shutdown object during system initialization is disclosed. The shutdown object may be read from a non-volatile memory device and loaded into a random access memory. A plurality of headers may then be scanned from the non-volatile memory device. The shutdown object may be referenced to determine whether each of the plurality of headers includes valid data. Each of the plurality of headers that includes valid data may be represented in the random access memory. | 2008-09-25 |
20080235436 | STORAGE ACCESS CONTROL - A system and device are disclosed. In one embodiment, the system includes a processor, system memory, chipset, flash memory, and flash memory controller. The flash memory controller includes a base address register for a flash memory hidden protected area (HPA) to store a flash memory HPA base address, a size register for a flash memory HPA to store a size of the flash memory HPA, and control logic to allocate a portion of the flash memory as a flash memory HPA using the flash memory HPA base address and the flash memory HPA size address. | 2008-09-25 |
20080235437 | Methods for forcing an update block to remain sequential - A method for operating a memory system is provided. In this method, a sequential update block and preexisting data associated with the sequential update block are provided. Here, an option to convert the sequential update block to a chaotic update block also is provided. A write command is received to write data following a previous write command, where the write command and the previous write command have a discontinuity in logical addresses. If a logical address of the write command is different from logical addresses of the preexisting data, then the data are written to the sequential update block. If the logical address of the write command matches one of the logical addresses of the preexisting data, then the sequential update block is converted to a chaotic update block. | 2008-09-25 |
20080235438 | System and method for effectively implementing a multiple-channel memory architecture - A system and method for implementing a multiple-channel memory architecture includes a plurality of memory channels that are configured in a parallel manner to store electronic data. In certain embodiments, the memory channels are implemented to include non-volatile flash memory devices. A transfer controller communicates with the memory channels to control concurrent data transfer operations for transferring the electronic data in and out of the memory channels. The transfer controller generates individual channel clock signals to the respective memory channels for triggering corresponding data transfer operations which occur in an overlapping temporal sequence. | 2008-09-25 |
20080235439 | Methods for conversion of update blocks based on association with host file management data structures - A method for operating a memory system is provided. In this method, a sequential update block is provided and a write command is received to write data. The write command comprises a logical address associated with the data. If the logical address is associated with a host file management data structure, then the sequential update block is converted to a chaotic update block. After the conversion, the data are written to the chaotic update block. | 2008-09-25 |
20080235440 | Memory device - A memory device includes a housing, a memory within the housing, and a first electrical interface accessible on a top surface of the housing and a second electrical interface accessible on a bottom surface of the housing. As such, at least one of the first electrical interface and the second electrical interface is configured to establish electrical connection of the memory device with an electrical interface of another memory device when the memory device and the another memory device are in a stacked configuration. | 2008-09-25 |
20080235441 | Reducing power dissipation for solid state disks - A data processing device including a computer, the computer including a solid state disk (SSD), including a primary memory for single level cell storage, and a secondary memory for multi-level cell storage, a limited internal battery for supplying power to the computer, a socket for connecting the computer to an external power supply source, a detector for indicating that the computer is connected to an external power source, a processor for transferring data from the primary memory to the secondary memory, and an SSD controller for deciding whether or not the processor may transfer data from the primary memory to the secondary memory, based on a signal received from said detector. A method for SSD memory management is also described and claimed. | 2008-09-25 |
20080235442 | FLASH MEMORY DEVICE CAPABLE OF IMPROVING READ PERFORMANCE - A flash memory device, related system ad method are disclosed. The memory device includes a memory cell array a page buffer receiving read data, wherein the page buffer includes a main register transferring read data to a cache register during an read operation, and a control logic block controlling operation of the page buffer during the read operation, such that initialization of the main register continuously extends beyond a time period during which read data is transferred from the main register to the cache register. | 2008-09-25 |
20080235443 | Intelligent Solid-State Non-Volatile Memory Device (NVMD) System With Multi-Level Caching of Multiple Channels - A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security. | 2008-09-25 |
20080235444 | SYSTEM AND METHOD FOR PROVIDING SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (SDRAM) MODE REGISTER SHADOWING IN A MEMORY SYSTEM - A system and method for providing SDRAM mode register shadowing in a memory system. A system includes a memory interface device adapted for use in a memory system. The memory interface device includes an interface to one or more ranks of memory devices, and each memory device includes one or more types of mode registers. The memory interface device also includes an interface to a memory bus for receiving commands from a memory controller. The commands include a mode register set command specifying a new mode register setting for one or more ranks of memory devices and a mode register type. The memory interface device further includes a mode register shadow module to capture settings applied to the mode registers. The module includes a shadow register for each type of mode register and a shadow log for each type of mode register. The module also includes mode register shadow logic to detect a mode register set command, to store the new mode register setting in the shadow register corresponding to the specified mode register type, and to set one or more bits in the shadow log corresponding to the specified mode register type to indicate which of the ranks of memory devices have been programmed with the new mode register setting. | 2008-09-25 |
20080235445 | IT Automation Appliance Imaging System and Method - A system, method, and computer program product for harvesting an image from a local disk of a managed endpoint to an image library is provided. In an embodiment of the method for harvesting an image, a managed endpoint is provided with a boot image that causes the endpoint to instantiate a RAM disk and execute the boot image from the RAM disk. The boot image is used to harvest an image by determining data on a local disk of the managed endpoint to be included in the image that are not already stored in the image library. In one embodiment, this is done by comparing hashes calculated on the data on the local disk to hashes of data in the image library. The data not already stored in the image library are then copied to the image library. | 2008-09-25 |
20080235446 | Method of monitoring status information of remote storage and storage subsystem - A host computer acquires remote copy status information of storage subsystems that are not directly coupled to the host computer. | 2008-09-25 |
20080235447 | Storage device - The present disclosure relates to a method for detecting a RAID device. The RAID device includes a disk set for storing a special data and the disk set is composed of a plurality of member disks. The method comprises the following steps. The first step is to read data stored in the RAID device to determine whether or not a data read from the disk set is equal to the special data. the second step is to set one of said member disks as a failure disk to determine whether or not the failure disk affects the disk set operation. The third step is to replace the failure disk with a non-member disk and rebuilding data of the failure disk in the non-member disk to determine whether or not the rebuilt data is equal to data of the failure disk. | 2008-09-25 |
20080235448 | Storage apparatus and storage area arrangement method - This storage apparatus for providing a dynamically expandable virtual volume to a host system to access the virtual volume comprises an allocation unit for configuring a group with a plurality of disks for providing a storage area to be allocated to the virtual volume, and allocating the storage area respectively from a plurality of the groups to the virtual volume; and a storage area arrangement unit for rearranging the storage area in each of the groups being used by the virtual volume to become optimal among each of the groups based on external operation. | 2008-09-25 |
20080235449 | REBALANCING OF STRIPED DISK DATA - Provided are a method, system, and article of manufacture, where a plurality of extents are stored in a first set of storage units coupled to a controller. A determination is made that a second set of storage units has been coupled to the controller. The plurality of extents are distributed among all storage units included in the first set of storage units and the second set of storage units. | 2008-09-25 |
20080235450 | Updating Entries Cached by a Network Processor - Machine-readable media, methods, and apparatus are described to update network processor cache entries in corresponding local memories and update cached entries based upon information stored in corresponding buffers for the microengines. A control plane of the network processor identifies each microengine having updated entry stored in corresponding local memory, and store information in the corresponding buffer for each identified microengine to indicate that the entry has been updated in the external memory. | 2008-09-25 |
20080235451 | NON-VOLATILE MEMORY DEVICE AND ASSOCIATED PROGRAMMING METHOD - A non-volatile memory device having a memory array is configured to prevent power voltage noise generation during programming, thereby improving reliability. An associated programming method of the non-volatile memory device includes storing data input from an external source to a cache register. The stored data is moved to a main register. The cache register is cleared and the data stored in the main register is programmed to the memory cell array. | 2008-09-25 |
20080235452 | DESIGN STRUCTURE FOR SHARED CACHE EVICTION - A design structure embodied in a machine readable storage medium for of designing, manufacturing, and/or testing for shared cache eviction in a multi-core processing environment having a cache shared by a plurality of processor cores is provided. The design structure includes means for receiving from a processor core a request to load a cache line in the shared cache; means for determining whether the shared cache is full; means for determining whether a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache if the shared cache is full; and means for evicting a cache line that has been accessed by fewer than all the processor cores sharing the cache if a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache. | 2008-09-25 |
20080235453 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR EXECUTING A CACHE REPLACEMENT ALGORITHM - A system, method and computer program product for executing a cache replacement algorithm. A system includes a computer processor having an instruction processor, a cache and one or more useful indicators. The instruction processor processes instructions in a running program. The cache includes two or more cache levels including a level one (L1) cache level and one or more higher cache levels. Each cache level includes one or more cache lines and has an associated directory having one or more directory entries. A useful indicator is located within one or more of the directory entries and is associated with a particular cache line. The useful indicator is set to provide an indication that the associated cache line contains one or more instructions that are required by the running program and cleared to provide lack of such an indication. | 2008-09-25 |
20080235454 | Method and Apparatus for Repairing a Processor Core During Run Time in a Multi-Processor Data Processing System - A data processing system includes multiple processors each having multiple processor cores. A core checkstop from a particular processor core indicates that a memory array associated with the particular core exhibits an error. In response to the core checkstop, the system migrates the workload of the particular processor core to another processor core. The system also removes the particular processor core from the current configuration of the system. In response to the core checkstop and error, the system initializes the particular processor core if the error is in a processor memory array associated with the particular core. The system then attempts correction of the error with array built-in self test (ABIST) circuitry. If the ABIST succeeds in correcting the error, the initialization of the particular processor core completes and the system returns the particular processor core to the current processor configuration. However, if the ABIST does not succeed in correcting the error, then the system removes the portion of the processor memory array including the error from future use. | 2008-09-25 |
20080235455 | CACHE ARCHITECTURE FOR A PROCESSING UNIT PROVIDING REDUCED POWER CONSUMPTION IN CACHE OPERATION - A cache memory processing system is disclosed that is coupled to a main memory and a processing unit. The cache memory processing system includes an input, a low order bit data path, a high order bit data path and an output. The input is for receiving input data that includes at least one low order input bit and at least one high order input bit. The low order bit data path is for processing the at least one low order input bit and providing at least one low order output bit. The high order bit data path for processing the at least one high order input bit and providing at least one high order output bit. The high order bit data path includes at least one exclusive or gate. The output is for providing the at least one low order output bit and the at least one high order output bit. | 2008-09-25 |
20080235456 | Shared Cache Eviction - Methods and systems for shared cache eviction in a multi-core processing environment having a cache shared by a plurality of processor cores are provided. Embodiments include receiving from a processor core a request to load a cache line in the shared cache; determining whether the shared cache is full; determining whether a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache if the shared cache is full; and evicting a cache line that has been accessed by fewer than all the processor cores sharing the cache if a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache. | 2008-09-25 |
20080235457 | Dynamic quality of service (QoS) for a shared cache - In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory by a core to indicate a priority level of a first thread, and associating a second priority indicator with data stored in a second entry of the shared cache memory by a graphics engine to indicate a priority level of a second thread. Other embodiments are described and claimed. | 2008-09-25 |
20080235458 | METHOD FOR TRACKING OF NON-RESIDENT PAGES - Embodiments of the present invention provide methods and systems for efficiently tracking evicted or non-resident pages. For each non-resident page, a first hash value is generated from the page's metadata, such as the page's mapping and offset parameters. This first hash value is then used as an index to point one of a plurality of circular buffers. Each circular buffer comprises an entry for a clock pointer and entries that uniquely represent non-resident pages. The clock pointer points to the next page that is suitable for replacement and moves through the circular buffer as pages are evicted. In some embodiments, the entries that uniquely represent non-resident pages are a hash value that is generated from the page's inode data. | 2008-09-25 |
20080235459 | PROCESSOR, METHOD, AND DATA PROCESSING SYSTEM EMPLOYING A VARIABLE STORE GATHER WINDOW - A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads. | 2008-09-25 |
20080235460 | APPARATUS AND METHOD FOR INFORMATION PROCESSING ENABLING FAST ACCESS TO PROGRAM - A main memory stores cache blocks obtained by dividing a program. At a position in a cache block where a branch to another cache block is provided, there is embedded an instruction for activating a branch resolution routine for performing processing, such as loading of a cache block of the branch target. A program is loaded into a local memory in units of cache blocks, and the cache blocks are serially stored in first through nth banks, which are sections provided in the storage area. Management of addresses in the local memory or processing for discarding a copy of a cache block is performed with reference to an address translation table, an inter-bank reference table and a generation number table. | 2008-09-25 |
20080235461 | Technique and apparatus for combining partial write transactions - A bridge includes a memory to establish a transaction table and write combining windows. Each write combining window is associated with a cache line and is subdivided into subwindows; and each of the subwindows is associated with a partial cache line. The bridge includes a controller to determine whether an incoming partial write transaction conflicts with a transaction stored in the transaction table. If a conflict occurs, the controller uses the write combining windows to combine the partial write transaction with another partial write transaction if one of the partial write combining windows is available. The controller issues a retry signal to a processor originating the partial write transaction if none of the partial write combining windows are available. | 2008-09-25 |
20080235462 | Device Having a Low Latency Single Port Memory Unit and a Method for Writing Multiple Data Segments to a Single Port Memory Unit - A method and a device. The device includes a single port memory unit that includes multiple memory regions, whereas each memory region is adapted to receive multiple data segments in parallel; whereas the single port memory unit receives a memory clock signal; characterized by including access logic adapted to receive multiple data segment write requests from multiple data sources; to write, during a first memory clock cycle, multiple data segments to a certain memory region in response to an availability of the certain memory region; to temporarily store rejected data segments; to write, during a second memory clock cycle, at least the rejected data segments, to another memory region. | 2008-09-25 |
20080235463 | Methods for conversion of update blocks based on comparison with a threshold size - A method for operating a memory system is provided. In this method, a write command is received to write data following a previous write command. The write command and the previous write command have a discontinuity in logical addresses and the discontinuity in logical addresses defines a gap between a logical address of the write command and a logical address of the previous write command. Here, a sequential update block and preexisting data associated with the sequential update block are provided. The gap is compared with a threshold size and the data are written to the sequential update block if the gap is less than the threshold size. | 2008-09-25 |
20080235464 | System for conversion of update blocks based on comparison with a threshold size - A non-volatile memory storage system is provided. The non-volatile memory storage system comprises a non-volatile memory cell array and a processor in communication with the non-volatile memory cell array. The processor is configured to receive a write command to write data following a previous write command. Here, the write command and the previous write command have a discontinuity in logical addresses, where the discontinuity in logical addresses defines a gap between a logical address of the write command and a logical address of the previous write command. A sequential update block and preexisting data associated with the sequential update block are provided. The processor is further configured to compare the gap with a threshold size and write the data to the sequential update block if the gap is less than the threshold size. | 2008-09-25 |
20080235465 | Systems for conversion of update blocks based on association with host file management data structures - A non-volatile memory storage system is provided. The non-volatile memory storage system comprises a non-volatile memory cell array and a processor in communication with the non-volatile memory cell array. Here, the processor is configured to receive a write command to write data, where the write command comprises a logical address associated with the data. The processor is further configured to allocate a chaotic update block if the logical address is associated with a host file management data structure. After the allocation, the data are written to the chaotic update block. | 2008-09-25 |
20080235466 | Methods for storing memory operations in a queue - A method for operating a non-volatile memory storage system is provided. In this method, a queue that is configured to store memory operations associated with two or more types of memory operations. Here, memory operations are associated with the maintenance of the non-volatile memory storage system. A memory operation is scheduled for execution in response to an event and the memory operation is stored in the queue. | 2008-09-25 |
20080235467 | MEMORY MANAGEMENT DEVICE AND METHOD, PROGRAM, AND MEMORY MANAGEMENT SYSTEM - A memory management device which is capable of allocating a memory unit accessible at a higher speed to data which is stored in a storage device having memory units different in access speed, without being limited in an storage area. The storage device comprises a BLC flash memory accessible at a predetermined access speed, an MLC flash memory accessible at a lower access speed than the predetermined access speed, a controller, and a RAM. The controller manages the BLC flash memory and the BLC flash memory in units each formed by a plurality of physical pages, and writes data in the physical pages, and the RAM holds page allocation information in which logical pages designated when writing data and the physical pages are associated with each other. | 2008-09-25 |
20080235468 | HYBRID DENSITY MEMORY STORAGE DEVICE - The present invention discloses a hybrid density memory storage device configured to store data responsive to a host and a file system thereof. The hybrid density memory storage device includes a non-volatile memory, a hot data buffer and a control unit. The non-volatile memory includes a high density storage space and a low density storage space. The control unit is coupled between the host, the non-volatile memory, and the hot data buffer. The control unit has a hot list used for recording a plurality of logical locations of hot data, and the control unit is capable of accessing data in/out the hot data buffer in accordance with the hot list. | 2008-09-25 |
20080235469 | Peak Data Retention of Signal Data In An Implantable Medical Device - Methods and apparatus for storing data records associated with an extreme value are disclosed. Signal data is stored in a first buffer of a set of buffers. If a local extreme value for the first buffer exceeds a global extreme value, signal data is stored in a second buffer of the set of buffers. This process is repeated, wrapping around and overwriting buffers until the signal data in a current buffer does not have a local extreme value that exceeds the global extreme value. When this happens, signal data may be stored in a subsequent buffer and if a local extreme value of the subsequent buffer does not exceed the global extreme value, further signal data may be stored in the subsequent buffer in a circular manner until either an instantaneous extreme value exceeds the global extreme value or the recording period ends. In an embodiment, the extreme value may be a peak value. | 2008-09-25 |
20080235470 | ACCESSING INFORMATION FROM A REMOVABLE STORAGE UNIT - A system comprising a processor and a removable solid-state storage unit adapted to be accessed by the processor and comprising information. Upon detecting the presence of the storage unit, the processor copies the information to a system storage coupled to the processor. The processor accesses the information from the system storage in response to a request to access a different storage apparatus. | 2008-09-25 |
20080235471 | Smart batteryless backup device and method therefor - A proposed smart batteryless backup device is designed for the reception of data transmitted by controlled equipment, backing up said data in the case of the controlled equipment power failure or in accordance with several program requirements, and also for the subsequent restoration. Proposed device improves trust level of the backup if device is powered by interface signal lines and doesn't have batteries and electrical characteristics of the backup device fluctuating due to humidity and temperature influences as well as during device lifetime. | 2008-09-25 |
20080235472 | Snapshot format conversion method and apparatus - A system according to this invention converts a full-copy snapshot into a differential snapshot. The system is composed of a storage subsystem and a server subsystem. The storage subsystem comprises a disk drive and a disk controller. The server subsystem comprises an interface, a processor, and a memory. The disk controller provides storage areas of the disk drive as logical volumes, and stores a differential block bitmap. The processor obtains the differential block bitmap, and identifies a block from the differential block bitmap. The processor obtains, from a full-copy snapshot volume, differential data that is stored in the identified block. The processor stores the obtained differential data in a differential volume. The processor stores, in differential block arrangement information, the location of the differential data stored in the differential volume. | 2008-09-25 |
20080235473 | PROTECTION UNIT FOR A PROGRAMMABLE DATA-PROCESSING SYSTEM - A data-processing system having at least one operating memory holding operating data is provided with a protection unit having an execution environment protected from unauthorized access. At least one monitoring logic in the execution environment is connected to the operating memory for monitoring unauthorized modifications, access, or similar protection violations of the operating data stored in the operating memory and for generating an output on detection of such a protection violation. A protection logic in the execution environment holds replacement data capable of replacing the operating data and is connected to the monitoring logic for, on generation of the output, providing to the operating memory the replacement data for the operation or for a substitute operation of the data-processing system. | 2008-09-25 |
20080235474 | METHOD AND SYSTEM FOR PROCESSING ACCESS TO DISK BLOCK - Provided are a method and a system for processing an access to a disk block. The system receives a disk block access request from an OS domain, determines whether the OS domain is permitted to access a disk block with reference to a predetermined block table and processes disk block access of the OS domain according to the determination result. Accordingly, OS domains can share caches without having data copy through memory access control in a virtual machine monitor environment. Furthermore, a device domain controls access to a disk drive so that data corruption can be prevented. | 2008-09-25 |
20080235475 | METHOD AND APPARATUS FOR INTERVALED DMA TRANSFER ACCESS - A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting the memory access controller from writing data to a memory until the memory access controller receives a periodic authorization signal to cause the memory access controller to remove the inhibition and write a predetermined amount of data to the memory through a data bus, and 2) releasing the data bus following writing of the predetermined amount of data to the memory by inhibiting the memory access controller from writing further data. | 2008-09-25 |
20080235476 | Media Vaulting in an Automated Data Storage Library - Disclosed are a system, a method, and article of manufacture to provide for managing data storage media to provide secure storage of the data storage media in an automated data storage library. A logical library partition vault is created in the automated data storage library that is not accessible by any host computer. Data storage media in the logical library partition vault may only be accessed by an operator using a secure means. The logical library partition vault may comprise various components of the automated data storage library by assigning storage shelves, service bays, data storage media, data storage drives or other library components to the logical library partition vault. | 2008-09-25 |
20080235477 | COHERENT DATA MOVER - A method and system for dynamically relocating regions of memory in computing systems. During the execution of software application(s) on a computing system, a relocation of data in a region of memory may be performed. A coherent data mover is coupled to system memory, memory controller(s), and processor(s) of a computing system. The mover executes commands such as copying a specific region of memory from its current source location in system memory to a new target location in system memory without suspending access of the data. During a copy of data from the first portion to the second portion, the mover monitors transactions which modify data in the first portion which has already been copied. Subsequent to copying all of the data, the mover re-copies those data elements which were detected to be modified during the copy operation. | 2008-09-25 |
20080235478 | MOVING HARDWARE CONTEXT STRUCTURES IN MEMORY WHILE MAINTAINING SYSTEM OPERATION - An adapter includes registers, a local context table, and logic that allows copying hardware context structures from a first location in memory to a second location in memory while the computer system continues to run. The local context table in the adapter is loaded with a desired block of context entries from the first location in memory. Values in the registers cause the adapter to write this desired block of context entries to the second location in memory in a way that does not inhibit the operation of the computer system. | 2008-09-25 |
20080235479 | Initializing File Data Blocks - A method and system is provided for initializing files such as, for example and without limitation, pre-allocated files or raw device mapping (RDM) files, by delaying initializing file blocks. In accordance with one or more embodiments of the present invention, file blocks are associated with corresponding indicators to track un-initialized blocks. | 2008-09-25 |
20080235480 | Systems for storing memory operations in a queue - A non-volatile memory storage system is provided. The non-volatile memory storage system is configured to store a queue. Here, the queue is configured to store memory operations associated with two or more types of memory operations. The memory operations are associated with maintenance of the non-volatile memory storage system. The non-volatile memory storage system further comprises a processor in communication with the non-volatile memory cell array. The processor is configured to schedule a memory operation for execution in response to an event and store the memory operation in the queue. | 2008-09-25 |