39th week of 2014 patent applcation highlights part 14 |
Patent application number | Title | Published |
20140284574 | DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - A display apparatus includes a pixel part disposed in a display area of a base substrate, including a switching element connected to a signal line, a pixel electrode connected to the switching element and a common electrode that overlaps the pixel electrode, a plurality of fan-out lines disposed in a peripheral area of the base substrate that are connected to the signal line of the display area, a plurality of pads disposed in the peripheral area of the base substrate that are respectively connected to end portions of the fan-out lines, an organic layer that covers the switching element of the display area and that extends from the display area to a portion of the fan-out lines, and an electrode pattern that overlaps the fan-out lines in a boundary portion of the organic layer. | 2014-09-25 |
20140284575 | DISPLAY DEVICE AND ELECTRONIC DEVICE - To inhibit surface reflection of a display device. A display device which includes a reflective electrode layer | 2014-09-25 |
20140284576 | DISPLAY DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - A display device that includes a reflective electrode; a transparent electrode; a partition; an EL layer formed over the partition and the transparent electrode; a semi-transmissive electrode formed over the EL layer; and a coloring layer over the semi-transmissive electrode. A light-emitting region is formed to overlap with the transparent electrode, the EL layer, the semi-transmissive electrode, and the coloring layer. A non-light-emitting region is formed to overlap with the transparent electrode, the partition, the EL layer, and the coloring layer. The non-light-emitting region is formed to surround the light-emitting region. The sum of the optical length of the transparent electrode and the optical length of the EL layer is adjusted to fulfil a condition of a microcavity intensifying light of the color of the coloring layer. The optical length of the partition in the non-light-emitting region is adjusted to weaken external light incident through the coloring layer. | 2014-09-25 |
20140284577 | HIGHLY REFRACTIVE THIN GLASSES - Thin glasses having high refractive index (n | 2014-09-25 |
20140284578 | Organic Compound, Light-Emitting Element, Light-Emitting Device, Electronic Device, and Lighting Device - An organic compound having a low HOMO level and a high hole-transport property is provided. The organic compound is represented by Formula (G1), where Ar | 2014-09-25 |
20140284579 | ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE - An organic EL display device has a pixel electrode and a common electrode, a first insulating layer that covers a thin-film transistor, a first wire provided on the first insulating layer to electrically connect the thin-film transistor and the pixel electrode, a second wire provided on the first insulating layer to be connected to a gate electrode of the thin-film transistor, and a conducting film formed on the first wire and the second wire from a material on which an oxide film is harder to be formed than those of the first wire and the second wire. At least one of the pixel electrode, the first wire, and the second wire and the conducting film are located to overlap above the first insulating layer in electrical insulation so that a capacitor that retains a control signal is formed between the first wire and the second wire. | 2014-09-25 |
20140284580 | ELECTRON TRANSPORTING COMPOUNDS AND ORGANIC ELECTROLUMINESCENT DEVICES USING THE SAME - Disclosed is a novel compound of Formula 1 and an organic electroluminescent device using the same. In Formula 1, X and Y independently represents a hydrogen, an aromatic or a hetero aromatic hydrocarbon having C5 to C10 carbons; X and Y may be the same or different; Ar | 2014-09-25 |
20140284581 | ORGANIC LIGHT EMITTING HOST MATERIALS - Disclosed herein are compounds represented by formula: | 2014-09-25 |
20140284582 | PHASE DIFFERENCE PLATE FOR CIRCULARLY POLARIZING PLATE, CIRCULARLY POLARIZING PLATE, AND ORGANIC ELECTROLUMINESCENCE DISPLAY APPARATUS - The phase difference plate for a circularly polarizing plate includes a first optically anisotropic layer; and a second optically anisotropic layer, in which the first and second optically anisotropic layers contain a liquid crystal compound that is helically aligned around a helical axis which is in a thickness direction of each of the layers, the liquid crystal compound has a same helix direction in the first optically anisotropic layer and in the second optically anisotropic layer, and a helix angle of the liquid crystal compound each in the first optically anisotropic layer and in the second optically anisotropic layer is in a predetermined range. The phase difference plate can sufficiently suppress the mixing of black with another color observed in the front direction when being stuck as a circularly polarizing plate on a display apparatus. | 2014-09-25 |
20140284583 | PHASE DIFFERENCE PLATE FOR CIRCULARLY POLARIZING PLATE, CIRCULARLY POLARIZING PLATE, AND ORGANIC ELECTROLUMINESCENCE DISPLAY APPARATUS - The phase difference plate for a circularly polarizing plate including a first optically anisotropic layer, and a second optically anisotropic layer, in which the first optically anisotropic layer contains a liquid crystal compound helically aligned around a helical axis in its thickness direction, a helix angle of the liquid crystal compound in the first optically anisotropic layer is in a predetermined range, and an in-plane slow axis in a surface of the first optically anisotropic layer at the second optically anisotropic layer side is in parallel with an in-plane slow axis of the second optically anisotropic layer. The phase difference plate can sufficiently suppress the mixing of black with another color observed in the front direction when being stuck as a circularly polarizing plate on a display apparatus. | 2014-09-25 |
20140284584 | ORGANIC LIGHT EMITTING BIPOLAR HOST MATERIALS - Disclosed herein are compounds represented by the formula: | 2014-09-25 |
20140284585 | ORGANIC ELECTROLUMINESCENT MATERIALS AND DEVICES - Phosphorescent materials and devices with improved device manufacturing, fabrication, stability, efficiency, and/or color is disclosed. | 2014-09-25 |
20140284586 | Display Device and Method for Manufacturing Thereof - It is a problem to provide an electric apparatus less in consumption power and long in life by the manufacture using the display device. An insulating bank is provided in a form surrounding the pixel portions on first electrodes over a substrate. The entire surface is applied, by a wet scheme (method), with an organic conductive film which has a thickness form of T2>T1>T3 under the influence of the insulating bank. Accordingly, the portion T3 has an increased resistance in a lateral direction, making possible to prevent against crosstalk. Due to a conductive polymer as a buffer layer, a display device can be provided which is low in drive voltage. Furthermore, because the portion T2 is increased in thickness, the electric-field concentration is relaxed at and around the pixel portion. This makes it possible to prevent the organic light-emitting element from deteriorating at around the pixel. | 2014-09-25 |
20140284587 | Light-Emitting Device, Lighting Device, and Manufacturing Method of Light-Emitting Device - The manufacturing method of the light-emitting device is provided in which an auxiliary electrode in contact with an electrode formed using a transparent conductive film of a light-emitting element is formed using a mask, and direct contact between the auxiliary electrode and an EL layer is prevented by oxidizing the auxiliary electrode. Further, the light-emitting device manufactured according to the method and the lighting device including the light-emitting device are provided. | 2014-09-25 |
20140284588 | ORGANIC EL DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - An organic electroluminescence display panel includes a thin-film transistor layer above a substrate. A planarizing film is above the thin-film transistor layer with contact holes being formed in the planarizing film. A bank is above the planarizing film. The bank includes openings arranged in rows and columns that define regions for forming organic electroluminescence elements. Each opening is between a pair of adjacent concaves in one of the columns. The concaves are formed in an upper surface of the bank and sunken into the contact holes. The upper surface of the bank has repellency. A light-emitting layer is formed in each opening by ejecting drops of an ink from nozzles of an inkjet head into the openings while moving the inkjet head relative to the substrate. The nozzles further eject drops of the ink into the concaves when above the concaves for ejecting the drops of the ink through every nozzle. | 2014-09-25 |
20140284589 | ELECTRODE FOIL AND ORGANIC DEVICE - An electrode foil which has both the functions of a supporting base material and a reflective electrode and also has superior thermal conductivity; and an organic device using the same are provided. The electrode foil comprises a metal foil and a reflective layer provided directly on the metal foil. | 2014-09-25 |
20140284590 | COLOR FILTER FOR ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE, AND ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE - When a large-screen organic EL display device is developed, the generation of a brightness unevenness is prevented between its screen central region and its screen outer circumferential region. Cost risk is decreased about the formation of a structure of preventing the generation of the brightness unevenness. Furthermore, an original protecting function for its organic EL elements is maintained. The color filter of the present invention comprises a transparent substrate, a colored layer that is a pixel region formed on the transparent substrate, and a non-pixel area formed around the colored layer, wherein a convex pillar is formed in at least one spot of the non-pixel area, and an auxiliary electrode layer on a top and a side of the convex pillar, and on the non-pixel area. | 2014-09-25 |
20140284591 | ORGANIC ELECTROLUMINESCENCE DISPLAY PANEL AND ORGANIC ELECTROLUMINESCENCE DISPLAY APPARATUS - An organic electroluminescence (EL) display panel includes an anode electrode formed above a bank and formed opposite to a plurality of cathode electrodes, and a charge functional layer commonly formed for each of the organic light-emitting layers across a plurality of aperture areas formed in the bank. An end portion of the anode electrode and an end portion of the charge functional layer are provided above the bank located adjacent to a boundary between a display region and a peripheral region of a display region. | 2014-09-25 |
20140284592 | MAGNETORESISTIVE EFFECT ELEMENT AND MANUFACTURING METHOD THEREOF - According to one embodiment, a magnetoresistive effect element includes a first ferromagnetic layer, a tunnel barrier provided on the first ferromagnetic layer, and a second ferromagnetic layer provided on the tunnel barrier. The tunnel barrier includes a nonmagnetic mixture containing MgO and a metal oxide with a composition which forms, in a solid phase, a single phase with MgO. | 2014-09-25 |
20140284593 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a substrate having an upper surface, a foundation insulating layer provided on the upper surface, and a thin film transistor. The thin film transistor includes a first gate electrode, first, second and third insulating layers, a semiconductor layer, and first and second conductive layers. The first gate electrode is provided on a portion of the foundation insulating layer. The first insulating layer covers the first gate electrode and the foundation insulating layer. The second insulating layer is provided on the first insulating layer, and has first, second and third portions. The semiconductor layer contacts the second insulating layer on the third portion, and has fourth, fifth portions and sixth portions. The first conductive layer contacts the fourth portion. The second conductive layer contacts the fifth portion. The third insulating layer covers a portion of the semiconductor layer. | 2014-09-25 |
20140284594 | DISPLAY DEVICE, THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING DISPLAY DEVICE, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR - According to one embodiment, a display device includes a substrate unit, a thin film transistor, a pixel electrode and a display layer. The substrate unit includes a substrate, a first insulating layer provided on the substrate, and a second insulating layer provided on the first insulating layer. The thin film transistor is provided on the substrate unit and includes a gate electrode provided on the second insulating layer, a semiconductor layer of an oxide separated from the gate electrode, a gate insulation layer provided between the gate electrode and the semiconductor layer, a first conductive portion, a second conductive portion, and a third insulating layer. The pixel electrode is connected to one selected from the first and second conductive portions. The display layer is configured to have a light emission or a change of optical characteristic occurring according to a charge supplied to the pixel electrode. | 2014-09-25 |
20140284595 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device for miniaturization is provided. The semiconductor device includes a semiconductor layer; a first electrode and a second electrode that are on the semiconductor layer and apart from each other over the semiconductor layer; a gate electrode over the semiconductor layer; and a gate insulating layer between the semiconductor layer and the gate electrode. The first and second electrodes comprise first conductive layers and second conductive layers. In a region overlapping with the semiconductor layer, the second conductive layers are positioned between the first conductive layers, and side surfaces of the second conductive layers are in contact with side surfaces of the first conductive layers. The second conductive layers have smaller thicknesses than those of the first conductive layers, and the top surface levels of the second conductive layers are lower than those of the first conductive layers. | 2014-09-25 |
20140284596 | OXIDE SEMICONDUCTOR - To provide an oxide semiconductor with a novel structure. Such an oxide semiconductor is composed of an aggregation of a plurality of InGaZnO | 2014-09-25 |
20140284597 | OXIDE SEMICONDUCTOR FILM AND METHOD FOR FORMING OXIDE SEMICONDUCTOR FILM - To improve crystallinity of an oxide semiconductor. To provide a crystalline oxide semiconductor film in which a crystallized region extends to the interface with a base or the vicinity of the interface, and to provide a method for forming the oxide semiconductor film. An oxide semiconductor film containing indium, gallium, and zinc is formed, and the oxide semiconductor film is irradiated with an energy beam, thereby being heated. Note that the oxide semiconductor film includes a c-axis aligned crystal region or microcrystal. | 2014-09-25 |
20140284598 | UV PHOTODETECTORS HAVING SEMICONDUCTOR METAL OXIDE LAYER - A method of forming an ultraviolet (UV) photodetector includes forming an epitaxial semiconductor metal oxide layer on a substrate, wherein the forming includes using an O | 2014-09-25 |
20140284599 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A first oxide insulating film is formed over a substrate. After a first oxide semiconductor film is formed over the first oxide insulating film, heat treatment is performed, so that hydrogen contained in the first oxide semiconductor film is released and part of oxygen contained in the first oxide insulating film is diffused into the first oxide semiconductor film. Thus, a second oxide semiconductor film with reduced hydrogen concentration and reduced oxygen defect is formed. Then, the second oxide semiconductor film is selectively etched to form a third oxide semiconductor film, and a second oxide insulating film is formed. The second oxide insulating film is selectively etched and a protective film covering an end portion of the third oxide semiconductor film is formed. Then, a pair of electrodes, a gate insulating film, and a gate electrode are formed over the third oxide semiconductor film and the protective film. | 2014-09-25 |
20140284600 | ARITHMETIC CIRCUIT AND METHOD OF DRIVING THE SAME - In order to reduce power consumption, an arithmetic circuit having a function of performing a logic operation processing based on an input signal, storing a potential set in accordance with the result of the logic operation processing as stored data, and outputting a signal with a value corresponding to the stored data as an output signal. The arithmetic circuit includes an arithmetic portion performing the logic operation processing, a first field-effect transistor controlling whether a first potential, which is the potential corresponding to the result of the logic operation processing is set, and a second field-effect transistor controlling whether the potential of the output signal data is set at a second potential which is a reference potential. | 2014-09-25 |
20140284601 | THIN FILM TRANSISTOR - A thin film transistor including an oxide semiconductor with favorable electrical characteristics is provided. The thin film transistor includes a gate electrode provided over a substrate, a gate insulating film provided over the gate electrode, an oxide semiconductor film provided over the gate electrode and on the gate insulating film, a metal oxide film provided on the oxide semiconductor film, and a metal film provided on the metal oxide film. The oxide semiconductor film is in contact with the metal oxide film, and includes a region whose concentration of metal is higher than that of any other region in the oxide semiconductor film (a high metal concentration region). In the high metal concentration region, the metal contained in the oxide semiconductor film may be present as a crystal grain or a microcrystal. | 2014-09-25 |
20140284602 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes an oxide semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate. | 2014-09-25 |
20140284603 | COMPOSITE MICRO-ELECTRO-MECHANICAL-SYSTEM APPARATUS AND MANUFACTURING METHOD THEREOF - A MEMS apparatus comprising composite vibrating unit and the manufacturing method thereof are disclosed. The vibrating unit includes a stiffness element on which a first material is disposed. A second material being a conductive material is disposed on the first material and is extended to the stiffness element to remove electric charge on first material. When a temperature is changed, a variation direction of a Young's modulus of the first material is opposite to a variation direction of a Young's modulus of the stiffness element. The unique attributes above allow vibrating unit of the MEMS apparatus such as resonator and gyroscope to have stable resonance frequency against the change of temperature. | 2014-09-25 |
20140284604 | SEMICONDUCTOR STRUCTURE FOR EXTREME ULTRAVIOLET ELECTROSTATIC CHUCK WITH REDUCED CLAMPING EFFECT - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate. | 2014-09-25 |
20140284605 | TFT-PIN ARRAY SUBSTRATE AND ASSEMBLY STRUCTURE FOR FLAT-PANEL X-RAY DETECTOR - A TFT-PIN array substrate and an assembly structure for a flat-panel x-ray detector are provided to overcome the problem that the conventional scintillator substrate and TFT-PIN array substrate are neither penetrated by UV-light nor assembled by UV curable LOCA. The metal layer of the PIN photodiode of the TFT-PIN array substrate is perforated to have at least one hole, whereby UV-light can pass through the TFT-PIN array substrate to cure UV curable LOCA. Therefore, UV curable LOCA can be used as an adhesive layer in the assembly structure of a scintillator substrate and a TFT-PIN array substrate to promote the detective quantum efficiency and image quality of a flat-panel X-Ray detector. | 2014-09-25 |
20140284606 | METHOD OF FABRICATING PIXEL STRUCTURE AND PIXEL STRUCTURE THEREOF - A method for fabricating a pixel structure includes the following steps. A patterned semiconductor layer, an insulation layer, and a patterned metal layer are formed on a substrate sequentially. A first inter-layer dielectric (ILD) layer is formed to cover the patterned metal layer. A low temperature annealing process is performed after forming the first ILD layer. A hydrogen plasma treatment process is performed after the low temperature annealing process. A second ILD layer is formed to cover the first ILD layer after the hydrogen plasma treatment process. A third ILD layer is formed to cover the second ILD layer. A source electrode and a drain electrode are formed on the third ILD layer. A passivation layer is formed on the source electrode and the drain electrode. A pixel electrode is formed on the passivation layer. A pixel structure manufactured by the above-mentioned method is also provided. | 2014-09-25 |
20140284607 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In this embodiment, a mask material is formed above a film to be processed, and a plurality of sacrifice films are formed above the mask material, each of the sacrifice films having a columnar shape. Then, a sidewall film is formed on a sidewall of the sacrifice films, and then the sacrifice films are removed. Thereafter, the sidewall films are caused to flow. In addition, a plurality of holes are formed in the mask material using the sidewall film as a mask. Then, isotropic etching is performed for the mask material to etch back the sidewall of the mask material with respect to a sidewall of the sidewall film by a first distance. Thereafter, a deposition layer is deposited inside the plurality of holes to close an opening of the plurality of holes with the deposition layer. Anisotropic etching is conducted to remove the deposition layer in the opening. | 2014-09-25 |
20140284608 | LASER ANNEALING APPARATUS AND METHOD, AND DISPLAY APPARATUS MANUFACTURED BY THIS METHOD - A laser annealing apparatus reduces laser annealing time and has a simple configuration. A laser annealing method is used to manufacture a display apparatus. The laser annealing apparatus includes a mounting unit, a substrate mounted on the mounting unit, first and second driving modules installed on the mounting unit and adjusting locations of first and second mark masks to be placed on a part of the substrate, first and second image modules that may obtain image data regarding the first and second mark masks to be location-adjusted by first and second driving modules, and a laser module that radiates a laser beam to the substrate and changes at least a part of an amorphous silicon layer of the substrate to crystalline silicon. | 2014-09-25 |
20140284609 | Method and Substrate for Thick III-N Epitaxy - A method of manufacturing an III-N substrate includes bonding a Si substrate to a support substrate, the Si substrate having a (111) growth surface facing away from the support substrate, thinning the Si substrate at the (111) growth surface to a thickness of 100 μm or less, and forming III-N material on the (111) growth surface of the Si substrate after the Si substrate is thinned. The support substrate has a coefficient of thermal expansion more closely matched to that of the III-N material than the Si substrate. Other methods of manufacturing an III-N substrate are disclosed, as well as the corresponding wafer structures. | 2014-09-25 |
20140284610 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode. | 2014-09-25 |
20140284611 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a method for manufacturing a semiconductor light-emitting device includes growing a semiconductor film including a group III nitride semiconductor on a silicon substrate, dividing the grown semiconductor film into a plurality of sections by selectively removing the semiconductor film, forming an aluminum film to cover the semiconductor film, removing the aluminum film selectively, oxidizing the remained aluminum film, and removing the silicon substrate. | 2014-09-25 |
20140284612 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - A light emitting diode includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer stacked on a face of the substrate successively, a first electrode electrically connected to the first semiconductor layer, and a second electrode electrically connected to the second semiconductor layer. The first semiconductor layer is disposed adjacent to the substrate. A plurality of nanoscale holes are defined in the face of the substrate contacting the first semiconductor layer. A method for manufacturing the light emitting diode is also provided. | 2014-09-25 |
20140284613 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes a nitride semiconductor layer, a gate electrode provided above the nitride semiconductor layer, a source electrode provided above the nitride semiconductor layer, a drain electrode provided above the nitride semiconductor layer at a side opposite to the source electrode with respect to the gate electrode, a first silicon nitride film provided above the nitride semiconductor layer between the drain electrode and the gate electrode, and a second silicon nitride film provided between the nitride semiconductor layer and the gate electrode, an atomic ratio of silicon to nitrogen in the second silicon nitride film being lower than an atomic ratio of silicon to nitrogen in the first silicon nitride film. | 2014-09-25 |
20140284614 | METHODS FOR EPITAXIAL DEVICES - Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride. | 2014-09-25 |
20140284615 | METHOD FOR MANUFACTURING A SILICON CARBIDE DEVICE AND A SILICON CARBIDE DEVICE - A method for manufacturing a silicon carbide device includes providing a silicon carbide wafer and manufacturing a mask layer on top of the silicon carbide wafer. Further, the method includes structuring the mask layer at an edge of a silicon carbide device to be manufactured, so that the mask layer includes a bevel at the edge of the silicon carbide device to be manufactured. Additionally, the method includes etching the mask layer and the silicon carbide wafer by a mutual etching process, so that the bevel of the mask layer is reproduced at the edge of the silicon carbide device. | 2014-09-25 |
20140284616 | SELF-FORMATION OF HIGH-DENSITY ARRAYS OF NANOSTRUCTURES - A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer. | 2014-09-25 |
20140284617 | SEMICONDUCTOR DEVICE - According to embodiments, a semiconductor device includes an insulating substrate, a first electrode plate disposed on the insulating substrate, a second electrode plate disposed on the insulating substrate, a third electrode plate disposed on the insulating substrate, a first semiconductor element disposed on the first electrode plate, a first electrode of the first semiconductor element being electrically connected to the first electrode plate, a second semiconductor element disposed on the second electrode plate, a first electrode of the second semiconductor element being electrically connected to the second electrode plate, a first bonding wire electrically connecting a second electrode of the first semiconductor element to the third electrode plate, and a second bonding wire electrically connecting a second electrode of the second semiconductor element to the third electrode plate. | 2014-09-25 |
20140284618 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - An aspect of the present embodiment, there is provided a semiconductor device, including a first electrode, a first semiconductor layer having a first conductive type connected to the first electrode, a second semiconductor layer having a second conductive type contacted to the first semiconductor layer, a third semiconductor layer having the first conductive type, an impurity concentration of the third semiconductor layer being smaller than an impurity concentration of the second semiconductor layer, the third semiconductor layer contacting to the second semiconductor layer to be separated from the first semiconductor layer by the second semiconductor layer, a gate insulator provided on the second semiconductor layer, and the first semiconductor layer and the third semiconductor layer arranged at both sides of the second semiconductor layer, respectively, a gate electrode on the gate insulator; and a second electrode connected to the third semiconductor layer. | 2014-09-25 |
20140284619 | SIC EPITAXIAL WAFER AND SEMICONDUCTOR DEVICE - An SiC epitaxial wafer of an embodiment includes, an SiC substrate, and a p-type first SiC epitaxial layer that is formed on the SiC substrate and contains a p-type impurity and an n-type impurity. An element A and an element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus) when the p-type impurity is the element A and the n-type impurity is the element D. The ratio of the concentration of the element D to the concentration of the element A in the combination(s) is higher than 0.33 but lower than 1.0. | 2014-09-25 |
20140284620 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes an n-type SiC substrate, an n-type SiC layer formed on the SiC substrate; a p-type first SiC region formed in the surface of the SiC layer and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the concentration of the element A in the combination(s) being higher than 0.33 but lower than 0.995, the concentration of the element A forming part of the combination(s) being not lower than 1×10 | 2014-09-25 |
20140284621 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes an n-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element A to the concentration of the element D in the above combination is higher than 0.40 but lower than 0.95, and the concentration of the element D forming the above combination is not lower than 1×10 | 2014-09-25 |
20140284622 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes a p-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element D to the concentration of the element A in the above combination is higher than 0.33 but lower than 0.995, and the concentration of the element A forming part of the above combination is not lower than 1×10 | 2014-09-25 |
20140284623 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes, an n-type SiC substrate that has first and second faces, and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus), the ratio of the concentration of the element A to the concentration of the element D in the combination(s) being higher than 0.40 but lower than 0.95, the concentration of the element D forming the combination(s) being not lower than 1×10 | 2014-09-25 |
20140284624 | Semiconductor Component, Semiconductor Module and Methods for Producing a Semiconductor Component and a Semiconductor Module - A semiconductor component includes a semiconductor body having a top side and a bottom side opposite the top side. A top metallization is applied to the top side and a bottom metallization is applied to the bottom side. A moisture barrier completely seals the semiconductor body in cooperation with the top metallization and the bottom metallization. | 2014-09-25 |
20140284625 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n | 2014-09-25 |
20140284626 | ENHANCED DISLOCATION STRESS TRANSISTOR - A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation. | 2014-09-25 |
20140284627 | WAFER AND METHOD OF FABRICATING THE SAME - Disclosed is a method of manufacturing a thin film, the method including: growing an epitaxial layer on a surface of a wafer at a growth temperature, wherein the growing of the epitaxial layer comprises controlling a defect present on a surface of the wafer. Also, disclosed is a wafer including: a substrate; and an epitaxial layer located on the substrate, wherein a basal dislocation density of the epitaxial layer is equal to or less than 1/cm2. | 2014-09-25 |
20140284628 | WAFER AND METHOD OF FABRICATING THE SAME - Disclosed is a method of manufacturing a thin film, the method including: growing an epitaxial layer on a surface of a wafer at a growth pressure, wherein the growing of the epitaxial layer comprises controlling a defect present on a surface of the wafer. Also, disclosed is a wafer including: a substrate; and a buffer layer and an epitaxial layer located on the substrate, wherein a surface dislocation density of the epitaxial layer is equal to or less than 1/cm2. | 2014-09-25 |
20140284629 | PHOTOCOUPLER - According to one embodiment, a photocoupler includes a light emitting element, a light receiving element, a bonding layer, input terminals, output terminals and a molded resin body. A light emitting element includes a transparent support substrate, a semiconductor stacked body, and first and second electrodes. A light receiving element includes a light reception surface, a first electrode, and a second electrode. A bonding layer is configured to bond the first surface of the support substrate to the light reception surface side of the light receiving element. The bonding layer is transparent and insulative. Input terminals are connected to the first and second electrodes of the light emitting element. Output terminals are connected to the first and second electrodes of the light receiving element. The light reception surface is included in the light emitting surface. An input electrical signal is converted into an output electrical signal. | 2014-09-25 |
20140284630 | OPTICAL COUPLING DEVICE - According to one embodiment, an optical coupling device includes a light emitting element configured to convert an electric signal into an optical signal, a photo transistor circuit configured to convert the optical signal into a current, the photo transistor circuit including a first transistor having a collector connected to a power source and an emitter through which the current is output, and a current mirror circuit including a second transistor having a collector connected to the emitter of the first transistor, a base connected to the emitter of the first transistor, and an emitter connected to a ground, and a third transistor having a collector connected to an output terminal, a base connected to the base of the second transistor, and a emitter connected to the ground. | 2014-09-25 |
20140284631 | METHOD AND SYSTEM FOR GENERATING A PHOTO-RESPONSE FROM MoS2 SCHOTTKY JUNCTIONS - Devices incorporating a single to a few-layer MoS | 2014-09-25 |
20140284632 | DISPLAY DEVICE HAVING MEMS TRANSMISSIVE LIGHT VALVE AND METHOD FOR FORMING THE SAME - A display device having a MEMS transmissive light valve and a method for forming the same are provided. The method includes: providing a multilayer semiconductor substrate comprising a bottom semiconductor layer, a middle buried layer and a top semiconductor layer; forming a light guide opening in the top semiconductor layer; forming at least one MOS device in a remaining part of the top semiconductor layer; forming an interconnection layer and an interlayer dielectric layer on the at least one MOS; forming a MEMS transmissive light valve, which is electrically connected to the interconnection layer, on the light guide opening, where the MEMS transmissive light valve is surrounded by the interlayer dielectric layer; forming a transparent backplane on a top surface of the interlayer dielectric layer; and removing the bottom semiconductor layer. | 2014-09-25 |
20140284633 | STACKED LIGHT EMITTING DIODE ARRAY STRUCTURE - The present invention provides a stacked LED array structure, comprising a substrate and a plurality of LED dies stacked on the substrate in turn. Each LED die comprises a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is provided thereon with a first electrode and stacked with the second semiconductor layer, while the second semiconductor layer is provided thereon with a second electrode and stacked with the first semiconductor layer of another LED die. The second electrode of each LED die is connected to the first electrode of another LED die in series via a metal layer to from an LED array. A plurality of LED dies may be stacked to be an LED array in a stacked manner, resulting in not only easy manufacturing, but also an effectively reduced volume for arranging the whole LED array. | 2014-09-25 |
20140284634 | LIGHT-EMISSION ELEMENT ASSEMBLY AND METHOD OF MANUFACTURING SAME, AS WELL AS DISPLAY - A light-emission element assembly includes: a light-emission element; a mold section in which the light-emission element is molded; a pad section protruding from an undersurface of the mold section, and electrically connected to the light-emission element; and a reinforcement section provided in the pad section, and projecting towards a side on which the mold section is provided. | 2014-09-25 |
20140284635 | INTEGRATED POWER SUPPLY ARCHITECTURE FOR LIGHT EMITTING DIODE-BASED DISPLAYS - An integrated circuit including a die of the integrated circuit, the die including an insulating layer, light emitting diodes, a semiconductor layer, and a control module. The insulating layer includes a first side and a second side. The second side is opposite to the first side. The light emitting diodes are arranged on the first side of the insulating layer. The semiconductor layer is arranged adjacent to the second side of the insulating layer. The light emitting diodes are connected to the semiconductor layer using connections from the first side of the insulating layer to the second side of the insulating layer. The control module is arranged on the semiconductor layer. The control module is configured to output pulse width modulated pulses to the light emitting diodes via the connections. | 2014-09-25 |
20140284636 | WHITE LIGHT SOURCE AND WHITE LIGHT SOURCE SYSTEM INCLUDING THE SAME - The present invention provides a white light source comprising: a light emitting diode (LED) having a light emission peak wavelength in a range of 350 or more and 420 nm or less; and a phosphor layer including four or more types of phosphors and resin, wherein the white light source satisfies a relational equation of: −0.2≦[(P(λ)×V(λ))/(P(λmax1)×V(λmax1))−(B(λ)×V(λ))/(B(λmax2)×V(λmax2))]≦+0.2, assuming that: a light emission spectrum of the white light source is P(λ); a light emission spectrum of black-body radiation having a same color temperature as that of the white light source is B(λ); a spectrum of a spectral luminous efficiency is V(λ); a wavelength at which P(λ)×V(λ) becomes largest is λmax1; and a wavelength at which B(λ)×V(λ) becomes largest is λmax2, and wherein an amount (difference) of chromaticity change on CIE chromaticity diagram from a time of initial lighting up of the white light source to a time after the white light source is continuously lighted up for 6000 hours is less than 0.010. According to the above white light source, there can be provided a white light source capable of reproducing the same light emission spectrum as that of natural light. | 2014-09-25 |
20140284637 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method for manufacturing a semiconductor light emitting device includes performing plasma processing of a stacked body. The stacked body has a first semiconductor layer and a second semiconductor layer provided on the first semiconductor layer. The plasma processing is performed on a surface of the stacked body where the second semiconductor layer is exposed such that the second semiconductor layer remains. The first semiconductor layer includes gallium and nitrogen. The second semiconductor layer includes aluminum and nitrogen. The method includes forming a plurality of protrusions by performing wet etching of the surface after the plasma processing is performed. At least a lower portion of the plurality of protrusions is made of the first semiconductor layer. | 2014-09-25 |
20140284638 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - A nitride semiconductor light emitting device includes a laminate, first and second electrodes, a conductive layer, and a phosphor layer. The laminate includes a first layer including a first electroconductive-type layer, a second layer including a second electroconductive-type layer, a light emitting layer between the first and second layers, and a nitride semiconductor. The laminate has a recessed portion extending from the first layer to the second layer in a central portion or an outer peripheral portion. The first electrode arranged on the first layer reflects light emitted from the light emitting layer. The second electrode is surrounded by the light emitting layer or on the periphery thereof and connected to a bottom surface of the recessed portion. The conductive layer is arranged on a surface of the second layer at a side opposite to the light emitting layer. The phosphor layer overlies the second layer and the conductive layer. | 2014-09-25 |
20140284639 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode (LED) package includes a substrate, a first electrode and a second electrode embedded in the substrate and spaced from each other, an LED die mounted on a top surface of the substrate and electrically connected to the first and the second electrodes. Both the first and the second electrodes include a top face and a bottom face, with the top face and the bottom face of each of the first and the second electrodes being exposed at the top surface and a bottom surface of the substrate, respectively. The top face of the first electrode defines a first groove corresponding to a positive bonding pad (p-pad) of the LED die. The p-pad is partially inserted into the first groove. An oxidation-resistant metal coating layer is filled between an insertion portion of the p-pad and an inner surface of the first groove. | 2014-09-25 |
20140284640 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode (LED) package includes a substrate, a first electrode, a second electrode, an LED die mounted on the substrate and electrically connected to the first and the second electrodes, and an encapsulation layer encapsulating the LED die. Both the first and the second electrodes are embedded in the substrate and spaced from each other. Each of the first and the second electrodes includes a top face and a bottom face, with the top face and the bottom face thereof being exposed at a top surface and a bottom surface of the substrate, respectively. The top face of the first electrode defines a first groove therein. An oxidation-resistant metal coating layer is filled in the first groove. A positive bonding pad of the LED die directly contacts with a top face of the first oxidation-resistant metal coating layer. | 2014-09-25 |
20140284641 | LED PACKAGES AND MANUFACTURING METHOD THEREOF - A method of manufacturing LED packages includes the steps of: forming a conductive circuit layer on a substrate; screen printing a wall layer on the conductive circuit layer to form a trellis with a plurality of wall units, so that regions of the conductive circuit layer surrounded by the wall units are exposed; mounting and electrically connecting at least one LED die on the conductive circuit layer within each of the wall units; molding a transparent layer to cover the LED dies; and cutting along the wall units to form a plurality of LED packages. | 2014-09-25 |
20140284642 | Light-Emitting Module and Light-Emitting Device - A light-emitting module which efficiently extracts light emitted from a light-emitting element is provided. Alternatively, a light-emitting module having lower power consumption or improved reliability is provided. A light-emitting module includes a window material having a light-transmitting property, a light-emitting element that emits light transmitted from a light-transmitting layer to the window material, and an optical bonding layer between the window material and the light-transmitting layer. The optical bonding layer includes a thick part overlapping the light-emitting element and a thin part surrounding the thick part. The light-transmitting layer, the optical bonding layer, and the window material are provided in decreasing order of refractive index. | 2014-09-25 |
20140284643 | POWER SURFACE MOUNT LIGHT EMITTING DIE PACKAGE - A light emitting die package is provided which includes a metal substrate having a first surface and a first conductive lead on the first surface. The first conductive lead is insulated from the substrate by an insulating film. The first conductive lead forms a mounting pad for mounting a light emitting device. The package includes a metal lead electrically connected to the first conductive lead and extending away from the first surface. | 2014-09-25 |
20140284644 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention is directed to reduction of angle dependence of chromaticity in a phosphor layer, without using a light scattering agent, the phosphor layer being made up of phosphor particles adhered tightly to one another via a binder according to the spray coating method. The phosphor layer contains phosphor particles laid along the top surface of the light emitting element and the binder embedded into a gap between the phosphor particles, and the phosphor layer does not contain the light scattering agent. The area of a region on the upper surface of the phosphor layer is between or equal to 3% and 10% with respect to the area of the top surface of the light emitting element, the region being positioned at the gap between the phosphor particles and allowing the light being outputted to pass through the binder and directly reach the upper surface of the phosphor layer. This configuration makes the asperities smaller on the surface of the phosphor layer and reduces the angular dependence of chromaticity. | 2014-09-25 |
20140284645 | OPTOELECTRONIC SEMICONDUCTOR COMPONENT - An optoelectronic semiconductor component includes an optoelectronic semiconductor chip having side areas covered by a shaped body, at least one plated-through hole including an electrically conductive material, and an electrically conductive connection electrically conductively connected to the semiconductor chip and the plated-through hole, wherein, the plated-through hole is arranged in a manner laterally spaced apart from the semiconductor chip, the plated-through hole completely penetrates through the shaped body, and the plated-through hole extends from a top side of the shaped body to an underside of the shaped body, the electrically conductive connection extends at the top side of the shaped body. | 2014-09-25 |
20140284646 | LIGHT GENERATING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light generating device and a method of manufacturing the light generating device are disclosed. The light generating device includes a p-type semiconductor layer, an n-type semiconductor layer, an active layer, a p-type electrode and an n-type electrode. The active layer is disposed between the p-type semiconductor layer and the n-type semiconductor layer. The p-type electrode provides the p-type semiconductor layer with holes. The n-type electrode provides the n-type semiconductor layer with electrons. At least one of the p-type electrode and n-type electrode has a protrusion protruding toward p-type semiconductor layer and the n-type semiconductor layer, respectively. Therefore, light efficiency is enhanced. | 2014-09-25 |
20140284647 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device has a light emitting element, a first electrode layer, a second electrode layer, a seed electrode layer and a plated layer. The light emitting element has a nitride-based III-V compound semiconductor on a substrate. The light emitting element having a light extraction surface. The first electrode layer on the light extraction surface. The second electrode layer is provided on a surface opposite to the light extraction surface of the light emitting element. The seed electrode layer is configured to cover the entire surface of the second electrode layer. The plated layer is provided on the seed electrode layer. The light emitting element has a light emitting layer, a first conductive type semiconductor layer, and a second conductive type semiconductor layer. The light emitting element has a forward tapered shape of a width which gradually narrows in order of the second conductive type semiconductor layer, the light emitting layer and the first conductive type semiconductor layer. | 2014-09-25 |
20140284648 | LIGHT EMITTING DEVICE WITH MOLDED WAVELENGTH CONVERTING LAYER - A flexible film comprising a wavelength converting material is positioned over a light source. The flexible film is conformed to a predetermined shape. In some embodiments, the light source is a light emitting diode mounted on a support substrate. The diode is aligned with an indentation in a mold such that the flexible film is disposed between the support substrate and the mold. Transparent molding material is disposed between the support substrate and the mold. The support substrate and the mold are pressed together to cause the molding material to fill the indentation. The flexible film conforms to the shape of the light source or the mold. | 2014-09-25 |
20140284649 | OPTOELECTRONIC COMPONENT AND PHOSPHORS - An optoelectronic component includes a layer sequence having an active region that emits primary electromagnetic radiation, wherein the primary electromagnetic radiation has a wavelength of 430 nm to 470 nm, a conversion material arranged in a beam path of the primary electromagnetic radiation and at least partly converts the primary electromagnetic radiation into a secondary electromagnetic radiation, wherein the conversion material includes a first phosphor having general composition A | 2014-09-25 |
20140284650 | LIGHT-EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING SAME - Disclosed are a light-emitting diode package and a method for manufacturing same. The method for manufacturing a light-emitting diode package comprises: preparing a package main body having a cavity and an air vent passageway which extends from the cavity; installing a light-emitting diode inside the cavity of the package main body; attaching a transparent member by means of an adhesive so as to cover the upper part of the cavity; and blocking the air vent passageway by forming a sealing member. As the air vent passageway is blocked after the transparent member is attached, the transparent member may be prevented from peeling off from the air pressure inside the cavity. | 2014-09-25 |
20140284651 | LIGHT-EMITTING DEVICE - A light-emitting device includes a thermally conductive substrate, a wiring electrode formed on the thermally conductive substrate, a resist formed on the wiring electrode except a terminal thereof, and a light-emitting element that is disposed in an element mounting region of the thermally conductive substrate and electrically connected to the terminal of the wiring electrode. A heat dissipation hole is formed in a region of the resist outside the element mounting region so as to expose a surface of the thermally conductive substrate. | 2014-09-25 |
20140284652 | METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE, AND LIGHT EMITTING DEVICE - A method for manufacturing a light emitting device comprises a package preparation step of preparing a package having a recess in which a light emitting element is locatable, wherein the package includes a projection extending from an upper surface of the package, the projection at least partially surrounding the recess, a sealing resin forming step of filling said recess in which said light emitting element is located with a sealing resin, and providing said sealing resin higher than the height of said package, and a sealing resin cutting step of cutting the sealing resin such that an upper surface of the sealing resin is at a height that is substantially the same as a height of the upper surface of the package. | 2014-09-25 |
20140284653 | METHOD OF MANUFACTURING A LIGHT GENERATING DEVICE AND LIGHT GENERATING DEVICE MANUFACTURED THROUGH THE SAME - A method of manufacturing a light generating device and a light generating device manufactured through the method are disclosed. The method of manufacturing a light generating device according to an exemplary embodiment of the present invention, includes preparing a semiconductor stacking structure including a p-type semiconductor layer, an n-type semiconductor layer and an active layer disposed between the p-type semiconductor layer and the n-type semiconductor layer; forming a metal thin film on the n-type semiconductor layer or on the p-type semiconductor layer; annealing the metal thin film to form a grain boundary at the metal thin film; applying liquid with graphite powder to the metal thin film with the grain boundary; thermally treating the semiconductor stacking structure to which the liquid with graphite power is applied; and removing the metal thin film with the grain boundary. | 2014-09-25 |
20140284654 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a semiconductor film, an electrode, a passivation film, a sealing resin body, and an intermediate film. The semiconductor film contains a Group III nitride semiconductor. The electrode is connected to a first surface of the semiconductor film. The passivation film covers an end surface of the semiconductor film and the first surface. The sealing resin body covers the first surface and a side surface of the electrode to leave a second surface of the semiconductor film exposed. The intermediate film is provided between the passivation film and the sealing resin body. The absolute value of the difference between an internal stress of the intermediate film and that of the sealing resin body is less than the absolute value of the difference between an internal stress of the passivation film and that of the sealing resin body. | 2014-09-25 |
20140284655 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment is provided with a normally-off transistor having a first source connected to a source terminal, a first drain, and a first gate connected to a gate terminal and a normally-on transistor having a second source connected to the first drain, a second drain connected to a drain terminal, and a second gate connected to the source terminal. A withstand voltage between the first source and the first drain when the normally-off transistor is turned off is lower than a withstand voltage between the second source and the second gate of the normally-on transistor. | 2014-09-25 |
20140284656 | MOS SEMICONDUCTOR DEVICE - An MOS semiconductor device including an MOS gate structure is disclosed. The MOS semiconductor device includes a p-type well region selectively disposed on the surface layer of an n-type drift layer formed on a semiconductor substrate forming an n-type drain region; an n-type source region selectively disposed on the surface layer of the p-type well region; and a gate electrode placed, via an insulating film, on the surface of a channel formation region on the surface layer of the p-type well region sandwiched between the n-type source region and the surface layer of the n-type drain region, wherein a surface in the channel formation region has a level difference formed in the direction of the peripheral length, and all over the length, of the channel formation region. | 2014-09-25 |
20140284657 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A p anode layer ( | 2014-09-25 |
20140284658 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first and second electrode, a first, second, third and fourth semiconductor region, and a first intermediate metal film. The first region is provided above the first electrode and has a first impurity concentration. The second region is provided above the first region and has a second impurity concentration lower than the first impurity concentration. The third region is provided above the second region and has a third impurity concentration. The fourth region is provided above the second region and has a fourth impurity concentration lower than the third impurity concentration. The second electrode is provided above the third region and the fourth region and is in ohmic contact with the third region. The intermediate metal film is provided between the second electrode and the fourth region. The intermediate metal film forms Schottky junction with the fourth region. | 2014-09-25 |
20140284659 | Transient Voltage Suppressor, Design and Process - A transient voltage suppressor (TVS) device design compatible with normal IC wafer process is provided. Instead of a thick base that requires double-sided wafer processing, a much thinner base with a modulated doping profile is used. In this base, a high doping layer is sandwiched by two lower layers of the same or different doping. The base is then sandwiched by two electrodes having opposite doping relative to the base center layer. In the base, the two lower doping layers will determine the breakdown voltage. The middle layer is used to reduce the transistor gain and thus produce an acceptable snapback characteristic. The presence of the higher doped middle layer allows the total base width to be as low as 5 μm for a breakdown voltage of about 30 V. | 2014-09-25 |
20140284660 | METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER - A method for manufacturing a semiconductor wafer includes the steps of forming, on a first principal surface of a substrate, a compound semiconductor layer different in kind from the substrate, and removing, by etching, a part of the compound semiconductor layer. The part of the compound semiconductor layer is formed on an outer peripheral portion of the first principal surface of the substrate. | 2014-09-25 |
20140284661 | MONOLITHIC INTEGRATED CIRCUIT (MMIC) STRUCTURE AND METHOD FOR FORMING SUCH STRUCTURE - A method for forming a semiconductor structure having a transistor device with a control electrode for controlling a flow of carriers between a first electrode and a second electrode. A passivation layer is deposited over the first electrode, the second electrode and the control electrode. An etch stop layer is deposited on the passivation layer over the control electrode. A dielectric layer is formed over the etch stop layer. A window is etched through a selected region in the dielectric layer over the control electrode, to expose a portion of the etch stop layer disposed over the control electrode. A metal layer is formed on a portion of the etch stop layer and the dielectric layer is also formed on the metal layer. A second metal layer is deposited on the portion of the dielectric layer formed on the first mentioned metal layer. | 2014-09-25 |
20140284662 | SEMICONDUCTOR DEVICE - A semiconductor device of an embodiment includes a normally-off transistor having a first source electrically connected to a source terminal, a first drain, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second source electrically connected to the first drain, a second drain electrically connected to a drain terminal, and a second gate, a capacitor having one end electrically connected to the gate terminal and the other end electrically connected to the second gate; and a first diode having a first anode electrically connected to the capacitor and the second gate and a first cathode electrically connected to the first source. | 2014-09-25 |
20140284663 | Method of Manufacturing an imager and imager device - Embodiments related to a method of manufacturing of an imager and an imager device are shown and depicted. | 2014-09-25 |
20140284664 | IMAGE SENSORS INCLUDING A GATE ELECTRODE SURROUNDING A FLOATING DIFFUSION REGION - Image sensors are provided. The image sensors may include first and second stacked impurity regions having different conductivity types. The image sensors may also include a floating diffusion region in the first impurity region. The image sensors may further include a transfer gate electrode surrounding the floating diffusion region in the first impurity region. Also, the transfer gate electrode and the floating diffusion region may overlap the second impurity region. | 2014-09-25 |
20140284665 | SOLID-STATE IMAGING DEVICE, PRODUCTION METHOD THEREOF, AND ELECTRONIC APPARATUS - There is provided a solid-state imaging device including a pixel array unit in which pixels are arrayed in a two-dimensional manner, each of the pixels including a plurality of photoelectric conversion elements and a floating diffusion configured to accumulate an electric charge from the plurality of photoelectric conversion elements, wherein the floating diffusion is shared by at least two or more of the photoelectric conversion elements, and wherein one or more of the plurality of photoelectric conversion elements include a transfer gate configured to transfer an electric charge between the photoelectric conversion elements that are adjacent. | 2014-09-25 |
20140284666 | INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL - A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate. | 2014-09-25 |
20140284667 | FINFET WITH REDUCED CAPACITANCE - An improved finFET structure, and method forming the same, including a plurality of fins etched from a semiconductor substrate, a plurality of gates above and perpendicular to the plurality of fins, each comprising a pair of spacers on opposing sides of the gates, and a gap fill material above the semiconductor substrate, below the gate, and between the plurality of fins, wherein the gate separates the gap fill material from each of the plurality of fins. | 2014-09-25 |
20140284668 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object of the present invention is to provide a semiconductor device having a conductive film, which sufficiently serves as an antenna, and a method for manufacturing thereof. The semiconductor device has an element formation layer including a transistor, which is provided over a substrate, an insulating film provided on the element formation layer, and a conductive film serving as an antenna, which is provided on the insulating film. The insulating film has a groove. The conductive film is provided along the surface of the insulating film and the groove. The groove of the insulating film may be provided to pass through the insulating film. Alternatively, a concave portion may be provided in the insulating film so as not to pass through the insulating film. A structure of the groove is not particularly limited, and for example, the groove can be provided to have a tapered shape, etc. | 2014-09-25 |
20140284669 | OPTOELECTRONIC INTEGRATED DEVICE INCLUDING A PHOTODETECTOR AND A MOSFET TRANSISTOR, AND MANUFACTURING PROCESS THEREOF - An optoelectronic integrated device includes a body made of semiconductor material, which is delimited by a front surface and includes a substrate having a first type of conductivity, an epitaxial region, which has the first type of conductivity and forms the front surface, and a ring region having a second type of conductivity, which extends into the epitaxial region from the front surface, and delimiting an internal region. The optoelectronic integrated device moreover includes a MOSFET including at least one body region having the second type of conductivity, which contacts the ring region and extends at least in part into the internal region from the front surface. A photodetector includes a photodetector region having the second type of conductivity, and extends into the semiconductor body starting from the front surface, contacting the ring region. | 2014-09-25 |
20140284670 | SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING SOLID-STATE IMAGING ELEMENT, AND SEMICONDUCTOR DEVICE - A solid-state imaging device includes a semiconductor substrate configured to include a solid-state imaging element that is provided with a photoelectric conversion region, and a scribe line region that is provided along a periphery of the solid-state imaging element, a wiring layer that is formed to be layered on the semiconductor substrate, a support substrate that is formed to be layered on the wiring layer, and a groove that is provided between a blade region in the scribe line region and the solid-state imaging element, in the semiconductor substrate and penetrates through the semiconductor substrate. | 2014-09-25 |
20140284671 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross- sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure. | 2014-09-25 |
20140284672 | MEMORY DEVICE COMPRISING AN ARRAY PORTION AND A LOGIC PORTION - In an embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures. | 2014-09-25 |
20140284673 | Memory Device And Electronic Device - A selection operation is performed for individual memory cells. A device includes a first memory cell and a second memory cell provided in the same row as the first memory cell, each of which includes a field-effect transistor having a first gate and a second gate. The field-effect transistor controls at least data writing and data holding in the memory cell by being turned on or off. The device further includes a row selection line electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, a first column selection line electrically connected to the second gate of the field-effect transistor included in the first memory cell, and a second column selection line electrically connected to the second gate of the field-effect transistor included in the second memory cell. | 2014-09-25 |