39th week of 2014 patent applcation highlights part 29 |
Patent application number | Title | Published |
20140286076 | SEMICONDUCTOR DEVICE - A nonvolatile semiconductor device which can be driven at low voltage is provided. A nonvolatile semiconductor device with low power consumption is provided. A Schmitt trigger NAND circuit and a Schmitt trigger inverter are included. Data is held in a period when the supply of power supply voltage is continued, and a potential corresponding to the data is stored at a node electrically connected to a capacitor before a period when the supply of power supply voltage is stopped. By utilizing a change in channel resistance of a transistor whose gate is connected to the node, the data is restored in response to the restart of the supply of power supply voltage. | 2014-09-25 |
20140286077 | RESISTANCE CHANGE TYPE MEMORY - According to one embodiment, a resistance change type memory includes a first and a second bit lines, a memory cell connected between the first and second bit lines and including a variable resistance element as a memory element and a first select element including a first control terminal connected to a word line, and an auxiliary circuit connected to the first bit line and including a second select element including a second control terminal connected to a control line. When data is read from the memory cell, a first current in a read current supplied to the first bit line is supplied to the memory element and the first select element, and a second current in the read current is supplied to the second select element. | 2014-09-25 |
20140286078 | RESISTANCE CHANGE MEMORY - According to one embodiment, a memory includes a resistance change element connected between first and second conductive lines, a write buffer which writes data in the resistance change element by flowing a write current to the resistance change element through the first and second conductive lines in a writing, a current/voltage converter which converts the write current into a sense voltage, the converter provided in the write buffer, the write buffer being non-activated when the sense voltage is larger than a first threshold value. | 2014-09-25 |
20140286079 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A control circuit, on selecting a memory cell as a selected memory cell to perform a write operation, before executing the write operation, applies a first voltage to the selected memory cell via a first line and a second line to perform a first read operation. The control circuit, when judged that a result of the first read operation does not match write data intended to be written, executes the write operation. The control circuit, when judged that a result of the first read operation matches write data intended to be written, omits a voltage application operation for the write operation. | 2014-09-25 |
20140286080 | RESISTANCE CHANGE MEMORY - According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors. | 2014-09-25 |
20140286081 | RESISTANCE CHANGE MEMORY - According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other. | 2014-09-25 |
20140286082 | MEMORY DEVICE - According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node. | 2014-09-25 |
20140286083 | SYSTEMS AND METHODS OF PIPELINED OUTPUT LATCHING INVOLVING SYNCHRONOUS MEMORY ARRAYS - Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output. | 2014-09-25 |
20140286084 | MAGNETORESISTIVE ELEMENT - According to one embodiment, a magnetoresistive element comprises a storage layer having perpendicular magnetic anisotropy with respect to a film plane and having a variable direction of magnetization, a reference layer having perpendicular magnetic anisotropy with respect to the film plane and having an invariable direction of magnetization, a tunnel barrier layer formed between the storage layer and the reference layer and containing O, and an underlayer formed on a side of the storage layer opposite to the tunnel barrier layer. The reference layer comprises a first reference layer formed on the tunnel barrier layer side and a second reference layer formed opposite the tunnel barrier layer. The second reference layer has a higher standard electrode potential than the underlayer. | 2014-09-25 |
20140286085 | POWER SUPPLY CIRCUIT AND PROTECTION CIRCUIT - According to one embodiment, a power supply circuit includes a first circuit connected to a first line, to which a power supply voltage is applied, and a second line, and a power supply clamp circuit connected to the first and second lines. The power supply clamp circuit includes a current path circuit which connects the first and the second lines to each other, and a control circuit which outputs a control signal to the current path circuit. The current path circuit includes a transistor and a diode group. The power supply clamp circuit is driven during a period in which a first voltage is applied to the first line and controls a potential of the first line so as to become a potential lower than the first voltage. | 2014-09-25 |
20140286086 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address. | 2014-09-25 |
20140286087 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer configured to hold data input to an input/output circuit and to hold data read from the memory cell array, and a controller configured to receive a first command and an address from the outside and to read data, in response to the first command, from a memory cell group coupled to a selected word line designated by the address to the buffer. The controller receives a second command which is input after the first command and indicates a last command of a group of commands including write commands and/or read commands, and starts a write operation from the buffer to the memory cell array in response to the second command. | 2014-09-25 |
20140286088 | MEMORY DEVICE - According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series. The reference signal generator includes first to fourth global lines, and first and second ones of the unit structures. The first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line. The second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line. | 2014-09-25 |
20140286089 | SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM AND METHOD FOR DRIVING THE SAME - A semiconductor integrated circuit system includes a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell, a write current providing unit configured to phase-change a selected one of the first and second phase-change areas, and a phase-change compensation unit configured to restore the other of the first and second phase-change areas by compensating for a dummy phase-change caused in the other phase-change area due to a phase-change of the selected phase-change area. | 2014-09-25 |
20140286090 | SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM AND METHOD FOR DRIVING THE SAME - A semiconductor integrated circuit system includes a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell, a write current providing unit configured to phase-change a selected one of the first and second phase-change areas, and a phase-change compensation unit configured to restore the other of the first and second phase-change areas by compensating for a dummy phase-change caused in the other phase-change area due to a phase-change of the selected phase-change area. | 2014-09-25 |
20140286091 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a reference voltage generation circuit configured to generate a reference voltage, and a voltage changing circuit configured to generate a second voltage from a first voltage based on a difference between the second voltage and the reference voltage and apply the second voltage to a load capacitance. The reference voltage generation circuit includes a variable current source and a capacitor which are connected in series and is configured to change the reference voltage linearly. | 2014-09-25 |
20140286092 | MEMORY KINK CHECKING - This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell. | 2014-09-25 |
20140286093 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a NAND string and a sense amplifier. The NAND string includes a memory cell transistor to be capable of holding any of three or more levels of values. The NAND string includes one end connected to a bit line and the other end connected to a source line. The sense amplifier connects the bit line. A first voltage is applied to the source line when a first read voltage is applied to a selected word line connected to a selected memory cell transistor. A second voltage is applied to the source line when a second read voltage is applied to the selected word line. The first voltage is higher than the second voltage. The first read voltage is the lowest voltage of a plurality of read voltage. The second read voltage is higher than the first read voltage. | 2014-09-25 |
20140286094 | DATA MODULATION FOR GROUPS OF MEMORY CELLS - Methods, devices, and systems for data modulation for groups of memory cells. Data modulation for groups of memory cells can include modulating N units of data to a combination of programmed states. Each memory cell of a group of G number of memory cells can be programmed to one of M number of programmed states, where M is greater than a minimum number of programmed states needed to store N/G units of data in one memory cell, and where the programmed state of each memory cell of the group is one of the combination of programmed states. | 2014-09-25 |
20140286095 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes first through third memory strings, a first word line group shared by first and second memory strings and a second word line group shared by second and third memory strings, the first and second word line groups extending in a first direction and disposed adjacent to each other in a second direction that is perpendicular to the first direction. The first word line group includes laminated first word lines with each upper first word line extending in the first direction less than the first word line directly below, and the second word line group includes laminated second word lines with each upper second word line extending in the first direction less than the second word line directly below. | 2014-09-25 |
20140286096 | MEMORY DEVICE AND METHOD OF CONTROLLING LEAKAGE CURRENT WITHIN SUCH A MEMORY DEVICE - A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column group includes circuitry to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell has coupling circuitry connected between the associated read bit line and a second voltage level different to the first voltage level. During read operation the coupling circuitry associated with the activated memory cell selectively discharges the associated read bit line towards the second voltage level dependent on the data value stored within that activated memory cell. The clamping circuitry connects the associated read bit line to the second voltage level. | 2014-09-25 |
20140286097 | THERMALLY ASSISTED FLASH MEMORY WITH DIODE STRAPPING - A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different than the first bias voltage, to a second set of spaced-apart locations on the word line or word lines, locations in the first set of spaced-apart locations being interleaved among locations in the second set of spaced-apart locations, whereby current flow is induced between locations in the first and second sets of locations that cause heating of the word line or word lines. | 2014-09-25 |
20140286098 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes a memory string having a plurality of electrically rewritable memory transistors connected in series therein. The memory string includes a first semiconductor layer including a columnar portion extending in a perpendicular direction to a substrate; a tunnel insulating film formed surrounding a side surface of the columnar portion; a charge storage film formed surrounding the tunnel insulating film; a block insulating film formed surrounding the charge storage film; and a plurality of first conductive layers formed surrounding the block insulating film and disposed with a certain spacing along the perpendicular direction. The charge storage film includes a first charge storage film having a conducting property and located in contact with the tunnel insulating film; and a second charge storage film having an insulating property and formed between the first charge storage film and the block insulating film. | 2014-09-25 |
20140286099 | SEMICONDUCTOR MEMORY DEVICE, CONTROLLER, AND MEMORY SYSTEM - A semiconductor memory device includes a memory cell array that is capable of storing data in a nonvolatile manner, and a control section that controls data access to the memory cell array. The memory cell array stores the same data redundantly in a plurality of pages. The control section executes a reading operation on the plurality of pages that store the same data redundantly to read the data. The data that is stored redundantly may be management data or user data. | 2014-09-25 |
20140286100 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line. | 2014-09-25 |
20140286101 | BACK BIAS DURING PROGRAM VERIFY OF NON-VOLATILE STORAGE - Different back bias (or body bias) conditions are applied to a non-volatile storage system during different program verify operations of a programming operation. A back bias may be applied during verify of an intermediate state (e.g., a lower page, middle page). The intermediate state is a state that exists during a program operation, but is not one of the final states. A lower back bias or no back bias is applied during verify of a final state (e.g., an upper page). Thus, a different back bias may be used when verifying an intermediate state than the back bias used when verifying a final state. Using the back bias makes it easier to verify a low V | 2014-09-25 |
20140286102 | Method of Optimizing Solid State Drive Soft Retry Voltages - A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a number of soft retry voltage reads based on a hard decision read. The spacing between each read reference voltage is constant since each SSD type requires a number of reads for an accurate presentation of soft retry voltages. The voltage distance between each successive read is limited to a multiple of the constant spacing while the multiple is based on success or failure of the first read. The method determines a limited number of reads, the constant spacing between reads, and a desired reference voltage for each read, thereby increasing valuable throughput of the channel and decreasing BER. | 2014-09-25 |
20140286103 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a memory cell configured to allow electrical writing and erasing, a bit line configured to transmit a potential corresponding to data stored in the memory cell in a column direction, a sense amplifier circuit configured to detect a potential of the bit line, and a bit line coupling circuit coupled between the bit line and the sense amplifier circuit. The bit line coupling circuit includes a first bit line coupling transistor in an outer layout area of the bit line coupling circuit and a second bit line coupling transistor in an inner layout area of the bit line coupling circuit. The first bit line coupling transistor has a longer distance in a channel length direction or in a channel width direction between an impurity diffused layer coupled to the bit line and an element isolation area than the second bit line coupling transistor. | 2014-09-25 |
20140286104 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a non-volatile semiconductor memory device which is provided with a memory cell array, bit lines, word lines, and a sense amplifier circuit is presented. The memory cell array includes memory cells. The bit lines are electrically connected to the memory cells. The word lines are electrically connected to gates of the non-volatile memory cells. The sense amplifier circuit includes sense amplifiers which are electrically connected to the bit lines. Each of the sense amplifiers includes a latch circuit which is capable of holding data, and a detection circuit. The sense amplifiers are configured to apply any one of a first voltage and a second voltage higher than the first voltage to the bit lines respectively. The sense amplifiers apply any one of the first voltage and the second voltage s a third voltage to the bit lines, and apply the third voltage to the detection circuit. | 2014-09-25 |
20140286105 | NAND FLASH MEMORY UNIT, OPERATING METHOD AND READING METHOD - A NAND flash memory unit, an operating method and a reading method are provided. The NAND flash memory unit includes a plurality of gate layers, a tunnel layer, a charge trapping layer, a conductor layer and a second dielectric layer. A first dielectric layer is included between two adjacent gate layers among the gate layers. The tunnel layer, the charge trapping layer, the conductor layer, and the second dielectric layer penetrate the gate layers. The charge trapping layer is disposed between the tunnel layer and the gate layers, and the second dielectric layer is disposed between the conductor layer and the tunnel layer. Therefore, an erasing speed may be increased; the charge trapping layer may be repaired; the controllability of the gate layers may be increased. | 2014-09-25 |
20140286106 | MEMORY DEVICES HAVING SOURCE LINES DIRECTLY COUPLED TO BODY REGIONS AND METHODS - Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing. | 2014-09-25 |
20140286107 | Memory System and Control Method Therefor - A memory system includes a plurality of memory devices having data terminals that are commonly connected to a memory controller. Each of the memory devices includes a data output circuit that outputs read data that is read from a memory cell array in response to a read command to the data terminal, and an output-timing adjustment circuit that adjusts an output timing of read data that is output from the data output circuit. The memory controller sets an adjustment amount of adjustment performed by an output-timing adjustment circuit such that delay times from when the read command is issued until when the read data is received match in the memory devices, by issuing a setting command to each of the memory devices. | 2014-09-25 |
20140286108 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes n (n being a natural number of 2 or more) data retention circuits connected to a data input/output terminal; n buses connected respectively to the n data retention circuits; m×n data latch circuits connected to the buses, with m (m being a natural number of 2 or more) data latch circuits being connected per one of the buses; and a selection circuit configured to simultaneously perform data transfer from/to the data retention circuits for a plurality of the data latch circuits in units of a group including the plurality of the data latch circuits, the data latch circuits being divided into the groups so that not all the data latch circuits connected to the same bus are included in the same group. | 2014-09-25 |
20140286109 | SEMICONDUCTOR DEVICE INCLUDING OUTPUT CIRCUIT CONSTITUTED OF PLURAL UNIT BUFFER CIRCUITS IN WHICH IMPEDANCE THEREOF ARE ADJUSTABLE - A semiconductor device includes an output circuit having a plurality of unit buffer circuits, an impedance of each unit buffer circuit of the plurality of unit buffer circuits being adjustable, a control circuit configured to selectively activate one or more unit buffer circuits of the plurality of unit buffer circuits, and an impedance adjustment unit configured to adjust the impedance of each of the unit buffer circuits of the plurality of unit buffer circuits. The impedance adjustment unit includes a first power line, a replica circuit, and a load current generation circuit. The replica circuit and the load current generation circuit are coupled in common to the first power line, the replica circuit has a replica impedance that is substantially equal to the impedance of the output circuit, and the load current generation circuit changes current flowing therethrough. | 2014-09-25 |
20140286110 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a plurality of on-die termination circuits connected to each of a plurality of input/output pads; and a control circuit for controlling the on-die termination circuit. The on-die termination circuit comprises: a pull-up element connected between a first terminal and an output terminal; and a pull-down element connected between the output terminal and a second terminal. The pull-up element is driven by a first pull-up element driver, and the pull-down element is driven by a first pull-down element driver. The control circuit activates a plurality of the on-die termination circuits at different timings. | 2014-09-25 |
20140286111 | DOMAIN CROSSING CIRCUIT OF SEMICONDUCTOR APPARATUS - A domain crossing circuit of a semiconductor apparatus includes a delay-locked loop block configured to generate a delay-locked loop clock signal in response to a clock signal and a clock enable signal; a clock enable block configured to generate the clock enable signal in response to the clock signal and a read command signal; and a command pass block configured to perform primary latency control according to the clock signal and secondary latency control according to the delay-locked loop clock signal, for the read command signal generated in response to a strobe signal, and generate a latency signal. | 2014-09-25 |
20140286112 | SEMICONDUCTOR DEVICE - Disclosed herein is an apparatus that includes a first semiconductor chip including a first electrode, and a second semiconductor chip including a second electrode connected to the first electrode. One of the first and second semiconductor chips includes a first temperature sensor circuit generating a first detection signal, the first detection signal taking a first level when a temperature is equal to or higher than a first temperature, the first detection signal taking a second level when the temperature is lower than the first temperature; and a first delay code generation circuit outputting a first delay code signal in response to the first level of the first detection signal, and outputting a second delay code signal different from the first delay code signal in response to the second level of the first detection signal. | 2014-09-25 |
20140286113 | SEMICONDUCTOR DEVICE HAVING ROLL CALL CIRCUIT - Disclosed herein is an apparatus that includes: a plurality of memory banks each including a plurality of memory cells; a plurality of redundant circuits each allocated to an associated one of the plurality of memory banks to replace a defective memory cell among the plurality of memory cells included in the associated memory bank; a plurality of roll call circuits allocated to an associated one of the plurality of memory banks to generate a roll call data when an address corresponding to the defective memory cell is supplied; and a plurality of data buses commonly allocated to the plurality of memory banks. The roll call circuits output the roll call data to the plurality of data buses in parallel. | 2014-09-25 |
20140286114 | Semiconductor Device, Method for Inspecting the Same, and Method for Driving the Same - A method for limiting writing of data to a specific memory cell without disconnecting a wiring of a memory cell array or placing a prober in contact with a memory cell, a row, or a column is provided. Row address data and column address data of a memory cell to which data cannot be written are stored in a register. Enable data which controls data writing is stored in the register. Next, in order to write data to a memory cell, row address data and column address data of a memory cell to which data is written, writing enable data, and the like are output from a logic circuit; thus, writing of data to a memory cell corresponding to the address data stored in the register is inhibited. | 2014-09-25 |
20140286115 | NONVOLATILE RANDOM ACCESS MEMORY - According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command. | 2014-09-25 |
20140286116 | NOISE TOLERANT SENSE CIRCUIT - A device and a method for a sense circuit have been disclosed. In an implementation, the sense circuit includes a sense amplifier and at least one decoupling device. The decoupling device is coupled to the sense amplifier through at least one reference line. The sense amplifier reads a data value and the decoupling device decouples the sense amplifier from a power supply during a read operation. | 2014-09-25 |
20140286117 | SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER - In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row. | 2014-09-25 |
20140286118 | SEMICONDUCTOR DEVICE VERIFYING SIGNAL SUPPLIED FROM OUTSIDE - A method for accessing a semiconductor device having a memory array, includes receiving a chip select signal, receiving a command signal and an address signal, receiving a verification signal, calculating an error signal based on the address signal, the command signal, and the verification signal, generating an internal chip select signal based on the received chip select signal if the error signal indicates no error, and generating an external alert signal if the error signal indicates an error. | 2014-09-25 |
20140286119 | MEMORY DEVICES, SYSTEMS AND METHODS EMPLOYING COMMAND/ADDRESS CALIBRATION - During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system. | 2014-09-25 |
20140286120 | POWERED BLENDING CONTAINER - A blending device is shown and described. The blending device may include a blending container and a power source operatively connected to the blending container. The power source may be configured to supply power to the blending container. The blending container may also include a feature that is powered by the power source. | 2014-09-25 |
20140286121 | Dynamic Mixing Pump - Apparatus ( | 2014-09-25 |
20140286122 | METHOD OF DYNAMIC MIXING OF FLUIDS - Methods are provided for achieving dynamic mixing of two or more fluid streams using a mixing device. The methods include providing at least two integrated concentric contours that are configured to simultaneously direct fluid flow and transform the kinetic energy level of the first and second fluid streams, and directing fluid flow through the at least two integrated concentric contours such that, in two adjacent contours, the first and second fluid streams are input in opposite directions. As a result, the physical effects acting on each stream of each contour are combined, increasing the kinetic energy of the mix and transforming the mix from a first kinetic energy level to a second kinetic energy level, where the second kinetic energy level is greater than the first kinetic energy level. | 2014-09-25 |
20140286123 | BLENDING SYSTEM - A blending system is shown and described herein. A blending system may include a base including a motor and a first shell that encases the motor. The blending system may also include a container that is removably coupled to the blender base. The blending system may also have a second shell selectively attached to the first shell. The blending system may also have a wall positioned within the base to direct airflow from the fan along a volute-shaped path. | 2014-09-25 |
20140286124 | Automated Reagent Manager of a Diagnostic Analyzer System - A reagent manager for a diagnostic analyzer system includes a reagent manager housing, a high-speed reagent bottle spinning device, a processor, and a memory. The reagent manager housing is for housing reagent bottles. The high-speed reagent bottle spinning device is disposed within the reagent manager housing for spinning at least one of the reagent bottles. The processor is in electronic communication with the high-speed reagent bottle spinning device. The memory is in electronic communication with the processor. The memory includes programming code for execution by the processor. The programming code is configured to spin the high-speed reagent bottle spinning device to spin the at least one reagent bottle to remove microparticles from a bottom surface of a septum of the at least one reagent bottle. | 2014-09-25 |
20140286125 | SEISMIC ACQUISITION METHOD AND APPARATUS - A system and method for performing a seismic survey. The system includes a first seismic source and a second seismic source configured for generating seismic signals. The first seismic source is configured for generating seismic signals ranging from about 4 Hz to about 120 Hz. The second seismic source is configured for generating seismic signals ranging from about 0 Hz to about 8 Hz. The system includes receivers to receive seismic data in response to seismic signals generated by the seismic sources. | 2014-09-25 |
20140286126 | CONTROL SYSTEM FOR POSITIONING OF MARINE SEISMIC STREAMERS - A method of controlling a streamer positioning device ( | 2014-09-25 |
20140286127 | PROCESSING SEISMIC DATA TO ATTENUATE VIBRATION NOISE - A technique includes receiving first data acquired by at least a particle motion gradient sensor or a rotation sensor of a streamer that is subject to vibration due to towing of the streamer; and receiving second data acquired by at least one particle motion sensor of the streamer and being indicative of particle motion and vibration noise. The technique includes processing the second data in a processor-based machine to, based at least in part on the first data, attenuate the vibration noise indicated by the second data to generate third data indicative of the particle motion. | 2014-09-25 |
20140286128 | SYSTEMS AND METHODS FOR PERFORMING DUAL-SCALE INTERPOLATION - Systems and methods are provided for processing seismic data and displaying an output associated with the seismic data. A method includes: separating the seismic data into a fine-scale dataset and a coarse-scale dataset, wherein each dataset includes a non-zero portion of the data; applying a first interpolation to the coarse-scale dataset which results in an interpolated coarse-scale dataset; applying a second interpolation to the fine-scale dataset which results in an interpolated fine-scale dataset, wherein the first and second interpolation are different interpolations; summing together the interpolated coarse-scale dataset and the interpolated fine-scale dataset which results in a summed interpolated dataset; and displaying at least one image based on the summed interpolated dataset. | 2014-09-25 |
20140286129 | ACOUSTIC DETECTION SYSTEM - A technique facilitates detection of an event in a subterranean environment, e.g. in a wellbore. A tool may be deployed to a desired wellbore location or other subterranean location for actuation between operational positions. An acoustic system also is deployed to detect a unique acoustic signature associated with an event related to operation of the tool. Upon detection of the unique acoustic signature, the acoustic system transmits data to a surface location or other suitable location to indicate occurrence of the event. An example of such an event is transition of the tool between operational positions. | 2014-09-25 |
20140286130 | Acoustic Transceiver with Adjacent Mass Guided by Membranes - An acoustic transceiver assembly including a housing, an oscillator, and at least one membrane. The housing has at least one inner wall defining a cavity. The housing also has a first end and a second end defining an axis of the acoustic transceiver assembly. The oscillator is provided in the cavity. The oscillator is provided with a transducer element, and a backing mass acoustically coupled to the transducer element. The at least one membrane extends outward from the backing mass to support at least the backing mass within the cavity. The at least one membrane is flexible in an axial direction parallel to the axis of the acoustic transceiver assembly to permit the backing mass to oscillate in the axial direction, and rigid in a transverse direction to restrict lateral movement of the backing mass relative to the housing. | 2014-09-25 |
20140286131 | WIDEBAND SONAR RECEIVER AND SONAR SIGNAL PROCESSING ALGORITHMS - A wideband sonar receiver is provided that includes: a selectable bandpass filter adapted to filter a received sonar signal to produce a filtered signal and a correlator adapted to correlate the baseband samples with baseband replica samples to provide a correlated signal. In addition, the wideband sonar receiver may include a shaping filter to shape unshaped received pulses. Finally, a variety of sonar processing algorithms are described with regard to reducing clutter and interference, target detection, and bottom detection. | 2014-09-25 |
20140286132 | AN ULTRASOUND DOPPLER DETECTION METHOD WITH GOLAY CODE EXCITATION - An ultrasound Doppler detection method with Golay-encoded excitation is used to obtain the flow information of a moving object. A first Golay code is transmitted to the moving object for a reflection signal of the first Golay code and a second Golay code is transmitted to the moving object for a reflection signal of the second Golay code after waiting for a pulse repetition interval. The received reflection signals are match-filtered to generate a first and a second wave. The above steps are repeated several times. Then, a slow-time filter in the Doppler frequency domain whose low-pass cut-off frequency is a quarter of the pulse repetition frequency is used to filter out the first sidelobes of the first waves and the second sidelobes of the second waves. Finally, the ultrasound Doppler detection is formed according to the first mainlobes of the first waves and the second mainlobes of the second waves. | 2014-09-25 |
20140286133 | DEVICE-TO-DEVICE ANGLE DETECTION WITH ULTRASOUND AND WIRELESS SIGNAL - A method for determining orientation of an electronic device relative to another electronic device is described. The method includes synchronizing internal clock of a first electronic device with internal clock of a second electronic device using electromagnetic signals communicated between the first electronic device and the second electronic device, sending two or more sound waves from the second electronic device, receiving the two or more sound waves at the first electronic device, and calculating orientation of the first electronic device relative to the second electronic device based on a difference in time of arrival of the two or more sound waves at the first electronic device. The first electronic device and the second electronic device each have at least one transceiver configured to send and receive electromagnetic signals. The first electronic device has two or more acoustoelectric transducers and the second electronic device has one or more acoustoelectric transducer. | 2014-09-25 |
20140286134 | Time Indicators for Calendars - In a multiday view of a calendar, a time indicator is shown adjacent to a graphical element for the current day. In the multiday view, such a time indicator accurately indicates the current time on the current day, but not on other days of the week. If the current day is not viewable, the time indicator is not shown. By being adjacent to the graphical element for the current day, the time indicator does not obscure information, such as events, for the current day. | 2014-09-25 |
20140286135 | ELECTRONIC TIMEPIECE WITH SOLAR CELL - An electronic timepiece with a solar cell is provided with a solar cell, a solar cell holding member, a light-transmissive character plate, a ground plate, and a ring-shaped calendar wheel. The solar cell includes a base material that is made of an insulating material, and a light-receiving unit that is arranged on a first surface of the base material. The solar cell holding member is fixedly attached to a second surface of the base material. The light-transmissive character plate is arranged on a timepiece front side of the solar cell. The ground plate is arranged on a back surface of the solar cell. The ring-shaped calendar wheel is disposed between the character plate and the ground plate. The solar cell holding member is arranged on a character plate side of the calendar wheel to position the calendar wheel. | 2014-09-25 |
20140286136 | Time Adjustment Device, Timekeeping Device With A Time Adjustment Device, And Time Adjustment Method - A timepiece can acquire time information in a short time, reduce power consumption, and display the correct time. A timepiece comprises a receiver to receive a satellite signal, and a time information generator to generate internal time information. The receiver runs a first reception process that acquires first information including week information from the satellite signal, a second reception process that acquires second information including leap second information from the satellite signal, or a third reception process that acquires third information including hour, minute and second information from the satellite signal. In the first reception timing, after the internal time information is initialized, the receiver runs the first reception process and runs the second reception process after running the first. In a next reception timing, after the first reception timing, the receiver runs the third reception process if the first and second information are acquired in the first reception timing. | 2014-09-25 |
20140286137 | METHOD OF CONTROLLING ALARM FUNCTION AND ELECTRONIC DEVICE SUPPORTING THE SAME - A method of controlling an alarm with a more improved alarm function and an electronic device supporting the same are provided. The method of controlling an alarm includes determining sleep start time information and alarm start time information, calculating a sleep time based on the sleep start time information and the alarm start time information, and outputting an alarm having a different characteristic according to a length of the calculated sleep time. | 2014-09-25 |
20140286138 | ANALOG ELECTRONIC TIMEPIECE - An analog electronic timepiece, including: a stepping motor; a first indicating unit which makes a step rotation by a predetermined first rotation angle according to the step drive; a second indicating unit which makes a step rotation by a second rotation angle which is smaller than the first rotation angle in conjunction with the step rotation of the first indicating unit; an independent rotation control unit; an interlocking rotation control unit; and a rotation selection unit which activates the independent rotation control unit when current processing is in an operation mode where the rotation position of the first indicating unit is changed or in an operation state where the rotation position of the first indicating unit is temporarily changed and which activates the interlocking rotation control unit when a setting relating to a final rotation position of the first indicating unit is fixed. | 2014-09-25 |
20140286139 | TIMEPIECE MECHANISM STRUCTURE - Timepiece mechanism structure ( | 2014-09-25 |
20140286140 | TIMEPIECE BALANCE SPRING - Timepiece escape mechanism sub-assembly including at least one bar and at least one balance spring, the outer end of which is secured to a balance spring stud. | 2014-09-25 |
20140286141 | TIMEPIECE MECHANISM CASSETTE - Timepiece mechanism cassette including at least one bearing surface for positioning the cassette in a movement, a plate and a bar, at least one of which is rigid, between or on which there are arranged functional components at least two of which are movable relative to each other. | 2014-09-25 |
20140286142 | TIMEPIECE MECHANISM CASSETTE - Timepiece mechanism cassette including at least one bearing surface for positioning the cassette in a movement, a plate and a bar, at least one of which is rigid, between or on which there are arranged functional components at least two of which are movable relative to each other. | 2014-09-25 |
20140286143 | TIMEPIECE BALANCE SPRING ADJUSTMENT MECHANISM - Mechanism for adjusting the active length of a timepiece balance spring whose outer end is fixed to a balance spring stud secured to a bar, this mechanism including two pins for clamping or touching the outer coil of the balance spring during the operation of this balance spring. | 2014-09-25 |
20140286144 | SYSTEM FOR ATTACHING A WRISTLET STRAND TO A CASE - Wristwatch including a case in or on which there is arranged a first open housing, a wristlet provided with one end arranged in the first open housing, and a fastening means for holding the end of the wristlet in the first housing. The fastening means includes a second housing opening onto the first housing and a fastening element arranged in the second housing and occupying one part of the first housing. The wristwatch further contains a means of retaining the fastening element. | 2014-09-25 |
20140286145 | INSEPARABLE SINGLE-PIECE TIMEPIECE COMPONENT - Inseparable single-piece timepiece component including a position adjustable mechanism having a rigid structure carrying, by means of at least one resilient strip, a position adjustable component including an indexing means arranged to cooperate with a complementary indexing means comprised in an adjustment mechanism. | 2014-09-25 |
20140286146 | SWITCH DEVICE AND TIMEPIECE INCLUDING SWITCH DEVICE - A switch device of the present invention includes a cylindrical member fitted into a through hole of a wristwatch case, an operating member having an operation shaft section to be inserted into the cylindrical member and an operation head section, and a lock member fixed inside the operation head section. The cylindrical member includes engaging projections, and the lock member includes resilient support sections which have a space with respect to the inner circumferential surface of the operation head section and are resiliently deformed in a radial direction, and lock sections with which the engaging projections are resiliently engaged. Accordingly, when the operating member is pushed inward and rotated, the engaging projections resiliently deform the resilient support sections and are engaged with the lock sections. Also, only by the operating member being rotated against the regulating force of the lock section, the lock sections are disengaged from the engaging projections. | 2014-09-25 |
20140286147 | PLASMON GENERATOR HAVING FLARE SHAPED SECTION - The present invention relates to a plasmon generator, in which a surface plasmon is excited by application of light. The plasmon generator extends along one direction. The plasmon generator includes a first end surface that is positioned on one end in the one direction and at which near-field light is generated along with the excitation of the plasmon; and a second cross section that is substantially parallel to the first end surface and is away from the first end surface. The first end surface has a polygonal shape that does not have a substantially acute inner angle. The second cross section has an upper part that has a shape substantially the same as or similar to that of the first end surface and a flare shaped lower part that is connected to the upper part and has a width that increases as it is far from the upper part. | 2014-09-25 |
20140286148 | OPTICAL DISC DEVICE - The optical disc device has a circuit which forms a focus error signal for focus servo control based on reflection light from an optical disc exposed to laser light. Also, the device has a data processing unit which can control by feedback a position to which an objective lens is moved by a focusing actuator based on a focus error signal. In label printing, the data processing unit controls, by feedforward, a position to which the objective lens is moved by the focusing actuator based on control data for label printing. The operation resolution of the focusing actuator in feedforward control is made higher than that in feedback control. Thus, an intended position control accuracy is achieved in feedforward control. For instance, in feedforward control, the gain of the driver circuit for the focusing actuator is switched to a smaller one in comparison to that in feedback control. | 2014-09-25 |
20140286149 | Automatic On-Drive Sync-Mark Search and Threshold Adjustment - A hard disk drive includes a processor to automatically adjust a threshold level for finding sync-marks. The processor determines all possible sync-mark patterns for a particular pattern length and analyzes each pattern with reference to real world data. The pattern with the largest distance gap is used. The threshold level is then adjusted dynamically to produce the lowest possible failure rate for the given pattern. | 2014-09-25 |
20140286150 | DATA ARCHIVE SYSTEM AND QUALITY INSPECTION METHOD - Disclosed is a data archive system that executes inspection of a recording quality of an optical disc, estimates a recording quality deterioration factor, and informs it to a user, and a method for estimating the recording quality deterioration factor. The data archive system has a server and a data library device. The server has a whole control part, a data library I/F part, and a recording medium. The data library device has multiple recording media, a recording medium storing part, multiple recording/reproducing parts, and a library control part. The recording medium stores attribute information about the recording medium. The whole control part executes first quality inspection on a first recording medium, executes second quality inspection on a second recording medium, refers to attribute information of the recording media recorded on the information recording medium, and controls so that a factor deteriorating the qualities of the recording media may be estimated. | 2014-09-25 |
20140286151 | OPTICAL PICKUP AND DISC DEVICE - An optical pickup includes a plurality of light sources, an objective lens, a diffractive optical element, and a light-detecting unit. The various light sources emit light of wavelengths that are different from each other. The objective lens focuses light on an optical disc. The diffractive optical element includes a diffracting portion and a light-blocking portion. The diffracting portion diffracts return light reflected from a first recording layer of the optical disc where information is being read or written. The light-blocking portion blocks stray light reflected from a second recording layer of the optical disc that is different from the first recording layer. The light-detecting unit receives the diffracted light of the diffractive optical element and generates an output signal to generate a tracking error signal based on this diffracted light. Furthermore, the light-blocking portion includes a plurality of light-blocking patterns which block light of wavelengths that are different from each other. | 2014-09-25 |
20140286152 | DATA RECORDING/REPRODUCING DEVICE, ARCHIVE SYSTEM, AND RECORDING CONTROL METHOD - A data recording/reproducing device for recording data on a recordable area of a recording medium in an arbitrary recording unit, includes a control unit that controls the operation of the data recording/reproducing device. The control unit designates a recording unit where data on the recordable area is not recorded as a non-use area, determines whether data has been recorded, or unrecorded in the recording unit on the recordable area, determines the recording unit designated as the non-use area to have been recorded, and records data in the recording unit determined to be unrecorded when data is recorded on the recording medium, under the control. | 2014-09-25 |
20140286153 | APPARATUS AND METHODS FOR UPDATE OF SYMBOL INFORMATION - Apparatus and methods for updating symbol information in a communication device with hardware such as a microcontroller are disclosed. The disclosed apparatus and methods employ waiting for the beginning of a symbol in a sample stream at a predetermined time. One or more programmed instructions are read at the beginning of the symbol, and then symbol information is updated based on the one or more programmable instructions and setting a time for a beginning of a next symbol. The programmed instructions consist of instruction code words that are executed by a dedicated microcontroller or similar hardware, which affords flexibility for updating symbol information, particularly for multimode communication devices operable across multiple communication technologies. | 2014-09-25 |
20140286154 | HYBRID DISTRIBUTED LINEAR PROTECTION - A method for linear protection for a network element communicatively coupled to another network element included in a node portal located at the edge of an administrative network domain includes exchanging linear automatic protection switching (“APS”) messages with clients in the administrative network domain over one or more path pairs. The path pairs include a working path communicatively coupling a client and the network element and a protect path communicatively coupling a client and the other network element. The method also includes translating the linear APS messages into a shared mesh protection message and exchanging the shared mesh protection message between the network element and the other network element over an intraportal link. The shared mesh protection messages include information concerning a plurality of working paths. | 2014-09-25 |
20140286155 | System and Method for Protection Against Edge Node Failure - In one embodiment, a method includes determining, by an edge router, a plurality of prefixes reachable by the edge router, each prefix indicating a range of Internet Protocol (IP) addresses. The method further includes grouping, by the edge router, the plurality of prefixes into one or more groups, wherein each group is associated with a particular repair edge router and the prefixes in each particular group are reachable by both the edge router and the particular repair edge router associated with the particular group. The method further includes communicating instructions, from the edge router to a core router, to send data packets associated with the prefixes in each particular group to the particular edge router associated with the particular group if the edge router becomes unreachable. | 2014-09-25 |
20140286156 | Distribution Node and Client Node for Next Generation Data Network - A Next Generation Data Network is described. It leverages the “cloud” for data management, low frequency data computation and analytics. The wireless network is a single frequency network that permits limited non-line of sight operation. The wireless network using packet switched beams, the beams are formed and switched electronically. It utilizes advanced signal processing to compensate for low transmit signal power and multipath reflections that can be frequency or flat fades. | 2014-09-25 |
20140286157 | SIGNAL PROCESSING METHOD IN WIRELESS COMMUNICATION SYSTEM AND DEVICE THEREFOR - A method for operating a relay node in a wireless communication system. The method includes communicating, by the relay node, with a base station using a specific subframe for the relay node only; detecting, by the relay node, a problem with a connection between the relay node and the base station; starting, by the relay node, a timer upon detecting the problem with the connection between the relay node and the base station; and releasing, by the relay node, a restriction of using the specific subframe for the relay node only, if the started timer expires. The problem with the connection between the relay node and the base station is associated with a radio link failure. | 2014-09-25 |
20140286158 | METHODS AND SYSTEMS FOR AUTOMATICALLY REROUTING LOGICAL CIRCUIT DATA IN A DATA NETWORK - A disclosed example method involves identifying a logical failover circuit comprising an alternate communication path in a failover network that is separate from a logical circuit comprising variable communication paths in at least one of a first logical telecommunications network or a second logical telecommunications network and a fixed communication path between the first and second logical telecommunications networks. The failed logical connection is between the first and second logical telecommunications networks. The failover network is reserved to provide failover circuits to communicate data rerouted from failed logical circuits, and the logical failover circuit identified by a second logical circuit identifier. The logical circuit identifier of the logical circuit is renamed to the second logical circuit identifier of the logical failover circuit when a logical connection in the logical circuit has failed. The data is rerouted from the logical circuit to the logical failover circuit without manual intervention. | 2014-09-25 |
20140286159 | WIRELESS LOCAL AREA NETWORK (WLAN) TRAFFIC OFFLOADING - Technology for communicating access point (AP) information for traffic offloading is disclosed. A request may be received, at a wireless local area network (WLAN) domain manager (DM) from an evolved node B (eNB), for access point (AP) information about one or more WLAN access points (APs) for traffic offloading. The access point (AP) information may be obtained for the one or more WLAN APs, at the WLAN DM, based on at least in part operations and management (OAM) reports from the one or more WLAN APs containing the AP information. The AP information may be communicated, from the WLAN DM to the eNB via a network manager (NM), about the one or more WLAN APs to enable traffic offloading from the eNB to at least one of the ALAN APs. | 2014-09-25 |
20140286160 | METHODS FOR ADJUSTING NETWORK TRANSMISSION SERVICE LEVEL AND DATA TERMINALS - This disclosure relates to methods for adjusting network transmission service levels, data terminals, and network servers. The method for adjusting a network transmission service level, used in a data terminal, comprises: obtaining data to be transmitted; inserting the data into specified queues or assigning priorities to the data according to one or more data characteristics selected from importance, instantaneity, data resources, and data types; transmitting a transmission service request to a network server, wherein the transmission service request includes information about the network transmission service level requested and corresponding network configuration parameters; and using the network transmission service provided by the network server according to the transmission service request to transmit the data in queues or the data whose priorities correspond to the network transmission service level provided. The data terminal could ask the network transmission service provider to provide different network transmission service to improve the instantaneity and stability of data transmission. | 2014-09-25 |
20140286161 | UPLINK CONGESTION CONTROL - The present disclosure relates to an uplink congestion control scheme. In one embodiment, an uplink congestion control method is provided, comprising steps of: determining whether or not a congestion status of a serving cell is changed based on a rise over thermal, RoT, measurement; sending to a set of user equipment, UEs, a signaling to indicate the change of the congestion status; and performing an uplink congestion control based on the RoT measurement and with enhanced transmission format combination, E-TFC, reselection by at least one UE from the set of UEs based at least on the signaling. | 2014-09-25 |
20140286162 | METHOD AND DEVICE FOR SUPPORTING MTC TRIGGER OF SERVING NODE IN WIRELESS COMMUNICATION SYSTEM - One embodiment of the present invention discloses a method for allowing a serving node to support a trigger request of a machine type communication-interworking function (MTC-IWF) in a wireless communication system, and the method for supporting the trigger request comprises the steps of: receiving, from a terminal, capability information which contains information on trigger transmission; and determining whether to transmit the information on the trigger transmission to a home subscriber server (HSS)/home location register (HLR), based on the information related to the terminal, which contains the capability information, and information related to the serving node, wherein the information on the trigger transmission contains information indicating whether the terminal supports a trigger request through the MTC-IWF and the serving node. | 2014-09-25 |
20140286163 | DATA CHANNEL SCHEDULING METHOD AND SYSTEM FOR ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING ACCESS (OFDMA)-BASED WIRELESS MESH NETWORK - Provided is a data channel scheduling system for an orthogonal frequency division multiplexing access (OFDMA)-based wireless mesh network, the system including a set classifying unit to classify a plurality of nodes included in the OFDMA-based wireless mesh network, into multiple requests allowing sets based on a preset reference, and an information providing unit to provide information on the classified sets such that multiple requests are performed on one of the classified multiple requests allowing sets. | 2014-09-25 |
20140286164 | FLOW MANAGEMENT FOR DATA STREAMS OVER CELLULAR NETWORKS - Methods and systems for data flow control include establishing a first connection between a gateway and a network client responsive to a connection request from the network client; establishing a second connection between the gateway and a server specified by the connection request; determining a user class for the network client based on a level of network congestion detected at the gateway based on throughput and round-trip-time delays; modifying a data flow received at the gateway on the second connection to remove data from the flow based on the determined user class of the network client; and transmitting the modified data flow to the network client via the first connection. | 2014-09-25 |
20140286165 | Optimization of a Backhaul Connection in a Mobile Communications Network - A system, a method, a device, and a computer program product for transmission of data between a user device and a server. A first data received from the user device and a second data received from the server are processed. A determination is made whether to store at least a portion of the second data in at least one memory. The stored portion of the second data is provided to the user device in response to receiving the first data. | 2014-09-25 |
20140286166 | Method and Device for Loading Read Content - The present disclosure is applied in field of mobile internet, and provides method and device for loading a read content, the method includes: acquiring a loading condition evaluation parameter of the mobile terminal, the loading condition evaluation parameter including a network environment parameter; determining a loading condition level of the mobile terminal according to the loading condition evaluation parameter; adapting a loading strategy corresponding to the loading condition level in a preset loading strategy table; loading the read content according to the loading strategy. The embodiments of the present method can adapt a suitable loading strategy for the read content needs to be loaded according to the network environment, in which the mobile terminal is currently, so as to implement an adaptive adjustment of the loading strategy and ensure that the read content can be loaded in a shortest time no matter of the network environment. | 2014-09-25 |
20140286167 | PATH CONTROL SYSTEM, PATH CONTROL DEVICE, COMMUNICATION DEVICE, PATH CONTROL METHOD, AND PROGRAM - A path control system according to the present invention includes: a network including a communication device that communicates via a wireless link using adaptive modulation; and a path control device ( | 2014-09-25 |
20140286168 | TRANSMISSION CONTROL METHOD AND NODE - Each of the nodes included in an ad-hoc network determines whether an identifier indicative of high-priority data is included in data received from another node. When the identifier is included in the received data, each of the nodes determines whether the subject node is a device that relays the received data to a destination. When determining that the subject node is a device that relays the received data to the destination, each of the nodes transmits the received data to the destination. When determining that the subject node is not a device that relays the received data to the destination, each of the nodes suppresses data transmission to the nodes included in the ad-hoc network. | 2014-09-25 |
20140286169 | ELASTIC TRAFFIC MARKING FOR MULTI-PRIORITY PACKET STREAMS IN A COMMUNICATIONS NETWORK - Routers in a communications network mark packets of a multi-priority stream to establish a drop precedence of the packets during network congestion. For each packet received, a router employs one of two types of packet-marking mechanisms to associate low drop precedence with a high-priority, out-of-profile packet. One type, called “token bucket with loan bucket,” uses a token bucket to determine whether a packet is in conformance, i.e., in-profile, with a traffic profile and at least one loan bucket to determine whether a high priority, out-of-profile packet may borrow bandwidth. Another mechanism type, called “token bucket with color-exchange queue,” uses a color-exchange queue to delay packet forwarding for a fixed period. During this delay, a high-drop-precedence marking of an out-of-profile, high-priority packet may be exchanged with a low-drop-precedence marking of an in-profile, low-priority packet. The packet-marking mechanisms are useful in improving the quality of video viewing. | 2014-09-25 |
20140286170 | METHOD IN A RADIO NETWORK NODE FOR CONTROLLING USAGE OF RAT AND FREQUENCY BANDWIDTH IN A RADIO COMMUNICATION SYSTEM - A radio network node, and a method therein, for controlling usage of RAT and frequency bandwidth in a radio communications system. The method includes allocating a first RAT to a first frequency bandwidth, and allocating a second RAT to a second frequency bandwidth. When a load on the first RAT is above a threshold, the method includes reallocating the first RAT to a third frequency bandwidth, and reallocating the second RAT to a fourth frequency bandwidth, wherein the third and fourth frequency bandwidths are a subset of the first and second frequency bandwidths. | 2014-09-25 |
20140286171 | NODE, COMMUNICATION METHOD, AND COMMUNICATION SYSTEM - A node in an ad-hoc network includes a memory unit storing a concatenated counter value including an erasure counter value and a transmission counter value for the node; and a processor configured to: add one to the transmission counter value, when the node transmits data to another node in the ad-hoc network; transmit to the other node, the data and the updated concatenated counter value; detect erasure of the concatenated counter value in the memory unit; distribute in the ad-hoc network and upon detecting the erasure, an acquisition request for the erasure counter value; receive the erasure counter value consequent to the acquisition request; generate the concatenated counter value to include the received erasure counter value plus one and the transmission counter value after the erasure and indicating the number of transmissions as zero due to the erasure; and archive to the memory unit, the generated concatenated counter value. | 2014-09-25 |
20140286172 | Network-Based Service for the Repair of IP Multicast Sessions - A system and method are disclosed for the repair of IP multicast sessions. A repair server polls multiple transmit servers to accumulate as many of the packets missing from the multicast session as possible. A network includes a source of multicast packets in a multicast session and a plurality of multicast recipients in that session. A repair server in the network provides the packets it receives to the recipients. The repair server includes a missing packet detector. There is a plurality of retransmit servers in the network buffering portions of the packets they respectively receive during the session. The repair server maintains an ordered list of the retransmit servers that are most likely to have buffered copies of packets missing from the session. When the repair server detects that there are packets missing from the session it has received, it uses the ordered list to sequentially request the missing packets from respective ones of the plurality of retransmit servers. | 2014-09-25 |
20140286173 | SYSTEM AND METHOD FOR LAYER 3 RING PROTECTION WITH ADAPTIVE BANDWIDTH MICROWAVE LINKS IN A NETWORK ENVIRONMENT - A method is provided in one example and includes receiving a current bandwidth characteristic for a link, where the current bandwidth characteristic is determined under fading conditions associated with signal propagation on the link. The method can also include calculating a new cost for the link that is different from a nominal cost associated with a nominal bandwidth of the link without the fading conditions. The method could also include routing at least a portion of a plurality of flows that are to traverse the link away from the link based, at least in part, on the new cost. Another example method includes receiving the current bandwidth characteristic for the link, comparing the current bandwidth characteristic with a preconfigured low watermark corresponding to a class-specific MTR topology associated with a class of traffic traversing the link, and removing the link from the MTR topology based on the current bandwidth characteristic. | 2014-09-25 |
20140286174 | APPARATUS AND METHOD FOR ANALYZING A PACKET - An apparatus captures packets transmitted between first and second devices in accordance with first and second communication protocols, where the first and second protocols each assign a value for identifying a packet transmitted between first and second devices. In a state in which a first packet transmitted from the first device to the second device has not been captured yet at a time point of capturing an acknowledgment packet, responsive to the first packet, including a first value, upon capturing a second packet assigned a second value indicating order earlier than the first value, the apparatus determines whether the second packet is the first packet that is captured later than the acknowledgment packet, based on a difference between third and fourth values respectively assigned to the second packet and a previous packet that is captured latest among packets transmitted from the first device and captured earlier than the acknowledgment packet. | 2014-09-25 |
20140286175 | APPARATUS AND METHOD FOR CONTROLLING PACKET TRANSFER - An apparatus includes a plurality of receiving ports and a plurality of transmitting ports. The apparatus stores, in a memory thereof, transfer control information for transferring a packet to a node that is able to transfer the received packet, and monitors packets received via the plurality of receiving ports. Upon receiving a first packet conforming to a predetermined communication protocol and containing a frame including destination information being registered in the transfer control information, the apparatus rewrites a header of the first packet, based on the transfer control information, and transmits the first packet whose header has been rewritten via corresponding one of the plurality of transmitting ports indicated by the transfer control information. | 2014-09-25 |