39th week of 2017 patent applcation highlights part 56 |
Patent application number | Title | Published |
20170278743 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - A method of fabricating a semiconductor device. The method includes forming source/drain features in a substrate on opposite sides of a gate structure, forming an etch stop layer over the source/drain features, and depositing a dielectric layer on the etch stop layer. The method further includes performing a first atomic layer etching (ALE) process having a first operating parameter value on the dielectric layer to form a first part of an opening, and performing a second ALE process having a second operating parameter value to extend the opening to expose the source/drain features. The first operating parameter value is different from the second operating parameter value. | 2017-09-28 |
20170278744 | METHOD OF FORMING TRENCHES WITH DIFFERENT DEPTHS - A method of fabricating a semiconductor device includes forming a first dielectric layer over a substrate that includes a gate structure, forming a first trench in the first dielectric layer, forming dielectric spacers along sidewalls of the first trench, removing a portion of the dielectric spacers to expose a portion of the sidewalls, forming a first metal feature in the first trench over the another portion of the dielectric spacers and along the exposed portions of the sidewalls of the first trench, forming a second dielectric layer over the first metal feature and the gate structure and forming a second trench through the second dielectric layer to expose a portion of the first metal feature and a third trench through the second dielectric layer and the first dielectric layer to expose a portion of the gate structure in the same etching process. | 2017-09-28 |
20170278745 | OVERLAY MARKS, METHODS OF FORMING THE SAME, AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING THE SAME - In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed. | 2017-09-28 |
20170278746 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a first insulating interlayer and a sacrificial layer is sequentially formed on a substrate. The sacrificial layer is partially removed to form a first opening exposing an upper surface of the first insulating interlayer. An insulating liner including silicon oxide is conformally formed on the exposed upper surface of the first insulating interlayer and a sidewall of the first opening. At least a portion of the insulating liner on the upper surface of the first insulating interlayer and a portion of the first insulating interlayer thereunder are removed to form a second opening connected to the first opening. A self-forming barrier (SFB) pattern is formed on a sidewall of the second opening and the insulating liner. A wiring structure is formed to fill the first and second openings. After the sacrificial layer is removed, a second insulating interlayer is formed. | 2017-09-28 |
20170278747 | HIGH PERFORMANCE MIDDLE OF LINE INTERCONNECTS - A method for formation of multi-level contact structures with reduced contact resistance is provided. The contact resistance of the multi-level contact structures can be reduced by selectively removing portions of a contact liner layer that are formed along sidewalls and bottom portions of contact openings located in each contact level from the bottom portions of the contact openings. | 2017-09-28 |
20170278748 | DIRECT PLASMA DENSIFICATION PROCESS AND SEMICONDUCTOR DEVICES - An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz. | 2017-09-28 |
20170278749 | TUNGSTEN FEATURE FILL - Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs). | 2017-09-28 |
20170278750 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - When a MISFET is formed by using a gate last process and replacing dummy gate electrodes with metal gate electrodes, both of respective cap insulating films and an interlayer insulating film over a control gate electrode and the dummy gate electrodes are polished to prevent excessive polishing of the upper surface of the interlayer insulating film and the occurrence of dishing. In the gate last process, the interlayer insulating film is formed to cover the control gate electrode and the dummy gate electrodes as well as the cap insulating films located thereover. After the upper surface of the interlayer insulating is polished to expose the cap insulating films from the interlayer insulating films, etching is performed to selectively remove the cap insulating films. Subsequently, the upper surfaces of the interlayer insulating films are polished. | 2017-09-28 |
20170278751 | Semiconductor Device with Self-Aligned Contact - Self-aligned contacts are provided. In an embodiment the self-aligned contacts are formed by partially removing a first dielectric material from adjacent to a gate electrode and fully removing a second dielectric material from adjacent to the gate electrode. A conductive material is deposited into the regions of the removed first dielectric material and the second dielectric material, and the conductive material and metal gates are recessed below a spacer. A dielectric layer is deposited over the recessed conductive material and the recessed metal gates, and the self-aligned contacts are formed through the dielectric layer. | 2017-09-28 |
20170278752 | SELF-ALIGNED GATE CONTACT - The disclosed technology generally relates to semiconductor devices, and more specifically to electrical contacts to a transistor device, and a method of making such electrical contacts. In one aspect, a method of forming one or more self-aligned gate contacts in a semiconductor device includes providing a substrate having formed thereon at least one gate stack, where the gate stack includes a gate dielectric and a gate electrode formed over an active region in or on the substrate, and where the substrate further has formed thereon a spacer material coating lateral sides of the at least one gate stack. The method additionally includes selectively recessing the gate electrode of the at least one gate stack against the spacer material, thereby creating a first set of recess cavities. The method additionally includes filling the first set of recess cavities with a dielectric material gate cap. The method additionally includes etching at least one via above the at least one gate stack and through the dielectric material gate cap, where etching the at least one via comprises selectively etching against the spacer material, thereby exposing the gate electrode. The method further includes forming, in the at least one via, a gate contact electrically connecting the gate electrode. | 2017-09-28 |
20170278753 | GATE TIE-DOWN ENABLEMENT WITH INNER SPACER - A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact. | 2017-09-28 |
20170278754 | METHOD FOR PRODUCING GROUP III NITRIDE CRYSTAL, AND RAMO4 SUBSTRATE - A method for producing a Group III nitride crystal, includes: preparing an RAMO | 2017-09-28 |
20170278755 | Semiconductor Structures and Methods of Forming the Same - A method of forming a semiconductor structure may include: forming a first dielectric layer having a first thickness over a substrate; removing a first portion of the first dielectric layer to expose a second region of the substrate; forming a second dielectric layer having a second thickness over the second region of the substrate; removing a second portion of the first dielectric layer to expose a third region of the substrate; forming a third dielectric layer having a third thickness over the third region of the substrate; and forming a first plurality of gate stacks comprising the first dielectric layer in a first region of the substrate, a second plurality of gate stacks comprising the second dielectric layer in the second region of the substrate, and a third plurality of gate stacks comprising the third dielectric layer in the third region of the substrate. | 2017-09-28 |
20170278756 | METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE - A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack, a second gate stack, and a third gate stack, which are positioned over a semiconductor substrate and spaced apart from each other. The method includes removing portions of the semiconductor substrate to form a first recess, a second recess, and a third recess in the semiconductor substrate. The method includes forming a first doped structure, a second doped structure, and an isolation structure in the first recess, the second recess, and the third recess respectively. The first gate stack, the second gate stack, the first doped structure, and the second doped structure together form a memory cell. The isolation structure is wider and thinner than the second doped structure. A top surface of the isolation structure has a fourth recess. | 2017-09-28 |
20170278757 | Methods of Manufacturing Semiconductor Devices - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes an array having at least one first region and at least one second region. The first region includes at least one first device oriented in a first direction. The second region includes at least one second device oriented in a second direction. The second direction is different than the first direction. | 2017-09-28 |
20170278758 | METHOD FOR DETECTING BONDING FAILURE PART AND INSPECTION SYSTEM - A method for detecting a bonding failure part of a compound semiconductor chip cut from a compound semiconductor wafer in which a first transparent substrate composed of a compound semiconductor having a light-emitting layer is bonded with a second transparent substrate composed of a compound semiconductor, includes: irradiating the compound semiconductor chip with a coaxial vertical light, and identifying a color of a reflected-light from the bonding failure part of the compound semiconductor chip to detect the bonding failure part. As a result, a method for detecting a bonding failure part can precisely detect a bonding failure part on a bonding interface of a compound semiconductor chip cut from a compound semiconductor wafer in which two transparent substrates composed of a compound semiconductor are directly bonded with each other. | 2017-09-28 |
20170278759 | WORKPIECE EVALUATING METHOD - A workpiece evaluating method evaluates the gettering property of a device wafer having a plurality of devices formed on the front side of the wafer and having a gettering layer formed inside the wafer. The method includes the steps of applying excitation light for exciting a carrier to the wafer, applying microwaves to a light applied area where the excitation light is applied and also to an area other than the light applied area, measuring the intensity of the microwaves reflected from the light applied area and from the area other than the light applied area, subtracting the intensity of the microwaves reflected from the area other than the light applied area from the intensity of the microwaves reflected from the light applied area to thereby obtain a differential signal, and determining the gettering property of the gettering layer according to the intensity of the differential signal obtained above. | 2017-09-28 |
20170278760 | Intermediate Structure for Transfer, Method for Preparing Micro-device for Transfer, and Method for Processing Array of Semiconductor Device - A method for preparing a plurality of micro-devices for transfer includes temporarily bonding the micro-devices onto a carrier substrate; testing the micro-devices on the carrier substrate to determine if there is at least one first failed micro-device in the micro-devices; and removing the first failed micro-device from the carrier substrate. | 2017-09-28 |
20170278761 | System and Method for Temperature Control in Plasma Processing System - Techniques herein include systems and methods for fine control of temperature distribution across a substrate. Such techniques can be used to provide uniform spatial temperature distribution, or a biased spatial temperature distribution to improve plasma processing of substrates and/or correct characteristics of a given substrate. Embodiments include a plasma processing system with temperature control. Temperature control systems herein include a primary heating mechanism to heat a substrate, and a secondary heating mechanism that precisely modifies spatial temperature distribution across a substrate being processed. At least one heating mechanism includes a digital projection system configured to project a pattern of electromagnetic radiation onto or into a substrate, or through the substrate and onto a substrate support assembly. The digital projection system is configured to spatially and dynamically adjust the pattern of electromagnetic radiation and selectively augment heating of the substrate by each projected point location. | 2017-09-28 |
20170278762 | Redirecting solder material to visually inspectable package surface - A package comprising an electronic chip, a laminate type encapsulant in and/or on which the electronic chip is mounted, a solderable electric contact on a solder surface of the package, and a solder flow path on and/or in the package which is configured so that, upon soldering the electric contact with a mounting base, part of solder material flows along the solder flow path towards a surface of the package at which the solder material is optically inspectable after completion of the solder connection between the mounting base and the electric contact. | 2017-09-28 |
20170278763 | SEMICONDUCTOR DEVICE PACKAGE AND METHODS OF MANUFACTURE THEREOF - A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. | 2017-09-28 |
20170278764 | Surface Mount Device Package Having Improved Reliability - A semiconductor package for mounting to a printed circuit board (PCB) includes a case comprising a ceramic base, a semiconductor die in the case, a mounting pad under the ceramic base and coupled to the semiconductor die through at least one opening in the ceramic base. The mounting pad includes at least one layer having a coefficient of thermal expansion (CTE) approximately matching a CTE of the ceramic base. The mounting pad includes at least one layer having a low-yield strength of equal to or less than 200 MPa. The mounting pad includes at least one copper layer and at least one molybdenum layer. The semiconductor package also includes a bond pad coupled to another mounting pad under the ceramic base through a conductive slug in the ceramic base. | 2017-09-28 |
20170278765 | Semiconductor Device and Method of Forming Encapsulated Wafer Level Chip Scale Package (EWLCSP) - A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The fan-in interconnect structure includes an insulating layer and a conductive layer formed over the semiconductor die. The conductive layer remains within a footprint of the semiconductor die. A portion of encapsulant is removed from over the semiconductor die. A backside protection layer is formed over a non-active surface of the semiconductor die after depositing the encapsulant. The backside protection layer is formed by screen printing or lamination. The backside protection layer includes an opaque, transparent, or translucent material. The backside protection layer is marked for alignment using a laser. A reconstituted panel including the semiconductor die is singulated through the encapsulant to leave encapsulant disposed over a sidewall of the semiconductor die. | 2017-09-28 |
20170278766 | FAN-OUT SEMICONDUCTOR PACKAGE - A fan-out semiconductor package includes: a fan-out semiconductor package may include: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a reinforcing layer disposed on the encapsulant. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip. | 2017-09-28 |
20170278767 | HERMETIC PACKAGE WITH IMPROVED RF STABILITY AND PERFORMANCE - The present disclosure relates to a hermetic package with improved RF stability and performance. The package includes a carrier, a bottom dielectric ring over the carrier, a bottom metal layer over the bottom dielectric ring, a top dielectric ring over the bottom metal layer, a top metal layer over the top dielectric ring, an exterior plated layer, and multiple top vias. Herein, the bottom metal layer includes signal sections and at least one ground section, which is electrically isolated from the signal sections. The exterior plated layer covers at least a portion of a first exterior sidewall of the bottom ring structure and electrically couples the carrier to the at least one ground section. The multiple top vias extend through the top dielectric ring and electrically couple the top metal layer to the at least one ground section. | 2017-09-28 |
20170278768 | Packaged device with extended structure for forming an opening in the encapsualant - A packaged device includes an extended structure located at a major side of the packaged device. The extended structure defines an outer area that includes encapsulated material on the major side and an inner area where there is a lack of encapsulant over a portion of the device at the major side. The extended structure prevents encapsulant from getting into the inner area during the encapsulating process. | 2017-09-28 |
20170278769 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package includes a chip, a dam layer, a permanent adhesive layer, a support, a buffer layer, a redistribution layer, a passivation layer, and a conducting structure. A conducting pad and a sensing device of the chip are located on a first surface of a substrate of the chip, and the conducting pad protrudes from the side surface of the substrate. The dam layer surrounds the sensing device. The permanent adhesive layer is between the support and the substrate. The support and the permanent adhesive layer have a trench to expose the conducting pad. The buffer layer is located on the support. The redistribution layer is located on the buffer layer and on the support, the permanent adhesive layer, and the conducting pad facing the trench. The passivation layer covers the redistribution layer, the buffer layer, and the conducting pad. | 2017-09-28 |
20170278770 | SEMICONDUCTOR MODULE - An object of the present invention is to provide a semiconductor module with high heat dissipation at a low cost. A semiconductor module according to the present invention includes: a case having a hollow portion; a base board made of an aluminum alloy having a first portion corresponding to the hollow portion of the case, and a second portion corresponding to a main body portion of the case, the base board being attached to a bottom face of the case via the second portion; a ceramic insulating substrate disposed on the first portion of the base board; a wiring pattern disposed on the ceramic insulating substrate; semiconductor elements disposed on the wiring pattern; metal wiring boards connected to the semiconductor elements; and a sealing resin that seals the hollow portion of the case. | 2017-09-28 |
20170278771 | SEMICONDUCTOR DEVICE - A highly-reliable semiconductor device has improved adhesion between a sealing material and a sealed metal member and/or a case member. In some implementations, the semiconductor device includes: a laminated substrate on which a semiconductor element is mounted; and a sealing material. In some implementations, the sealing material contains an epoxy base resin, a curing agent, and a phosphonic acid. | 2017-09-28 |
20170278772 | DIELECTRIC HEAT PATH DEVICES, AND SYSTEMS AND METHODS USING THE SAME - Devices, systems, and methods for dissipating heat generated from an electrical current carrying device are provided herein. The disclosed concept provides a dielectric heat path device that assists in heat dissipation of an electrical current carrying device by transferring heat from one end of the device to another. The disclosed concept also provides systems that communicate heat generated by an electrical device to a thermally grounded secondary device through a dielectric heat path device to dissipate heat. | 2017-09-28 |
20170278773 | WATER-COOLING THERMAL DISSIPATING SYSTEM AND THERMAL DISSIPATIING METHOD - A water-cooling thermal dissipating system includes an electronic device and a thermal dissipating device. The electronic device includes a computing module includes a computing unit releasing heat when operation. The thermal dissipating device includes a thermal conducting unit, a pump, a tank, a thermal exchanger, and a controlling module; the thermal conductive unit is attached to the computing unit for thermal conduction; the pump is coupled to the thermal conductive unit, the pump, the tank, and the thermal exchanger for pumping a cooling-liquid therethrough, such that the cooling liquid is allowed to flow into the thermal conductive unit for absorbing heat. The controlling module generates an abnormal signal when the thermal dissipating device is sensed to be in an abnormal state, and the computing module forces to shut down the electronic device after continually receiving the abnormal signal for a predetermined time. | 2017-09-28 |
20170278774 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a semiconductor chip having an electrode on one surface; a first conductive member disposed on one surface side of the semiconductor chip; a metal member having a base member and a membrane and disposed between the semiconductor chip and the first conductive member; a first solder disposed between the electrode of the semiconductor chip and the metal member; and a second solder disposed between the metal member and the first conductive member. The membrane has a metal thin film arranged on the surface of the base member and an uneven oxide film. The uneven oxide film is arranged on the metal thin film in at least a part of a connection region of a surface of the metal member, the connection region connecting a first connection region to which the first solder is connected and a second connection region to which the second solder is connected. | 2017-09-28 |
20170278775 | SEMICONDUCTOR DIES WITH RECESSES, ASSOCIATED LEADFRAMES, AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one embodiment includes a semiconductor die having a first surface and a second surface facing opposite from the first surface, with the first surface having a die recess. The system can further include a support paddle carrying the semiconductor die, with at least part of the support paddle being received in the die recess. In particular embodiments, the support paddle can form a portion of a leadframe. In other particular embodiments, the support paddle can include a paddle surface that faces toward the semiconductor die and has an opening extending through the paddle surface and through the support paddle. | 2017-09-28 |
20170278776 | STRUCTURE AND METHOD FOR STABILIZING LEADS IN WIRE-BONDED SEMICONDUCTOR DEVICES - A semiconductor device having a leadframe including a pad ( | 2017-09-28 |
20170278777 | Package Structures and Methods for Forming the Same - A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface. | 2017-09-28 |
20170278778 | MICROELECTRONIC INTERCONNECT ADAPTOR - An interconnect adaptor may be fabricated having a substantially planar surface, to which a microelectronic package may be electrically attached, and a non-planar surface with at least one interconnect extending from the interconnect adaptor planar surface to the interconnect adaptor non-planar surface. The interconnect adaptor non-planar surface may be shaped to substantially conform to a shape of a microelectronic substrate to which it may be attached, which eliminates the need to bend or otherwise adapt the microelectronic package to conform to the microelectronic substrate. | 2017-09-28 |
20170278779 | PACKAGE SUBSTRATE WITH EMBEDDED CIRCUIT - A package substrate with embedded circuit is disclosed. The package substrate comprises a redistribution layer, the redistribution layer comprises a plurality of circuits, each circuit of the plurality of circuits runs with a top surface coplanar with a top surface of the dielectric material. | 2017-09-28 |
20170278780 | FORMING INTERCONNECT STRUCTURES UTILIZING SUBTRACTIVE PATERNING TECHNIQUES - Methods of forming conductive interconnect structures are described. Those methods/structures may include providing a package substrate comprising a substrate core, and forming at least one conductive interconnect structure disposed on the substrate core. The conductive interconnect structure may comprise a first side that is directly disposed on a surface of the substrate core, and a second side opposite the first side, wherein the second side comprises a greater length than a length of the first side. | 2017-09-28 |
20170278781 | WIRING BOARD - A wiring board of the present disclosure includes a core substrate, insulating layers, signal wiring conductors, ground wiring conductors, power-supply wiring conductors, a first mounting portion on which a first semiconductor device is to be mounted, a second mounting portion on which a second semiconductor device is to be mounted, many first-semiconductor-device connection pads connectable to signal electrodes of the first semiconductor device, many second-semiconductor-device connection pads connectable to signal electrodes of the second semiconductor device, and many signal connection conductors that connect the first-semiconductor-device connection pads to the second-semiconductor-device connection pads. The signal connection conductors include signal connection conductors of a first wiring group that extend only through a region above the top surface of the core substrate, and signal connection conductors of a second wiring group that extend through a region below the bottom surface of the core substrate. | 2017-09-28 |
20170278782 | ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME - An electrical interconnect assembly for use in an integrated circuit package includes a mounting substrate having a thickness defined between a first surface and a second surface thereof and at least one electrically conductive pad formed on the first surface of the mounting substrate. A metallization layer coats a surface of the at least one electrically conductive pad and is electrically coupled thereto. The metallization layer also coats portion of the first surface of the mounting substrate and extends through at least one via formed through the thickness of the mounting substrate. | 2017-09-28 |
20170278783 | MAGNETIC ALIGNMENT FOR FLIP CHIP MICROELECTRONIC DEVICES - Incorporating at least one magnetic alignment structure on a microelectronic device and incorporating at least one alignment coil within a microelectronic substrate, wherein the alignment coil may be powered to form a magnetic field to attract the magnetic alignment structure, thereby aligning the microelectronic device to the microelectronic substrate. After alignment, the microelectronic device may be electrically attached to the substrate. Embodiments may include additionally incorporating an alignment detection coil within the microelectronic substrate, wherein the alignment detection coil may be powered to form a magnetic field to detect variations in the magnetic field generated by the alignment coil in order verify the alignment of the microelectronic device to the microelectronic substrate. | 2017-09-28 |
20170278784 | IMAGING ELEMENT, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC DEVICE - An imaging element includes a layered structural body formed of a first electrode, a light receiving layer formed on the first electrode, and a second electrode formed on the light receiving layer, and a single first buffer layer formed of an amorphous organic material and a single second buffer layer formed of an amorphous inorganic material are provided between the light receiving layer and the second electrode from the light receiving layer side. | 2017-09-28 |
20170278785 | Interconnect Structure for Semiconductor Devices - An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing. | 2017-09-28 |
20170278786 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first lower line and a second lower line on a substrate, the first and second lower lines extending in a first direction, being adjacent to each other, and being spaced apart along a second direction, orthogonal the first direction, an airgap between the first and second lower lines and spaced therefrom along the second direction, a first insulating spacer on a side wall of the first lower line facing the second lower line, wherein a distance from the first airgap to the first lower line along the second direction is equal to or greater than an overlay specification of a design rule of the semiconductor device, and a second insulating spacer between the airgap and the second lower line. | 2017-09-28 |
20170278787 | MICROELECTRONIC COMPONENTS WITH FEATURES WRAPPING AROUND PROTRUSIONS OF CONDUCTIVE VIAS PROTRUDING FROM THROUGH-HOLES PASSING THROUGH SUBSTRATES - In a microelectronic component having conductive vias ( | 2017-09-28 |
20170278788 | STRUCTURE AND METHOD FOR MAXIMIZING AIR GAP IN BACK END OF THE LINE INTERCONNECT THROUGH VIA LANDING MODIFICATION - A method of forming an interconnect to an electrical device is provided. The structure produced by the method may include a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parallel lengths; and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines. | 2017-09-28 |
20170278789 | METHOD FOR LAYOUT DESIGN AND STRUCTURE WITH INTER-LAYER VIAS - A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. Such a method includes: placing a power supply rail pattern in a first device layer of the IC; bundling, for purposes of placement, a voltage level shifter and one or more inter-layer vias together as an integral unit; and placing the integral unit in the first device layer of the IC design such that one or more metal line patterns in the voltage level shifter are located parallel to albeit without overlapping the power supply rail pattern. The placing the integral unit forms a direct electrical connection channel between the voltage level shifter and a metal pattern in a second device layer of the IC design. At least one of the placing operations is performed using a layout generating machine. | 2017-09-28 |
20170278790 | ADVANCED E-FUSE STRUCTURE WITH CONTROLLED MICROSTRUCTURE - In one aspect of the invention, a method for fabricating an e-Fuse device is described. A trench structure is provided. The trench structure includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions. The trench is provided in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The trench is filled with copper. An annealing step converts the copper to create a large grained copper structure in the anode and cathode regions and a fine grained copper structure in the fuse element. Another aspect of the invention is an e-Fuse device which includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper structure and the fuse element is comprised of a fine grained copper structure. | 2017-09-28 |
20170278791 | ADVANCED E-FUSE STRUCTURE WITH HYBRID METAL CONTROLLED MICROSTRUCTURE - A structure and method for fabricating an e-Fuse device in a semiconductor device is described A method for fabricating an e-Fuse device includes providing a trench structure including an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. An aspect ratio reducing layer is selectively formed in the anode and cathode regions of the trench while leaving the fuse element region of the trench substantially free of the aspect ratio reducing layer. The trench is filled with copper, both over the aspect ratio reducing layer in the anode and cathode regions and in the fuse element region. The copper is annealed to create a large grained copper structure in the anode and cathode regions and a fine grained copper structure in the fuse element. Another aspect of the invention is an e-Fuse device. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper layer and an aspect ratio reducing layer, and the fuse element is comprised of a fine grained copper structure. | 2017-09-28 |
20170278792 | ADVANCED E-FUSE STRUCTURE WITH ENHANCED ELECTROMIGRATION FUSE ELEMENT - A structure and method for fabricating an e-Fuse device in a semiconductor device is described. A method for fabricating an e-Fuse device includes providing a trench structure including an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The trench is filled in the anode and cathode regions with a high electromigration (EM) resistant conductive material. The trench in the fuse element region is filled with a low EM resistant conductive material. Another aspect of the invention is an e-Fuse device. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a high EM-resistant conductive material. The fuse element is comprised of low EM-resistant conductive material. | 2017-09-28 |
20170278793 | ADVANCED E-FUSE STRUCTURE WITH HYBRID METAL CONTROLLED MICROSTRUCTURE - A structure of an e-Fuse device in a semiconductor device is described. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper layer and an aspect ratio reducing layer, and the fuse element is comprised of a fine grained copper structure. | 2017-09-28 |
20170278794 | ADVANCED E-FUSE STRUCTURE WITH ENHANCED ELECTROMIGRATION FUSE ELEMENT - A structure for an e-Fuse device in a semiconductor device is described. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a high EM-resistant conductive material. The fuse element is comprised of low EM-resistant conductive material. | 2017-09-28 |
20170278795 | ADVANCED E-FUSE STRUCTURE WITH CONTROLLED MICROSTRUCTURE - An advanced e-Fuse structure is described. An e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper structure and the fuse element is comprised of a fine grained copper structure. | 2017-09-28 |
20170278796 | Method for Maximizing Air Gap in Back End of the Line Interconnect through Via Landing Modification - A method of forming an interconnect to an electrical device is provided. The structure produced by the method may include a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parrallel lengths; and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines. | 2017-09-28 |
20170278797 | Semiconductor Devices Including a Capping Layer - Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided. | 2017-09-28 |
20170278798 | SEMICONDUCTOR DEVICE - An object of the present invention is to shorten the switching delay time of a semiconductor device. | 2017-09-28 |
20170278799 | PACKAGE-ON-PACKAGE TYPE PACKAGE INCLUDING INTEGRATED CIRCUIT DEVICES AND ASSOCIATED PASSIVE COMPONENTS ON DIFFERENT LEVELS - A package-on-package (PoP)-type package includes a first semiconductor package having a first passive element and a first semiconductor device mounted on a first substrate, and a second semiconductor package having a second semiconductor device mounted on a second substrate. The first passive element is electrically connected to the second semiconductor device. Related devices are also discussed. | 2017-09-28 |
20170278800 | HIGH ASPECT RATIO CONTACT METALLIZATION WITHOUT SEAMS - A low resistance middle-of-line interconnect structure is formed without liner layers. A contact metal layer is deposited on source/drain regions of field-effect transistors and directly on the surfaces of trenches within a dielectric layer using plasma enhancement. Contact metal fill is subsequently provided by thermal chemical vapor deposition. The use of low-resistivity metal contact materials such as ruthenium is facilitated by the process. The process further facilitates the formation of metal silicide regions on the source/drain regions. | 2017-09-28 |
20170278801 | HYBRID WAFER DICING APPROACH USING A ROTATING BEAM LASER SCRIBING PROCESS AND PLASMA ETCH PROCESS - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a rotating laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits. | 2017-09-28 |
20170278802 | TEST KEY STRCUTURES, INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING THE SAME - Test key structures, integrated circuit packages and methods of forming the same are disclosed. One of the test key structures includes a first pattern over a polymer layer, and at least one second pattern covering the first pattern. Besides, the second pattern and the first pattern have substantially the same outer profile, one of the first pattern and the second pattern includes a dielectric material and the other of the first pattern and the second pattern includes a metal material. | 2017-09-28 |
20170278803 | APPARATUS FOR STACKING SUBSTRATES AND METHOD FOR THE SAME - A substrate stacking apparatus that stacks first and second substrates on each other, by forming a contact region where the first substrate held by a first holding section and the second substrate held by a second holding section contact each other, at one portion of the first and second substrates, and expanding the contact region from the one portion by releasing holding of the first substrate by the first holding section, wherein an amount of deformation occurring in a plurality of directions at least in the first substrate differs when the contact region expands, and the substrate stacking apparatus includes a restricting section that restricts misalignment between the first and second substrates caused by a difference in the amount of deformation. In the substrate stacking apparatus above, the restricting section may restrict the misalignment such that an amount of the misalignment is less than or equal to a prescribed value. | 2017-09-28 |
20170278804 | ELECTRONIC CIRCUIT PACKAGE - Disclosed herein is an electronic circuit package includes: a substrate having a power supply pattern; an electronic component mounted on a surface of the substrate; a mold resin covering the surface of the substrate so as to embed therein the electronic component; a magnetic film formed so as to contact at least a top surface of the mold resin; and a metal film electrically connected to the power supply pattern and covering the mold resin through the magnetic film. | 2017-09-28 |
20170278805 | LARGE SCALE INTEGRATED CIRCUIT CHIP AND LARGE SCALE INTEGRATED CIRCUIT WAFER - A large scale integrated circuit chip includes a semiconductor circuit having a multilayered wiring structure, a metal guard ring surrounding the semiconductor circuit, and a plurality of external connection terminals, on a semiconductor circuit. The plurality of external connection terminals connect to an uppermost-layer wiring of the multilayered wiring structure and are exposed on a surface of the large scale integrated circuit chip. A predetermined external connection terminal conducts to a predetermined wiring through a conductive via within the guard ring and conducts to a conductive piece through another conductive via outside the guard ring. One side of the external connection terminal extending over the guard ring connects to the conductive piece, and the other side of the external connection terminal connects to the uppermost-layer wiring within the guard ring. Thus, a cutout part is not necessary in the guard ring. | 2017-09-28 |
20170278806 | COAXIAL THROUGH VIA WITH NOVEL HIGH ISOLATION CROSS COUPLING METHOD FOR 3D INTEGRATED CIRCUITS - A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground. The ground shielding layer drives radiation signals received therein to ground to prevent induced noise in the first signal path. | 2017-09-28 |
20170278807 | ELECTRONIC PACKAGE WITH ANTENNA STRUCTURE - Provided is an electronic package, including: a carrier, an electronic component disposed on the carrier, and an antenna structure, wherein the antenna structure has a plurality of spacing members and at least one wire connected among the spacing members. No additional layout area is required to be formed on a surface of the carrier, such that the objective of miniaturization can be achieved. | 2017-09-28 |
20170278808 | ANTENNA CAVITY STRUCTURE FOR INTEGRATED PATCH ANTENNA IN INTEGRATED FAN-OUT PACKAGING - A method for forming an integrated fan-out package includes depositing an adhesive layer on a carrier, forming a back-side buffer layer over the adhesive layer, forming a back-side redistribution metal layer on the back-side buffer layer, wherein the back-side redistribution metal layer includes one or more ground plane structures, forming one or more through-insulator vias (TIVs) and one or more cavity sidewalls on the one or more ground plane structures, placing a radio frequency (RF) integrated circuit (IC) die on the back-side buffer layer, laterally encapsulating the RF IC die, the one or more TIVs, the one or more cavity sidewalls, with a molding compound, thus forming an interim substrate, wherein the cavity sidewalls and their associated ground plane structure define one or more antenna cavities, and forming a top-side redistribution (RDL) wiring structure on the interim substrate, the top-side RDL wiring structure including one or more integrated patch antenna structure, wherein the one or more integrated patch antenna structure is coupled to the RF IC die and each of the one or more integrated patch antenna structure is positioned over one of the antenna cavities. | 2017-09-28 |
20170278809 | SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF - A method of fabricating a semiconductor structure includes: forming a conductive layer on a first insulating layer; etching a portion of the conductive layer to expose a portion of the first insulating layer; deforming a surface of the portion of the first insulating layer to form a rough surface of the first insulating layer; and removing a residue of the conductive layer on the rough surface of the first insulating layer. | 2017-09-28 |
20170278810 | EMBEDDED DIE IN PANEL METHOD AND STRUCTURE - Methods for an embedded die panel are disclosed and may include fabricating a first layered structure by: forming first redistribution layers on a first carrier, forming a first dielectric layer on the first redistribution layers and carrier, forming a mask pattern on the first dielectric layer exposing a portion of the first dielectric layer, forming a second dielectric layer on the exposed portion of the first dielectric layer, forming vias in the first and second dielectric layers, and forming second redistribution layers on the second dielectric layer. The mask pattern may be removed forming a die cavity defined by the second dielectric layer. A second layered structure coupled to the first layered structure may be formed comprising a second carrier, a third dielectric layer, third and fourth redistribution layers on opposite surfaces of the third dielectric layer, and a semiconductor die. | 2017-09-28 |
20170278811 | SIGNAL TRANSMISSION INSULATIVE DEVICE AND POWER SEMICONDUCTOR MODULE - A signal transmission insulating device includes: a first coil; a second coil opposing the first coil to form a transformer together with the first coil; a first insulating film provided between the opposing first coil and second coil and made of a first dielectric material; a second insulating film surrounding the first coil and made of a second dielectric material having a lower resistivity or a higher permittivity than the first dielectric material; and a third insulating film surrounding the second coil and made of a third dielectric material having a lower resistivity or a higher permittivity than the first dielectric material. | 2017-09-28 |
20170278812 | FAN-OUT SEMICONDUCTOR PACKAGE - A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; a passivation layer disposed on the second interconnection member; and an under-bump metal layer including an external connection pad formed on the passivation layer and a plurality of vias connecting the external connection pad and the redistribution layer of the second interconnection member to each other, wherein the first interconnection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chip. | 2017-09-28 |
20170278813 | PLATING METHOD - A plating method which can achieve a desired dome height is disclosed. The method includes: preparing correlation data showing a relationship between proportion of dome height to bump height and concentration of chloride ions; producing a plating solution containing chloride ions at a concentration which has been selected based on a desired proportion of dome height to bump height and on the correlation data, the selected concentration being in a range of 100 mg/dm | 2017-09-28 |
20170278814 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR PACKAGES - A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall. | 2017-09-28 |
20170278815 | METAL PILLAR WITH CUSHIONED TIP - A metal pillar with cushioned tip is disclosed. The cushioned tip offsets height difference among metal pillars. So that the height difference among metal pillars gives no significant effect to electrical coupling. The cushioned tip is a metal sponge. Additional one embodiment shows a second metal is plated on a tip of the metal sponge. A hardness of the second metal is greater than a hardness of a metal of the metal sponge, so that the second metal can stab into a corresponding metal sponge for electrical coupling. | 2017-09-28 |
20170278816 | VARIABLE BALL HEIGHT ON BALL GRID ARRAY PACKAGES BY SOLDER PASTE TRANSFER - BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold solder paste material applied to the mold, for example with a solder paste printing process. The depth and/or diameter of the cavities may be predetermined as a function of spatial position within the mold working surface area. Mold cavity dimensions may be specified corresponding to package position to account for one or more pre-existing or expected spatial variations in the package, such as a package-level warpage measurement. Any number of different ball heights may be provided. The molds may be employed in a standardize process that need not be modified with each change in the mold. | 2017-09-28 |
20170278817 | CHIP ALIGNMENT UTILIZING SUPEROMNIPHOBIC SURFACE TREATMENT OF SILICON DIE - Certain embodiments of the present disclosure provide a method for soldering a chip onto a surface. The method generally includes forming a bonding pad on the surface on which the chip is to be soldered, wherein the bonding pad is surrounded, at least in part, by dielectric material. The method may also include treating the dielectric material to render the dielectric material superomniphobic, and soldering the chip onto the bonding pad. | 2017-09-28 |
20170278818 | HIGH TEMPERATURE SOLDER PASTE - Embodiments herein may relate to a solder paste. The solder paste may include a solder powder and a flux. In embodiments, the flux may be a non-rosin based flux. The flux may further include a thixotropic agent (TA) that may be a non-polymer based TA. Other embodiments may be described and/or claimed. | 2017-09-28 |
20170278819 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - A semiconductor device includes a board having a solder resist layer with first and second openings on a first surface, and a first electrode on the first surface, a portion thereof exposed in the first opening and electrically connected to the board. A second electrode is located on the first surface having a portion exposed in the second opening and electrically connected to the board. A portion of the second electrode is covered by the solder resist layer. A first solder bump is on the first electrode and covers a side surface. A second solder bump is on the second electrode. A semiconductor chip has a first region and a second region facing the first surface. A third electrode is in the first region and electrically connected to the first solder bump. A fourth electrode is in the second region and electrically connected to the second solder bump. | 2017-09-28 |
20170278820 | ANISOTROPIC CONDUCTIVE FILM AND CONNECTION STRUCTURE - An anisotropic conductive film including an electrically insulating adhesive layer, and electrically conductive particles disposed on the electrically insulating adhesive layer. In such an anisotropic conductive film, the electrically conductive particles are disposed in a lattice by being arranged in first direction rows and second direction rows, and narrow and wide intervals are provided between neighboring rows in at least one of the direction rows. As a result, opposing terminals are stably connected using the anisotropic conductive film, inspection after the connecting is more easily performed, and the number of electrically conductive particles not involved in the connection are reduced and, thereby, the manufacturing cost of the anisotropic conductive film is reduced, even in FOG connections or the like with finer bump pitches. | 2017-09-28 |
20170278821 | OVERLAPPING STACKED DIE PACKAGE WITH VERTICAL COLUMNS - Some forms relate to an electronic assembly ( | 2017-09-28 |
20170278822 | METHOD FOR PRODUCING A SEMI-CONDUCTOR ARRANGEMENT AND CORRESPONDING SEMI-CONDUCTOR ARRANGEMENT - A method for producing a semiconductor arrangement, said method includes fastening a semiconductor on a base element by means of a sintered layer, wherein a side of the sintered layer which faces the base element is configured planar; and perforating a region of the base element, which directly contacts the sinter, wherein the perforating includes generating a plurality of through-openings having a closed border in the region of the base element for adjusting a stiffness of at least a portion of the base element in a targeted manner | 2017-09-28 |
20170278823 | PACKAGE PROCESS AND PACKAGE STRUCTURE - A package structure includes: 1) a circuit substrate; 2) a first semiconductor device disposed on the circuit substrate; 3) a first insulation layer covering a sidewall of the first semiconductor device; 4) a second insulation layer covering the first insulation layer; and 5) a third insulation layer disposed on the circuit substrate and in contact with the second insulation layer. | 2017-09-28 |
20170278824 | SEMICONDUCTOR MODULE - A semiconductor module ( | 2017-09-28 |
20170278825 | Apparatus and Methods for Multi-Die Packaging - A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate. | 2017-09-28 |
20170278826 | SOLID-STATE IMAGE CAPTURING APPARATUS AND ELECTRONIC DEVICE - The present technology relates to a solid-state image capturing apparatus and an electronic device that can acquire a normal image and a narrow band image at the same time. The solid-state image capturing apparatus includes a plurality of substrates laminated in two or more layers, and two or more substrates of the plurality of substrates have pixels that perform photoelectric conversion. At least one substrate of the substrates having the pixels is a visible light sensor that receives visible light, and at least another substrate of the substrates having the pixels is a narrow band light sensor that includes narrow band filters being optical filters permeating light in a narrow wavelength band, and receives narrow band light in the narrow band. | 2017-09-28 |
20170278827 | PACKAGE-ON-PACKAGE SEMICONDUCTOR DEVICE - Some embodiments relate to a semiconductor device. The semiconductor device includes a substrate. A first die is coupled beneath a lower surface of the substrate. A second die is coupled beneath the lower surface of the substrate and is disposed over the first die. A thermal contact pad is arranged beneath a lower surface of the second die and an upper surface of the first die. The thermal contact pad thermally isolates the first die from the second die. | 2017-09-28 |
20170278828 | Die Stack Assembly Using An Edge Separation Structure For Connectivity Through A Die Of The Stack - A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends from the top planar semiconductor surface of the first die all the way to the bottom planar semiconductor surface of the die, and that is doped at least in part with aluminum. The backside of the first die is mounted to the backside of the second die. A metal feature that is not covered with passivation, and that can serve as a bonding pad, is disposed on part of the peripheral edge separation structure. A metal member (for example, a bond wire or metal clip) contacts the metal feature such that an electrical connection is established from the metal member, through the metal feature, through the peripheral edge separation structure of the first die, and to an electrode of the second die. | 2017-09-28 |
20170278829 | OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND FLASHLIGHT - Optoelectronic semiconductor component includes at least four different light sources each including at least one optoelectronic semiconductor chip, which during operation emit radiation having mutually different colour loci in the CIE standard chromaticity diagram, wherein the semiconductor component is designed to emit white or coloured light having a variable correlated colour temperature during operation. | 2017-09-28 |
20170278830 | SEMICONDUCTOR PACKAGES HAVING REDUCED STRESS - A semiconductor package comprises a lower package, a metal layer on the lower package, a ground member on the metal layer, coupled thereto, and an upper package on the lower package. The upper package comprises a ground pattern on a first insulation pattern. The first insulation pattern is on a bottom surface of the upper package and has a hole through which the ground pattern is exposed. The ground member extends inside the hole and is coupled to the ground pattern. | 2017-09-28 |
20170278831 | ARRAY SUBSTRATE OF ORGANIC LIGHT-EMITTING DIODES AND METHOD FOR PACKAGING THE SAME - An array substrate of organic light-emitting diodes and a method for fabricating the same are provided to narrow an edge frame of product device of organic light-emitting diodes, to shorten the package process time, and to improve the substrate utilization and the production efficiency. The array substrate of organic light-emitting diodes includes a plurality of display panels disposed in an array of rows and columns, wherein at least two adjacent display panels are connected through a frame adhesive, and there is no cutting headroom between at least one side of the at least two adjacent display panels. | 2017-09-28 |
20170278832 | SEMICONDUCTOR PACKAGE ASSEMBLY - In one implementation, a semiconductor package assembly includes a first semiconductor package having a first semiconductor die and a first redistribution layer (RDL) structure coupled to the first semiconductor die. The first redistribution layer (RDL) structure includes a first conductive trace at a first layer-level, a second conductive trace at a second layer-level, and a first inter-metal dielectric (IMD) layer and a second inter-metal dielectric (IMD) layer , which is beside the first inter-metal dielectric (IMD) layer, wherein the second inter-metal dielectric (IMD) layer is disposed between the first conductive trace and the second conductive trace, and the second inter-metal dielectric (IMD) layer is zigzag shape in a cross-sectional view. | 2017-09-28 |
20170278833 | SEMICONDUCTOR PACKAGE - A semiconductor package may include a DRAM chip mounted on a substrate; an interposer stacked over the DRAM chip and including redistribution structures; a nonvolatile memory chip stacked over the interposer; a memory controller chip mounted on the substrate, and including a control circuit for controlling the nonvolatile memory chip and first pads and second pads electrically coupled to the control circuit; first conductive coupling members configured to electrically couple bonding pads of the nonvolatile memory chip to the redistribution structures; second conductive coupling members configured to electrically couple the redistribution structures to the first pads; and third conductive coupling members configured to electrically couple the second pads to the substrate. | 2017-09-28 |
20170278834 | METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE - A method of manufacturing a light emitting element includes forming a resin film including a phosphor containing layer on a transparent board side surface of a wafer including a transparent board and a plurality of light emitting parts formed on the transparent board, forming a scribing line along a scheduled separation surface in a surface of the transparent board by scribing before or after forming the resin film, cutting the resin film along the scheduled separation surface before or after forming the scribing line, and separating the transparent board along the scheduled separation surface by breaking after forming the scribing line and cutting the resin film. | 2017-09-28 |
20170278835 | LED CHIP MOUNTING APPARATUS AND METHOD OF MANUFACTURING DISPLAY APPARATUS BY USING THE LED CHIP MOUNTING APPARATUS - A light emitting diode chip mounting apparatus includes a guide plate including a first surface and a second surface opposite to the first surface, the second surface including at least one first tunnel that extends in a first direction, wherein the first tunnel defines a concave portion and the second surface includes a convex portion adjacent to the concave portion. The first tunnel is sized to accommodate a light emitting diode chip flowing therethrough. | 2017-09-28 |
20170278836 | Integrated System and Method of Making the Integrated System - A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads. | 2017-09-28 |
20170278837 | SEMICONDUCTOR POWER DEVICE HAVING SHIELDED GATE STRUCTURE AND ESD CLAMP DIODE MANUFACTURED WITH LESS MASK PROCESS - A semiconductor power device having shielded gate structure in an active area and having ESD clamp diode with two poly-silicon layer process is disclosed, wherein: the shielded gate structure comprises a first poly-silicon layer to serve as a shielded electrode and a second poly-silicon layer to serve as a gate electrode, and the ESD clamp diode formed between two protruding electrodes is also formed by the first poly-silicon layer. A mask specially used to define the ESD clamp diode portion is saved. | 2017-09-28 |
20170278838 | SENSOR DEVICE - In conventional sensor devices, it has been difficult to achieve both EMC resistance and ESD resistance, which are required at the output terminals of an automobile sensor device. A sensor device | 2017-09-28 |
20170278839 | ELECTROSTATIC DISCHARGE PROTECTION USING A GUARD REGION - A silicon controlled rectifier (SCR) circuit is configured to shunt electrostatic discharge (ESD) current from a node to a reference voltage. The SCR circuit includes a first bipolar PNP transistor having a first emitter connected to the node, a first base, and a first collector. A second bipolar NPN transistor has a second collector sharing a first region with the first base, a second base sharing a second region with the first collector, and an emitter electrically connected to the reference voltage. A guard region is configured and arranged to delay triggering of the SCR circuit in response to an ESD event by impeding current flow in the second region. | 2017-09-28 |
20170278840 | ELECTROSTATIC DISCHARGE (ESD) PROTECTION IN AN ELECTRONIC SWITCHING CIRCUIT - Aspects disclosed herein include electrostatic discharge (ESD) protection in an electronic switching circuit. An electronic switching circuit includes switching circuitry configured to provide interconnectivity between a common port in at least one common branch and an input/output (I/O) port in at least one I/O branch. The common branch and the I/O branch each include a blocking capacitor element that is inherently incapable for ESD discharging. As such, an ESD clamp is disposed in parallel to the blocking capacitor element to provide a low-impedance ESD discharging path around the blocking capacitor element. By disposing the ESD clamp in parallel to the blocking capacitor element, it is possible to minimize detrimental parasitic effects of the ESD clamp, thus improving performance and reliability of the electronic switching circuit, especially for high power switching circuits such as a radio frequency (RF) switching circuits. | 2017-09-28 |
20170278841 | ELECTRONIC DEVICE WITH INTEGRATED GALVANIC ISOLATION, AND MANUFACTURING METHOD OF THE SAME - An electronic device includes a semiconductor body and a dielectric layer extending over the semiconductor body. A galvanic isolation module includes a first metal region extending in the dielectric layer at a first height and a second metal region extending in the dielectric layer at a second height greater than the first height. The first and second metal regions are capacitively or magnetically coupleable together. The second metal region includes a side wall and a bottom wall coupled to one another through rounded surface portions. | 2017-09-28 |
20170278842 | INTEGRATED CIRCUITS INCLUDING A FINFET AND A NANOSTRUCTURE FET - An integrated circuit includes a FinFET and a nanostructure FET. The integrated circuit includes a bulk substrate. The integrated circuit also includes a fin field effect transistor (FinFET) coupled to the bulk substrate. The FinFET includes a first source region, a first drain region, and a fin extending between the first source region and the first drain region. The integrated circuit also includes a nanostructure FET coupled to the bulk substrate. The nanostructure FET includes a second source region, a second drain region, and a stack of at least two nanostructures extending between the second source region and the second drain region. | 2017-09-28 |