39th week of 2021 patent applcation highlights part 78 |
Patent application number | Title | Published |
20210305923 | PROTECTION CIRCUIT FOR AN ELECTRIC MOTOR WITH A SINGLE-PHASE WINDING, AN ELECTRIC CENTRIFUGAL PUMP AND AN OIL MIST SEPARATOR WITH SUCH A PROTECTION CIRCUIT - A protection circuit for an electric motor with a single phase winding, consisting of two coil sections with central tapping, wherein the two coil ends of the coil sections are each connected to ground via a switching element. The task of the invention is for an electric motor of this type to ensure a thermal relief for the switching elements, improved and smoother running, reduced warming of the printed circuit board, improved EMC characteristics, a more robust design of the overall switching, a focused conduction of the losses and an extra protection against any surge impulses from a mains network. | 2021-09-30 |
20210305924 | MOTOR CONTROL APPARATUS - A motor control apparatus includes control circuitry and rotation direction adjusting circuitry. The control circuitry is configured to output, in accordance with a phase sequence with respect to a motor, a drive command signal which is generated based on a motor rotation signal output from a motor rotation detector to control the motor. The rotation direction adjusting circuitry is configured to match the phase sequence with rotation direction information included in the motor rotation signal if a first trouble signal showing excessive motor current or excessive motor speed is input via an operation unit. | 2021-09-30 |
20210305925 | DRIVE CONTROLLER, SHEET PROCESSING APPARATUS AND LOAD STARTING METHOD - A drive controller includes a first drive circuit, a first capacitance element and a first processing part and a second processing part. The first drive circuit supplies a current output from a power source to a first load. The first capacitance element is connected to a power supply path between the power source and the first drive circuit. The first processing part is configured to apply a charge from the power source and to charge the first capacitance element before power supply to the first load is started. The second processing part is configured to supply a current output from the power source and a current corresponding to a charge charged in the first capacitance element to the first load through the first drive circuit after the first capacitance element is charged. | 2021-09-30 |
20210305926 | ROTATIONAL ELECTRIC MACHINE, DRIVE CONTROL SYSTEM, AND POWER GENERATION METHOD - A rotational electric machine includes: a stator configured to generate a rotating magnetic field by an alternating current converted from a power supply voltage of a battery; a rotor configured to rotate by the rotating magnetic field; a field coil configured to excite the rotor by a direct current converted from a power supply voltage of the battery; an acquisition unit configured to acquire the power supply voltage and an induced voltage of the rotational electric machine; and a power generation control unit configured to perform regenerative power generation when the induced voltage acquired is lower than a preset voltage equal to or lower than the power supply voltage acquired, and to perform alternator power generation by the induced voltage when the induced voltage acquired is equal to or higher than the preset voltage. | 2021-09-30 |
20210305927 | FLEXIBLE FAULT DETECTION - A system for controlling a high-power drive device includes a fault detection integrated circuit product configured to provide an indication of a fault condition associated with the high-power drive device to a first terminal in a first voltage domain in response to detecting the fault condition in a second voltage domain. The system includes a gate driver controller integrated circuit product configured to drive a second terminal coupled to a control node in a second voltage domain based on a control signal and an enable signal received from a third terminal in the first voltage domain. The second voltage domain is higher than the first voltage domain. The system may include a redundant fault reporting integrated circuit product or an additional fault detection integrated circuit product configured to detect a second fault condition in the second voltage domain that is different from the fault condition. | 2021-09-30 |
20210305928 | MOTOR-DRIVING APPARATUS - A motor-driving apparatus for driving a motor having a plurality of windings respectively corresponding to a plurality of phases is provided. The motor-driving apparatus includes a first inverter having a plurality of first switching devices and connected to first ends of the plurality of windings and a second inverter having a plurality of second switching devices and connected to second ends of the plurality of windings. A third switching device is configured to selectively connect and disconnect points at which a number of turns of each of the windings is divided in a preset ratio. A controller is configured to adjust an on/off state of the first to third switching devices based on required output of the motor. | 2021-09-30 |
20210305929 | DETECTION OF UNBALANCED PHASE RESISTANCES IN SYNCHRONOUS MOTOR DRIVES - A system for controlling a synchronous motor drive may be configured to receive a command voltage signal and to identify, in the synchronous motor drive, a resistance imbalance signature from the command voltage signal. The system may determine, based on the resistance imbalance signature, respective phase resistances that correspond to phases of a synchronous motor of the synchronous motor drive. Each respective phase resistance may include a phase transistor resistance and a phase winding resistance. The system may identify, based on the phase resistances and an estimated average resistance between the phases of the synchronous motor, one or more phases of the synchronous motor that correspond to one or more phase resistances representing a resistance imbalance. | 2021-09-30 |
20210305930 | ROTARY CONNECTOR - In response to a measured value of temperature of a stator by a thermometer exceeding a first temperature threshold, an overheat signal may be output to a rotor of a rotary connector via a communication device. In response to the measured value of the temperature exceeding a second temperature threshold higher than the first temperature threshold, power supply to a transmission coil that transmits power to a receiving coil of the rotor in a non-contact manner is stopped. In response to the overheat signal being received or a measured value of temperature of the rotor by a thermometer exceeding a third temperature threshold, a limit signal for limiting current flowing through a load circuit is output. In response to the measured value of the temperature by the thermometer exceeding a fourth temperature threshold higher than the third temperature threshold, output of power received from the stator is stopped. | 2021-09-30 |
20210305931 | AC ROTATING ELECTRIC MACHINE CONTROL DEVICE - A control device for an AC rotating electric machine includes: a temperature detection unit configured to detect a temperature of a protection part; a maximum current adjustment unit configured to adjust a maximum current of an AC rotating electric machine so as to prevent the temperature of the protection part from exceeding a set temperature; an allowable torque calculation unit configured to calculate an allowable torque based on the maximum current adjusted; a torque command adjustment unit configured to adjust a torque command value directed to the AC rotating electric machine based on the allowable torque; an upper limit number-of-rotation calculation unit configured to calculate an upper-limit number of rotations of the AC rotating electric machine based on the maximum current adjusted; and a number-of-rotation adjustment unit configured to adjust the number of rotations of the AC rotating electric machine based on the upper-limit number of rotations. | 2021-09-30 |
20210305932 | SELF-POWERED SOLAR TRACKER APPARATUS - A solar tracker apparatus includes an adjustable hanger assembly that has a clam shell hanger assembly. The clam shell hanger assembly may hold a torque tube comprising a plurality of torque tubes configured together in a continuous length from a first end to a second end. A center of mass of the solar tracker apparatus may be aligned with a center of rotation of the torque tubes, in order to reduce a load of a drive device operably coupled to the torque tube. Solar modules may be coupled to the torque tubes. The solar tracker includes an energy system that includes solar panel, a DC to DC converter, a battery, and a micro-controller. The energy system may facilitate full operation movement of the tracker apparatus without any external power lines. | 2021-09-30 |
20210305933 | Systems For Cleaning And Analysis of NonPorous Surfaces - Implementations of a solar panel cleaning system may include an extrusion frame; a driver end coupled to a first side of the extrusion frame; a battery end coupled to a second side of the extrusion frame; a solar panel coupled to a largest planar surface formed by the extrusion frame, the solar panel electrically coupled with a battery included in the battery end, the battery electrically coupled with one or more motors and with a controller included in the driver end; and one or more brushes coupled between the driver end and the battery end, an end of the one or more brushes coupled with the one or more motors. The driver end and the battery end may be configured to couple with one of a track that extends on either side of one or more solar panels or with edges of the one or more solar panels. | 2021-09-30 |
20210305934 | Wiring Device Of Photovoltaic Equipment - A wiring device of photovoltaic power generation equipment includes an aluminum wire and a copper-aluminum transition element. One end of the aluminum end is connected with the aluminum end of the copper-aluminum transition piece, and the other end of the aluminum end is configured to connect with an external connecting component. The copper end is configured to connect with photovoltaic power generation equipment. In the wiring device of the photovoltaic power generation equipment provided in the present application, the copper-aluminum transition piece is arranged at the position of the photovoltaic power generation equipment, and the aluminum end of the copper-aluminum transition piece is connected to the external connecting component by the aluminum wire, avoiding using copper wire for long-distance conduction. The cost of the aluminum wire is much lower than that of the copper wire. Therefore, the cost of the wiring device provided by the application is reduced. | 2021-09-30 |
20210305935 | SOLAR THERMAL UNIT - Solar thermal units and methods of operating solar thermal units for the conversion of solar insolation to thermal energy are provided. In some examples, solar thermal units have an inlet, and a split flow of heat absorbing fluid to either side of the solar thermal unit, along a first fluid flow path and a second fluid flow path. Optionally, one or more photovoltaic panels can be provided as part of the solar thermal unit, which may convert solar insolation to electric power that may be used by a system connected to the solar thermal unit. | 2021-09-30 |
20210305936 | METHOD, COMPUTER-IMPLEMENTED TOOL AND POWER PLANT CONTROL DEVICE FOR DETECTING POWER PRODUCTION DEGRADATION OF SOLAR POWER PLANTS AND SOLAR POWER PLANT SYSTEM - In order to detect power production degradation of a solar power plant (SPP) with at least one photovoltaic module (PVM), by which the detection of power production degradation, affected for instance by long term aging or soiling of the photovoltaic module of the solar power plant, is automated and carried out sensorless, it is proposed to determine the degradation by calibrating local measurements of data related to module/plant-internal parameters (PT) such as irradiance I and temperature T or electric power P and temperature as measurement data (MD | 2021-09-30 |
20210305937 | DEVICE AND METHOD FOR DETERMINING WHETHER POWER GENERATION SYSTEM IS ABNORMAL - The present invention relates to a device for determining whether a power generation system is abnormal. More specifically, the device may comprise: a communication unit for receiving power generation data from at least one power generation system; a storage unit for storing the received data; and a processor for selecting, from the collected data, power generation systems in a similar region, and determining whether a specific power generation system is abnormal by comparing the power generation times and power generation amounts of the power generation systems in the similar region. | 2021-09-30 |
20210305938 | OPTOELECTRONIC SOLAR CELL TEST SYSTEM FOR AN IN-LINE SOLAR CELL PRODUCTION PLANT, AND METHOD FOR OPTIMIZING THE IN-LINE PRODUCTION OF SOLAR CELLS USING AN OPTOELECTRONIC SOLAR CELL TEST SYSTEM OF THIS TYPE - An optoelectronic solar cell test system including an exposure and measuring device for in-line measurement of solar cells and a control and evaluation unit, the exposure and measuring device configured to carry out test measurements for generating test-measurement data on a solar cell. The control and evaluation unit is configured to perform statistical analyses using data from identical test measurements undertaken by the exposure and measuring device on a plurality of solar cells produced in-line, and to correlate statistical analyses of the data from different test measurements with one another, and/or to correlate statistical analyses of test measurement data with statistical analyses of production measurement data, and/or to correlate statistical analyses of test measurement data and/or statistical analyses of production measurement data with production input data, in order generate correlation results, and to derive from the correlation results, and communicate, an action recommendation or instruction to a personnel group. | 2021-09-30 |
20210305939 | FAST START-UP CRYSTAL OSCILLATOR - An apparatus injects a start clock to a crystal at the beginning to increase an overall start up speed of the crystal. The apparatus relies on an impedance change inside the crystal itself instead of searching for a synchronization on the yet small crystal oscillation. The apparatus includes an oscillator (separate from the crystal) to search for the crystal's resonance frequency by detecting the crystal's impedance change. Once the frequency of the oscillator matches the crystal's resonance, there is significant change in the crystal's impedance. Using that information, the apparatus can lock the oscillator frequency at the crystal resonance frequency and inject the clock with high efficiency. | 2021-09-30 |
20210305940 | APPARATUS, CIRCUITS AND METHODS FOR CLOCK GENERATION - Apparatus, circuits and methods for clock generation are disclosed herein. In some embodiments, an apparatus is disclosed. The apparatus includes: a first transistor pair electrically coupled to a pair of output nodes; a second transistor pair electrically coupled to the pair of output nodes; and an inductive unit electrically coupled between the output nodes and electrically coupled between gates of the first transistor pair. The inductive unit comprises: a first inductive element electrically coupled to one gate of the first transistor pair; and a second inductive element electrically coupled to one of the output nodes. The first inductive element and the second inductive element are configured to be magnetically coupled to each other. | 2021-09-30 |
20210305941 | SEMICONDUCTOR INTEGRATED CIRCUIT AND RECEIVER - According to one embodiment, a semiconductor integrated circuit includes first and second power supply lines, first and second nodes, and first and second circuits. The first circuit is configured to supply a first current to the second power supply line, from the first node or the second node. The second circuit is configured to supply a second current from the first power supply line to the first node based on a magnitude of the first current, and to supply a third current from the first power supply line to the second node based on the magnitude of the first current. | 2021-09-30 |
20210305942 | DOHERTY RADIO FREQUENCY AMPLIFIER CIRCUITRY - Doherty radio frequency (RF) amplifier circuitry includes an input node, an output node, a main amplifier path, and a peaking amplifier path. The main amplifier path is coupled between the input node and the output node and includes a main amplifier. The peaking amplifier path is coupled in parallel with the main amplifier path between the input node and the output node, and includes a peaking amplifier and a peaking variable gain preamplifier between the input node and the peaking amplifier. The peaking variable gain preamplifier is configured to adjust a current provided to the peaking amplifier. | 2021-09-30 |
20210305943 | TRANSCONDUCTANCE AMPLIFIER BASED ON SELF-BIASED CASCODE STRUCTURE - Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M | 2021-09-30 |
20210305944 | DEVICE AND DEVICE PROTECTION SYSTEM - A device having device function circuitry configured to receive a device signal and output a modified device signal is disclosed. The device includes a device temperature sensor configured to generate a device temperature signal that is proportional to a temperature of the device function circuitry. The device function circuitry is further configured to maintain power dissipation of the device function circuitry to below a predetermined safe power dissipation level in response to a control signal that is generated based upon the device temperature signal. | 2021-09-30 |
20210305945 | LINEARITY OPTIMIZER FOR A MILLIMETER-WAVE BEAMFORMING SYSTEM - An example apparatus includes a power amplifier (PA) and a linearity optimizer. The optimizer includes a PA actuator and a linearity adaptation circuit. The actuator is configured to generate an actuator output based on an actuator input and a vector of complex gains computed by the linearity adaptation circuit based on a feedback signal indicative of PA's output. The adaptation circuit is configured to compute the vector of complex gains in a manner that maximizes the power of the actuator output while ensuring that the deviation of PA's behavior from a linear behavior (e.g., in terms of one or more linearity parameters) is below a threshold. Controlling actuator output in a manner that maximizes its power while taking into consideration one or more linearity parameters to ensure that target linearity is achieved controls drive signals for the PA and, thus, may help in terms of PA linearity and efficiency. | 2021-09-30 |
20210305946 | DISTORTION COMPENSATION DEVICE, DISTORTION COMPENSATION METHOD, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM - Provided is a distortion compensation device performing distortion compensation on a signal to be amplified by an amplifier, of which an internal state affecting a distortion characteristic varies, using a distortion compensation model, wherein the distortion compensation model includes a plurality of calculation models having respective distortion compensation characteristic for the amplifier in different internal states, and a combiner combining the plurality of calculation models at a combination ratio corresponding to the internal state that varies. | 2021-09-30 |
20210305947 | MINIATURIZED WIDEBAND ACTIVE BALUN WITH CONTROLLABLE EQUALIZATION - Embodiments of active baluns are disclosed. In an embodiment, an active balun includes input terminals configured to receive a single-ended input signal and a linear redriver configured to transform the single-ended input signal into a differential output signal. | 2021-09-30 |
20210305948 | All-digital Transmitter with Wideband Beamformer - An all-digital transmitter (ADT) is provided. The ADS includes a baseband interface configured to store and transmit an (baseband) input signal at a corresponding frequency band, a polyphase finite impulse response filter configured to receive and convert the baseband input signal into different phases, a digital upconverter configured to upconvert each of the different phase baseband input signal to a predetermined carrier frequency in a digital domain, a set of multi-core 2-dimensional network-resonant digital plane wave beamfilters, wherein each of the multi-core 2D NR-DPW beamfilters is configured to transmit the upconverted baseband input signal by a target angle, a multi-core delta-sigma modulator configured to encode the upconverted input signal into pulsating signals, and a serializer configured to serialize the encoded pulsating signals into a RF bitstream. | 2021-09-30 |
20210305949 | POWER AMPLIFYING DEVICE - Multiple bipolar transistors are disposed side by side in the first direction on a substrate. Multiple first capacitance devices are provided corresponding to the respective base electrodes of the bipolar transistors. A radio frequency signal is supplied to the bipolar transistors through the first capacitance devices. Resistive devices are provided corresponding to the respective base electrodes of the bipolar transistors. A base bias is supplied to the bipolar transistors through the resistive devices. The first capacitance devices are disposed on the same side relative to the second direction orthogonal to the first direction, when viewed from the bipolar transistors. At least one of the first capacitance devices is disposed so as to overlap another first capacitance device partially when viewed in the second direction from the bipolar transistors. | 2021-09-30 |
20210305950 | POWER AMPLIFIER EVALUATION METHOD AND MEASUREMENT SYSTEM - A radio frequency signal having a constant amplitude is modulated by a digital modulation signal and a radio frequency input signal whose amplitude changes stepwise is generated. The radio frequency input signal is input into a power amplifier that is an evaluation target. A period in which an amplitude of the radio frequency input signal is constant is defined as a measurement period and an output signal of the power amplifier is measured in each of measurement periods in which amplitudes of the radio frequency input signal are different from each other. | 2021-09-30 |
20210305951 | POWER AMPLIFIER CIRCUIT - A power amplifier circuit includes a first amplifier that amplifies a first RF signal and outputs a second RF signal, a second amplifier that amplifies the second RF signal and outputs a third RF signal, a bias circuit that supplies a bias current or voltage to the first or second amplifier, and a bias adjustment circuit that adjusts the bias current or voltage on the basis of the first RF signal, the second RF signal, or the third RF signal. The bias adjustment circuit includes a first diode having an anode to which a control signal indicating a signal based on the first, second, or third RF signal is inputted, and a cathode connected to a ground. The bias circuit includes a bias transistor that outputs the bias current or voltage on the basis of a voltage at the anode of the first diode. | 2021-09-30 |
20210305952 | COMMON MODE VOLTAGE CONTROLLER FOR SELF-BOOSTING PUSH PULL AMPLIFIER - Various implementations include systems for amplifying input signals. In particular implementations, a system includes a common mode voltage controller configured to receive an input signal and output a pair of adjusted signals; a modulator that generates a pair of pulse width modulation (PWM) signals in response to the adjusted signals; and a self-boosting push pull amplifier configured to receive the PWM signals and generate an amplified output, wherein the self-boosting push pull amplifier is configured to generate a differential mode voltage representative of an amplified version of the input signal, wherein the adjusted audio signals generated by the common mode voltage controller include a dynamically adjusted gain and duty cycle offset that causes the self-boosting push pull amplifier to operate with a reduced common mode voltage. | 2021-09-30 |
20210305953 | AMPLIFIER CIRCUIT WITH DISTRIBUTED DYNAMIC CHOPPING - Embodiments relate to an amplifier circuit. The amplifier circuit includes multiple transistors. Each transistor is configured to receive an input signal and output an amplified signal. The amplifier circuit additionally includes a set of input chopper circuits and a set of output chopper circuits. Each output chopper circuit corresponds to one input chopper of the set of input choppers. Each input chopper circuit and its corresponding output chopper are controlled by one or more control signals from a set of control signals. Each input chopper circuit is configured to selectively connect each transistor of a transistor pair to a first input terminal or a second input terminal based on a value of the one or more control signals. Moreover, each output chopper circuit is configured to selectively connect each transistor of the transistor pair to a first output terminal or a second output terminal based on the value of the one or more control signals. | 2021-09-30 |
20210305954 | DIFFERENTIAL AMPLIFIER - A differential amplifier of a memory controller may include: an amplification stage configured to amplify input differential signals to generate intermediate differential signals; a control circuit configured to control slew rates for the intermediate differential signals; and an output circuit configured to selectively perform one or more switching operations according to the intermediate differential signals to generate output differential signals. | 2021-09-30 |
20210305955 | AMPLIFIER CIRCUIT WITH DYNAMIC OFFSET CALIBRATION - An amplifier circuit includes multiple transistors, a set of input routing circuits, and a set of output routing circuits. Each output routing circuit corresponds to an input routing circuit. Each input routing circuit and its corresponding output routing circuit are controlled by one or more control signals. Each input routing circuit is configured to selectively connect each transistor of a transistor pair to a first input terminal of the amplifier circuit, a second input terminal of the amplifier circuit, or a third input terminal of the amplifier based on a value of the one or more control signals. Each output routing circuit is configured to selectively connect each transistor of the transistor pair to a first output terminal of the amplifier circuit, a second output terminal of the amplifier circuit, or a calibration circuit based on the value of the one or more control signals. | 2021-09-30 |
20210305956 | Direct-Switching H-Bridge Current-Mode Drivers - A current-mode transmitter amplifies a differential input signal to a differential, current-mode output signal. A split-input, current-mode-logic stage produces small, analog signals to limit switching currents and thus power consumption and power-supply noise. These small, analog signals are driven through a source-follower stage to reduce loading and shift the common-mode voltage to a desired level. A switched-current-source H-bridge driver combines differential outputs from the source-follower stage to provide an amplified differential output current. The output swing from the H-bridge driver is controlled by the voltage level from the source follower and derived from a replica-bias structure. | 2021-09-30 |
20210305957 | AUTO-ZERO AMPLIFIER FOR REDUCING OUTPUT VOLTAGE DRIFT OVER TIME - According to an aspect, an auto-zero amplifier includes a main amplifier, a secondary amplifier connected to the main amplifier, a plurality of switching including a first switch and a second switch, and a leakage control circuit. | 2021-09-30 |
20210305958 | CRYOGENIC INTEGRATED CIRCUIT, INTEGRATED MODULE, AND ARRANGEMENT FOR PRODUCING AND DETECTING EXCITATION AND READOUT SIGNALS OF QUBITS - A cryogenic integrated circuit or integrated module includes a travelling wave parametric amplifier or a Josephson parametric amplifier. The cryogenic integrated circuit or integrated module also includes an oscillator, a signal input, a biasing input, and a signal output. The oscillator is connected to an input of the amplifier and is configured to produce an oscillating drive signal. The signal input couples input signals into the amplifier. The biasing input couples biasing signals into the oscillator. The signal output conveys output signals from the amplifier out of the cryogenic integrated circuit or integrated module. | 2021-09-30 |
20210305959 | AUDIO DEVICE AND AUDIO SIGNAL PROCESSING METHOD - An audio device including: an audio signal input section that receives an audio signal; a signal processor that performs signal processing on the audio signal; an amplifier that amplifies the audio signal; an audio signal output section that outputs the amplified audio signal; a feeder that feeds electric power to an external device; a feed detector that detects a state of feeding of the electric power by the feeder; a controller that causes the signal processor to perform level limiting processing to limit a level of the audio signal in a case where the feed detector detects that the feeder is feeding the electric power to the external device. | 2021-09-30 |
20210305960 | DYNAMIC AND SELF-ADJUSTING MICROPHONE GAIN FOR VOICE-ENABLED DEVICES - Various acoustic manipulation and microphone gain adjustment techniques are enabled. For instance, a method comprises receiving, by a voice-enabled device comprising a processor and from a microphone, an input comprising environmental audio, determining, by the voice-enabled device, a level of the environmental audio, determining, by the voice-enabled device, a gain-adjust value based on the environmental audio, and adjusting, by the voice-enabled device, a gain of the microphone by the gain-adjust value. | 2021-09-30 |
20210305961 | METHOD FOR THE RECONFIGURATION OF A VORTEX DENSITY IN A RARE EARTH MANGANATE, A NON-VOLATILE IMPEDANCE SWITCH AND USE THEREOF - A method for reconfiguration of a vortex density in a rare earth manganate, to a non-volatile impedance switch having reconfigurable impedance, and to the use thereof as micro-inductance is disclosed. A unique voltage-time profile is applied between a first and a second electrically conductive contact attached to the rare earth manganate, such that the rare earth manganate passes through an ordering temperature in a region of an electric field forming between the two electrically conductive contacts during a cooling process during and after application of the voltage pulse or the voltage ramp, and the vortex density is thus influenced and adjusted locally in the region of the electric field forming between the two electrically conductive contacts. | 2021-09-30 |
20210305962 | ANTENNA STRUCTURE AND COMMUNICATIONS TERMINAL - An antenna structure includes a first antenna radiator, a second antenna radiator, a first impedance matching circuit, a second impedance matching circuit, and a signal source, wherein the first antenna radiator is coupled to the second antenna radiator by means of a slot; the end of the first antenna radiator away from the slot is grounded, and the first antenna radiator is provided with a feed point, the end of the second antenna radiator away from the slot is grounded; a first end of the first impedance matching circuit is connected to the feed point, and a second end of the first impedance matching circuit is connected to a first end of the signal source; a first end of the second impedance matching circuit is connected to a third end of the first impedance matching circuit, and a second end of the second impedance matching circuit is grounded. | 2021-09-30 |
20210305963 | Integrated Isolator Circuit in a Time Division Duplex Transceiver - An integrated isolator circuit for isolating receiver and transmitter in a Time-Division Duplex transceiver is disclosed. The integrated isolator circuit comprises a first node, a second node and. a third node. The integrated isolator circuit further comprises a first capacitor connected in series with a first switch and connected between the first and second nodes. The integrated isolator circuit further comprises a first inductor connected between the first and second nodes and a second capacitor connected between the second node and the third node. The first switch has an on state and an off state, and the integrated isolator circuit is configured to have a different impedance at a certain operating frequency by controlling the state of the first switch. | 2021-09-30 |
20210305964 | ACOUSTIC WAVE DEVICE - An acoustic wave device includes a support substrate, a piezoelectric layer, and an IDT electrode. The piezoelectric layer is directly or indirectly provided on the support substrate. The IDT electrode includes a plurality of electrode fingers and is provided on a main surface of the piezoelectric layer. The thickness of the piezoelectric layer is about 1λ or less when a wavelength of an acoustic wave determined by an electrode finger period of the IDT electrode is defined as λ. The support substrate is an A-plane sapphire substrate. | 2021-09-30 |
20210305965 | SURFACE ACOUSTIC WAVE DEVICES USING PIEZOELECTRIC FILM ON SILICON CARBIDE - An acoustic resonator includes a piezoelectric thin film (PTF) disposed on a carrier substrate. The PTF confines a fundamental shear-horizontal (SH0) surface-acoustic wave (SAW) within the PTF. The acoustic resonator includes an input bus line coupled to an input source and a ground bus line coupled to a ground potential. The acoustic resonator includes a first grating reflector disposed at a first end of the PTF and coupled between the input bus line and the ground bus line. The acoustic resonator includes a second grating reflector disposed at a second end of the PTF and coupled between the input bus line and the ground bus line. The acoustic resonator includes interdigital transducers (IDTs) disposed between the first grating reflector and the second grating reflector. Each IDT includes an input electrode coupled to the input bus line, and a ground electrode coupled to the ground bus line. | 2021-09-30 |
20210305966 | Vibrator Device - A vibrator device includes a vibrator element, a container in which the vibrator element is housed, a circuit which is disposed in the container, and which overlaps the vibrator element in a plan view, and an inductor which is disposed in the container, which fails to overlap the vibrator element in the plan view, and which is electrically coupled to the circuit. The container includes at least a first member and a second member, and a bonding area configured to bond the first member and the second member to each other, and the inductor is disposed in the bonding area. | 2021-09-30 |
20210305967 | FILTER DEVICE AND FILTER CIRCUIT - A filter device includes a first substrate, a first input electrode and a first output electrode on the first substrate, a first ground electrode on the first substrate and receiving a ground potential, an electrically open portion in or on the first substrate, a second substrate mounted on the first substrate, a second input electrode on a surface of the second substrate and connected to the first input electrode, a second output electrode on the surface of the second substrate and connected to the first output electrode, a second ground electrode on the surface of the second substrate and connected to the first ground electrode, and at least one first functional electrode on the second substrate and disposed on a first connecting path connecting the second input electrode and the second output electrode. The open portion is connected to the first connecting path. | 2021-09-30 |
20210305968 | ACTIVE FEEDBACK ANALOG FILTERS WITH COUPLED RESONATORS - A variable filter for an RF circuit has a signal loop comprising a signal input port and a signal output port, and a plurality of circuit elements connected within the signal loop. The plurality of circuit elements comprise a multi-pole resonator comprising a plurality of frequency tunable resonators and an adjustable scaling block that applies a gain factor. Adjacent frequency tunable resonators within the multi-pole resonator are reciprocally coupled. A controller is connected to tune the multi-pole resonator and to adjust the gain factor of the adjustable scaling block such that the signal loop generates a desired bandpass response. | 2021-09-30 |
20210305969 | PHASE ROTATOR CONTROL APPARATUS AND METHOD THEREFOR - A phase rotator control circuit is provided. The phase rotator control circuit is coupled to a phase rotator core and includes a first set of transistors coupled to receive digital control signals. The first set of transistors is coupled to a second set of transistors configured and arranged to form a filtered current mirror. An output of the filtered current mirror is coupled to provide an analog phase control signal to the phase rotator core. | 2021-09-30 |
20210305970 | PHASE TRACKING PULSE GENERATION CIRCUIT AND POWER SUPPLY DEVICE - Disclosed are a phase-tracked pulse generation circuit and a power supply device. The present application uses a driving pulse rising edge of a power supply as a reference, and uses a constant current circuit to charge a charging and discharging circuit at a constant current. When the reference driving pulse rising edge comes, the charging and discharging circuit is discharged; the peak voltage on the charging and discharging circuit is taken out and then divided for comparison with the voltage on the charging and discharging circuit; when the voltage on the charging and discharging circuit is equal to a divided voltage value of the peak voltage, the output of a comparison circuit turns high, and the output of a comparator is the phase-tracked pulse; the rising edge of the phase-tracked pulse can be used for synchronizing another power supply. | 2021-09-30 |
20210305971 | TUNING METHOD FOR CURRENT MODE RELAXATION OSCILLATOR - A relaxation oscillator includes an adjustable reference circuit generator to produce a reference current which is applied to a charging circuit. The charging circuit is configured to charge a capacitive node as a function of the reference current and a capacitance of an adjustable capacitor that is operably coupled to the capacitive node. A comparator having inputs operatively coupled to a reference voltage node and to the capacitive node, generates a comparator output. A control circuit alternatively enables the charging circuit to charge the capacitive node and to discharge the capacitive node in response to changes in the comparator output. Also, the control circuit outputs and oscillator output signal have an oscillator period as a function of the adjustable capacitance and the adjustable reference current. | 2021-09-30 |
20210305972 | LOW-SWING SCHMITT TRIGGERS - Systems and methods are disclosed for low-swing Schmitt triggers. For example, an apparatus includes a Schmitt trigger including an input node, an output node, and a feedback node that is configured to bear a feedback voltage level that is a sum of an input voltage level at the input node and an attenuated voltage level of the output node; a current source connected to the output node; a voltage sensor connected to the feedback node and configured to cause the current source to pull up an output voltage level at the output node responsive to the feedback voltage level crossing a threshold. | 2021-09-30 |
20210305973 | LOW DISTORTION TRIANGULAR WAVE GENERATOR CIRCUIT AND LOW DISTORTION TRIANGULAR WAVE GENERATION METHOD - A low distortion triangular wave generator circuit generates a triangular wave signal by performing integration on an integration capacitor via a charging current and a discharging current during a charging period and a discharging period within a switching period of an external clock signal. A time length of the charging period is identical to a time length of the discharging period. A common mode related signal related to a common mode characteristic of the triangular wave signal is generated. An adjusting signal is generated according to a difference between the common mode related signal and a predetermined DC (direct current) level. The adjusting signal adjusts at least one of the charging current and the discharging current via feedback mechanism such that the triangular wave signal is a symmetrical triangular wave, and an average voltage of the triangular wave signal is equal to a target DC level. | 2021-09-30 |
20210305974 | CIRCUIT FOR SUPPRESSING ELECTROMAGNETIC INTERFERENCE - A circuit for suppressing electromagnetic interference signal on power lines. The circuit includes a first sensing circuit, a first amplifier, and a first controlled signal source. The first sensing circuit is arranged to sense a first electromagnetic interference signal. The first amplifier is arranged to be powered by a power source. The first amplifier provides a first amplification factor and being operably connected with the first sensing circuit to amplify a signal sensed by the first sensing circuit. The first controlled signal source provides a second amplification factor and is operably connected with the first amplifier to regulate or further amplify the amplified signal to provide a first suppression signal that reduces the first electromagnetic interference signal. Multiple such circuits can be cascaded to form a mufti-stage electromagnetic interference suppression circuit. | 2021-09-30 |
20210305975 | GATED TRI-STATE INVERTER, AND LOW POWER REDUCED AREA PHASE INTERPOLATOR SYSTEM INCLUDING SAME, AND METHOD OF OPERATING SAME - A phase interpolating (PI) system includes: a phase-interpolating (PI) stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal, the PI stage being further configured to avoid a pull-up/pull-down (PUPD) short-circuit situation by using the multi-bit weighting signal and a logical inverse thereof (multi-bit weighting_bar signal); and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component; the capacitive component being tunable; and the capacitive component having a Miller effect configuration resulting in a reduced footprint of the amplifying stage. | 2021-09-30 |
20210305976 | EQUALIZER AND COMMUNICATION MODULE USING THE SAME - An equalizer has a first tapped delay line in which N taps (N is a positive integer) are connected in cascade, a second tapped delay line having one tap and connected in parallel with the first tapped delay line, a first multiplier configured to multiply signals extracted from the N taps by corresponding coefficients, a second multiplier configured to multiply a signal output from the second tapped delay line by a second coefficient, and an adder configured to add products of the first multiplier and a product of the second multiplier. The first tapped delay line has a fixed delay, and the second tapped delay line has a variable delay changeable at a 1/M resolution of the fixed delay, where M is a number greater than 1. | 2021-09-30 |
20210305977 | CURRENT DETECTION CIRCUIT - A current detection circuit includes normally-on-type and a first normally-off-type switching elements with main current paths that are connected in series, and a second normally-off-type switching element that has a source and a gate that are connected to a source and a gate of the first normally-off-type switching element and a drain that is connected to a constant current source, and executes a division process by using drain voltages of the two normally-off-type switching elements. | 2021-09-30 |
20210305978 | METHOD OF TUNING LIGHT COLOR TEMPERATURE FOR LED LIGHTING DEVICE AND APPLICATION THEREOF - A color temperature switching scheme for an LED lighting device is disclosed. The color temperature switching scheme comprises a plurality of different color temperature performances correspondingly generated by a plurality of different paired combinations of a first electric power allocated to a first LED load emitting a light with a first color temperature and a second electric power allocated to a second LED load emitting a light with a second color temperature such that a mingled color temperature between the first color temperature and the second color temperature can be generated thru a light diffuser. For tuning the mingled color temperature of the LED lighting device a reverse yet complementary power adjustment process for distributing a total electric power T between the first LED circuit and the second LED circuit is required such that a total light intensity remains essentially unchanged while the mingled color temperature is being adjusted. | 2021-09-30 |
20210305979 | DISCHARGE CONTROL CIRCUIT AND CURRENT SOURCE CIRCUIT - A discharge control circuit includes discharge elements, logic circuits, and at least one delay circuit. Each of the logic circuits controls turning-on and turning-off the discharge elements based on a control signal inputted externally. The delay circuit delays an output signal of a first logic circuit among the logic circuits. The discharge control circuit pulls out charges from a corresponding terminal in response to turning-on of the discharge elements. A signal delayed by the delay circuit is inputted to a second logic circuit among the logic circuits so that the discharge elements are controlled in a predetermined order by one control signal. | 2021-09-30 |
20210305980 | BIDIRECTIONAL SEMICONDUCTOR CIRCUIT BREAKER - The present disclosure relates to a bidirectional semiconductor circuit breaker including a primary circuit unit connected between a power supply and a load and in which a first semiconductor switch and a second semiconductor switch are arranged in series and a snubber circuit unit of which one end is connected to the front end of the first semiconductor switch and the other end is connected to the rear end of the second semiconductor switch, in parallel. The snubber circuit unit includes a first circuit line, a second circuit line, and a third circuit line of which one end and the other end are connected to the first circuit line and the second circuit line, respectively, and in which a first resistor and a second resistor are arranged in series, and provide a snubber circuit which is applicable to a bidirectional fault current and satisfies semiconductor protection and current restraining performance. | 2021-09-30 |
20210305981 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND RECEPTION DEVICE - According to one embodiment, a semiconductor integrated circuit device comprises first and second transistors having control terminals receiving an input signal and an inversion signal of the input signal, third and fourth transistors having control terminals receiving the input signal and the inversion signal, first and second inverters in which outputs are connected to inputs of other converters, and a fifth transistor connected to the first to fourth transistors. The third and fourth transistors are connected to outputs of the second and the first inverters. Clock signal is supplied to the fifth transistor. | 2021-09-30 |
20210305982 | METHOD FOR OPERATING AN APPLIANCE, DEVICE FOR PERFORMING THE METHOD, VEHICLE DOOR, AND COMPUTER PROGRAM - Technologies and techniques for operating an appliance. A command button of an operating part is actuated, the actuation of the command button being detected by a microcontroller using measuring instruments. The read-in measured values are evaluated such that it is determined whether the measuring signal has a regular form for actuating the command button, or an irregular form. A function associated with the actuated command button is implemented if it is established that the measuring signal has a regular form. When a regular form is identified, optionally an acoustic, haptic or optical acknowledgement signal is emitted, and when an irregular form is identified, an acoustic, haptic or optical fault signal is emitted. | 2021-09-30 |
20210305983 | Multi-Termination Scheme Interface - In an embodiment, a method includes programming a control signal that specifies a target resistance and a target voltage in a circuit. The method further includes sending the control signal to at least one transistor configured to control a current flow in the circuit. The method further includes providing, as an output, a signal with the target voltage and target resistance. | 2021-09-30 |
20210305984 | APPARATUS AND METHODS FOR SENSING - An apparatus and method wherein the apparatus comprises; a sensor arrangement comprising a plurality of sensor cells wherein a sensor cell comprises a transistor and a sensor coupled to the transistor; first selection circuitry configured to sequence a subset of sensor cells to which a gate input signal is provided, wherein the gate input signal is provided to the gate of the transistors within the sensor cells; second selection circuitry configured to sequence a subset of sensor cells from which an output signal is received; sensing signal circuitry configured to provide a sensing signal, wherein the sensors are provided between the sensing signal circuitry and the second selection circuitry such that the output signal provides an indication of the impedance of the sensors. | 2021-09-30 |
20210305985 | Logic Configuration Techniques - Various implementations described herein are directed to a device having logic circuitry with multiple inversion stages. One or more of the multiple inversion stages may be configured to operate as first inversion logic with a first number of transistors. One or more of the multiple inversion stages may be configured to operate as second inversion logic with a second number of transistors that is greater than the first number of transistors. | 2021-09-30 |
20210305986 | Method and System Providing FPGA Device Identification via A Set of Embedded Signature Registers - A programmable integrated circuit (“PIC”) device includes configurable logic blocks (“LBs”), routing connections, and configuration memory for performing user defined programmed logic functions. Each configurable LB, in one example, includes a set of lookup tables (“LUTs”) and associated registers. The LUTs, for example, are configured to generate one or more output signals in accordance with a set of input signals. The registers are arranged so that each register corresponds to one LUT. In one embodiment, a group of registers, instead of assigning to a group of LUTs across multiple configurable LBs, is allocated or configured as embedded signature registers in PSD. For example, a first register which corresponds or physically situated in the vicinity of first LUT can be designated as an embedded signature register for storing a fixed value or signature information for facilitating device or IC identification. | 2021-09-30 |
20210305987 | OPERATING A SUPERCONDUCTING CHANNEL BY ELECTRON INJECTION - The invention is notably directed to a method of operating a superconducting channel. The method relies on a device including: a potentially superconducting material; a gate electrode; and an electrically insulating medium. A channel is defined by the potentially superconducting material. The gate electrode positioned adjacent to the channel, such that an end surface of the gate electrode faces a portion of the channel. The electrically insulating medium is arranged in such a manner that it electrically insulates the gate electrode from the channel. Rendering the channel superconducting by cooling down the device. Next, a voltage difference is applied between the gate electrode and the channel to inject electrons in the channel through the electrically insulating medium and thereby generate a gate current between the gate electrode and the channel. The electrons are injected with an average energy sufficient to modify a critical current I | 2021-09-30 |
20210305988 | DELAY ESTIMATION DEVICE AND DELAY ESTIMATION METHOD - The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code. | 2021-09-30 |
20210305989 | DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT - A delay locked loop circuit includes a delay line, a phase detector, a selection controller, and a charge pump. The delay line delays, based on a delay control voltage, a reference clock signal to generate an internal clock signal and a feedback clock signal. The phase detector compares phases of the internal clock signal and the feedback clock signal to generate a first detection signal and a second detection signal. The selection controller provides the reference clock signal as an up-signal and a down-signal. The charge pump generates the delay control voltage based on the up-signal and the down-signal. | 2021-09-30 |
20210305990 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND ASSOCIATED CONTROL METHOD - A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is disclosed. The SAR ADC includes a switched capacitor array, a buffer, a comparator and a control logic circuit. The switched capacitor array is arranged to sample an input signal according to a switch control signal to generate a sampling signal. The buffer is arranged to generate a common mode voltage. The comparator is arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result. The control logic circuit is arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array. The control logic circuit further generates an operation control signal to adjust a Miller compensation capacitor inside the buffer. An associated control method is also disclosed. | 2021-09-30 |
20210305991 | AMPLIFIER AMPLITUDE DIGITAL CONTROL FOR A MASS SPECTROMETER - Control of an amplitude of a signal applied to rods of a quadrupole is described. In one aspect, a mass spectrometer includes an amplifier circuit that causes a radio frequency (RF) signal to be applied to the rods of the quadrupole based on an amplifier RF input signal. An analog-to-digital converter (ADC) can generate a digital representation of the RF signal. A controller circuit can receive the digital representation and adjust an amplitude of the amplifier RF input signal based on differences between an amplitude of a fundamental frequency of the RF signal being different than an expected amplitude. | 2021-09-30 |
20210305992 | Receiver Circuit for an Antenna Array System - A receiver circuit for an antenna array system (AAS) is disclosed. The receiver circuit ( | 2021-09-30 |
20210305993 | DYNAMIC INTEGRATION TIME ADJUSTMENT OF A CLOCKED DATA SAMPLER USING A STATIC ANALOG CALIBRATION CIRCUIT - Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler. | 2021-09-30 |
20210305994 | ANALOG-DIGITAL CONVERTER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - An analog-digital converter includes a first analog-digital conversion unit configured to, during a first analog-digital conversion operation, sequentially charge each of n first differential node pairs, in response to a respective one of a differential sampling signal pair and first to (n−1) | 2021-09-30 |
20210305995 | OVERLOAD RECOVERY METHOD IN SIGMA DELTA MODULATORS - A delta sigma modulator includes two adders, an integrator stage, a reconfigurable local resonator, an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC). A first adder receives an analog input signal at an additive input, and the integrator stage receives an output from the first adder and generates an integrated signal. The reconfigurable local resonator receives the integrated signal and generates a resonator output signal. A second adder receives the resonator output signal, the integrated signal, and the input signal. The ADC receives an output from the second adder and generates a digital output signal which can be provided to other circuits. The DAC receives the digital output signal, and generates and provides a feedback signal to a subtractive input of the first adder. The reconfigurable local resonator acts as a resonator, but reconfigures to act as a low pass filter in response to overload conditions. | 2021-09-30 |
20210305996 | ANALOG TO DIGITAL CONVERTER WITH VCO-BASED AND PIPELINED QUANTIZERS - An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal. | 2021-09-30 |
20210305997 | DEVICE COMPRISING A SENSOR, CONTROLLER AND CORRESPONDING METHODS - A device includes a sensor configured to output an analog sensor signal, an analog-to-digital converter circuit configured to convert the analog sensor signal into a sigma-delta-modulated digital signal having a bit width of n bits, and a pulse width modulator configured to generate a pulse-width-modulated signal based on the sigma-delta-modulated digital signal. | 2021-09-30 |
20210305998 | DATA MANAGEMENT SYSTEM, DATA MANAGEMENT METHOD, AND STORAGE MEDIUM WITH DATA MANAGEMENT PROGRAM STORED THEREON - Provided is a data management system which includes a data acquisition unit configured to acquire measurement data obtained by measuring a measurement target, a data storage unit configured to store the acquired measurement data, a data size reduction unit configured to deletes at least a part of the stored measurement data to reduce a data size of the measurement data, and a data compression unit configured to perform data compression on the measurement data reduced in data size. | 2021-09-30 |
20210305999 | GENERIC COMPRESSION RATIO ADAPTER FOR END-TO-END DATA-DRIVEN COMPRESSIVE SENSING RECONSTRUCTION FRAMEWORKS - A compression ratio (CR) adapter (CRA) for end-to-end data-driven compressive sensing (CS) reconstruction (EDCSR) frameworks is provided. EDCSR frameworks achieve state-of-the-art reconstruction performance in terms of reconstruction speed and accuracy for images and other signals. However, existing EDCSR frameworks cannot adapt to a variable CR. For applications that desire a variable CR, existing EDCSR frameworks must be trained from scratch at each CR, which is computationally costly and time-consuming. Embodiments described herein present a CRA framework that addresses the variable CR problem generally for existing and future EDCSR frameworks with no modification to given reconstruction models nor enormous additional rounds of training needed. The CRA exploits an initial reconstruction network to generate an initial estimate of reconstruction results based on a small portion of acquired image measurements. Subsequently, the CRA approximates full measurements for the main reconstruction network by complementing the sensed measurements with a re-sensed initial estimate. | 2021-09-30 |
20210306000 | Systems, Methods, and Media for Low-Power Encoding of Continuous Physiological Signals in a Remote Physiological Monitor - In accordance with some embodiments of the disclosed subject matter, mechanisms (which can, for example, include systems, methods, and media) for low-power encoding of continuous physiological signals are provided. In some embodiments, a system comprises: a physiological sensor; and a remote monitor comprising: a battery; memory storing a k-ary tree including a root with k branches corresponding to k delta values, k nodes at a first depth below the root node each having k branches corresponding to the k delta values the nodes indexed to indicate the lateral position of the node within the depth; a processor programmed to: receive a first sample value from the sensor; receive a second sample value; calculate a difference between the second first sample values; determine that the delta corresponds to a first delta of the k delta values; encode a sequence of deltas based on a depth and node index. | 2021-09-30 |
20210306001 | Coded Stream Processing - Described herein is a system and method for coded streaming data to facilitate recovery from failed or slow processor(s). A batch of processing stream data can be partitioned into a plurality of data chunks. Parity chunk(s) for the plurality of data chunks. The plurality of data chunks and the parity chunk(s) can be provided to processors for processing. Processed data of at least some (e.g., one or more) of the plurality of data chunks, and, processed data of parity chunk(s) are received. When it is determined that processed data for a pre-defined quantity of data chunks has not been received by a pre-defined period of time, the processed data for particular data chunk(s) of particular processor(s) from which processed data has not been received are determined based, at least in part, upon the received processed parity chunk(s) and the received processed data chunk(s). | 2021-09-30 |
20210306002 | FAST CRC COMPUTATION CIRCUIT USING AN ON-THE-FLY RECONFIGURABLE GENERATOR POLYNOMIAL - A circuit for generating an N-bit cyclic redundancy code of a k-bit digit d, the code based on a reconfigurable generator polynomial P of degree N, the circuit including a dynamic table comprising a multiplication sub-table storing products resulting from multiplication by the polynomial P of each element definable over k bits, in the order of the scalar values of the k-bit elements; a division sub-table storing quotients resulting from Euclidean division by the polynomial P of each k-bit element shifted by N bits to the left, in the order of the scalar values of the k-bit elements; and a group of first multiplexers, each multiplexer connected to be indexed by a respective cell of the division table to transmit the contents of a corresponding cell of the multiplication table to an output of the dynamic table, of same rank as the respective cell of the division table. | 2021-09-30 |
20210306003 | APPARATUS AND METHOD FOR RECOVERING A DATA ERROR IN A MEMORY SYSTEM - A memory system includes a memory device and a controller. The memory device includes a plurality of non-volatile memory groups individually storing a plurality of data segments, each data segment corresponding to a codeword. The controller is configured to perform hard decision decoding to correct an error when the error is included in a first data segment among the plurality of data segments, determine whether other data segments associated with the first data segment, among the plurality of data segments, are readable when the hard decision decoding fails, and perform chipkill decoding based on the first data segment and the other data segments when the other data segments are readable. | 2021-09-30 |
20210306004 | Method and System for Generating Parity Check Matrix for Low-Density Parity Check Codes - A system for generating a parity check matrix for low-density parity-check (LDPC) codes includes a memory and a processing circuitry that retrieves a base matrix from the memory. The base matrix represents sets of valid and invalid positions for a set of circulant matrices. The processing circuitry determines a value for each valid position based on a heuristic function. The value for each valid position indicates a corresponding circulant matrix of the set of circulant matrices. The processing circuitry replaces each valid position with the corresponding circulant matrix based on the determined value, and each invalid position with a null matrix, to generate the parity check matrix. The parity check matrix thus generated has a high girth and equal distribution of cycles within the parity check matrix. | 2021-09-30 |
20210306005 | POLAR ENCODING AND POLAR DECODING SYSTEMS AND METHODS - In encoding systems and methods, data or information is encoded using one or more encoding methodologies to generate encoded data or information corresponding to the data or information. Similarly, in decoding systems and methods, encoded data or information is decoded using one or more decoding methodologies to generate the data or information corresponding to the encoded data or information. The encoding/decoding systems and methods can include polar encoding/decoding systems and methods operable for encoding data or information to generate polar codes and for decoding polar codes to generate the corresponding data or information. The information or data can be control information and application data for communication over networks. The networks can include wireless and wireline networks, and network segments, links or channels, including mixed wireline and wireless networks. | 2021-09-30 |
20210306006 | PROCESSING-IN-MEMORY (PIM) DEVICES - A processing-in-memory (PIM) device includes an ECC logic circuit configured to generate write data and write parity from write input data when a write operation in an operation mode is performed, and generate converted data from read data and read parity when a read operation in an operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the converted data and buffer data to generate MAC operation result data. | 2021-09-30 |
20210306007 | TRANSMITTER, RECEIVER, TRANSMISSION METHOD, AND RECEPTION METHOD - One coding scheme is selected from a plurality of coding schemes, an information sequence is encoded by using the selected coding scheme, and an obtained encoded sequence is modulated to obtain a modulated signal. The obtained modulated signal is subjected to a phase change and is transmitted. The plurality of coding schemes include at least a first coding scheme and a second coding scheme. The first coding scheme is a coding scheme with a first coding rate for forming a generated first codeword as a first encoded sequence by using a first parity check matrix. The second coding scheme is a coding scheme with a second coding rate obtained after puncturing processing, for generating a second encoded sequence by performing the puncturing processing on a generated second codeword by using a second parity check matrix different from the first parity check matrix. The number of bits of the first encoded sequence is equal to the number of bits of the second encoded sequence. | 2021-09-30 |
20210306008 | ENCODING/DECODING METHOD, DEVICE, AND SYSTEM - Embodiments of the present disclosure provide an encoding/decoding method, apparatus, and system. The method includes: encoding information bits to obtain a first-level encoded code word; obtaining a sorting value of each check bit of the first-level encoded code word, and adjusting each check bit to a corresponding position according to the sorting value of each check bit, where the sorting value refers to a value of S when the check bit is related to first S information bits of the information bits in the first-level encoded code word, and S is a non-zero integer; and performing second-level encoding on the first-level encoded code word after positions of the check bits are adjusted, thereby obtaining a second-level encoded code word. The present disclosure is applicable to various communication systems. | 2021-09-30 |
20210306009 | MAXIMUM LIKELIHOOD ERROR DETECTION FOR DECISION FEEDBACK EQUALIZERS WITH PAM MODULATION - The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well. | 2021-09-30 |
20210306010 | DECODING METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROLLING CIRCUIT UNIT - A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: receiving a read command sequence for reading a plurality of bits from the memory cells; calculating a first count value of a first value and a second count value of a second value in the bits; and adjusting a decoding parameter corresponding to the bits to a specific decoding parameter according to the first count value and the second count value, and performing a decoding operation according to the specific decoding parameter, where the adjusted decoding parameter affects a probability that the bits are considered as an error bit in the decoding operation. | 2021-09-30 |
20210306011 | RADIO FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio frequency module includes: a module board that includes a first principal surface and a second principal surface on opposite sides of the module board; a first power amplifier disposed on the first principal surface and configured to amplify a transmission signal in a first frequency band; a second power amplifier disposed on the first principal surface and configured to amplify a transmission signal in a second frequency band different from the first frequency band; and a switch disposed on the second principal surface and connected to an output terminal of the first power amplifier and an output terminal of the second power amplifier. | 2021-09-30 |
20210306012 | RADIO FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio frequency module includes: a module board that includes a first principal surface and a second principal surface on opposite sides of the module board; a first power amplifier disposed on the first principal surface and configured to amplify a transmission signal in a first frequency band; a second power amplifier disposed on the first principal surface and configured to amplify a transmission signal in a second frequency band different from the first frequency band; and a power amplifier (PA) control circuit disposed on the second principal surface and configured to control the first power amplifier and the second power amplifier. | 2021-09-30 |
20210306013 | RADIO FREQUENCY CIRCUIT, ANTENNA MODULE, AND COMMUNICATION DEVICE - A radio frequency circuit includes: a first filter having a first passband that corresponds to a portion of a frequency range of a first communication band allocated as a communication band for TDD; a second filter having a second passband that corresponds to a portion of the frequency range of the first communication band, the second passband being different from the first passband; a power amplifier that amplifies a transmission signal in the first communication band; a low-noise amplifier that amplifies a reception signal in the first communication band; and a switch that switches between connecting the first filter and the power amplifier and connecting the first filter and the low-noise amplifier, and switches between connecting the second filter and the power amplifier and connecting the second filter and the low-noise amplifier. | 2021-09-30 |
20210306014 | Electronic Device With Millimeter Wave Antennas - An electronic device may be provided with wireless circuitry. The wireless circuitry may include one or more antennas. The antennas may include phased antenna arrays each of which includes multiple antenna elements. Phased antenna arrays may be mounted along edges of a housing for the electronic device, behind a dielectric window such as a dielectric logo window in the housing, in alignment with dielectric housing portions at corners of the housing, or elsewhere in the electronic device. A phased antenna array may include arrays of patch antenna elements on dielectric layers separated by a ground layer. A baseband processor may distribute wireless signals to the phased antenna arrays at intermediate frequencies over intermediate frequency signal paths. Transceiver circuits at the phased antenna arrays may include upconverters and downconverters coupled to the intermediate frequency signal paths. | 2021-09-30 |
20210306015 | RADIO FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio frequency module includes: a plurality of external connection terminals including at least one input terminal and at least one output terminal; at least one power amplifier; at least one low-noise amplifier; a first switch connected between the at least one input terminal and the at least one power amplifier; a second switch connected between the at least one output terminal and the at least one low-noise amplifier; and a module substrate including a first principal surface and a second principal surface on opposite sides of the module substrate. The first switch is disposed on one of the first principal surface and the second principal surface, and the second switch is disposed on the other of the first principal surface and the second principal surface. | 2021-09-30 |
20210306016 | SEMICONDUCTOR INTEGRATED CIRCUIT, TRANSMISSION DEVICE, AND CONTROL METHOD OF TRANSMISSION DEVICE - A semiconductor integrated circuit includes a first circuit configured to carry out digital-to-analog conversion on input data; a high-pass filter configured to reduce a component, the component having a frequency lower than a predetermined cutoff frequency, in delayed input data obtained by delaying the input data, and output the delayed input data; a second circuit configured to carryout the digital-to-analog conversion on the delayed input data that passes through the high-pass filter; and a third circuit configured to drive a transmission signal, the transmission signal based on an addition signal obtained by adding an output signal of the first circuit and an output signal of the second circuit. | 2021-09-30 |
20210306017 | RADIO FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio frequency module includes: a module board; a first semiconductor device containing a first power amplifier and a second power amplifier, the first power amplifier being configured to amplify a radio frequency signal of a first communication band, the second power amplifier being configured to amplify a radio frequency signal of a second communication band, the second communication band being different from the first communication band; and a second semiconductor device containing a control circuit configured to control the first power amplifier and the second power amplifier. In the radio frequency module, the first semiconductor device and the second semiconductor device are stacked together and disposed on the module board. | 2021-09-30 |
20210306018 | RADIO FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio frequency module includes: a module board; a first semiconductor device containing a first power amplifier and a second power amplifier; and a second semiconductor device containing a first switch, the first switch including a first terminal connected to the first power amplifier and a second terminal connected to the second power amplifier. In the radio frequency module, the first semiconductor device and the second semiconductor device are stacked together and disposed on the module board. | 2021-09-30 |
20210306019 | RADIO FREQUENCY MODULE AND COMMUNICATION DEVICE - A radio frequency module includes: a module board that includes a first principal surface and a second principal surface on opposite sides of the module board; a first power amplifier configured to amplify a transmission signal in a first frequency band; a second power amplifier configured to amplify a transmission signal in a second frequency band different from the first frequency band; and a switch having a first pole connected to an input terminal of the first power amplifier and a second pole connected to an input terminal of the second power amplifier. The first power amplifier and the second power amplifier are disposed on the first principal surface, and the switch is disposed on the second principal surface. | 2021-09-30 |
20210306020 | RADIO-FREQUENCY SWITCHING APPARATUS - A radio-frequency switching apparatus that can be used to turn a signal path on or off or to attenuate a radio-frequency signal. The switching apparatus comprises at least one radio-frequency input, at least one radio-frequency output, at least one transmission line providing a signal path between the at least one radio-frequency input and the at least one radio-frequency output, and at least one transition metal oxide portion. The radio-frequency switching apparatus also comprises direct current blocking means electrically coupled between the at least one transition metal portion and the at least one radio-frequency input. The radio-frequency switching apparatus also comprises biasing means for providing a bias across the at least one transition metal oxide portion such that power transferred between the radio-frequency input and the radio-frequency output is controlled by controlling the bias level across the at least one transition metal oxide portion. | 2021-09-30 |
20210306021 | MULTILAYER SUBSTRATE AND WIRELESS MODULE MOUNTED SUBSTRATE - A multilayer substrate includes a first dielectric layer, a first conductive layer, and a conductor portion. The first dielectric layer has a first region. The first conductive layer is laminated on the first dielectric layer, excluding the first region. The conductor portion has one or more auxiliary conductors disposed at a distance from the first conductive layer, and one or more connecting conductors that connect said one or more auxiliary conductors to the first conductive layer. | 2021-09-30 |
20210306022 | CALIBRATION OF OPEN SPACE FOR AN ANTENNA ARRAY MODULE - Aspects relate to a calibration of an antenna array module of a wireless communication device in open space. The antenna array module may be used as a proximity sensor to detect an object's proximity relative to the antenna array module. Aspects include displaying an open space calibration instruction on a display of the wireless communication device, transmitting a proximity test signal from the antenna array module, measuring a value of a first signal received at the antenna array module in response to transmitting the proximity test signal, and storing the value of the first signal as an open space calibration value of the antenna array module. The first signal may be measured at cross-polarized antennas of the antenna array module. The value of the first signal may be representative of perturbations of the proximity test signal at the cross-polarized antennas. | 2021-09-30 |