40th week of 2015 patent applcation highlights part 75 |
Patent application number | Title | Published |
20150279392 | HIGHER STABILITY READ HEAD UTILIZING A PARTIAL MILLING PROCESS - In one embodiment, a method for forming a magnetoresistive read head includes forming a fixed layer having a first ferromagnetic material that has a fixed direction of magnetization above a lower shield layer, forming a free layer having a second ferromagnetic material positioned above the fixed layer, the free layer having a non-fixed direction of magnetization, forming a first mask above the free layer, the first mask having a predetermined width based on a track width of a magnetic medium, etching the free layer down to the fixed layer using the first mask as a guide, wherein substantially none of the fixed layer is etched, and wherein the fixed layer extends beyond both sides of the free layer in a cross-track direction, and forming magnetic domain control films on both sides of the free layer in the cross-track direction, the magnetic domain control films including a soft magnetic material. | 2015-10-01 |
20150279393 | TUNNEL MAGNETORESISTANCE READ HEAD WITH NARROW SHIELD-TO-SHIELD SPACING - A tunnel magnetoresistance (TMR) read sensor having a tabbed AFM layer and an extended pinned layer and methods for making the same are provided. The TMR read sensor has an AFM layer recessed from the air bearing surface, providing a reduced shield-to-shield distance. | 2015-10-01 |
20150279394 | BRANCHED WAVEGUIDE CONFIGURATION - An apparatus including a waveguide input coupler, a tapered branch waveguide, and a waveguide adaptor physically connected to the waveguide input coupler proximal end and to the branch waveguide proximal end. The waveguide input coupler includes a distal end having a distal end width and a proximal end having a proximal end width. The tapered branch waveguide includes a distal end having a distal end width and a proximal end having a proximal end width, the branch waveguide distal end width being greater than the branch waveguide proximal end width. The waveguide input coupler, the branch waveguide, and the waveguide adapter are configured to convert input light having a base transverse waveguide mode to output light having a higher-order waveguide mode. | 2015-10-01 |
20150279395 | DATA WRITE MANAGEMENT - Implementations disclosed herein provide systems and methods for data write management in a storage device responsive to detection of a disturbance. Responsive to the detection of the disturbance, a write operation is paused and a transducer head is moved from a first position on the target data track to a second position separated from the first position by at least one data track. At the second position, the write operation is resumed. | 2015-10-01 |
20150279396 | TAPE RECORDING HEAD HAVING NON-PARALLEL GAPS AND DISSIMILAR TRANSDUCER PITCHES - An apparatus according to one embodiment includes first and second arrays of transducers, each array having a longitudinal axis defined between outermost transducers thereof. The longitudinal axes of the arrays are not parallel to one another. At least one servo track reader is associated with each array for reading servo data from the medium. The transducers are for reading and/or writing data in data bands of the magnetic medium. A computer program product for writing data to a magnetic recording tape, according to one embodiment, includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a controller to cause the controller to determine an extent of tape dimensional instability, cause adjustment of a tilt angle of a first array of transducers to perform a readback operation based on the determined extent, and cause performance of the readback operation. | 2015-10-01 |
20150279397 | TAPE SERVO TRACK WRITE COMPENSATION - Recording a servo write head spacing for writing servo tracks on a magnetic tape in a manufacturing environment. One or more environmental condition measurements of the manufacturing environment are received by a computer. A pair of servo tracks is written on a magnetic tape by a pair of servo write heads at a nominal spacing. The one or more environmental condition measurements of the manufacturing environment and information pertaining to the spacing of the servo tracks on the magnetic tape are recorded in one or more data stores. | 2015-10-01 |
20150279398 | Locking a Disk-Locked Clock Using Timestamps of Successive Servo Address Marks in a Spiral Servo Track - Described embodiments provide a magnetic mass storage device with a system clock phase-locked to servo address marks on the magnetic disk. A head sequentially reads multiple adjacent servo address marks in a spiral track of servo address marks. When a servo address mark detector detects a mark, the count value of a counter driven by the system clock is sampled and held by a latch. A system clock synthesizer calculates differences in value between successively sampled count values from the latch, averages the differences in value to create an average difference value, and normalizes a difference between the average difference value and a target value to create a phase error value. The phase of the system clock is updated using the phase error value. | 2015-10-01 |
20150279399 | PLANAR PLASMON GENERATOR WITH THICKENED REGION AND PEG REGION - An apparatus (e.g., a heat assisted magnetic recording read/write element) that has an optical component that extends to a location adjacent a media-facing surface of a slider body. The apparatus further includes a planar plasmon antenna that is disposed between the tip portion of the magnetic write pole and the optical component. The planar plasmon antenna can be formed of a plasmonic material operationally capable of a plasmonic excitation in response to an evanescent coupling with an optical mode of the optical component. In some instances, the planar plasmon antenna includes an enlarged region spaced from the optical component and a peg region formed in the enlarged region. The peg region has a thickness in a direction substantially transverse to the optical component that is less than a thickness of a portion of the enlarged region that spaces the peg region from the optical component. | 2015-10-01 |
20150279400 | High Density Granular Perpendicular Recording Media for Mechanical Reliability and Corrosion Resistance - An embodiment of the invention relates to a perpendicular magnetic recording medium comprising (1) a substrate, (2) an interlayer comprising hexagonal columns and (3) a magnetic layer, wherein the magnetic layer is deposited applying a bias voltage to the substrate such that the magnetic layer comprises magnetic grains having substantially no sub-grains within the magnetic layer, and the magnetic layer has perpendicular magnetic anisotropy. | 2015-10-01 |
20150279401 | MAGNETIC RECORDING MEDIUM, METHOD FOR MANUFACTURING SAME, AND FILM-FORMING APPARATUS - A magnetic recording medium including a base material which has flexibility, and a laminated film, in which a variation in magnetic characteristics is within ±10% over a division of 300 m in a longitudinal direction of the base material. | 2015-10-01 |
20150279402 | MAGNETIC RECORDING MEDIUM - A magnetic recording medium includes a base material which has flexibility, a lower coating layer, and a recording layer, in which, in X-ray diffraction peaks, a value of Δθ | 2015-10-01 |
20150279403 | MAGNETIC RECORDING MEDIUM AND MAGNETIC COATING COMPOSITION FOR MAGNETIC RECORDING MEDIUM - An aspect of the present invention relates to a magnetic recording medium, which comprises a magnetic layer comprising ferromagnetic powder and binder on a nonmagnetic support, wherein the magnetic layer further comprises a compound which has a weight average molecular weight of equal to or more than 1,000 but less than 20,000 and is denoted by formula (1): | 2015-10-01 |
20150279404 | MAGNETIC RECORDING MEDIUM AND MAGNETIC COATING COMPOSITION FOR MAGNETIC RECORDING MEDIUM - An aspect of the present invention relates to a magnetic recording medium, which comprises a magnetic layer comprising ferromagnetic powder and binder on a nonmagnetic support, wherein the magnetic layer further comprises a compound which has a weight average molecular weight of equal to or more than 1,000 but less than 20,000 and is denoted by formula (1): | 2015-10-01 |
20150279405 | BINDER FOR MAGNETIC RECORDING MEDIUM AND METHOD OF MANUFACTURING THE SAME, COMPOSITION FOR MAGNETIC RECORDING MEDIUM, AND MAGNETIC RECORDING MEDIUM - An aspect of the present invention relates to binder for a magnetic recording medium, which is vinyl chloride resin comprising at least one side chain, the side chain comprising at least one urethane bond and at least one monovalent sulfur-containing substituent denoted by formula (1): | 2015-10-01 |
20150279406 | METHOD OF MANUFACTURING HEXAGONAL FERRITE POWDER, HEXAGONAL FERRITE POWDER, AND MAGNETIC RECORDING MEDIUM - An aspect of the present invention relates to A method of manufacturing hexagonal ferrite powder, which comprises heating to equal to or higher than 300° C. and pressurizing to equal to or higher than 20 MPa a hexagonal ferrite precursor-containing water-based solution, to convert the precursor to hexagonal ferrite, wherein the water-based solution comprises at least a reducing compound selected from the group consisting of a reducing inorganic compound and a reducing organic compound that have a reducing property and exist as a solid or a liquid at ordinary temperature and ordinary pressure, as well as, when the reducing compound is a reducing inorganic compound, the water-based solution further comprises an organic compound. | 2015-10-01 |
20150279407 | METHOD OF MANUFACTURING HEXAGONAL FERRITE POWDER, HEXAGONAL FERRITE POWDER, AND MAGNETIC RECORDING MEDIUM - An aspect of the present invention relates to a method of manufacturing hexagonal ferrite powder, which comprises introducing a hexagonal ferrite precursor and an organic compound, either simultaneously or sequentially, into a feed passage into which water is being continuously fed while being heated and pressurized, continuously feeding a water-based solution comprising at least the hexagonal ferrite precursor, the organic compound, and water through the feed passage to a reaction flow passage within which a fluid flowing therein is subjected to heating and pressurizing to convert the hexagonal ferrite precursor into hexagonal ferrite in the reaction flow passage, discharging and feeding a water-based comprising the hexagonal ferrite from the reaction flow passage to a cooling element, and recovering the hexagonal ferrite from the water-based solution that has been cooled in the cooling element, wherein a solution temperature at the point of first contact between the hexagonal ferrite precursor and the organic compound is equal to or higher than 200° C. but lower than 300° C., and a pH of the water-based solution that has been cooled is equal to or higher than 6.0 but equal to or lower than 12.0. | 2015-10-01 |
20150279408 | HEXAGONAL FERRITE POWDER AND MAGNETIC RECORDING MEDIUM - An aspect of the present invention relates to hexagonal ferrite powder, which comprises equal to or more than 70% on a particle number basis of isotropic hexagonal ferrite particles satisfying equation (1): | 2015-10-01 |
20150279409 | OPTICAL RECORDING METHOD, OPTICAL RECORDING MEDIUM, OPTICAL RECORDING MEDIUM RECORDING APPARATUS, OPTICAL RECORDING APPARATUS, OPTICAL DISK, AND OPTICAL DISK RECORDING/REPRODUCING APPARATUS - A mark having a length nT (n being an integer equal to or greater than 3 and T being a clock period) is formed by modulating irradiation laser power with three values of recording power Pw, erase power Pe, and bias power Pb (Pw>Pe>Pb). Constant strength periods (A | 2015-10-01 |
20150279410 | OPTICAL RECORDING AND PLAYBACK APPARATUS - An optical recording and playback apparatus o includes: a light source configured to emit a light beam; a tracking mirror configured to change a direction of the light beam; a collimator configured to form the light beam into a parallel light beam; an objective lens configured to collect the parallel light beam to the optical tape; a lens actuator configured to adjust a position of the objective lens in a focus direction of the optical tape and a position of the objective lens in a tracking direction of the optical tape; a polarization hologram plate configured to separate a reflected light beam of the light beam; a photodetector receiving elements configured to receive the plurality of light fluxes; and a control circuit configured to control the lens actuator and the tracking mirror. The tracking mirror is disposed near the light source, and movable in the tracking direction. | 2015-10-01 |
20150279411 | OPTICAL RECORDING MEDIUM AND MANUFACTURING METHOD OF THE SAME - Provided is an optical recording medium including: two discs, each of which includes a substrate and a plurality of recording layers; and an attachment layer which is provided between the two discs and includes ultraviolet curable resin, wherein thickness of each of the substrates in the two discs is equal to or greater than 0.3 mm and equal to or less than 0.545 mm, wherein transmittance of the two discs is equal to or less than 20%, and wherein inversion rates on both surface sides of the attachment layer are equal or substantially equal to each other, and are equal to or greater than 70%. | 2015-10-01 |
20150279412 | RECORDING MEDIUM AND MANUFACTURING METHOD OF RECORDING MEDIUM - Provided is a recording medium including an ink receiving layer. The ink receiving layer includes a hydrophilic resin and a low oil absorbing porous silica. | 2015-10-01 |
20150279413 | INTEGRATED REEL HUB AND MOTOR SHAFT ASSEMBLY FOR TAPE DRIVES - An integrated reel hub and motor shaft assembly for a tape drive that limits axial and radial run-out of tape (e.g., magnetic, optical) relative to a read/write head assembly and the various errors (e.g., loading, tension, reading, writing, and the like) associated therewith. In one arrangement, a reel hub of a reel assembly is directly molded (e.g., via an injection molding process) onto and around an end of a drive or motor shaft of a drive assembly. As a result, a more consistent head to tape interface, greater tape tracking performance, increased track density, and the like may be achieved. | 2015-10-01 |
20150279414 | DATA ARCHIVE SYSTEM - A data archive system includes a data library apparatus and a server. The data library apparatus includes recording media having recording surfaces on both surfaces, a recording media storage unit for storing the recording media, a recording/reproducing unit for the surface for recording/reproducing the data on/from the surface of the recording media, a recording/reproducing unit for the rear surface for recording/reproducing the data on/from the rear surface, and a recording media transporting unit for transporting the recording media between the recording media storage units. The server includes a data configuration unit for allocating the data for recording on the surface and the rear surface of the recording media and a controller for controlling the data library apparatus. The data configuration unit of the server alternately allocates the recording data on the surface and the rear surface of the recording media different from each other. | 2015-10-01 |
20150279415 | Systems and Methods for Skew Tolerant Multi-Head Data Processing - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing skew tolerant processing of data derived from multiple read heads. | 2015-10-01 |
20150279416 | Magnetization Control For Magnetic Shield In Magnetic Recording Head - A hard disk drive (HDD) is described which includes a magnetic field-generating device in the vicinity of a load/unload ramp such that the write head moves into a magnetic field generated by the device while the head is being unloaded from disk, whereby the magnetic field pins in a predominant direction the direction of magnetization of a magnetic shield associated with the write head, and away from the direction toward the disk. Recording magnetic field leakage associated with the shield is thereby suppressed and corresponding far track interference is inhibited. | 2015-10-01 |
20150279417 | DEMODULATION METHOD OF MAGNETIC DATA AND DEMODULATION DEVICE OF MAGNETIC DATA - A demodulation method of magnetic data may include a first data creating step which creates a preliminary data string for creating the demodulation data on a basis of an interval that is a time interval between peaks of a read signal of an analog-shaped magnetic data, and a second data creating step which creates a demodulation data creating data for creating the demodulation data on a basis of the preliminary data string created in the first data creating step. When a peak of the read signal is not detected for a predetermined time, a pseudo-peak is generated and a pseudo-interval is stored in a data storage section, and steps similar to the first data creating step and the second data creating step are executed, and the pseudo-peak is generated until the demodulation data creating data corresponding to a final interval is created. | 2015-10-01 |
20150279418 | VIDEO SYSTEM WITH FOVEA TRACKING AND METHODS FOR USE THEREWITH - A viewer fovea tracking generator is configured to analyze image data corresponding to a viewing of the video program via an A/V player by at least one viewer, and to generate fovea tracking data corresponding to the at least one viewer. A network interface configured to transmit the fovea tracking data to the video source via a network. The video program is fovea encoded by the video source in accordance with the fovea tracking data. | 2015-10-01 |
20150279419 | MULTI-SENSOR MEDIA DEFECT SCAN - Apparatus and method for detecting media defects using a multi-sensor transducer. In some embodiments, a first pattern is written to a first track on a rotatable storage media and a second pattern is written to a second track on the media. A first read sensor of a multi-sensor transducer senses the first pattern from the first track and a second read sensor of the multi-sensor transducer concurrently senses the second pattern from the second track. At least one storage media defect is detected responsive to the sensed first and second patterns. | 2015-10-01 |
20150279420 | SIGNAL-QUALITY-INFORMATION CORRECTION DEVICE, SIGNAL-QUALITY-INFORMATION CORRECTION METHOD, AND INFORMATION REPRODUCTION SYSTEM - Measured signal quality information obtained by measuring signal quality information showing signal quality obtained when an information reproduction device reproduces information from an information recording medium includes a device-caused variation which is a variation in the signal quality information that has degraded due to the information reproduction device, and a medium-caused variation which is a variation in the signal quality information that has degraded due to the information recording medium. A signal-quality-information correction device includes a device-caused-variation detection section which detects the device-caused variation included in the measured signal quality information, and a signal-quality-information correction section which corrects the measured signal quality information to signal quality information resulting from removal of the device-caused variation detected by the device-caused-variation detection section from the measured signal quality information. | 2015-10-01 |
20150279421 | ADAPTIVE CALIBRATION OF NOISE PREDICTIVE FINITE IMPULSE RESPONSE FILTER BASED ON DECODER CONVERGENCE - A communication system and a noise predictive calibration method are disclosed. The communication system includes a decoder configured to decode an input signal, wherein the decoder produces one of: a converged data output when the decoder decodes the input signal successfully, and a non-converged data output when the decoder decodes the input signal unsuccessfully. The communication system also includes a convergence monitor configured to determine a calibration procedure based on at least one of: a number of times where the decoder decodes successfully, and a number of times where the decoder decodes unsuccessfully. A noise predictive calibration circuit is configured to utilize output produced by the decoder without qualification when the convergence monitor indicates utilization of a first calibration procedure. The noise predictive calibration circuit is further configured to utilize only the converged data output produced by the decoder when the convergence monitor indicates utilization of a second calibration procedure. | 2015-10-01 |
20150279422 | TAPE DRIVE WITH INTEGRATED REEL HUB AND MOTOR SHAFT ASSEMBLY - An integrated reel hub and motor shaft assembly for a tape drive that limits axial and radial run-out of tape (e.g., magnetic, optical) relative to a read/write head assembly and the various errors (e.g., loading, tension, reading, writing, and the like) associated therewith. In one arrangement, a reel hub of a reel assembly is directly molded (e.g., via an injection molding process) onto and around an end of a drive or motor shaft of a drive assembly. As a result, a more consistent head to tape interface, greater tape tracking performance, increased track density, and the like may be achieved. | 2015-10-01 |
20150279423 | RECORD FILE EDITING METHOD AND SYSTEM - The present invention is applicable to the field of multimedia technologies and provides a record file editing method and system, where the method includes: performing fragmentation on an audio file to acquire multiple audio fragments; performing fragment cutting on the multiple acquired audio fragments; storing a fragment time period, a quantity of audio fragments, a fragment cutting time point, and an audio fragment number in a preset record file of the fragment cutting time point; reading each fragment cutting time point from the record file of the fragment cutting time point, performing time mapping on the fragment cutting time point, and storing, in an array, a new fragment cutting time point that is obtained after the mapping; and reading a prestored interaction mapping file between a document and audio, and performing an adjustment on a time point in the interaction mapping file between a document and audio according to the new fragment cutting time point. According to the present invention, a problem that inconsecutive edited document files and audio are not synchronized during playback can be effectively resolved. | 2015-10-01 |
20150279424 | SOUND QUALITY OF THE AUDIO PORTION OF AUDIO/VIDEO FILES RECORDED DURING A LIVE EVENT - A digital audio/video (AV) file, or media file (File A) recorded at a live event using a handheld AV recording device is uploaded by a client to an audio replacement service. The audio portion of the digital AV file is of relatively low quality compared to an audio file (File B) of the live event created by sound engineers or other event personnel during the live event. File B is also uploaded to the audio replacement service. A computing device at the audio replacement service automatically identifies a segment of File B corresponding to the audio portion of File A and then creates a new, enhanced digital AV file (File C) on which the low quality audio portion of File A is replaced with the corresponding high quality segment from File B. File C is then downloaded to the client. | 2015-10-01 |
20150279425 | SYSTEM AND METHOD FOR SPACE-TIME ANNOTATION-CAPABLE MEDIA SCRUBBING - A system for creating a streaming media navigation and annotation display, allowing for deep annotation and efficient browsing of annotations. A system which additionally allows for annotating spatial elements of media, for example cinematic effects. A method which implements this using reactive methods which allow integration with advanced knowledge representation and display systems. | 2015-10-01 |
20150279426 | Learning Environment Systems and Methods - A system includes one or more devices for use in a learning environment that transmit information about the learning environment to a computing system. A recording device for use in the learning environment includes a camera, a processing device, and a storage device. The processing device is configured to process each of a plurality of video files including video data captured by the camera to generate information about which of the plurality of video files satisfy a particular characteristic. The recording device is configured to transmit the information about which of the plurality of video files satisfy the particular characteristic to the computing system, and is configured to transmit a particular video file of the plurality of video files in response to a download request for the particular video file. Wearable devices are wearable by students in the learning environment and transmit signals to provide information about the students. | 2015-10-01 |
20150279427 | Coordinated Audiovisual Montage from Selected Crowd-Sourced Content with Alignment to Audio Baseline - A generally diverse set of audiovisual clips is sourced from one or more repositories for use in preparing a coordinated audiovisual work. In some cases, audiovisual clips are retrieved using tags such as user-assigned hashtags or metadata. Pre-existing associations of such tags can be used as hints that certain audiovisual clips are likely to share correspondence with an audio signal encoding of a particular song or other audio baseline. Clips are evaluated for computationally determined correspondence with an audio baseline track. In general, comparisons of audio power spectra, of rhythmic features, tempo, pitch sequences and other extracted audio features may be used to establish correspondence. For clips exhibiting a desired level of correspondence, computationally determined temporal alignments of individual clips with the baseline audio track are used to prepare a coordinated audiovisual work that mixes the selected audiovisual clips with the audio track. | 2015-10-01 |
20150279428 | METHOD FOR GENERATING THUMBNAIL AND ELECTRONIC DEVICE THEREOF - A method and apparatus for generating a thumbnail of a video content in an electronic device is provided. The method for generating the thumbnail of the video content in the electronic device includes dividing a video content into a plurality of pieces, extracting a characteristic point of each of the plurality of pieces, comparing the characteristic point of each of the plurality of pieces and a characteristic point of each of a plurality of pieces of at least one other video content, and determining a thumbnail of the video content from a piece of the video content that is not the same as a piece of the at least one other video content, based on a result of the comparing. | 2015-10-01 |
20150279429 | VIDEO PROCESSING SYSTEM WITH DIGEST GENERATION AND METHODS FOR USE THEREWITH - Aspects of the subject disclosure may include, for example, a system receives indexing data delineating a plurality of program segments in a video signal that each include a sequence of images of the video signal. The indexing data further indicates content contained in the plurality of program segments. A digest generator generates digest data associated with the video signal based on the indexing data, wherein the digest data indicates a plurality of digest segments that constitute a noncontiguous subset of the video signal. Other embodiments are disclosed. | 2015-10-01 |
20150279430 | HAMR DRIVE FAULT DETECTION SYSTEM - A data storage apparatus includes a controller capable of being coupled to a read/write head. The controller is configured to receive a fault signal from a sensor of the read/write head. The sensor indicates whether an energy source used to heat the recording medium is malfunctioning during a write operation. In response to the fault signal, the controller takes remedial action to protect the data associated with the write operation. | 2015-10-01 |
20150279431 | STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH PARTITIONED LOGIC AND ASSOCIATED SYSTEMS AND METHODS - Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies. | 2015-10-01 |
20150279432 | MEMORY DEVICES WITH LOCAL AND GLOBAL DEVICES AT SUBSTANTIALLY THE SAME LEVEL ABOVE STACKED TIERS OF MEMORY CELLS AND METHODS - In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a tier of global devices at substantially a same level as the tier of local devices. A local device may provide selective access to a data line. A global device may provide selective access to a global access line. A tier of memory cells may be selectively coupled to a global access line by the global device of the tier of global devices. | 2015-10-01 |
20150279433 | ALLOCATING MEMORY ADDRESS SPACE BETWEEN DIMMS USING MEMORY CONTROLLERS - A memory controller enters a memory mode, allocating memory address space within a pair of DIMMs such that each DIMM of the pair contains unallocated memory address space corresponding to allocated memory space in the other DIMM. The memory controller enters another memory mode, modifying the allocation of the memory address space from a first DIMM of the pair of DIMMs to a second DIMM of the pair of DIMMs. The data is moved from allocated memory address space of the first DIMM to unallocated memory address space in the second DIMM. | 2015-10-01 |
20150279434 | SENSING MARGING EXPANDING SCHEME FOR MEMORY - A sensing margin expanding scheme for a memory and a method therefor is disclosed. A first terminal of a first capacitor is coupled to a bit line. A first terminal of a second capacitor is coupled to a reference voltage. In a first phase, the controller controls a first common switch and a second common switch to store the voltage difference between the bit line and the reference voltage to the first capacitor and the second capacitor. In a second phase, controlling the first common switch and the second common switch to open the first terminal of the first capacitor and the second terminal of the second capacitor and open the second terminal of the first capacitor and the first terminal of the second capacitor, and then coupling the second terminal of the first capacitor and the second terminal of the second capacitor to a common voltage. | 2015-10-01 |
20150279435 | LOW POWER MEMORY DEVICE - A memory device includes a memory cell unit, a bit line unit and a buffering unit. The memory cell unit includes a plurality of memory cell groups. Each memory cell group includes at least one memory cell for storing data therein. The bit line unit includes a plurality of first bit lines each coupled to the at least one memory cell of a respective memory cell group, and a second bit line for transmitting to-be-read data. The buffering unit includes a plurality of two-state buffers. Each two-state buffer has an input terminal coupled to a respective first bit line, and an output terminal coupled to the second bit line. The memory device does not require a sense amplifier, and thus consumes relatively small power. The memory device can operate at a relatively high frequency when properly configured. | 2015-10-01 |
20150279436 | Low Latency, High Bandwidth Memory Subsystem Incorporating Die-Stacked DRAM - A memory subsystem incorporating a die-stacked DRAM (DSDRAM) is disclosed. In one embodiment, a system include a processor implemented on a silicon interposer of an integrated circuit (IC) package, a DSDRAM coupled to the processor, the DSDRAM implemented on the silicon interposer of the IC package, and a DRAM implemented separately from the IC package. The DSDRAM and the DRAM form a main memory having a contiguous address space comprising a range of physical addresses. The physical addresses of the DSDRAM occupy a first contiguous portion of the address space, while the DRAM occupies a second contiguous portion of the address space. Each physical address of the contiguous address space is augmented with a first bit that, when set, indicates that a page is stored in the DRAM and the DSDRAM. | 2015-10-01 |
20150279437 | PACKET PROCESSING APPARATUS AND PACKET PROCESSING METHOD - A packet processing apparatus includes a processor configured to execute a process. The process includes: determining a memory from which packets are read, out of a first memory that stores the packets and a second memory that stores the packets, in accordance with number of pointers indicative of storage locations of the packets in the first memory; and reading the packets stored at the storage locations indicated by the pointers, from the memory determined at the determining. | 2015-10-01 |
20150279438 | ASSIST CIRCUIT FOR MEMORY - Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit. | 2015-10-01 |
20150279439 | NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE HAVING THE SAME - A nonvolatile memory device according to the inventive concepts performs a read operation from a true cell storing data and complementary cell storing complementary data, thereby increasing or maximizing sensing margin. Also, the nonvolatile memory device connects a plurality of true cell/complementary cells to a word line, thereby markedly reducing the size of a memory cell array. | 2015-10-01 |
20150279440 | RESISTANCE CHANGE TYPE MEMORY - According to one embodiment, a resistance change type memory includes a first and a second bit lines, a memory cell connected between the first and second bit lines and including a variable resistance element as a memory element and a first select element including a first control terminal connected to a word line, and an auxiliary circuit connected to the first bit line and including a second select element including a second control terminal connected to a control line. When data is read from the memory cell, a first current in a read current supplied to the first bit line is supplied to the memory element and the first select element, and a second current in the read current is supplied to the second select element. | 2015-10-01 |
20150279441 | MOST ACTIVATED MEMORY PORTION HANDLING - Activation of portions of a memory is tracked to allow an affected portion of the memory to be refreshed before it is corrupted by multiple activations. An address for the accessed portion of memory, called the aggressor row, is compared to addresses stored in a content addressable memory (CAM). If the address is not already stored in the CAM, it is stored, casting out another address if necessary, and a count based on an Others value is stored in the CAM with the address. If the address is already stored in the CAM, its associated count is incremented. If a count associated with an address exceeds a threshold based on a maximum activation count, another portion of memory, such as a victim row of memory adjacent to the aggressor row of memory, is refreshed, and the count reset. | 2015-10-01 |
20150279442 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SAME - A semiconductor memory device includes a plurality of normal word lines and a plurality of redundancy word lines which are disposed adjacent to the normal word lines, a detection block suitable for detecting a first word line whose active history satisfies a predetermined condition and a second word line adjacent to the first word line as a target word line and a target neighboring word line, among the normal word lines and the redundancy word lines, and a control block suitable for sequentially refreshing the normal word lines and the redundancy word lines whenever a refresh command is applied, and additionally refreshing the target word line, the target neighboring word line and a normal word line adjacent to the redundancy word lines among the normal word lines. | 2015-10-01 |
20150279443 | SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING THE SAME - A semiconductor memory may include: a bank control signal generation unit suitable for sequentially generating a plurality of bank control signals for controlling a memory bank based on an active command, a signal detection unit suitable for detecting a firstly activated signal and a lastly activated signal among the bank control signals, and a bank enable control unit suitable for controlling an active period of the memory bank in response to the detected signals. | 2015-10-01 |
20150279444 | APPARATUS, METHOD AND SYSTEM FOR PROVIDING TERMINATION FOR MULTIPLE CHIPS OF AN INTEGRATED CIRCUIT PACKAGE - Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series | 2015-10-01 |
20150279445 | METHOD AND APPARATUS FOR DATA CAPTURE IN DDR MEMORY INTERFACE - A method for data acquisition in a memory system includes oversampling a data signal and a strobe signal with a multiphase clock having n phases to generate a series of data signals and a series of strobe signals representing a first data series and a first strobe series respectively, generating a second strobe series by edge detection of the first strobe series followed by retiming of the edge detected series, generating a third strobe series by edge adjustment of the second strobe series, wherein the edge adjustment ensures that there are no overlapping edges among the signals of the third strobe series, generating a sample selected series by linear shifting of each signal of the third strobe series by n/2, generating a second data series by retiming the first data series, generating a third data series by sample adjustment of the second data series, wherein the sample adjustment ensures that the third data series is in synchronization with a sampling window of the sample selected series, and determining a final data signal by multiplexing the third data series with the sample selected series. | 2015-10-01 |
20150279446 | METHOD, APPARATUS AND SYSTEM FOR DETERMINING A WRITE RECOVERY TIME OF A MEMORY BASED ON TEMPERATURE - Techniques and mechanisms for determining a write recovery time of a memory device. In an embodiment, thermal detection logic detects a signal from a thermal sensor indicating a temperature state of a resource of the memory device. A value of a write recovery parameter is set based on the signal from the thermal sensor. In another embodiment, command logic generates a signal to precharge one or more cells of the memory device. The write recovery parameter is used by timer logic to control a timing of the signal to precharge the one or more cells. | 2015-10-01 |
20150279447 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM - A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble register configured to be capable of storing the information. | 2015-10-01 |
20150279448 | REFERENCE CIRCUIT TO COMPENSATE FOR PVT VARIATIONS IN SINGLE-ENDED AMPLIFIERS - The disclosure relates to semiconductor memory devices and related methods. A semiconductor memory device comprises: a single-ended sense amplifier circuit for reading data sensed from selected memory cells in a memory array, the sense amplifier having a first node used to feed in a reference signal, a second node coupled to a bit line, and sense transistors responsible for amplifying the content of a selected memory cell during a sense operation, a reference circuit having replica transistors of the sense transistors and further comprising a regulation network designed so that each replica transistor operates in a stable operating point, and wherein the regulation network generates a control voltage that is applied to the sense amplifier circuit. | 2015-10-01 |
20150279449 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE - A semiconductor device includes a circuit block that is switchable between selection and non-selection, and a leakage current control circuit disposed between the circuit block and a first power supply line. The leakage current control circuit includes a first transistor disposed between the circuit block and the first power supply line, and a resistor device disposed between the circuit block and the first power supply line. | 2015-10-01 |
20150279450 | Data-Aware SRAM Systems and Methods Forming Same - Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively. | 2015-10-01 |
20150279451 | EDGE-TRIGGERED PULSE LATCH - A pulse latch is provided that latches a ground signal responsive to decoded signal carried on a decoded signal node. The pulse latch includes a reset logic circuit that controls a switch coupled between the decoded signal node and ground such that when the switch is turned on by the reset logic circuit, the decoded signal node is grounded. The reset of the decoded signal node by the reset logic circuit is responsive to a ground signal. The ground signal is generated so as to be responsive to a clock edge. Thus, the reset of the decoded signal node is also responsive to the clock edge. | 2015-10-01 |
20150279452 | MEMORY HAVING A PULL-UP CIRCUIT WITH INPUTS OF MULTIPLE VOLTAGE DOMAINS - A memory and a method for operating the memory having a precharge circuit with inputs of multiple voltage domains are provided. In one aspect, a memory includes a bitline and one or more storage elements coupled to the bitline. The one or more storage elements are configured to operate in a first voltage domain using a first supply voltage. A pull-up circuit is configured to pull up the bitline to a second supply voltage in a second voltage domain. The pull-up circuit is responsive to a first control signal in the first voltage domain and a second control signal in the second voltage domain. The first supply voltage is different than the second supply voltage. | 2015-10-01 |
20150279453 | MEMORY CIRCUIT HAVING SHARED WORD LINE - A memory circuit includes a plurality of memory cells arranged into columns and one or more pairs of adjacent rows and one or more first word lines. Each memory cell of the plurality of memory cells includes a data node, a first access node, and a first pass gate coupled to the first access node and configured to selectively alter a voltage level at the first access node according to a voltage level at the data node if the first pass gate is turned on. A word line of the one or more first word lines is coupled with the first pass gates of a pair of the one or more pairs of adjacent rows, and the first pass gates of the pair of the one or more pairs of adjacent rows are configured to be selectively turned on responsive to a voltage level at the word line. | 2015-10-01 |
20150279454 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring. | 2015-10-01 |
20150279455 | SOLID HARD DISK AND CHARGING/DISCHARGING CONTROL METHOD FOR FLASH CHIP - A method comprises steps of mapping a same physical page to two mutually coupled logic pages, one logic page being formed by mapping the least significant bit on the physical page, and the other logic page being formed by mapping the most significant bit on the physical page; buffering write data in a buffer memory, and merging the data, which is corresponding to the two mutually coupled logic pages, in the buffer memory into a piece of data corresponding to the physical page according to the mapping relationship between the physical page and the two mutually coupled logic pages; and performing charging/discharging control for the multi-layer memory cell of the physical page according to the merged data, so that a voltage state of the multi-layer memory cell is expressed as a numerical value of the merged data. | 2015-10-01 |
20150279456 | SEMICONDUCTOR MEMORY DEVICE AND FILE MEMORY SYSTEM - According to an embodiment, a semiconductor memory device has: a memory cell array formed by stacking through insulation layers a plurality of memory mats which each have a plurality of first lines, a plurality of second lines and a plurality of resistance varying memory cells provided at intersection portions of the pluralities of first lines and second lines; and an accessing circuit which applies voltages to the memory cell array. A number of the first lines included in the memory mat is greater than a number of the second lines. When the accessing circuit accesses the selected memory cell, the accessing circuit selects a plurality of first lines and a second line connected to selected memory cells to which the accessing circuit needs to be connected and judges data stored in the selected memory cells according to currents flowing to the selected memory cells. | 2015-10-01 |
20150279457 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor memory device includes: a memory cell (MC | 2015-10-01 |
20150279458 | DETERMINING A CELL STATE OF A RESISTIVE MEMORY CELL - A device for determining an actual cell state of a resistive memory cell having a plurality M of programmable cell states comprising a sensing circuit, a settling circuit, a prebiasing circuit, and a resistor coupled in parallel to the resistive memory cell, wherein the resistor is configured to reduce an effective resistance seen by the prebiasing circuit. The sensing circuit is configured to sense a sensing voltage of the resistive memory cell and output a resultant value in response to the sensing voltage which is indicative for the actual cell state. The settling circuit is configured to settle the sensing voltage to a certain target voltage representing one of the M programmable cell states. The prebiasing circuit is configured to prebiase a bitline capacitance of the resistive memory cell such the sensing voltage is close to the certain target voltage. | 2015-10-01 |
20150279459 | CONFIGURABLE REFERENCE CURRENT GENERATION FOR NON VOLATILE MEMORY - This disclosure relates to generating a reference current for a memory device. In one aspect, a non-volatile memory device, such as a phase change memory device, can determine a value of a data digit, such as a bit, stored in a non-volatile memory cell based at least partly on the reference current. The reference current can be generated by mirroring a current at a node that is biased by a voltage bias. A configurable resistance circuit can have a resistance that is configurable. The resistance of the configurable resistance circuit can be in series between the node and a resistive non-volatile memory element. In some embodiments, a plurality of non-volatile memory elements can each be electrically connected in series between the resistance of the configurable resistance circuit and a corresponding selector. | 2015-10-01 |
20150279460 | CROSS-POINT MEMORY COMPENSATION - The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop. | 2015-10-01 |
20150279461 | ALLOCATING MEMORY ADDRESS SPACE BETWEEN DIMMS USING MEMORY CONTROLLERS - A memory controller enters a memory mode, allocating memory address space within a pair of DIMMs such that each DIMM of the pair contains unallocated memory address space corresponding to allocated memory space in the other DIMM. The memory controller enters another memory mode, modifying the allocation of the memory address space from a first DIMM of the pair of DIMMs to a second DIMM of the pair of DIMMs. The data is moved from allocated memory address space of the first DIMM to unallocated memory address space in the second DIMM. | 2015-10-01 |
20150279462 | NON-VOLATILE MEMORY BASED ON RETENTION MODULATION - A mechanism that provides a source of reliability concern is leveraged to establish a non-volatile memory element. A memory cell may be programmed to have a longer retention time or a shorter retention time. Such mechanisms include, but are not limited to, threshold voltage modulation by charge trapping in the gate dielectric of an access transistor of a dynamic random access memory (DRAM) cell. A memory cell is programmed with a voltage pulse into a long retention time mode or into a short retention time mode. The programmed mode of each memory cell may be read by storing electrical charges in the DRAM cells, and by measuring whether the electrical charges remain after a threshold retention time. Further, a dual mode memory cell may be operated as a conventional DRAM cell, or as a non-volatile memory storing retention time as data. | 2015-10-01 |
20150279463 | ADJUSTABLE NON-VOLATILE MEMORY REGIONS OF DRAM-BASED MEMORY MODULE - An information handling system and method provide for: electrically powering, with a primary power source and an independent power source, a dynamic random access memory (DRAM) module having an amount of memory space that is addressed by a host processor of an information handling system; measuring an energy capacity value of the independent energy storage device; determining a persistent value corresponding to a fraction of the memory space of the DRAM module that can be protected based at least in part on the measured energy capacity value of the independent energy storage device; reporting the persistent value to the host processor; and communicating by the host processor to the DRAM module a dynamic assignment of persistent and non-persistent memory allocations in accordance to the fraction of the memory space of the DRAM module that can be protected in an event of loss of the primary power source. | 2015-10-01 |
20150279464 | MANAGED RUNTIME EXTENSIONS TO REDUCE POWER CONSUMPTION IN DEVICES WITH HYBRID MEMORY - Systems and methods may provide for identifying an object in a managed runtime environment and determining an age of the object at a software level of the managed runtime environment. Additionally, the object may be selectively allocated in one of a dynamic random access memory (DRAM) or a non-volatile random access memory (NVRAM) based at least in part on the age of the object. In one example, the data type of the object is also determined, wherein the object is selectively allocated further based on the data type. | 2015-10-01 |
20150279465 | SYSTEMS AND METHODS FOR ORDER SCOPE TRANSITIONS USING CAM - A data processing system includes a content addressable memory (CAM). Each entry of the CAM corresponds to a task and is configured to store a current scope of each task. A random access memory (RAM) is configured to shadow information of the CAM. Transition position storage circuitry is configured to store transition age positions for tasks. Control circuitry is configured to, in response to a command to transition a selected task to a destination scope, access the RAM to determine the current scope for the selected task, use the current scope to perform a match determination with the CAM to determine if any entries corresponding to tasks other than the selected task match the current scope; and for any matching entries, updating a transition age position in the transition position storage circuitry for the corresponding task within the current scope. | 2015-10-01 |
20150279466 | APPARATUSES AND METHODS FOR COMPARING DATA PATTERNS IN MEMORY - The present disclosure includes apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array to a target data pattern. The method can include determining whether a data pattern of the number of data patterns matches the target data pattern without transferring data from the memory array via an input/output (I/O) line. | 2015-10-01 |
20150279467 | AMPLIFIER STAGE - An input signal is amplified into an output signal that is to be applied to an electrical load including a capacitive component. An amplifier stage includes a pre-amplifier module to receive a first supply voltage, and an output module to receive a second supply voltage. The pre-amplifier module includes a first gain block to pre-amplify the input signal into a first pre-amplified signal, and a second gain block to pre-amplify the input signal into a second pre-amplified signal. A feedback block feeds back the output signal as a feedback signal. A combination element combines the first pre-amplified signal and the feedback signal into a combined signal. The output module combines the combined signal and the second pre-amplified signal into the output signal. | 2015-10-01 |
20150279468 | COMPOSITE IMPURITY SCHEME FOR MEMORY TECHNOLOGIES - An integrated circuit comprises a memory array including diffusion bit lines having composite impurity profiles in a substrate. A plurality of word lines overlies channel regions in the substrate between the diffusion bit lines, with data storage structures such as floating gate structures or dielectric charge trapping structures, at the cross-points. The composite impurity diffusion bit lines provide source/drain terminals on opposing sides of the channel regions that have high conductivity, good depth and steep doping profiles, even with channel region critical dimensions below 50 nanometers. | 2015-10-01 |
20150279469 | NONVOLATILE MEMORY DEVICE, PROGRAM METHOD THEREOF, AND DATA PROCESSING SYSTEM INCLUDING THE SAME - A program method of a nonvolatile memory device includes a pre-program verify step for verifying a threshold voltage of a selected memory cell; a step of setting a bit line voltage of the selected memory cell according to the threshold voltage of the selected memory cell which is determined through the pre-program verify step; a step of applying a program voltage to the selected memory cell set with the bit line voltage; and a post-program verify step for verifying a programmed state of the selected memory cell applied with the program voltage. | 2015-10-01 |
20150279470 | SOLID-STATE MEMORY DEVICE WITH PLURALITY OF MEMORY CARDS - A solid-state memory device includes a physical port, an interface controller connected to the physical port, a serial peripheral interface, and a plurality of memory card sticks connected to the serial peripheral interface. Each memory card stick has a plurality of memory cards. The solid-state memory device further includes a controller core connected between the interface controller and the serial peripheral interface. The controller core is configured to present to a host connected at the physical connector a single non-volatile storage unit with a total capacity substantially equal to a sum of capacities of the plurality of memory card sticks. | 2015-10-01 |
20150279471 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of memory blocks, wherein each of the plurality of memory blocks includes a first select transistor electrically coupled to a common source line, a second select transistor electrically coupled to a bit line, and a plurality of memory cells electrically coupled between the first and second select transistors, and an operation circuit suitable for applying operation voltages for a program operation, a read operation, and an erase operation to a selected memory block selected from the plurality of memory blocks, and applying a first positive voltage to gates of the first select transistors in unselected memory blocks of the plurality of memory blocks when an erase voltage is applied to the common source line during the erase operation. | 2015-10-01 |
20150279472 | TEMPERATURE COMPENSATION VIA MODULATION OF BIT LINE VOLTAGE DURING SENSING - Embodiments of systems and methods described herein relate to temperature compensation of the sense conditions of memory cells during cross temperatures read operations. One embodiment provides a memory device comprising one or more memory cells, a temperature sensor and a controller coupled to the temperature sensor. The temperature sensor measures a temperature of at least one memory cell. The controller modulates a bit line voltage of the at least one memory cell during a program verify or read operation if the read temperature of the at least one memory cell is different from a first temperature of the memory cell. | 2015-10-01 |
20150279473 | FLASH MEMORY DEVICE WITH SENSE-AMPLIFIER-BYPASSED TRIM DATA READ - A non-volatile memory device includes a two-dimensional array of non-volatile memory cells where a first portion of memory cells being configured as an one-time-programmable memory area; a bypass read-out circuit configured to sense a signal level on a bit line in response to a memory cell in the one-time-programmable memory area being selected and to generate a first signal indicative of the signal level on the bit line; and a trim data latch circuit having an input terminal configured to receive the first signal. The trim data latch circuit is configured to store a signal related to the first signal as a trim data value and to provide trim data value to circuitry of the non-volatile memory device. The trim data value may be applied to adjust a signal level of the circuitry of the non-volatile memory device. | 2015-10-01 |
20150279474 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a memory cell array including a plurality of memory cells, and a control circuit for the memory cell array. The control circuit is configured to perform a pre-read operation to read pre-selected memory cells before a read operation on target memory cells is performed and to change a read voltage to be applied to the target memory cells during the read operation based on a result of the pre-read operation. | 2015-10-01 |
20150279475 | NONVOLATILE MEMORY MODULE, MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY MODULE, AND CONTROLLING METHOD OF NONVOLATILE MEMORY MODULE - A memory system is provided, which includes a nonvolatile memory module including a plurality of nonvolatile memory devices, and a memory module controller configured to control the nonvolatile memory module. At least two nonvolatile memory devices of the plurality of nonvolatile memory devices are configured to store serial presence detect (SPD) information. The memory module controller is configured to read the SPD information from the nonvolatile memory module and to set a communication mode with the nonvolatile memory module based on the read SPD information. | 2015-10-01 |
20150279476 | RAMPING INHIBIT VOLTAGE DURING MEMORY PROGRAMMING - The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb. | 2015-10-01 |
20150279477 | FUSE ARRAY - A fuse array may include: an E-fuse including a plurality of active regions having a floating node and a contact node, and a plurality of gates overlapping the respective active regions and separated from each other between the floating node and the contact node; and a plurality of fuse sets each including two or more E-fuses and sharing the floating node or the contact node. | 2015-10-01 |
20150279478 | FUSE ELEMENT PROGRAMMING CIRCUIT AND METHOD - In one embodiment, a programming circuit is configured to form a programming current for a silicide fuse element by using a non-silicide programming element. | 2015-10-01 |
20150279479 | ANTI-FUSE ONE-TIME PROGRAMMABLE RESISTIVE RANDOM ACCESS MEMORIES - An anti-fuse device includes a first electrode, an insulator on the first electrode, a second electrode on the insulator, and selector logic coupled to the second electrode. The device also includes a conductive path between the first and second electrodes. The conductive path may be configured to provide a hard breakdown for one-time programmable non-volatile data storage. | 2015-10-01 |
20150279480 | SHIFT REGISTER, DISPLAY DEVICE PROVIDED THEREWITH, AND SHIFT-REGISTER DRIVING METHOD - Provided is a shift register with which an increase in power consumption can be inhibited, and with which malfunctions due to electric potential Modification Example between gate terminals of output transistors can be inhibited, while inhibiting an increase in circuit size. A bistable circuit of a shift register is provided with first to fourth transistors. In the third transistor, a gate terminal thereof is connected to second conduction terminals of the first and second transistors, a first conduction terminal thereof is connected to a second input terminal, and a second conduction terminal thereof is connected to an output terminal. In the fourth transistor, a gate terminal thereof is connected to the second input terminal, and a second conduction terminal thereof is connected to the gate terminal of the third transistor and the output terminal. | 2015-10-01 |
20150279481 | SHIFT REGISTER - A shift register is realized having a simple construction with which it is possible to switch the scanning order of gate bus lines and the occurrence of an erroneous operation caused by a threshold voltage drop can be prevented. Unit circuits that make up the shift register are configured of: a thin film transistor in which a third clock is supplied to the gate terminal, the drain terminal is connected to a first node, and a first input signal (output signal of prior stage) is supplied to the source terminal; a thin film transistor in which a second clock is supplied to the gate terminal, the drain terminal is connected to the first node, and a second input signal (output signal of subsequent stage) is supplied to the source terminal; and a thin film transistor in which the gate terminal is connected to the first node, a first clock is supplied to the drain terminal, and the source terminal is connected to an output terminal. The shift direction is switched by changing the generation order of pulses of clock signals. | 2015-10-01 |
20150279482 | DATA TRANSFER CIRCUIT - A data transfer circuit has a first data transmission unit and two or more second shift registers. The first data transmission unit has a first shift register which has a plurality of first flip flop circuits which store data, shifts the data of the plurality of first flip flop circuits, and transmits data of two or more output terminals out of output terminals of the plurality of first flip flop circuits to the two or more second shift registers. The two or more second shift registers each shift data inputted from the two or more output terminals out of the output terminals of the plurality of first flip flop circuits. | 2015-10-01 |
20150279483 | ALLOCATION TECHNIQUE FOR MEMORY DIAGNOSTICS - An apparatus for allocating computer memory for memory diagnostics is disclosed. The apparatus may include a processor and memory that stores code executable by the processor, and may include code that identifies an unreserved amount of memory in a computer system, code that requests a portion of the memory based on the unreserved amount of memory, and code that determines whether an allocated portion of the memory comprises non-contiguous memory addresses. In some embodiments, the apparatus includes code that locks the allocated portion of the memory in response to the allocated portion consisting solely of contiguous memory addresses, and code that performs a memory diagnostic test on the allocated portion of the memory. | 2015-10-01 |
20150279484 | MEMORY TEST CIRCUIT AND METHOD FOR CONTROLLING MEMORY TEST CIRCUIT - A test circuit includes a control circuit that tests a memory having a plurality of data holding circuits holding data, a plurality of write ports, and a plurality of read ports, a write port selection circuit that selects any one of the plurality of write ports based on the write port identification information identifying any one of the plurality of write ports; and a read port selection circuit that selects any one of the plurality of read ports based on the read port identification information identifying any one of the plurality of read ports, wherein the control circuit sets the write port identification information and sets the read port identification information and carries out a test on the memory via the selected write port and the selected read port. | 2015-10-01 |
20150279485 | ADVANCED MEMORY TEST DIAGNOSTICS - For performing advanced memory test diagnostics, an apparatus, method, and computer program product are disclosed. The apparatus may include a processor, a memory that stores code executable by the processor, an address space module that identifies an address space having a plurality of blocks of memory addresses, a memory diagnostic module that performs, at least three times, a memory test procedure using a block pattern, wherein a first block pattern is used the first time, a second block pattern is used the second time, and a third block pattern is used the third time, and a memory fault module that determines the presence of a memory fault based on results of the memory test procedures. | 2015-10-01 |
20150279486 | SYSTEM AND METHOD FOR ADDING ERROR PROTECTION CAPABILITY TO A DIGITAL LOGIC CIRCUIT - A system and method for adding error protection capability to a digital logic circuit, for example including random storage logic. Various aspects of the present disclosure, for example, comprise providing error protection against soft errors that occur during operation of digital logic circuitry. | 2015-10-01 |
20150279487 | Memory Repair Categorization Tracking - An integrated circuit includes a set of non-volatile bits that may be programmed during multiprobe testing of the integrated circuit (IC). A defective portion of the IC is identified by testing the IC during multiprobe testing prior to packaging the IC. The IC is scrapped if the defective portion of IC does not meet repair criteria. A defect category is selected that is indicative of the defective portion, wherein the defect category is selected from a set of defect categories. The defective portion is replaced with a standby repair portion by modifying circuitry on the IC. The selected defect category is recorded in a plurality of non-volatile bits on the IC. The non-volatile bits may be read after extended testing or after end-user deployment in order to track failure rate of repaired ICs based on the defect category. | 2015-10-01 |
20150279488 | METHOD AND APPARATUS FOR INSPECTION OF COOLING TOWERS - A method and apparatus for inspecting cooling tower fill pack to detect the presence of fouling, wherein the method comprises using ground penetrating radar (GPR). The method comprises transmitting GPR to the fill pack and detecting reflected radar signals from the fill pack. A method of cleaning fouling from a cooling tower, comprising the steps of: inspecting the cooling tower fill pack with ground penetrating radar (GPR); identifying those parts of the fill pack in which unacceptable levels of fouling are present; and cleaning the parts so identified is also presented. | 2015-10-01 |
20150279489 | NON-INVASIVE IN-SITU IMAGING OF INTERIOR OF NUCLEAR REACTORS - Techniques, systems, and devices are disclosed for non-invasive monitoring and imaging of nuclear fuel inside a nuclear reactor using muon detector arrays. In one aspect, these detector arrays are placed outside the reactor vessel or building for investigating the reactors without access to the cores, therefore the imaging process is non-invasive. In some implementation, these detector arrays measure both muon scattering and absorption to enable imaging and characterizing not only the very high-Z fuel materials, but also other materials in the reactor, thereby obtaining a more complete picture of reactor status. When applied to damaged reactors, the disclosed proposed techniques, systems, and devices, through the process of providing an image, can reveal the presence (or absence) of damage to fuel rod assemblies or puddles of molten fuel at the bottom of the containment vessel, thus providing crucial information to guide decisions about remedial actions. | 2015-10-01 |
20150279490 | RADIOISOTOPE CONCENTRATOR - A system using a radioisotope concentrator device comprising a body having at least one injection port and at least one valve being configurable between a first open configuration for allowing fluid communication between the at least one injection port and the concentrator column and a second open configuration to prevent fluid communication between the at least one injection port and the concentrator column in use, the system further comprising an injection device comprising an eluent for eluting through the concentrator column via the at least one injection port when the at least one valve of the radioisotope concentrator device is in a selected open configuration in use. | 2015-10-01 |
20150279491 | NUCLEAR RADIATION PARTICLE POWER CONVERTER - Various embodiments of a nuclear radiation particle power converter and method of forming such power converter are disclosed. In one or more embodiments, the power converter can include first and second electrodes, a three-dimensional current collector disposed between the first and second electrodes and electrically coupled to the first electrode, and a charge carrier separator disposed on at least a portion of a surface of the three-dimensional current collector. The power converter can also include a hole conductor layer disposed on at least a portion of the charge carrier separator and electrically coupled to the second electrode, and nuclear radiation-emitting material disposed such that at least one nuclear radiation particle emitted by the nuclear radiation-emitting material is incident upon the charge carrier separator. | 2015-10-01 |