40th week of 2008 patent applcation highlights part 18 |
Patent application number | Title | Published |
20080237544 | Thermally Modulated Antioxidants - Most carbon-centered free radical antioxidants are generated through hydrogen abstraction. Disclosed herein a new class of antioxidant precursor compounds of the formula A-B, wherein upon exposure of the compounds to an increase in temperature, the compounds undergo at least partial dissociation into free radicals Ao and Bo at least one of which may be functional as an antioxidant. Preferably, each of Ao and Bo is a carbon centered free radical. | 2008-10-02 |
20080237545 | Advanced Anisotropic Insulated Conductive Ball For Electric Connection, Preparing Method Thereof and Product Using the Same - Disclosed are anisotropic conductive balls for electric connection comprised of conductive balls and insulation resin layers coating the surfaces of those conductive balls. The conductive balls are coated with a core-shell-structured emulsion-phase or suspension-phase or water-dispersible resin to form insulation resin layers as the shells of the insulation resin layers are coated with resin layers having the water-emission ability. Also disclosed are methods of manufacturing anisotropic conductive balls for electric connection as well as the products using them. Although the surfaces of the anisotropic conductive balls are coated with single- or multi-layered insulation resin layers, they show superior alive and insulation characteristics. | 2008-10-02 |
20080237546 | Method of making semiconductor nanocrystal composites - A semiconductor nanocrystal composite comprising a semiconductor nanocrystal composition dispersed in an inorganic matrix material and a method of making same are provided. The method includes providing a semiconductor nanocrystal composition having a semiconductor nanocrystal core, providing a surfactant formed on the outer surface of the composition, and replacing the surfactant with an inorganic matrix material. The semiconductor nanocrystal composite emits light having wavelengths between about 1 and about 10 microns. | 2008-10-02 |
20080237547 | TRANSPARENT CONDUCTIVE MATERIAL AND TRANSPARENT CONDUCTOR - A transparent conductive material contains a conductive particle, a polyfunctional compound, and an organic compound having a side chain including an ester group, while the ester group is expressed by —COOR, where R is a substituted or unsubstituted alkyl group having a carbon atom number of 2 or greater. | 2008-10-02 |
20080237548 | Ultrafine metal powder slurry - In an ultrafine metal powder slurry containing an organic solvent, a surfactant, and an ultrafine metal powder, the surfactant is oleoyl sarcosine, the content of the ultrafine metal powder in the ultrafine metal powder slurry is 70 to 95 percent by mass, and more than 0.05 to less than 2.0 parts by mass of the surfactant is contained relative to 100 parts by mass of the ultrafine metal powder. By the above slurry, reduction in labor and treatment time can be realized in a conductive paste forming process. In addition, since aggregation of particles of the ultrafine metal powder is prevented, an ultrafine metal powder slurry can be provided having superior dispersibility and dry film density. | 2008-10-02 |
20080237549 | PHOSPHOR MATERIAL AND MANUFACTURING METHOD THEREOF - A novel phosphor material which can be manufactured without utilizing a fault formation process which is difficult to be controlled. The phosphor material has a eutectic structure formed of a base material that is a semiconductor formed of a Group 2 element and a Group 6 element, a semiconductor formed of a Group 3 element and a Group 5 element, or a ternary phosphor formed of an alkaline earth metal, a Group 3 element, and a Group 6 element, and a solid solution material including a transition metal. The phosphor material is suited for an EL element because of less variation of characteristic since defect formation process in which stress is applied externally to form a defect inside of a phosphor material is not needed. | 2008-10-02 |
20080237550 | PARTICLES FOR ELECTROPHORETIC MEDIA - Compositions of encapsulated triboelectrically charged particles and methods for making them using a spinning disc process are disclosed. The methods can be used to make charged pigment particles embedded in a neutral polymer matrix. The polymer matrix keeps oppositely charged pigment particle from agglomerating. The particles can be used for electrophoretic displays. | 2008-10-02 |
20080237551 | Ferroelectric thin film and device including the same - A composition for forming a ferroelectric thin film includes: a PZT sol-gel solution including at least one of: a whole or partial hydrolysate of a lead precursor and a whole or partial hydrolyzed and polycondensated product thereof; a whole or partial hydrolysate of a zirconium precursor, a whole or partial hydrolyzed and polycondensated product thereof, and a zirconium complex having at least one hydroxy ion and at least one non-hydrolyzable ligand; and a whole or partial hydrolysate of a titanium precursor, a whole or partial hydrolyzed and polycondensated product thereof, and a titanium complex having at least one hydroxyl ion and at least one non-hydrolyzable ligand; and a Bi | 2008-10-02 |
20080237552 | Optical compensation films with mesogen groups for liquid crystal display - Optical compensation films (positive C-plate) with mesogen anisotropic subunits (OASUs) that have high positive birefringence throughout the wavelength range 400 nm<λ<800 nm are provided. The optical compensation films may be processed by solution casting to yield a polymer film with high birefringence without the need for stretching, photopolymerization, or other processes. Such optical compensation films are suitable for use as a positive C-plate in LCDs, particularly IPS-LCDs. | 2008-10-02 |
20080237553 | Colored photosensitive resin composition, and color filter array and solid-state image pickup device using the same - A colored photosensitive resin composition comprising an alkali-soluble resin, a photosensitive compound, a curing agent, a solvent and a colorant represented by the formula (I): | 2008-10-02 |
20080237554 | Colored photosensitive resin composition, and color filter array and solid-state image pickup device using the same - A colored photosensitive resin composition comprises a compound represented by the formula (I) or a salt thereof: | 2008-10-02 |
20080237555 | Scorch prevention in flexible polyurethane foams - Compositions are provided for alleviating or preventing discoloration, known as “scorching”, in flame-retarded flexible polyurethane foams. The anti-scorch compositions contain combinations of antioxidant agents, epoxy compounds, organic phosphites—alone or in combination with metal salts of carboxylic acids. The compositions are useful, for example, for polyurethane foams retarded with aliphatic or aromatic phosphorus-based flame retardants, or with halogen-containing flame retardants. | 2008-10-02 |
20080237556 | Electronic Device with an Elevating Mechanism - An electronic device with an elevating mechanism includes a body and the elevating mechanism connected with the body. The elevating mechanism includes a support base, an elevating element, and a fastening element. The elevating element capable of moving between a first position and a second position relative to the support base is connected with both the support base and the body. The elevating element includes a first wedging component. The fastening element disposed around the second position relative to the support base is rotatable between a third position and a fourth position. The fastening element includes a second wedging component. When the fastening element is rotated to the fourth position, the second wedging component is wedged on the first wedging component for fastening the elevating element at the second position. | 2008-10-02 |
20080237557 | Door and Board Lifting Device - A door and board lifting device comprising a foot operated lever and locking means wherein said locking means is operative to releasably secure the lever in a substantially fixed position. | 2008-10-02 |
20080237558 | Electric Fence Tape and Method of Weaving and Installing - An interwoven, adhesive backed, electric fence barrier ribbon and tape and a method of weaving thereof. The present invention discloses a fully self contained electric fencing system that is adaptable to many conditions and one that does not require a ground rod or any special soil conditions to operate. The invention accomplishes this by providing two different groups of conductors, each being electrically potentially different from the other and all weaved within the same tape for use with high voltage or low voltage systems. The invention also provides for an efficient and cost effective system to mass produce the product and further more it can be produced in a multitude of color coordinated choices as set forth in the following specifications. | 2008-10-02 |
20080237559 | High security gate assembly and method of installation - A gate assembly prevents keyless ingress into, and enables keyless egress from, a gated area. The gate assembly comprises a gate frame and a gate. The gate frame comprises rectangular or 360 degree frame structure for maintaining a planar gate-receiving area despite ground deformations and the like. The gate comprises rectangular gate structure that defines a planar frame-engaging area. The gate-receiving area is greater in magnitude than the frame-engaging area. The gate further comprises a state of the art interior push bar latch for enabling keyless egress, and state of the art keyed lock for preventing keyless ingress into the gated or secure area. An inferior frame member is anchored in subterranean media for positioning the gate frame during installation for maintaining the gate-receiving area should ground deformations occur. | 2008-10-02 |
20080237560 | Two-part fence base - An anchor assembly for a temporary fence; said assembly comprising a base portion and a superposed insert portion; each said base portion and said superposed insert portion comprising a composite of a shell open at the underside, and a settable material filling said shell; and wherein respective pairs of formers integral to each said shell of said base portion and said superposed portion, define substantially vertical pairs of passages through said base portion and said superposed insert portion; said passages arranged so that when said base portion and said superposed insert portion are assembled together, respective pairs of said passages are in vertical alignment; said passages adapted for receiving therethrough respective ends of uprights of adjacent panels of said temporary fence; said ends passing through both said superposed insert portion and said base portion. | 2008-10-02 |
20080237561 | HINGELESS FENCE - A hingeless fence assembly is described as having a free-standing post and a tubular member. The free-standing post extends upwardly from a hole in the ground and is positioned within the ground to a depth sufficient to provide the necessary stability. The tubular member is rotatably received over the free-standing post and has a greater diameter than the free-standing post. The tubular member is free to rotate about the free-standing post. | 2008-10-02 |
20080237562 | PHASE CHANGE MEMORY DEVICES AND FABRICATION METHODS THEREOF - Phase change memory devices and fabrication methods thereof. A phase change memory device comprises a stacked heating element with a conductive portion and a relatively high resistive portion, wherein the relatively high resistive portion includes a nitrogen-containing metal silicide part. The heating stacked element such as a highly resistive nitrogen-containing metal silicide (MSi | 2008-10-02 |
20080237563 | Diode/superionic conductor/polymer memory structure - A conjugated polymer layer with a built-in diode is formed by providing a first metal-chalcogenide layer over a bottom electrode. Subsequently, a second metal-chalcogenide layer is provided over and in contact with the first metal-chalcogenide layer. The first metal-chalcogenide layer has a first conductivity type and the second metal-chalcogenide layer has a second conductivity type. The plane of contact between the first and second metal-chalcogenide layers creates the p-n junction of the built-in diode. Then a polymer layer is selectively deposited on the second metal-chalcogenide layer. The second metal-chalcogenide layer provides ions to the polymer layer to change its resistivity. A top electrode is then provided over the polymer layer. An exemplary memory cell may have the following stacked structure: first electrode/n-type semiconductor/p-type semiconductor/conjugated polymer/second electrode. | 2008-10-02 |
20080237564 | Phase-Change Memory Device Using Sb-Se Metal Alloy and Method of Fabricating the Same - Provided are a phase-change memory device using a phase-change material having a low melting point and a high crystallization speed, and a method of fabricating the same. The phase-change memory device includes an antimony (Sb)-selenium (Se) chalcogenide Sb | 2008-10-02 |
20080237565 | PHASE CHANGE MEMORY DEVICE TO PREVENT THERMAL CROSS-TALK AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device for preventing thermal cross-talk includes lower electrodes respectively formed in a plurality of phase change cell regions of a semiconductor substrate. A first insulation layer is formed on the semiconductor substrate including the lower electrodes having holes for exposing the respective lower electrodes. Heaters are formed on the surfaces of the respective holes to contact the lower electrodes. A second insulation layer is formed to fill the holes in which the heaters are formed. A mask pattern is then formed on the first and second insulation layers, including the heaters, to have openings that expose portions of the respective heaters having a constant pitch. A phase change layer is formed on the mask pattern including the exposed portions of the heaters and the first and second insulation layers and subsequently, upper electrodes are formed on the phase change layer. | 2008-10-02 |
20080237566 | Phase change memory device and method of fabricating the same - A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second electrode may be spaced apart from the first electrode. A third electrode may be formed corresponding to the first electrode. A fourth electrode may be formed corresponding to the second electrode. A first phase change pattern may be interposed between the first surface and the third electrode. A second phase change pattern may be interposed between the second surface and the fourth electrode. Upper surfaces of the first and second phase change patterns may be on the same plane | 2008-10-02 |
20080237567 | OPTIMIZED SOLID ELECTROLYTE FOR PROGRAMMABLE METALLIZATION CELL DEVICES AND STRUCTURES - A microelectronic programmable structure suitable for storing information and array including the structure and methods of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure. | 2008-10-02 |
20080237568 | Methods of making nano-scale structures having controlled size, nanowire structures and methods of making the nanowire structures - Methods of making nanometer-scale semiconductor structures with controlled size are disclosed. Semiconductor structures that include one or more nanowires are also disclosed. The nanowires can include a passivation layer or have a hollow tube structure. | 2008-10-02 |
20080237569 | SEMICONDUCTOR LIGHT EMITTING ELEMENT, METHOD FOR MANUFACTURING THE SAME, AND LIGHT EMITTING DEVICE - The present invention provides a semiconductor light emitting element with excellent color rendering properties, a method for manufacturing the semiconductor light emitting element, and a light emitting device. The semiconductor light emitting element includes: a semiconductor substrate that has a convex portion having a tilted surface as an upper face, and a concave portion formed on either side of the convex portion, the concave portion having a smaller width than the convex portion, a bottom face of the concave portion being located in a deeper position than the upper face of the convex portion; and a light emitting layer that is made of a nitride-based semiconductor and is formed on the semiconductor substrate so as to cover at least the convex portion. | 2008-10-02 |
20080237570 | LIGHT EMITTING DIODE HAVING WELL AND/OR BARRIER LAYERS WITH SUPERLATTICE STRUCTURE - A light emitting diode (LED) having well and/or barrier layers with a superlattice structure is disclosed. An LED has an active region between an N-type GaN-based semiconductor compound layer and a P-type GaN-based semiconductor compound layer, wherein the active region comprises well and/or barrier layers with a superlattice structure. As the well and/or barrier layers with a superlattice structure are employed, it is possible to reduce occurrence of defects caused by lattice mismatch between the well layer and the barrier layer. | 2008-10-02 |
20080237571 | Semiconductor light emitting device and nitride semiconductor light emitting device - The present invention is a semiconductor light emitting device including an n-type semiconductor layer, an active layer, a first p-type semiconductor layer between the n-type semiconductor layer and the active layer, and a second p-type semiconductor layer on the opposite side of the first p-type semiconductor layer from the active layer. Further, the present invention is a nitride semiconductor light emitting device including an n-type nitride semiconductor layer, a nitride semiconductor active layer, a first p-type nitride semiconductor layer between the n-type nitride semiconductor layer and the nitride semiconductor active layer, and a second p-type nitride semiconductor layer on the opposite side of the first p-type nitride semiconductor layer from the nitride semiconductor active layer. | 2008-10-02 |
20080237572 | FORMING A TYPE I HETEROSTRUCTURE IN A GROUP IV SEMICONDUCTOR - In one embodiment, the present invention includes a method for forming a transistor that includes forming a first buffer layer of silicon germanium tin (SiGe(Sn)) on a silicon (Si) substrate, forming a barrier layer on the first buffer layer, the barrier layer comprising silicon germanium (Si | 2008-10-02 |
20080237573 | Mechanism for forming a remote delta doping layer of a quantum well structure - A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well. | 2008-10-02 |
20080237574 | Metal-Base Nanowire Transistor - A metal-base transistor is suggested. The transistor comprises a first and a second electrode ( | 2008-10-02 |
20080237575 | Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications - A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region. | 2008-10-02 |
20080237576 | Voltage Controlled Computing Element for Quantum Computer - A computing element for use in a quantum computer has at least three coupled quantum dots, and at least one gate for applying an electric field to manipulate the state of said qubit. | 2008-10-02 |
20080237577 | Forming a non-planar transistor having a quantum well channel - In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed. | 2008-10-02 |
20080237578 | ULTRAHIGH DENSITY PATTERNING OF CONDUCTING MEDIA - A nanoscale device and a method for creating and erasing of nanoscale conducting regions at the interface between two insulating oxides SrTiO | 2008-10-02 |
20080237579 | QUANTUM COMPUTING DEVICE AND METHOD INCLUDING QUBIT ARRAYS OF ENTANGLED STATES USING NEGATIVE REFRACTIVE INDEX LENSES - A quantum computing device and method employs qubit arrays of entangled states using negative refractive index lenses. A qubit includes a pair of neutral atoms separated by or disposed on opposite sides of a negative refractive index lens. The neutral atoms and negative refractive index lens are selectively energized and/or activated to cause entanglement of states of the atoms. The quantum computing device enjoys a novel architecture that is workable and scalable in terms of size and wavelength. | 2008-10-02 |
20080237580 | Organic Semiconductor Element and Organic El Display Device Using the Same - It is provided an organic semiconductor element having an FET which can control a channel length to a small value and does not cause a rise in contact resistance due to a step portion, and an organic light emitting display device with a large aperture using the same. A first conductive layer ( | 2008-10-02 |
20080237581 | DEVICE WITH PHASE-SEPARATED DIELECTRIC STRUCTURE - An electronic device including in any sequence: (a) a semiconductor layer; and (b) a phase-separated dielectric structure comprising a lower-k dielectric polymer and a higher-k dielectric polymer, wherein the lower-k dielectric polymer is in a higher concentration than the higher-k dielectric polymer in a region of the dielectric structure closest to the semiconductor layer. | 2008-10-02 |
20080237582 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURE THEREOF - A method for a thin film transistor array panel includes forming a gate line and a pixel electrode on a substrate, forming a gate insulating layer covering the gate line, forming a data line including a source electrode and a drain electrode on the gate insulating layer, forming an interlayer insulating layer covering the data line and the drain electrode on the gate insulating layer, forming a first opening in the interlayer insulating layer, forming an organic semiconductor in the first opening, forming a passivation layer on the organic semiconductor and the interlayer insulating layer, and forming a second opening in the interlayer insulating layer to expose the pixel electrode. | 2008-10-02 |
20080237583 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, SEMICONDUCTOR CIRCUIT, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC APPARATUS - A method for manufacturing a semiconductor device includes: forming a source electrode and a drain electrode on a substrate; forming an organic semiconductor layer including a π conjugated organic compound at least between the source electrode and the drain electrode; applying an application liquid on the organic semiconductor layer, the application liquid being made of a polymer of an alicyclic compound dissolved in a paraffin hydrocarbon solvent that is a carbocyclic compound without having aromaticity; forming a gate insulation layer including the polymer of the alicyclic compound by removing the paraffin hydrocarbon solvent from the application liquid; and forming a gate electrode on the gate insulation layer. | 2008-10-02 |
20080237584 | Organic Component and Electric Circuit Comprising Said Component - The invention relates to an organic component and an electric circuit containing at least one organic component of this type, comprising the following layers:
| 2008-10-02 |
20080237585 | Flat panel display device and method of fabricating the same - A flat panel display device including a first region having an organic light emitting diode and a thin film transistor and a second region having a capacitor is disclosed. The capacitor comprises first, second, and third electrodes, where the area of a third capacitor electrode is reduced, thereby ensuring a distance between a first power voltage line and the third capacitor electrode. The total area of the capacitor is compensated by increasing the area of the first capacitor electrode. Thus, the area of the third capacitor electrode is reduced while the total capacitance of the capacitor is maintained, thereby preventing a dark spot caused by a short circuit between the first power voltage line and the third capacitor electrode. | 2008-10-02 |
20080237586 | Semiconductor Integrated Test Structures For Electron Beam Inspection of Semiconductor Wafers - Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features. | 2008-10-02 |
20080237587 | Method and circuit for stressing upper level interconnects in semiconductor devices - A device or method for effectively stressing an interconnect in a test current path of a semiconductor device, which test current path is other than a current path used during normal operation of the semiconductor device. An operational voltage is adjusted to a test voltage, the test current path is opened and the test voltage is supplied to the test current path. | 2008-10-02 |
20080237588 | METHOD AND SEMICONDUCTOR STRUCTURE FOR MONITORING ETCH CHARACTERISTICS DURING FABRICATION OF VIAS OF INTERCONNECT STRUCTURES - By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective openings may be used for generating a corresponding variation of electrical characteristics of the test metal region. Consequently, by means of the electrical characteristics, respective variations of the etch process may be identified. | 2008-10-02 |
20080237589 | Semiconductor device comprising circuit substrate with inspection connection pads and manufacturing method thereof - A semiconductor device includes a first circuit substrate having a plurality of lower wiring lines and a plurality of upper wiring lines on the lower surface side and upper surface side thereof, respectively. A second circuit substrate is provided on a lower side of the first circuit substrate, the second circuit substrate having an opening which exposes part of the first circuit substrate, the second circuit substrate also having, on the lower surface side thereof, a plurality of external-connection connection pads and a plurality of test connection pads connected to the lower wiring lines. A first semiconductor construct is disposed on the lower side of the first circuit substrate within the opening of the second circuit substrate, the first semiconductor construct having a plurality of external connection electrodes connected to the lower wiring lines. A third circuit substrate and/or an electronic component is provided on an upper side of the first circuit substrate and connected to the upper wiring lines. | 2008-10-02 |
20080237590 | DESIGN STRUCTURE FOR ELECTRICALLY TUNABLE RESISTOR - A design structure for an electrically tunable resistor. In one embodiment, the design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and includes a resistor including: a first resistive layer; at least one second resistive layer; and an intermediate interdiffused layer of the first resistive layer and the at least one second resistive layer. | 2008-10-02 |
20080237591 | Vertical system integration - The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs. | 2008-10-02 |
20080237592 | Semiconductor device and its test method - A second semiconductor chip including the operation of receiving operation instructions given from a first semiconductor chip and outputting a signal corresponding to it is mounted on mounting means. Internal wirings for interconnecting the first and second semiconductor chips, and external terminals respectively connected to the internal wirings are provided in the mounting means to constitute a multi chip module. Further, a signal path for selectively invalidating operation instructions from the first semiconductor chip to the second semiconductor chip is provided inside the module. | 2008-10-02 |
20080237593 | Semiconductor Device, Method of Fabricating the Same, and Apparatus for Fabricating the Same - There is provided a semiconductor device including a substrate and a semiconductor film deposited on the substrate, characterized in that the semiconductor film has a laterally grown crystal having an end with a surface projection height smaller than the thickness of the semiconductor film. There are also provided a semiconductor device fabrication method and apparatus utilizing a method and apparatus for fabricating the semiconductor device, that is capable of reducing a surface projection height or a ridge formed in a last region in repeating laser exposure in the SLS method, and a semiconductor device fabricated thereby. | 2008-10-02 |
20080237594 | PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a pixel structure is provided. A first patterned conductive layer including a gate and a data line is formed on a substrate. A gate insulating layer is formed to cover the first patterned conductive layer and a semiconductor channel layer is formed on the gate insulating layer above the gate. A second patterned conductive layer including a scan line, a common line, a source and a drain is formed on the gate insulating layer and the semiconductor channel layer. The scan line is connected to the gate and the common line is located above the data line. The source and drain are located on the semiconductor channel layer, and the source is connected to the data line. A passivation layer is formed on the substrate to cover the second patterned conductive layer. A pixel electrode connected to the drain is formed on the passivation layer. | 2008-10-02 |
20080237595 | THIN FILM TRANSISTOR INCLUDING TITANIUM OXIDES AS ACTIVE LAYER AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a method of manufacturing a thin film transistor including titanium oxides as an active layer and the structure of the thin film transistor film manufactured using the method. The thin film transistor includes: a substrate; an active layer formed on the substrate using polycrystalline or amorphous titanium oxides; and an insulating layer formed on the active layer. Further, the method of manufacturing the thin film transistor includes: forming a substrate; forming an active layer on the substrate using polycrystalline or amorphous titanium oxides; and forming an insulating layer on the active layer. The present invention is advantageous in that the performance of the thin film transistor can be improved, the thin film transistor can be manufactured at low cost, harmful environmental problems can be solved, and the thin film transistor can be widely applied to various electronic apparatuses including, but not limited to, integrated drivers in active-matrix displays and transparent electronic devices. | 2008-10-02 |
20080237596 | Liquid crystal display device and fabrication method thereof - A liquid crystal display (LCD) includes: a first substrate divided into a pixel part and first and second pad parts; a gate electrode and a gate line formed at the pixel part of the first substrate; an active pattern formed as an island on the gate electrode and having a width smaller than the gate electrode; an insulation film formed on the first substrate and having first and second contact holes exposing source and drain regions of the active pattern, respectively; source and drain electrodes formed at the pixel part of the first substrate and electrically connected with the source and drain regions of the active pattern via the first and second contact holes; a data line formed at the pixel part of the first substrate and crossing the gate line to define a pixel region; an etch stopper positioned between the source and drain electrodes and formed as an insulation film; a pixel electrode electrically connected with the drain electrode; and a second substrate attached with the first substrate in a facing manner. | 2008-10-02 |
20080237597 | THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively; first and second source members connected to each other and located near the first and the second semiconductor members, respectively; first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members with respect to the first and the second gate members, respectively; and a pixel electrode connected to the first and the second drain members. The first gate, semiconductor, source, and drain members form a first TFT, and the second gate, semiconductor, source, and drain members form a second TFT. | 2008-10-02 |
20080237598 | THIN FILM FIELD EFFECT TRANSISTOR AND DISPLAY - A thin film field effect transistor including, on a substrate, at least a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode, wherein an electric resistance layer is provided in electric connection between the active layer and at least one of the source electrode or the drain electrode. | 2008-10-02 |
20080237599 | MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT - A rewritable nonvolatile memory cell is disclosed comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels. | 2008-10-02 |
20080237600 | Thin film transistor - One embodiment of the present invention is a thin film transistor, including: an insulating substrate; a gate electrode, a gate insulating layer and a semiconductor layer including an oxide, these three elements being formed over the insulating substrate in this order, and the gate insulating layer including: a lower gate insulating layer, the lower gate insulating layer being in contact with the insulating substrate and being an oxide including any one of the elements In, Zn or Ga; and an upper gate insulating layer provided on the lower gate insulating layer, the upper gate insulating layer comprising at least one layer; and a source electrode and a drain electrode formed on the semiconductor layer. | 2008-10-02 |
20080237601 | TRANSISTORS AND SEMICONDUCTOR CONSTRUCTIONS - A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer. | 2008-10-02 |
20080237602 | THREE DIMENSIONAL NAND MEMORY - A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell. | 2008-10-02 |
20080237603 | METHOD OF FORMING CMOS TRANSISTORS WITH DUAL-METAL SILICIDE FORMED THROUGH THE CONTACT OPENINGS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include amorphizing at least one contact area of a source/drain region of a transistor structure by implanting through at least one contact opening, forming a first layer of metal on the at least one contact area, forming a second layer of metal on the first layer of metal, selectively etching a portion of the second metal layer, and annealing the at least one contact area to form at least one silicide. | 2008-10-02 |
20080237604 | PLASMA NITRIDED GATE OXIDE, HIGH-K METAL GATE BASED CMOS DEVICE - In accordance with the invention, there are CMOS devices and semiconductor devices and methods of fabricating them. The CMOS device can include a substrate including a first active region and a second active region and a first transistor device over the first active region, wherein the first transistor device includes a high-K layer over the first active region, a first dielectric capping layer on the high-K layer, and a first metal gate layer over the first dielectric capping layer. The CMOS device can also include a second transistor device over the second active region, wherein the second transistor device includes a high-K layer over the second active region, a second dielectric capping layer on the second high-K layer, and a second metal gate layer over the second dielectric capping layer. | 2008-10-02 |
20080237605 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes: a first semiconductor layer which is made of a first group III nitride semiconductor; a cap layer which is formed on the first semiconductor layer, which is made of a second group III nitride semiconductor, and which has an opening for exposing the first semiconductor layer; and a source electrode and a drain electrode which are formed on the cap layer so as to oppose to each other with the opening interposed. A gate electrode is formed on the bottom face of the opening with an insulating film interposed. The insulating film is formed on at least a part of the first semiconductor layer which is exposed through the opening. | 2008-10-02 |
20080237606 | COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device having a transistor structure, includes a substrate, a first layer formed on the substrate and comprising GaN, a second layer formed over the first layer and containing InN whose lattice constant is larger than the first layer, a third layer formed over the second layer and comprising GaN whose energy bandgap is smaller than the second layer, and a channel region layer formed on the third layer. | 2008-10-02 |
20080237607 | LIGHT EMITTING ELEMENT AND METHOD OF MAKING SAME - A light emitting element has a substrate of gallium oxides and a pn-junction formed on the substrate. The substrate is of gallium oxides represented by: (Al | 2008-10-02 |
20080237608 | Molybdenum barrier metal for SiC Schottky diode and process of manufacture - A method for fabricating a diode is disclosed. In one embodiment, the method includes forming a Schottky contact on an epitaxial layer of silicon carbide (SiC) and annealing the Schottky contact at a temperature in the range of 300° C. to 700° C. The Schottky contact is formed of a layer of molybdenum. | 2008-10-02 |
20080237609 | Low Micropipe 100 mm Silicon Carbide Wafer - A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 100 mm and a micropipe density of less than about 25 cm | 2008-10-02 |
20080237610 | COMPOUND SEMICONDUCTOR DEVICE INCLUDING AIN LAYER OF CONTROLLED SKEWNESS - A semiconductor epitaxial substrate includes: a single crystal substrate; an AlN layer epitaxially grown on the single crystal substrate; and a nitride semiconductor layer epitaxially grown on the AN layer, wherein an interface between the AlN layer and nitride semiconductor layer has a larger roughness than an interface between the single crystal substrate and AlN layer, and a skewness of the upper surface of the AlN layer is positive. | 2008-10-02 |
20080237611 | ELECTROLUMINESCENT DEVICE HAVING IMPROVED CONTRAST - A method for increasing ambient light contrast ratio within an electroluminescent device, including: a reflective electrode and a transparent electrode having an EL unit formed there-between. The EL unit includes a light-emitting layer containing quantum dots. Additionally, the method includes locating a contrast enhancement element on a side of the transparent electrode opposite the EL unit. The contrast enhancement element includes a patterned reflective layer and a patterned light-absorbing layer whose patterns define one or more transparent openings, so that light emitted by the light-emitting layer passes through the one or more transparent openings. The patterned reflective layer is located between the patterned light absorbing layer and the transparent electrode. | 2008-10-02 |
20080237612 | DEVICE HAVING SPACERS - An electroluminescent device comprising: a substrate; one or more light-emitting elements formed over the substrate, the one or more light-emitting elements including first and second spaced-apart electrodes wherein at least one of the first and second electrodes is transparent and a light-emitting layer comprising quantum dots formed between the first and second electrodes; a cover located over the one or more light-emitting elements and spaced apart from the one or more light-emitting elements to form a gap between the cover and the one or more light-emitting elements; and separately formed spacer elements located in the gap between the cover and the one or more light-emitting elements and wherein the spacer elements are in physical contact with the one or more light-emitting elements, the cover, or both the one or more light-emitting elements and the cover. | 2008-10-02 |
20080237613 | Ac Light Emitting Device Having Photonic Crystal Structure and Method of Fabricating the Same - Disclosed is an AC light emitting device having photonic crystal structures and a method of fabricating the same. The light emitting device includes a plurality of light emitting cells and metallic wirings electrically connecting the light emitting cells with one another. Further, each of the light emitting cells includes a first conductive type semiconductor layer, a second conductive type semiconductor layer disposed on one region of the first conductive type semiconductor layer, and an active layer interposed between the first and second conductive type semiconductor layers. In addition, a photonic crystal structure is formed in the second conductive type semiconductor layer. The photonic crystal structure prevents light emitted from the active layer from laterally propagating by means of a periodic array, such that light extraction efficiency of the light emitting device can be improved. Furthermore, the metallic wirings electrically connect a plurality of light emitting cells with one another such that an AC light emitting device can be provided. | 2008-10-02 |
20080237614 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - A semiconductor light-emitting device of the present invention includes a first LED chip whose emitted light is wavelength-converted by a fluorescent substance layer formed by applying and curing a fluorescent substance material, and a second LED chip whose emitted light is not wavelength-converted by the fluorescent substance layer, wherein the first LED chip and the second LED chip are arranged on a substrate in such a way that a level of an emission layer of the second LED chip is higher than that of a top face of the first LED chip above the substrate. | 2008-10-02 |
20080237615 | LIGHT-EMITTING DEVICE - A light-emitting device including: a substrate; a light-emitting diode; and an optical resonance layer to resonate light emitted from the light-emitting diode. The optical resonance layer includes a first layer, including a polysilsesquioxane-based copolymer. A linking group connecting two different silicon (Si) atoms of the polysilsesquioxane-based copolymer can be —O—, or a substituted or unsubstituted C | 2008-10-02 |
20080237616 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light emitting device, includes an active layer radiating a light having a predetermined wavelength; a first semiconductor layer of a first conductivity type, provided on the active layer. A semiconductor substrate has a first principal surface in contact with the active layer, a second principal surface facing the first principal surface, and side surfaces connected to the second principal surface. Each of the side surfaces has a bevel angle in a range from about 45 degrees to less than 90 degrees with respect to the second principal surface. A second semiconductor layer of a second conductivity type is provided under the active layer. A first electrode is provided under the second semiconductor layer. A distance between the active layer and the first electrode depends on the wavelength and a refractive index of the second semiconductor layer. | 2008-10-02 |
20080237617 | Adhesive Sheet for Light-Emitting Diode Device and Light-Emitting Diode Device - [Problem] To provide an adhesive sheet which is used for a light-emitting diode device, and which is free from cracks and peeling off of the adhered portions. [Means for Solving the Problem] An adhesive sheet for a light-emitting diode device, which comprises a thermoplastic polymer containing epoxy groups and a compound containing functional groups which are addition reactive with the epoxy groups or a polymerization catalyst which can effect a ring opening polymerization of the epoxy groups, and in which said thermoplastic polymer is cross-linked so that its flowability is restrained. | 2008-10-02 |
20080237618 | LIGHT EMITTING DIODE MODULE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) module. The LED module includes: an LED chip, for emitting a light beam; a packaging structure, for packaging the LED chip; and a light direction changing unit, connected to the packaging structure, for changing a direction of the light beam, wherein the light direction changing unit has a base material and at least a photoluminescent material, and the photoluminescent material is mixed within the base material to form the light direction changing unit. | 2008-10-02 |
20080237619 | LED with Porous Diffusing Reflector - In one embodiment, an AlInGaP LED includes a bottom n-type layer, an active layer, a top p-type layer, and a thick n-type GaP layer over the top p-type layer. The thick n-type GaP layer is then subjected to an electrochemical etch process that causes the n-type GaP layer to become porous and light-diffusing. Electrical contact is made to the p-GaP layer under the porous n-GaP layer by providing metal-filled vias through the porous layer, or electrical contact is made through non-porous regions of the GaP layer between porous regions. The LED chip may be mounted on a submount with the porous n-GaP layer facing the submount surface. The pores and metal layer reflect and diffuse the light, which greatly increases the light output of the LED. Other embodiments of the LED structure are described. | 2008-10-02 |
20080237620 | LIGHT EMITTING DIODE APPARATUS - A light emitting diode apparatus includes a heat dissipating substrate, a composite layer, an epitaxial layer, a first electrode and a second electrode. The composite layer includes a reflective layer, a transparent conductive layer and a patterned insulating thermoconductive layer, which is disposed between the reflective layer and the transparent conductive layer. The composite layer is disposed between the heat dissipating substrate and the epitaxial layer and allows currents to concentrate to the reflective layer or the transparent conductive layer and then to be diffused evenly through the transparent conductive layer. The epitaxial layer includes a first semiconductor layer electrically connected with the first electrode, an active layer and a second semiconductor layer electrically connected with the second electrode. | 2008-10-02 |
20080237621 | LIGHT EMITTING DEVICE AND METHOD OF PRODUCING THE SAME - To provide a light emitting device that is improved in intensity of light emitted from a light outgoing surface and has excellent heat releasing property, the light emitting device according to the present invention includes an LED chip | 2008-10-02 |
20080237622 | Light emitting device and package having the same - There is provided a light emitting device that can minimize reflection or absorption of emitted light, maximize luminous efficiency with the maximum light emitting area, enable uniform current spreading with a small area electrode, and enable mass production at low cost with high reliability and high quality. A light emitting device according to an aspect of the invention includes a light emitting lamination including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer, and a conductive substrate at one surface thereof. Here, the light emitting device includes a barrier unit separating the light emitting lamination into a plurality of light emitting regions, a first electrode structure, and a second electrode structure. The first electrode structure includes a bonding unit, contact holes, and a wiring unit connecting the bonding unit to the contact holes. | 2008-10-02 |
20080237623 | LIGHT EMITTING DEVICE - A light emitting device includes a pair of electrodes, wherein at least one electrode is transparent or semi-transparent, and an phosphor layer provided between the pair of electrodes, wherein the phosphor layer includes a layer having nitride semiconductor particles, and wherein the nitride semiconductor particles have metal nano structures precipitated in grain boundaries between the nitride semiconductor particles. | 2008-10-02 |
20080237624 | LED PACKAGE WITH METAL PCB - The present invention relates to a light emitting diode (LED) package. An object of the present invention is to provide an LED package having a metal PCB, which has a superior heat dissipation property and a compact structure, does not largely restrict use of conventional equipments, and is compatible with an electronic device or illumination device currently used widely. | 2008-10-02 |
20080237625 | LIGHT EMITTING DIODE LAMP WITH LOW THERMAL RESISTANCE - Disclosed is a light emitting diode lamp that has low resistance to heat emitted therefrom. The LED lamp may include a heat coupling member thermally coupling a top part of a first lead to a top part of a second lead. The LED lamp may further include one or more top parts for lowering thermal resistance of the LED lamp. This configuration facilitates heat transfer from the first lead having an LED chip mounted thereon to the top part of the second lead and/or to the other top parts, lowering resistance to heat emitted from the LED lamp. | 2008-10-02 |
20080237626 | LED chip packaging structure - An improved LED chip packaging structure includes a substrate, an insulating layer, a light emitting chip and sealing adhesive. At least two conductive traces are disposed on at least one side surface of the substrate. The insulating layer attaches on one side surface of the substrate and includes an insulating film. The light emitting chip is received in the through hole of the insulating layer and attaches on one side surface of the substrate. An adhesive is securing the light emitting chip on the substrate, and the light emitting chip connects with at least one conducting wire. The sealing adhesive is filled into the through hole of the insulating layer. By the direct combination of the light emitting chip and the substrate, the present invention has the advantageous of low cost, the heat dispersal effect is improved, the packaging efficiency is increased, and the market competition is enhanced. | 2008-10-02 |
20080237627 | Semiconductor light-emitting device - A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region. | 2008-10-02 |
20080237628 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD - A light emitting device of the invention includes an electron transporting layer, a hole transporting layer provided mutually facing the electron transporting layer with a distance between the hole transporting layer and the electron transporting layer, a phosphor layer having a layer of a plurality of semiconductor fine particles sandwiched between the electron transporting layer and the hole transporting layer, a first electrode provided facing the electron transporting layer and connected electrically, and a second electrode provided facing the hole transporting layer and connected electrically: in which the semiconductor fine particles composing the phosphor layer have a p-type part and an n-type part inside of the particles and have a pn-junction in the interface of the p-type part and the n-type part and are arranged in a manner that the p type part is partially brought into contact with the hole transporting layer and at the same time, the n type part is partially brought into contact with the electron transporting layer. | 2008-10-02 |
20080237629 | Group III-V Semiconductor device and method for producing the same - A Group III-V semiconductor device bonded to a conductive support substrate, which device has a side surface whose surface layer has a high-resistance region formed through ion implantation. | 2008-10-02 |
20080237630 | Semiconductor switch - A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor. | 2008-10-02 |
20080237631 | HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME - In a high breakdown voltage semiconductor element among elements integrated together on an SOI substrate in which its rated voltage is shared between an embedded oxide layer and a drain region formed by an element active layer, both high integration and high breakdown voltage are realized while also securing suitability for practical implementation and practical use. The high breakdown voltage is realized without hampering size reduction of the element by forming an electrically floating layer of a conductivity type opposite to that of the drain region at the surface of the drain region. Further, the thickness of the embedded oxide layer is reduced to a level suitable for the practical implementation and practical use by setting the thickness of the element active layer of the SOI substrate at 30 μm or more. | 2008-10-02 |
20080237632 | III-nitride power semiconductor device - A III-nitride power semiconductor device that includes a first III-nitride power semiconductor device and a second III-nitride power semiconductor device formed in a common semiconductor die and operatively integrated to form a half-bridge. | 2008-10-02 |
20080237633 | Radiation Detector - The invention specifies a radiation detector for detecting radiation ( | 2008-10-02 |
20080237634 | CRYSTALLOGRAPHIC RECESS ETCH FOR EMBEDDED SEMICONDUCTOR REGION - Source and drain regions of an FET are etched by a crystallographic anisotropic etch to form a cavity surrounded by crystallographic facets. The exposure of the sidewalls of shallow trench isolation (STI) is avoided or reduced compared to the prior art. The crystallographic anisotropic etch may be combined with an isotropic etch or a recess etch to create undercuts beneath gate spacers and/or a pegging line beneath a top surface of the STI. The at least one cavity is then filled with a lattice-mismatched embedded material so that stress is applied to the channel of the FET. The resulting structure has increased containment of the embedded semiconductor region by shallow trench isolation. A reduction in stress due to the unconstrained sidewall area and an increase in the junction current due to the recessing of the pegging line are eliminated or alleviated. | 2008-10-02 |
20080237635 | STRUCTURE AND METHOD FOR STRAINED TRANSISTOR DIRECTLY ON INSULATOR - A semiconductor device ( | 2008-10-02 |
20080237636 | Transistor having tensile strained channel and system including same - A transistor structure and a system including the transistor structure. The transistor structure comprises: a substrate including a first layer comprising a first crystalline material; a tensile strained channel formed on a surface of the first layer and comprising a second crystalline material having a lattice spacing that is smaller than a lattice spacing of the first crystalline material; a metal gate on the substrate; a pair of sidewall spacers on opposite sides of the metal gate; and a source region and a drain region on opposite sides of the metal gate adjacent a corresponding one of the sidewall spacers. | 2008-10-02 |
20080237637 | ULTRA SCALABLE HIGH SPEED HETEROJUNCTION VERTICAL n-CHANNEL MISFETS AND METHODS THEREOF - A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials. | 2008-10-02 |
20080237638 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate common to a first field effect transistor and a second field effect transistor, a channel layer of a first conductivity type formed on the substrate and common to the first and second field effect transistors, a an upper compound semiconductor layer formed on the channel layer and common to the first and second field effect transistors, a compound semiconductor region of a second conductivity type formed in the same layer as the upper compound semiconductor layer, a gate electrode of the first field effect transistor in ohmic contact with the compound semiconductor region, and a gate electrode of the second field effect transistor in Schottky contact with the upper compound semiconductor layer. | 2008-10-02 |
20080237639 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. | 2008-10-02 |
20080237640 | N-FACE HIGH ELECTRON MOBILITY TRANSISTORS WITH LOW BUFFER LEAKAGE AND LOW PARASITIC RESISTANCE - A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed. | 2008-10-02 |
20080237641 | Surrounded-Channel Transistors with Directionally Etched Gate or Insulator Formation Regions - An elongate stacked semiconductor structure is formed on a substrate. The stacked semiconductor structure includes a second semiconductor material region disposed on a first semiconductor material region. The first semiconductor material region is selectively doped to produce spaced-apart impurity-doped first semiconductor material regions and a lower dopant concentration first semiconductor material region therebetween. Etching exposes a portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. The etching removes at least a portion of the lower dopant concentration first semiconductor material region to form a hollow between the substrate and the portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. An insulation layer that surrounds the exposed portion of the second semiconductor material region between the impurity-doped first semiconductor material regions is formed. The hollow may be filled with a gate electrode that completely surrounds the exposed portion of the second semiconductor material region, or the gate electrode may partially surround the exposed portion of the second semiconductor material region and an insulation region may be formed in the hollow. | 2008-10-02 |
20080237642 | Method to Reduce Boron Penetration in a SiGe Bipolar Device - The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer. | 2008-10-02 |
20080237643 | TRANSISTOR - A heterojunction bipolar transistor comprising
| 2008-10-02 |