40th week of 2008 patent applcation highlights part 40 |
Patent application number | Title | Published |
20080239747 | LINE ILLUMINATION DEVICE AND IMAGE INPUT APPARATUS USING THE SAME - A line illumination device includes: a frame; a rod-shaped light-guiding member housed in the frame; a flexible substrate; and a light source that is provided on the flexible substrate and emits light to the light-guiding member. The flexible substrate is bent so that the light source is disposed at an end of the light-guiding member and that the flexible substrate is housed in the frame. Power is supplied to the light source through a wiring provided on the flexible substrate so that the light source emits light and the light-guiding member emits light in line-shape. | 2008-10-02 |
20080239748 | Illumination device, in particular for vehicles - The invention relates to an illumination device, in particular for vehicles. The illumination device comprises at least two semiconductor light sources which emit light with different colours, as well as at least one light guide into which the light from the semiconductor light sources is injected, and a light mixer device that is arranged on the entry side of the light guide and has a transparent light-refracting element, by which the spatial distribution of the light from the light sources is mixed so as to generate light that constitutes a colour superposition of the light from the semiconductor light sources. The transparent light-refracting element comprises an end face which forms a light entry face for the light emitted by the semiconductor light sources, the semiconductor light sources being arranged next to one another and in front of the light entry face. | 2008-10-02 |
20080239749 | LUMINAIRE HAVING A TWO-WAY WAVEGUIDE - A luminaire includes a waveguide having first and second opposing ends and first and second opposing sides between the first and second ends. The waveguide is configured to totally internally reflect light propagating through the waveguide in a first direction and direct light propagating through the waveguide in a second direction through at least one of the first and second sides. A reflective body is coupled to the second end of the waveguide and configured to reflect light propagating towards the second end of the waveguide such that the light propagates towards the first end of the waveguide. | 2008-10-02 |
20080239750 | LED LAMP ASSEMBLY - An exemplary LED lamp includes a housing, a printed circuit board, at least one LED, a light reflective module and a lamp cover. The printed circuit board is positioned on a bottom of the housing. The LED electrically connects with the printed circuit board. The light reflective module includes at least one light-shielding sheet and a bottom reflective plate disposed between the printed circuit board and the light-shielding sheet. The bottom reflective plate defines at least one through hole. The LED passes through the at least one through hole correspondingly. Each light-shielding sheet defines a plurality of light holes and covers the LED correspondingly. The lamp cover is fixed on the opening of the housing. The LED lamp has a uniformity brightness. | 2008-10-02 |
20080239751 | LED LAMP ASSEMBLY - An exemplary LED lamp includes a housing having an opening, a printed circuit board, at least one LED, a light reflective plate, a light reflective module and a lamp cover. The printed circuit board is positioned on a bottom of the housing. The LED is electrically connected with the printed circuit board. The light reflective plate defines at least one through hole, the LED passing through the corresponding through hole. The light reflective module includes a bottom reflective plate, at least two opposite reflective sidewalls, at least one light-shielding sheet extending at midsections from the opposing reflective sidewalls. The bottom reflective plate defines at least one first cutout, the at least one LED passing through the corresponding first cutout. The at least one light-shielding sheet defines a plurality of light holes and covers the corresponding LED. The LED lamp assembly has a uniform luminance. | 2008-10-02 |
20080239752 | Light emitting diode having electrodes with branches and backlight module using same - An exemplary light emitting diode ( | 2008-10-02 |
20080239753 | TRANSREFLECTORS, TRANSREFLECTOR SYSTEMS AND DISPLAYS AND METHODS OF MAKING TRANSREFLECTORS - The transreflectors may comprise a transparent substrate having reflective surfaces and other light transmissive surfaces for respectively reflecting and transmitting a greater portion of the light striking opposite sides of the substrate. Alternatively, the transreflectors may comprise two or more transparent substrates of different indices of refraction bonded together, with a pattern of optical deformities in the mating side of one of the substrates and an inverse pattern of optical deformities in the mating side of an other substrate in mating engagement with each other. The transreflectors are used in a transreflector system or display to transmit more of the light emitted by a backlight or other light source incident on one side of the transreflectors and reflect more of the light incident on the opposite side of the transreflectors. The transreflectors and backlight may be tuned to each other to enable the transreflectors to better transmit more of the light emitted by the backlight. | 2008-10-02 |
20080239754 | BACKLIGHT ASSEMBLY, DISPLAY APPARATUS HAVING THE SAME AND METHOD FOR MANUFACTURING THE SAME - A backlight assembly, a display apparatus and a method for manufacturing the backlight assembly. The backlight assembly includes a light-guide plate, a point light source unit, a fixing plate and a cover. The point light source unit includes at least one point light source disposed at a side of the light-guide plate, and a flexible printed circuit board (FPC) disposed under the light-guide plate and having the point light source. The fixing plate is disposed under the FPC and has at least one first combining member. The cover is disposed under the fixing plate and has a first surface on which at least one second combining member is formed. The first and second combining members are combined with each other. Thus, assembling time may be decreased, heat may be efficiently dissipated, and manufacturing costs may be decreased. | 2008-10-02 |
20080239755 | LIGHT REDIRECTING FILMS AND FILM SYSTEMS - Light redirecting films and film systems include a thin optically transparent substrate having a pattern of individual optical elements of well defined shape on or in the substrate. At least some of the optical elements may vary at different locations on the substrate to redistribute or redirect light passing through the substrate. | 2008-10-02 |
20080239756 | Backlight assembly of liquid crystal display - A backlight assembly of an LCD is provided. The backlight assembly includes a lamp for generating a light, a light guide plate disposed at a side of the lamp, for guiding the light, and a diffusion sheet and a prism sheet disposed on the light guide plate, for enhancing efficiency of the light outputted from the light guide plate, wherein the prism sheet comprises a body part and a plurality of protrusion parts each having a concavely inclined surface formed on the body part. | 2008-10-02 |
20080239757 | LIQUD CRYSTAL DSIPLAY DEVICE HAVING A CONTAINER MODULE WITH A NOVEL STRUCTURE - A liquid crystal display has a mold frame divided into several parts. The liquid crystal display device includes a display unit for displaying an image, a back light assembly having a light source for generating a light, a light guiding plate for guiding the light, and a light focusing portion for focusing the light, and a mold frame divided into a first frame and a second frame. The mold frame receives the display unit and the back light assembly. The first frame receives the light guiding plate and the light focusing portion and the second frame receives the light source. A reflection sheet is integrally formed at an inner surface of the second frame so as to perform the function of a lamp reflector. Accordingly, a lamp cover is not required so that the number of parts and the manufacturing cost are reduced. A lamp can be exchanged by simply separating the second frame from the mold frame, so the fault of the light source caused by the friction with other elements is reduced when exchanging the lamp. | 2008-10-02 |
20080239758 | Snap-in lamp for an electric light string - A snap-in lamp for an electric light string includes a lamp base housing a light bulb and a lamp holder. The lamp base is removably and frictionally housed in the lamp holder. The light bulb has a filament that illuminates the light bulb when electrical current passes through the filament. The light bulb filament is connected to a bottom portion of the lamp base by a pair of opposed lead wires. The lamp holder is dimensioned to frictionally receive and removably house the lamp base. The lamp holder includes a metal conductor strap and a non-conductive strap holder that provide a path for the continued flow of current through the lamp even when the lamp base is removed from the lamp holder. The lamp is more useful than conventional lamps by virtue of the ability to preserve the closed circuit even when one or more lamp bases are removed from their respective lamp holders. | 2008-10-02 |
20080239759 | DC/DC CONVERTER - Primary and secondary coils are provided in the first through section and a coil group is also provided in the second through section. Hence, the surface area over which the coil group extends within a plane which is perpendicular to the through sections is greater than in the case where all of the coils are provided in a single through section. The surface area which is not covered by the magnetic body cores of the platelike members increases. In cases where the surface area of the members is large, the heat radiation characteristic is enhanced. Hence, the cooling efficiency of the transformer improves. In cases where there is a plurality of coil groups which are magnetically coupled to one another in particular, because it is difficult to move the heat produced in the plurality of coil groups through heat conduction, heat transfer, or heat radiation, a heat radiation structure of this kind is effective. | 2008-10-02 |
20080239760 | Primary only constant voltage/constant current (CVCC) control in quasi resonant convertor - A power supply apparatus and method of regulating is provided. A converter circuit includes a primary switching element and an auxiliary switching element. The auxiliary switching element is for transferring a reflected voltage signal. A transformer includes a primary and a secondary, the primary is coupled with the converter circuit. The primary and the secondary each comprise a single winding. An output rectifier circuit is coupled with the secondary of the transformer. A resonant circuit is included in the converter circuit and is coupled with the primary. The resonant circuit includes one or more resonance capacitors that are configured for providing a transformer resonance. The transformer resonance comprises the reflected voltage signal, the capacitance of the one or more resonance capacitors and a parasitic capacitance of the transformer. The reflected voltage signal is reflected from the secondary to the primary. A current feedback circuit is coupled between the primary and a controller. A virtual output current feedback loop is provided for regulating an output current using the reflected voltage signal. | 2008-10-02 |
20080239761 | Forward power converter controllers - This invention relates to control techniques and controllers for resonant discontinuous forward power converters (RDFCs). | 2008-10-02 |
20080239762 | Forward power converter controllers - This invention relates to control techniques and controllers for resonant discontinuous forward power converters (RDFCs). | 2008-10-02 |
20080239763 | METHOD AND APPARATUS FOR QUASI-RESONANT CURRENT MODE POWER CONVERSION - A method and apparatus to magnetically couple AC power from the high voltage electric utility power line current induced magnetic field over a wide voltage and current range to provide a low voltage, low current DC power supply useful in powering other remotely located or limited accessibility circuitry requiring low voltage DC power to operate. | 2008-10-02 |
20080239764 | Forward power converter controllers - This invention relates to control techniques and controllers for resonant discontinuous forward power converters (RDFCs). | 2008-10-02 |
20080239765 | System and Method for a Bridgeless Power Supply - A system and method for a bridgeless power supply is disclosed. The bridgeless power supply includes a digital control module that controls a first switch, a second switch, and a transistor, thereby the bridgeless power supply rectifies an alternating current (AC) variable input voltage and regulates a direct current (DC) output voltage. The digital control module applies a first and second control signal to the first and second switches thereby rectifying and regulating the AC variable input voltage. Additionally, the digital control module provides a high frequency and constant duty cycle third control signal to the transistor in series with an output transformer of the bridgeless power supply device, to assure primary-to-secondary isolation. | 2008-10-02 |
20080239766 | Control System for a Voltage Converter and Method - A control arrangement ( | 2008-10-02 |
20080239767 | Power supply circuit with pulse generating circuit and current-limiting circuit - An exemplary power supply circuit ( | 2008-10-02 |
20080239768 | DIRECT-CURRENT CONVERTER - A direct-current converter includes a high-frequency converting circuit converting voltage of a direct-current power source to alternating-current voltage, a transformer having primary and secondary windings P, S and a rectification smoothing circuit rectifying and smoothing voltage induced in the secondary winding. This converting circuit includes other transformer having first and second windings n | 2008-10-02 |
20080239769 | DEVICE FOR TRANSFORMING A PRIMARY AC VOLTAGE IN A LOWER AC VOLTAGE FOR SUPPLYING AN ELECTRICAL LOAD - A device for transforming an AC voltage to a lower AC voltage includes a generator of a PWM control signal and a first bidirectional switch to couple a load to the AC voltage during a conduction-phase. A second bidirectional switch discharges energy from the load during an off-phase of the first bidirectional switch. A first driving circuit of the first bidirectional switch is input with the PWM control signal and generates a first PWM signal, applied between control and conduction terminals of the first bidirectional switch. A second driving circuit for the second bidirectional switch is input with the PWM control signal and generates a second PWM signal, in phase opposition to the first PWM signal, applied between control and conduction terminals of the second bidirectional switch. An electric decoupling circuit is between the generator and second driving circuit. A transformer is between respective conduction terminals of the bidirectional switches. | 2008-10-02 |
20080239770 | Active Network Filter - The invention relates to a supply device ( | 2008-10-02 |
20080239771 | Asymmetrical Interleaving Strategy for Multi-Channel Power Converters - In a power converter having m=two or more channels of power factor correction (PFC) circuits connected in parallel and an electromagnetic interference (EMI) filter connected in series therewith, phase shifts in switching between the respective PFC channels can allow increase of EMI filter corner frequency allowing reduction of size and cost of the EMI filter at some switching frequencies. Asymmetrical phase shifts (other than 360°/m) such as 360°/2m and other phase shifts and variations in m allow increase of EMI filter corner frequency at switching frequencies where symmetrical, 360°/m phase shifts provide no benefit to EMI filter design by providing cancellation or partial cancellation of different harmonics of the switching noise; which cancellation may be arranged to be complementary to the EMI filter function at more than one peak of the noise spectrum. (Such asymmetrical phase shifts do not significantly increase ripple and consequent switching noise). Alteration of m and corresponding alteration of phase shift may be performed adaptively for purposes of improving efficiency at light loads and the like. | 2008-10-02 |
20080239772 | SWITCHED CAPACITOR CONVERTERS - A switched capacitor converter has a supply voltage input, an output circuit with one or more load capacitors, a semiconductor switch network. The switch network is connected at a switch junction point and across the voltage input, and has one or more pairs of said first and second switches. Each pair of switches is associated with one of the load capacitors and each pair is connected in series. The converter also has a charging capacitor network connected across the semiconductor switch network and across the voltage input. The charging capacitor network has one or more charging capacitors and inductances connected between the switch junction point and the output circuit. Each of the charging capacitors and inductances is associated with one of the load capacitors. The load capacitors are each charged by the associated charging capacitor when the associated first switch is closed and the associated second switch is open. And the load capacitors are each discharged by the associated inductance when the associated first switch is closed and the associated second switch is open. | 2008-10-02 |
20080239773 | VOLTAGE CONVERTER CAPABLE OF CORRECTLY ENABLING SECONDARY CONVERTING MODULE COUPLED TO OUTPUT PORT OF VOLTAGE CONVERTER BY UTILIZING SLOPE INDICATION SIGNAL HAVING DIFFERENT PULSE AMPLITUDES REPRESENTATIVE OF DIFFERENT SLOPE VALUES - A method for converting an input voltage signal into an output voltage signal is disclosed. The method includes: providing a primary converting module and coupling the primary converting module to an input port of the voltage converter; providing a secondary converting module having a second electronic induction device and a switch device, coupling the secondary converting module to an output port of the voltage converter, and utilizing the switch device to enable the secondary converting module; measuring a slope of an output at a detection end of the second electronic induction device to generate a slope indication signal having different pulse amplitudes representative of different slope values; and referencing the output at the detection end of the second electronic induction device, the slope indication signal, a first predetermined reference level, and a second predetermined reference level to generate a control signal for controlling an on/off status of the switch device. | 2008-10-02 |
20080239774 | Synchronous rectifier control for synchronous boost converter - A synchronous boost DC/DC conversion system comprises an input for receiving a DC input voltage, an output for producing a DC output voltage, a power switch controllable to adjust an output signal of the conversion system, and an inductor coupled to the input. A synchronous rectifier is configurable to create a conduction path between the inductor and the output to provide the inductor discharge. A control circuit is provided for controlling the synchronous rectifier as the input voltage approaches the output voltage, so as to adjust average impedance of the conduction path over a discharge period of the inductor. | 2008-10-02 |
20080239775 | Power Converter Apparatus and Methods Using Neutral Coupling Circuits with Interleaved Operation - A power converter apparatus, such as an uninterruptible power supply (UPS), includes an inverter having an input coupled to a first DC bus and a second DC bus and configured to generate an AC output with respect to a neutral terminal at a phase output terminal thereof. The apparatus further includes first and second neutral coupling circuits, each configured to selectively couple the first DC bus and the second DC bus to the neutral terminal, and a control circuit configured to cause interleaved operation of the neutral coupling circuits. | 2008-10-02 |
20080239776 | Cooling electronic components - An illustrative embodiment of the invention provides an electronic power inverter for a traction motor and a coolant for the inverter. The power inverter comprises an aluminum component and the coolant is a non-aqueous dielectric liquid coolant composition including an inhibitor. The coolant consists essentially of a mixture of an oligo-(alkyl siloxane), such as hexamethyldisiloxane, and a monomer or oligomer of an alkyl ether alkylene glycol, such as 1-methoxy-2-propanol, and including an azole in an amount for inhibiting dissolution of the aluminum electronic component. | 2008-10-02 |
20080239777 | Apparatus for Converting an Electrical Current and Method for Reducing the Load-Change Stress of Power Semiconductor Units in the High-Voltage Energy Distribution and Transmission Sector - An apparatus for converting an electrical current in a high-voltage energy distribution and transmission system has one or more current converter valves with a series circuit of a plurality of power semiconductor units. A cooler cools the power semiconductor units. Temperature deviations of the power semiconductor units can be decreased in a cost-effective manner in that the cooler is provided with a control unit that provides cooling in dependence on a current flow via the power semiconductor units. | 2008-10-02 |
20080239778 | HYBRID DUAL MATCH LINE ARCHITECTURE FOR CONTENT ADDRESSABLE MEMORIES AND OTHER DATA STRUCTURES - A hybrid dual match line circuit may include a hit match line coupled to a first group of load devices and a miss match line coupled to discharge through a second group of load devices. Both the hit and miss match lines may be configured to be precharged to an asserted state. Each of the second group of load devices may be activated for discharging by a respective miss signal. The hit match line may be additionally coupled to discharge through first and second discharge path respectively activated for discharging in response to a hit signal and a read/write enable signal. The hit and miss match lines may be electrically isolated from one another, such that when one or more of the respective miss signals are asserted, current from the hit match line does not discharge through the miss match line. | 2008-10-02 |
20080239779 | System and Method for Detecting Multiple Matches - A system for identifying asserted signals includes a plurality of input ports, a priority encoding module, and a match module. The plurality of input ports receive one of a plurality of input signals. The priority encoding module is coupled to the plurality of input ports and outputs a signal indicating a highest-priority input signal that is asserted. The match module is also coupled to the plurality of input ports and receives a plurality of match detect signals from the priority encoding module. Each match detect signal is associated with a particular input signal and indicates whether another input signal having a higher-priority than the associated input signal is asserted. The match module also generates a multiple match signal based on the input signals and the match detect signals. The multiple match signal indicates whether more than one of the input signals is asserted. | 2008-10-02 |
20080239780 | SEMICONDUCTOR DEVICE - A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches. | 2008-10-02 |
20080239781 | Semiconductor memory device and method of forming a layout of the same - A semiconductor memory device having a double-patterned memory cell array that includes a plurality of first bit lines spaced apart from each other and having a first pattern, a plurality of second bit lines spaced apart from each other and having a second pattern, the second bit lines being between the first bit lines to define an alternating array of first and second bit lines, the first and second patterns being different from each other, a first main memory cell array defined by a first portion of the alternating array, a second main memory cell array defined by a second portion of the alternating array, bit lines in the first main memory cell array having a substantially same regularity as bit lines in the second main memory cell array, and a dummy array between the first main memory cell array and the second main memory cell array. | 2008-10-02 |
20080239782 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a bit line which is provided above a semiconductor substrate and runs in a first direction, a source line which is provided above the semiconductor substrate and runs in the first direction, an active area which is provided in the semiconductor substrate and extends in the first direction, first and second selection transistors which are formed on the active area and share a source region electrically connected to the source line, a first memory element having one end electrically connected to a drain region of the first selection transistor and the other end electrically connected to the bit line, and a second memory element having one end electrically connected to a drain region of the second selection transistor and the other end electrically connected to the bit line. | 2008-10-02 |
20080239783 | Semiconductor memory devices having strapping contacts - Semiconductor memory devices having strapping contacts with an increased pitch are provided. The semiconductor memory devices include cell regions and strapping regions between adjacent cell regions in a first direction on a semiconductor substrate. Active patterns extend in the first direction throughout the cell regions and strapping regions and are spaced apart from one another in a second direction intersecting the first direction. First interconnection lines extend in the first direction throughout the cell regions and the strapping regions and are spaced apart from one another in the second direction while overlapping with the active patterns. Second interconnection lines extend in the second direction to intersect the active patterns and the first interconnection lines in the cell regions. The second interconnection lines are spaced apart from one another in the first direction. Memory cells are positioned at intersection portions of the first and second interconnection lines in the cell regions. Strapping contacts are in the strapping regions and configured such that the active patterns contact with the first interconnection lines through the strapping contacts. | 2008-10-02 |
20080239784 | HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS - A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures. | 2008-10-02 |
20080239785 | HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS - A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of the plurality of discontinuities in the associated shift register structure. | 2008-10-02 |
20080239786 | LOGIC CODING IN AN INTEGRATED CIRCUIT - The programming of a read-only memory formed of MOS transistors, the programming being set by a mask for forming an insulating layer prior to the forming of contacts of active regions of the transistors. An interconnection structure and a read-only memory. | 2008-10-02 |
20080239787 | LARGE ARRAY OF UPWARD POINTING P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT - An upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium is disclosed. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top heavily doped p-type region is doped with arsenic, and the semiconductor material of the diode is crystallized in contact with an appropriate silicide, germanide, or silicide-germanide. A large array of such upward-pointing diodes can be formed with excellent uniformity of current across the array when a voltage above the turn-on voltage of the diodes is applied. This diode is advantageously used in a monolithic three dimensional memory array. | 2008-10-02 |
20080239788 | INTEGRATED CIRCUIT HAVING A RESISTIVELY SWITCHING MEMORY AND METHOD - An integrated circuit having a resistance-based or resistively switching memory cell, and a method for operating a resistively switching memory cell is disclosed. One embodiment is adapted to be put in a low-resistance state by applying a first threshold voltage and in a high-resistance state by applying a second threshold voltage, wherein reading out of the data content from the memory cell is performed by applying a voltage to the memory cell in the range of the first or second threshold voltage or a higher voltage. | 2008-10-02 |
20080239789 | SEMICONDUCTOR MEMORY DEVICE - The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film. | 2008-10-02 |
20080239790 | METHOD TO FORM A MEMORY CELL COMPRISING A CARBON NANOTUBE FABRIC ELEMENT AND A STEERING ELEMENT - A method to form a rewriteable nonvolatile memory cell is disclosed, the cell comprising a steering element in series with a carbon nanotube fabric. The steering element is preferably a diode, but may also be a transistor. The carbon nanotube fabric reversibly changes resistivity when subjected to an appropriate electrical pulse. The different resistivity states of the carbon nanotube fabric can be sensed, and can correspond to distinct data states of the memory cell. A first memory level of such memory cells can be monolithically formed above a substrate, a second memory level monolithically formed above the first, and so on, forming a highly dense monolithic three dimensional memory array of stacked memory levels. | 2008-10-02 |
20080239791 | Nano-Electronic Memory Array - A memory device includes an array of memory cells disposed in rows and columns and constructed over a substrate, each memory cell comprising a first signal electrode, a second signal electrode, and a nano-layer disposed in the intersecting region between the first signal electrode and the second signal electrode; a plurality of word lines each connecting the first signal electrodes of a row of memory cells; and a plurality of bit lines each connecting the second signal electrodes of a column of memory cells. | 2008-10-02 |
20080239792 | METAL SILICIDE ALLOY LOCAL INTERCONNECT - A local interconnect is formed with a gate conductor line that has an exposed sidewall on an active area of a semiconductor substrate. The exposes sidewall comprises a silicon containing material that may form a silicide alloy upon silicidation. During a silicidation process, a gate conductor sidewall silicide alloy forms on the exposed sidewall of the gate conductor line and an active area silicide is formed on the active area. The two silicides are joined to provide an electrical connection between the active area and the gate conductor line. Multiple sidewalls may be exposed on the gate conductor line to make multiple connections to different active area silicides. | 2008-10-02 |
20080239793 | Generalized Interlocked Register Cell (GICE) - A memory element which includes a family of fault-tolerant storage elements using complementary metal-oxide-semiconductor (CMOS) technology is provided. The memory element provides arbitrary levels of redundancy, allowing the tolerance of multiple single event upsets due to particle hits. The memory element may be used in memory arrays such as caches and register files, and clocked registers and latches found in data path and control structures. | 2008-10-02 |
20080239794 | Magnetoresistive random access memory device with small-angle toggle write lines - Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally speaking, the disclosed principles provide for non-orthogonally aligned toggle-mode write lines used to switch toggle-mode MRAM devices that employ a bias field to decrease the threshold needed to switch the magnetic state of each device. While the conventional toggle-mode write lines provide for the desired orthogonal orientation of the applied magnetic fields to optimize device switching, the use of a bias field affects this orthogonal orientation. By non-orthogonally aligning the two write lines as disclosed herein, the detrimental affect of the bias field may be compensated for such that the net fields applied to the device for both lines are again substantially orthogonal, as is desired. | 2008-10-02 |
20080239795 | NONVOLATILE MEMORY DEVICE WITH WRITE ERROR SUPPRESSED IN READING DATA - A data write current from a pinned layer to a free layer is larger than a data write current from the free layer to the pinned layer. A data read current is smaller in value than the data write current. In the case where a difference in data read current between a high-resistance state and a low-resistance state is relatively small, a sense amplifier is connected so that the data read current flows from the pinned layer to the free layer, namely from a source line to a bit line. | 2008-10-02 |
20080239796 | MAGNETIC MEMORY DEVICE AND METHOD OF WRITING INTO THE SAME - A magnetic memory device includes a memory cell including magnetoresistance effect elements MTJ | 2008-10-02 |
20080239797 | INFORMATION RECORDING/REPRODUCING DEVICE - There is proposed a nonvolatile information recording/reproducing device with low power consumption and high thermal stability. The information recording/reproducing device according to an aspect of the present invention includes a recording layer, and mechanism for recording information by generating a phase change in the recording layer while applying a voltage to the recording layer. The recording layer is comprised one of a Wolframite structure and a Scheelite structure. | 2008-10-02 |
20080239798 | Compensation circuit and memory with the same - One embodiment of the invention provides a compensation circuit. The compensation circuit comprises a writing driver, a distance detection circuit, an operating element and an auxiliary writing driver. The writing driver provides a writing current to a writing path. The distance detection circuit is coupled to the writing path to detect a distance that the writing current has travelled and outputs a control signal based on the distance. The operating element is coupled to the writing path. The auxiliary writing driver provides an auxiliary current to the writing path based on the control signal. | 2008-10-02 |
20080239799 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DATA ERASE/WRITE METHOD THEREOF - A nonvolatile semiconductor memory device includes a memory cell array which includes a memory cell string including a plurality of memory cells each having a variable resistor element and a switching element having a current path with one end and the other end, between which the variable resistor element is connected, the plurality of memory cells having current paths thereof being connected in series, the memory cell array further including a first select element connected to one end of a current path of the memory cell string, and a second select element connected to the other end of the current path of the memory cell string, a bit line which is electrically connected to one end of a current path of the first select element, and a source line which is electrically connected to one end of a current path of the second select element. | 2008-10-02 |
20080239800 | MAGNETIC MEMORY ARRAYS - A magnetic memory array. A first bit line provides a first writing magnetic field to a magnetic memory cell. A second bit line provides a second writing magnetic field to a reference magnetic memory cell. A word line provides a third writing magnetic field to the magnetic memory cell and a fourth writing magnetic field to the reference magnetic memory cell. The third writing magnetic field exceeds the fourth writing magnetic field. | 2008-10-02 |
20080239801 | Load Management for Memory Device - Methods and apparatus for managing electrical loads of electronic devices are disclosed. According to one embodiment, a current load imposed by an electronic device, such as a memory device (or memory system), can be measured. Then, using the measured current load, the memory device can determine whether (and to what extent) operational performance should be limited. By limiting operational performance, the memory device is able to limit its current load so as to satisfy a specification criterion or other requirement. The electrical load management is well suited for use in portable memory products (e.g., memory cards) to manage current loads being drawn. | 2008-10-02 |
20080239802 | Device with Load-Based Voltage Generation - Method and device for providing voltage generation with load-based control are disclosed. The voltage generation can be provided within an electronic device, such as a memory system that provides data storage. In one embodiment, an electrical load imposed on a generated voltage can be monitored and used to dynamically control strength of the generated voltage. For example, for greater electrical loads, the generated voltage can be provided with a greater strength, and for lesser electrical loads, the generated voltage can be provided with a lesser strength. By compensating the generated voltage for the nature of the imposed electrical load, the generated voltage can be provided in a stable manner across a significant range of loads. In the case of a memory system, stability in the generated voltage provides for reduced voltage ripple and thus improved sensing margins. The voltage generation is well suited for use in portable memory products (e.g., memory cards) to generate one or more internal voltages. | 2008-10-02 |
20080239803 | MEMORY CELLS, MEMORY DEVICES AND INTEGRATED CIRCUITS INCORPORATING THE SAME - A memory cell is provided which includes an access transistor and a gated lateral thyristor (GLT) device. The access transistor includes a source node. The gated lateral thyristor (GLT) device includes an anode node coupled to the source node of the access transistor. | 2008-10-02 |
20080239804 | Method for reading multiple-value memory cells - A read method for multiple-value information in a semiconductor memory such as a nonvolatile semiconductor memory is introduced. The method includes obtaining a first data from a selected multiple-value memory cell by applying a first voltage to a control gate of the selected multiple-value memory cell. A second data from the selected multiple-value memory cell is obtained by applying a second voltage to the control gate of the selected multiple-value memory cell. A first bit of the plurality of bits stored in the selected multiple-value memory cell is then obtained by performing a predetermined calculation on the first data and the second data. A second bit of the plurality of bits is obtained from the selected multiple-value memory cell by applying a third voltage to the control gate of the selected multiple-value memory cell. | 2008-10-02 |
20080239805 | NONVOLATILE SEMICONDUCTOR MEMORY AND DATA READING METHOD - A nonvolatile semiconductor memory according to the present invention includes a memory cell array including a plurality of electrically writable memory cells; a plurality of word lines and a plurality of bit lines connected to the plurality of memory cells; and a data reading and programming control section for, when performing 4-value data programming, read or erasure with respect to at least one of the plurality of memory cells, selecting and applying a voltage to a corresponding word line and a corresponding bit line among the plurality of word lines and the plurality of bit lines; wherein the data reading and programming control section includes an adjacent memory cell data reading section for reading, at a reading voltage of a predetermined reading voltage level, whether or not data is programmed in a lower page of a second memory cell adjacent to a first memory cell in the memory cell array, and generating adjacent memory cell state data which represents a data state of the second memory cell; an adjacent memory cell data memory section for storing the adjacent memory cell state data generated by the adjacent memory cell data reading section; a reading voltage level control section for defining a plurality of predetermined reading voltage verify levels for reading data from the first memory cell based on the adjacent memory cell state data; a data reading section for reading the data from the first memory cell at a plurality of reading voltages corresponding to the plurality of predetermined reading voltage verify levels; and a data determining section for determining which data of 4-value data is programmed in the first memory cell based on the data which is read by the data reading section. | 2008-10-02 |
20080239806 | NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming multilevel non-volatile multilevel memory cells. One method includes increasing a threshold voltage (Vt) for each of a number of memory cells until the Vt reaches a verify voltage (VFY) corresponding to a program state among a number of program states. The method includes determining whether the Vt of each of the cells has reached a pre-verify voltage (PVFY) associated with the program state, selectively biasing bit lines coupled to those cells whose Vt has reached the PVFY, adjusting the PVFY to a different level, and selectively biasing bit lines coupled to cells whose Vt has reached the adjusted PVFY, wherein the PVFY and the adjusted PVFY are less than the VFY. | 2008-10-02 |
20080239807 | Transition areas for dense memory arrays - A non-volatile memory chip has word lines spaced a sub-F (sub-minimum feature size F) width apart with extensions of the word lines in at least two transition areas. Neighboring extensions are spaced at least F apart. The present invention also includes a method for word-line patterning of a non-volatile memory chip which includes generating sub-F word lines with extensions in transition areas for connecting to peripheral transistors from mask generated elements with widths of at least F. | 2008-10-02 |
20080239808 | Flash Memory Refresh Techniques Triggered by Controlled Scrub Data Reads - The quality of data stored in individual blocks of memory cells of a flash memory system is monitored by a scrub read of only a small portion of a block, performed after data are read from less than all of a block in response to a read command from a host or memory controller. The small portion is selected for the scrub read because of its greater vulnerability than other portions of the block to being disturbed as a result of the commanded partial block data read. This then determines, as the result of reading a small amount of data, whether at least some of the data in the block was disturbed by the command data read to a degree that makes it desirable to refresh the data of the block. | 2008-10-02 |
20080239809 | FLASH MEMORY DEVICE AND METHOD FOR PROVIDING INITIALIZATION DATA - A flash memory device includes a cell array and a decision unit. The cell array includes multiple regions corresponding to multiple input/output lines. Initialization data are repeatedly stored in each of the regions. The decision unit determines whether the stored data are valid based on values of bits of the stored data read from each region. | 2008-10-02 |
20080239810 | CELL ARRAY OF SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A cell array of a flash memory device includes first and second memory block units, and a voltage generator. Each of the first and second memory block units includes a plurality of memory blocks having a plurality of memory cells. The voltage generator outputs a source voltage, a power supply voltage and a positive bias to the first and second memory block units. The first and second memory block units are connected in parallel through a bit line. | 2008-10-02 |
20080239811 | METHOD FOR CONTROLLING A NON-VOLATILE SEMICONDUCTOR MEMORY, AND SEMICONDUCTOR STORAGE SYSTEM - A semiconductor storage system includes a first memory region including at least one block constituted from a plurality of memory cells, the memory cell is capable of storing n bits data, the block is a minimum unit which is capable of being independently erased, a second memory region including at least one block constituted from a plurality of memory cells, the memory cell is capable of storing m (m>n: m is integer) bits data, the block is a minimum unit which is capable of being independently erased, and a controller which controls a number of rewrites for the block in the first memory region not to be more than a first predetermined number of times, and controls a number of rewrites for the block in the second memory region not to be more than a second predetermined number of times. | 2008-10-02 |
20080239812 | NONVOLATILE SEMICONDUCTOR MEMORY SYSTEM - According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to readout data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors. | 2008-10-02 |
20080239813 | Method of Compensating Variations along a Word Line in a Non-Volatile Memory - Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage by a first voltage shifter and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage by a second voltage shifter. | 2008-10-02 |
20080239814 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a plurality of memory cells coupled in series, a plurality of word lines coupled to the respective memory cells, and a plurality of spacers interposed between the word lines and having different dielectric constants according to line widths of the word lines. | 2008-10-02 |
20080239815 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a memory cell area of a semiconductor device, first, second, and third inter-layer insulating films respectively cover a cell transistor, a bit wiring line, and a capacitor which are connected to each other. In an adjacent peripheral circuit area, a peripheral-circuit transistor is covered with the first inter-layer insulating film, a first-layer wiring line connected to the peripheral-circuit transistor is provided on the first inter-layer insulating film and covered with the second inter-layer insulating film, and a second-layer wiring line is provided on the third inter-layer insulating film. In the memory cell area, a landing pad is provided on the second inter-layer insulating film and between the capacitor and a contact plug for connecting the capacitor to the cell transistor. An assist wiring line connected to the first-layer wiring line is provided on the main surface of the second inter-layer insulating film, on which the landing pad is provided. | 2008-10-02 |
20080239816 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device comprises a memory cell unit including at least one memory cell having a structure with a floating gate and a control gate stacked via an insulator on a semiconductor substrate. A common source line is connected to one end of the memory cell unit. A bit line is connected to the other end of the memory cell unit. The control gate has at least an upper portion with a width along the gate length formed wider than the width of the floating gate. | 2008-10-02 |
20080239817 | Nonvolatile semiconductor memory device and method of erasing and programming the same - A nonvolatile semiconductor memory device includes a semiconductor substrate having a source, a drain, and a channel region between the source and the drain. The channel region has a first end portion near the drain, a second end portion near the source, and a middle portion between the first and second end portions. The first and second end portions having approximately same width. The memory device is electrically erased by using a hot carrier generated in the first end portion due to avalanche breakdown. The channel region includes a first channel extending from the drain and a second channel adjacent to the first channel. An impurity concentration of the second channel is higher than that of the first channel. An interface between the first and second channels is located in the middle portion between the first and second end portions. | 2008-10-02 |
20080239818 | THREE DIMENSIONAL NAND MEMORY - A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell, a select transistor, a first word line of the first memory cell, a second word line of the second memory cell, a bit line, a source line, and a select gate line of the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line. | 2008-10-02 |
20080239819 | NAND FLASH MEMORY WITH FIXED CHARGE - A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also. | 2008-10-02 |
20080239820 | SELF-ADAPTIVE AND SELF-CALIBRATED MULTIPLE-LEVEL NON-VOLATILE MEMORIES - Innovative self-adaptive and self-calibrated methods and structures for Multi-Level Cell (MLC) Non-Volatile Memory (NVM) are disclosed. In the MLC NVM, NVM cells are self-adaptively programmed into a fixed response tolerance window centered at the reference current or voltage corresponding to a selected level gate voltage applied to the controlled gates of NVM cells. The fixed response tolerance window is related to the threshold voltage tolerance window through the sense circuit gain. Properly choosing the sense circuit gain and the response window can control the threshold voltage tolerance window to a desired value. An incremental gate voltage larger than the threshold voltage tolerance window of each NVM cell will guarantee that each NVM cell will produce the correct output current (voltage) in response to applying to the control gate of the NVM cell the stepped voltage corresponding to the level of information stored in the NVM cell. As the stepped voltage applied to the gate of an NVM cell transitions from a voltage just below the threshold voltage of the NVM cell to a voltage corresponding to the threshold voltage of the NVM cell, the output current (voltage) from the NVM cell will pass the current (voltage) transition in comparison with the reference current (voltage). The current (voltage) transition can be detected and converted into the bit-word information representing the voltage level stored in the NVM cell. When the response of an NVM cell falls outside the response tolerance window into the guard-band regions, the NVM cell can be re-calibrated and the bit-word information can be saved from fading away. | 2008-10-02 |
20080239821 | NAND MEMORY WITH SIDE-TUNNELING - A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling between control gates and floating gates is used for programming. A process for forming a memory array forms odd numbered floating gates from a first layer and even numbered floating gates from a second layer. | 2008-10-02 |
20080239822 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - A semiconductor memory device with NAND cell units arranged therein, the NAND cell unit including: a plurality of electrically rewritable and non-volatile memory cells connected in series; first and second select gate transistors disposed at the both ends of the NAND cell unit for coupling it to a bit line and a source line, respectively; and dummy cells disposed adjacent to the first and second select gate transistors in the NAND cell unit, wherein the dummy cells are set at a state with a threshold voltage higher than that of an erase state of the memory cell. | 2008-10-02 |
20080239823 | NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR CONTROLLING THE SAME - A nonvolatile semiconductor memory includes a memory cell array, a flag information storage that stores a write flag indicating success/failure of writing in association with each address of a plurality of data segments contained in the data block, an internal address storage that selects the address where the writing has failed, a write circuit that performs data writing, a comparator that performs verify operation to verify success/failure of the data writing, and a sequence controller that updates a write flag according to the result of the verify operation. | 2008-10-02 |
20080239824 | Non-Volatile Memory with Compensation for Variations Along a Word Line - Variation in programming efficacy due to variation in time constants along a word line that spans across a memory plane is compensated by adjusting the bit line voltages across the plane to modify the programming rates. In this way, the variation in programming efficacy is substantially reduced during programming of a group of memory cells coupled to the word line. This will allow uniform optimization of programming across the group of memory cells and reduce the number of programming pulses required to program the group of memory cells, thereby improving performance. In one embodiment, during programming, the bit lines in a first half of the memory plane closer to a source of word line voltage is set to a first voltage and the bit lines in a second half of the memory plane further from the source of word line voltage is set to a second voltage. | 2008-10-02 |
20080239825 | FLOATING GATE MEMORY DEVICE WITH IMPROVED REFERENCE CURRENT GENERATION - A non-volatile semiconductor memory device is provided with: a first memory cell including a floating gate transistor; a first bitline connected to a diffusion layer which is used as a source of the first memory cell; a second bitline connected to a diffusion layer which is used as a drain of the first memory cell; a first reference cell including a floating gate transistor; a third bitline electrically isolated from the first bitline and connected to a diffusion layer which is used as a source of the first reference cell; a read circuit identifying data stored in the first memory cell in response to a memory cell signal received from the first memory cell through the second bitline and a reference signal received from the first reference cell through the fourth bitline; and a bitline level controller controlling a voltage level of the third bitline. | 2008-10-02 |
20080239826 | Semiconductor memory device capable of achieving narrower distribution width of threshold voltages of memory cells and method of data write in the same - When a data write sequence is started, initially, write data is latched in a data latch circuit corresponding to one memory mat. Then, a program pulse is applied to the memory mat, and data read from a memory cell, which is a data write target bit in the memory mat, is performed. Thereafter, verify determination of the memory mat is performed. After a verify operation for the memory mat is completed, a program pulse is applied to another memory mat, and a verify operation for another memory mat is performed. | 2008-10-02 |
20080239827 | METHODS OF FORMING AND OPERATING NAND MEMORY WITH SIDE-TUNNELING - A string of nonvolatile memory cells are formed with control gates extending between floating gates, control gates and floating gates separated by tunnel dielectric layers. Electron tunneling between control gates and floating gates is used for programming. A process for forming a memory array forms odd numbered floating gates from a first layer and even numbered floating gates from a second layer. | 2008-10-02 |
20080239828 | FLASH MEMORY DEVICE AND ERASE METHOD THEREOF - An erase operating time can be shortened and an erase operating characteristic can be improved in a flash memory device. The flash memory device includes a plurality of memory cell blocks, an operating voltage generator and a controller. Each of the plurality of memory cell blocks includes memory cells connected to a plurality of word lines. A voltage generator is configured to apply an erase voltage to a memory cell block selected for an erase operation, and change a level of the erase voltage if an attempt of the erase operation is not successful. A controller is configured to control the voltage generator to apply a first erase voltage to a memory cell block selected for an erase operation. The first erase voltage corresponds to a previous erase voltage that was used successfully in completing a previous erase operation. The first erase voltage is an erase voltage that is used in a first erase attempt for the erase operation. | 2008-10-02 |
20080239829 | MEMORY APPARATUS INCLUDING PROGRAMMABLE NON-VOLATILE MULTI-BIT MEMORY CELL, AND APPARATUS AND METHOD FOR DEMARCATING MEMORY STATES OF THE CELL - Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can thus be programmed without reading out its memory state during the programming process, with programming margins being assured by the dependence of the read reference signals on the programming reference signals. Both sets of reference signals may be generated by reference cells which track variations in the operating characteristics of the memory cell with changes in conditions, such as temperature and system voltages, to enhance the reliability of memory programming and readout. | 2008-10-02 |
20080239830 | Methods of Operating Memory Devices Including Discharge of Source/Drain Regions and Related Electronic Devices - A memory device may include a memory cell array having a plurality of memory cell transistors serially coupled in a string between a string selection transistor and a ground selection transistor. The string selection transistor may be coupled between the string and a bit line, and the ground selection transistor may be coupled between the string and a common source line. In addition, each memory cell transistor may includes a floating gate between a control gate electrode and a semiconductor substrate, and source/drain regions of the semiconductor substrate may be included on opposite sides of the control gate electrode. Responsive to an erase command, the memory cell transistors of the string may be erased. Further responsive to the erase command and after erasing the memory cell transistors of the string, electrical charge from the source/drain regions of the memory cell transistors may be discharged through the ground selection transistor to the common source line and/or through the string selection transistor to the bit line. Related devices are also discussed. | 2008-10-02 |
20080239831 | Clock synchronizer - Disclosed herein are synchronization latch solutions. | 2008-10-02 |
20080239832 | FLASH MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A flash memory device includes a data input/output pad and a core region in which a plurality of unit cells are arranged. A data input buffer is configured to receive command and address data through the data input/output pad and transfer the received command and address to the core region. A data output buffer is configured to output the data through the data input/output pad, and a data input controller is configured to detect an outputting of the data and disable the data input buffer. | 2008-10-02 |
20080239833 | Readout of multi-level storage cells - A multi-level sensing scheme compares the state of a multi-level storage cell with monotonously changing reference states, which are associated to different information values. That particular information value is identified to be the information stored in the multi-level storage cell, which has associated that reference state which, in a changing direction, firstly exceeds the state. | 2008-10-02 |
20080239834 | SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING - A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node. | 2008-10-02 |
20080239835 | Semiconductor memory device with high voltage generator - A semiconductor memory device which prevents a drop of the level of an external voltage due to generation of high voltage, thereby ensuring an effective data window. The semiconductor memory device includes a level detecting unit and a voltage generating unit. The level detecting unit is configured to detect a level of an internal voltage based on a reference voltage to output a level detection signal. The voltage generating unit is configured to generate the internal voltage by selectively pumping an external voltage according to the level detection signal and a refresh signal. | 2008-10-02 |
20080239836 | Method for Managing Electrical Load of an Electronic Device - Methods and apparatus for managing electrical loads of electronic devices are disclosed. According to one embodiment, a current load imposed by an electronic device, such as a memory device (or memory system), can be measured. Then, using the measured current load, the memory device can determine whether (and to what extent) operational performance should be limited. By limiting operational performance, the memory device is able to limit its current load so as to satisfy a specification criterion or other requirement. The electrical load management is well suited for use in portable memory products (e.g., memory cards) to manage current loads being drawn. | 2008-10-02 |
20080239837 | SEMICONDUCTOR DEVICE - A semiconductor memory device includes a boosting circuit which boosts in a second voltage higher than an external power supply by using a first voltage as a reference voltage, and a bandgap reference circuit which operates by using the second voltage generated by the boosting circuit as a power supply voltage. | 2008-10-02 |
20080239838 | Semiconductor memory device for reducing power consumption - A semiconductor memory device which includes: a voltage supplying unit for outputting a power source voltage as a driving source signal during a predetermined time, and then outputting a high voltage as the driving source signal in response to a driving control signal activated in response to an address signal; and a word line control unit for activating a word line at a voltage level of the driving source signal in response to the driving control signal. | 2008-10-02 |
20080239839 | METHOD FOR USING A SPATIALLY DISTRIBUTED AMPLIFIER CIRCUIT - An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array. | 2008-10-02 |
20080239840 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A GLOBAL INPUT/OUTPUT LINE OF A DATA TRANSFER PATH AND ITS SURROUNDING CIRCUITS - A semiconductor memory device includes an input/output line of a data transfer path and its surrounding circuits, comprising a controller which generates a control signal corresponding to command and address input in read and write operation; and a repeater which selects any one of the plurality of bank groups as the control signal to control data transfer between the selected bank group and an input/output pad. | 2008-10-02 |
20080239841 | Implementing Calibration of DQS Sampling During Synchronous DRAM Reads - A method and calibration apparatus implement calibration of sampling of a data strobe signal (DQS) during synchronous dynamic random access memory (DRAM) reads. A calibration control is provided to enable calibration testing. A selected one of a received DQS signal and an internal Enable signal is driven onto a data mask (DQM) IO during a DRAM read for calibration testing. The received DQS signal and the internal Enable signal are used to adjust the Enable delay to generally center the preamble time at the DQS receiver. | 2008-10-02 |
20080239842 | Semiconductor memory device - A semiconductor memory device is capable of controlling a tRCD (RAS to CAS Delay) time regardless of an address input timing during a test operation of the semiconductor memory device. The semiconductor memory device includes a column address strobe pulse generator for generating a column address strobe pulse in response to a column command signal and a row address strobe pulse generator for receiving an active command signal or the column command signal to produce a row address strobe pulse in response to a test mode signal. | 2008-10-02 |
20080239843 | INTERFACE CIRCUIT, MEMORY INTERFACE SYSTEM, AND DATA RECEPTION METHOD - An interface circuit is disclosed that can include a delay circuit that generates a delay signal obtained by delaying a data strobe signal; a first logical circuit that performs a logical operation of on the data strobe signal and the delay signal, and outputs an operation result as a first strobe signal; a second logical circuit that receives the first strobe signal and generates a second strobe signal that is complementary to the first strobe signal; a first latch circuit that latches a data signal based on the first strobe signal; and a second latch circuit that latches the data signal based on the second strobe signal. | 2008-10-02 |
20080239844 | IMPLEMENTING CALIBRATION OF DQS SAMPLING DURING SYNCHRONOUS DRAM READS - A method and calibration apparatus implement calibration of sampling of a data strobe signal (DQS) during synchronous dynamic random access memory (DRAM) reads. A calibration control is provided to enable calibration testing. A selected one of a received DQS signal and an internal Enable signal is driven onto a data mask (DQM) 10 during a DRAM read for calibration testing. The received DQS signal and the internal Enable signal are used to adjust the Enable delay to generally center the preamble time at the DQS receiver. | 2008-10-02 |
20080239845 | Semiconductor memory device and method for driving the same - A semiconductor memory device includes a delay locked loop (DLL) unit configured to generate a plurality of DLL clocks, each having a different phase according to delay values predefined by a DLL operation; a data output buffering unit configured to output data in response to the DLL clocks; and a skew compensating unit disposed between the DLL unit and the data output buffering unit to remove a clock skew occurring when the DLL clocks are transferred to the data output buffering unit. | 2008-10-02 |
20080239846 | Delay locked loop and semiconductor memory device with the same - A semiconductor memory device is capable of controlling a delay locked loop appropriately based on operation modes, particularly in a fast power-down mode to reduce an amount of current maximumly. The semiconductor memory device includes a delay-locked clock signal generating unit, a mode signal generating unit, and a delay locking control unit. The delay-locked clock signal generating unit performs a delay locking operation on a clock signal, thereby generating a delay-locked clock signal. The mode signal generating unit enables a fast precharge power-down mode signal in a fast precharge power-down mode. The delay locking control unit controls the delay-locked clock signal generating unit to be activated in a predetermined cycle in response to the fast precharge power-down mode signal. | 2008-10-02 |